Chip area determination method, area model construction method and electronic equipment

Abstract

The invention discloses a chip area determination method, an area model construction method and electronic equipment, and relates to the technical field of computers. The electronic equipment can predict the area of a target chip based on a pre-constructed area model, and the area model comprises a plurality of groups of corresponding relations between micro-architecture parameters and sub-module area functions, so that the area of each sub-module in the target chip can be determined based on the area model; therefore, the overall area of the target chip can be accurately determined. In the embodiment of the invention, analysis modeling and process scaling mapping do not need to be carried out, the pre-constructed area model can be used for rapidly predicting the area in the design process of different types of chips, and the accuracy of predicting the area is improved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a chip area determination method, an area model construction method and an electronic device. Background Art

[0002] With the continuous development of chip design technology, it is now possible to use hardware design language to write chip code. The same version of the code can generate circuit structures with different micro-architecture parameters after different configurations. Chips with different circuit structures will also have different chip areas.

[0003] In order to produce chips with an area that meets the usage requirements, the area of ​​the produced chip can be predicted based on the micro-architecture parameters configured for the chip before the actual chip production. Currently, when predicting the chip area, it is usually necessary to use analytical modeling and process scaling mapping to build a chip model based on the micro-architecture parameters. This process not only requires chip developers to be very familiar with the micro-architecture of the processor core, but also the accuracy of the chip area obtained is not high. Summary of the invention

[0004] The embodiments of the present application provide a chip area determination method, an area model construction method and an electronic device, which can improve the accuracy of predicted area.

[0005] In a first aspect, an embodiment of the present application provides a chip area determination method, which can be used to determine the area information of a target chip, wherein the target chip can be any chip to be produced, and the target chip can include multiple sub-modules. The method can include: obtaining a micro-architecture parameter table to be tested of the target chip to be produced, wherein the micro-architecture parameter table to be tested includes the micro-architecture parameters to be tested of each sub-module of the target chip. According to the micro-architecture parameters to be tested of each sub-module and a pre-constructed area model, the area of ​​each sub-module in the target chip is determined, and according to the area of ​​each sub-module, the area information of the target chip is determined, wherein the area model includes a correspondence between multiple sets of micro-architecture parameters and sub-module area functions.

[0006] The chip area determination method provided in the embodiment of the present application predicts the area of ​​the target chip based on a pre-built area model. Since the area model includes the correspondence between multiple sets of micro-architecture parameters and sub-module area functions, the area of ​​each sub-module in the target chip can be determined separately based on the area model, thereby accurately determining the overall area of ​​the target chip. The method provided in the embodiment of the present application does not require analytical modeling and process scaling mapping. The pre-built area model can be used to quickly predict the area in different types of chip design processes, thereby improving the accuracy of the predicted area.

[0007] In an optional implementation, for each submodule in the target chip, the following operations can be performed respectively: in the area model, find the target submodule area function corresponding to the micro-architecture parameter to be tested of the submodule, and determine the area of ​​the submodule based on the target submodule area function.

[0008] According to the micro-architecture parameters to be tested of each sub-module, the corresponding target sub-module area function is searched in the area model. Through the target sub-module area function, the area of ​​each sub-module can be quickly determined.

[0009] In an optional implementation, the area model can be constructed in the following manner: obtain multiple chip samples, each chip sample contains at least one submodule sample. Determine the multiple submodule samples contained in the multiple chip samples, determine the logic area area and micro-architecture parameters of the multiple submodule samples, and determine the storage area area of ​​at least one target submodule sample, and construct the area model based on the logic area area and micro-architecture parameters of the multiple submodule samples and the storage area area of ​​the at least one target submodule sample. Wherein, the at least one target submodule sample is a submodule sample containing a storage area in the multiple submodule samples.

[0010] The above implementation method determines the logical area areas of multiple sub-module samples respectively, and for the target sub-module samples including the storage area, determines the storage area area of ​​the target sub-module sample; based on the logical area areas of multiple sub-module samples and the storage area area of ​​at least one target sub-module sample, determines the correspondence between the micro-architecture parameters and the area function, which can make the obtained area model more accurate.

[0011] In an optional implementation, the logic area of ​​each sub-module sample among multiple sub-module samples includes multiple tracks. For the logic area of ​​the first sub-module sample among the multiple sub-module samples, the following operations can be performed: respectively determine the effective area covered by the standard logic unit contained in each track in the first sub-module sample, and take the sum of the effective areas of the multiple tracks as the logic area area in the first sub-module sample.

[0012] In the above implementation, by determining the effective area covered by the standard logic unit contained in each track in the sub-module sample, the area of ​​the logic region in the sub-module sample can be accurately determined.

[0013] In an optional implementation, for the logic area of ​​the first submodule sample, if there are standard logic units to be processed that occupy multiple tracks in the logic area, the standard logic units to be processed are cut, and each of the obtained standard logic units occupies one track. For the first track in the first submodule sample, the following operations can be performed: according to the set expansion coefficient, the standard logic units contained in the first track are expanded horizontally to obtain at least one rectangular block, the end coordinates of each rectangular block in the at least one rectangular block are determined, and according to the end coordinates of each rectangular block, the effective area of ​​the first track is determined.

[0014] In the above implementation, by horizontally expanding the standard logic units contained in a track to obtain a rectangular block, the effective area of ​​the track can be quickly determined according to the end coordinates of the rectangular block.

[0015] In an optional implementation, for the first rectangular block in at least one rectangular block obtained after expansion, the following operations can be performed: respectively determine the horizontal coordinate expansion values ​​of the standard logic units corresponding to the two ends of the first rectangular block; determine the end coordinates of the first rectangular block according to the horizontal coordinate expansion values ​​of the standard logic units corresponding to the two ends of the first rectangular block and the horizontal coordinate values ​​of the two ends of the first rectangular block.

[0016] In the above implementation, the horizontal coordinate values ​​of the two ends of the rectangular block are corrected according to the horizontal coordinate expansion values ​​of the corresponding standard logic units at the two ends of the rectangular block, so that the effective area of ​​the obtained track can be more accurate.

[0017] In an optional implementation, the following operations can be performed for the logic area of ​​the second sub-module sample among multiple sub-module samples: color the standard logic units contained in the logic area of ​​the second sub-module sample, and determine the area of ​​the logic area in the second sub-module sample based on the ratio of the number of pixels of the colored part in the second sub-module sample to the total number of pixels of the chip sample to which the second sub-module sample belongs, and the area of ​​the chip sample to which the second sub-module sample belongs.

[0018] In the above implementation, the area of ​​the logic region in the submodule sample can be quickly determined by the coloring method.

[0019] In an optional implementation, the following operations can be performed for the storage area of ​​the third sub-module sample in at least one target sub-module sample: obtain the micro-architecture parameters of the storage area of ​​the third sub-module sample; determine the target logical depth and target logical bit width corresponding to the micro-architecture parameters of the storage area based on the correspondence between multiple pre-stored micro-architecture parameters and the logical depth and logical bit width of the storage area; determine the target physical width corresponding to the target logical depth based on the correspondence between the pre-stored logical depth and the physical width, and determine the target physical height corresponding to the target logical bit width based on the correspondence between the pre-stored logical bit width and the physical height; and use the product of the target physical width and the target physical height as the storage area area of ​​the third sub-module sample.

[0020] In the above implementation, the storage area in the submodule sample can be quickly determined by looking up the table.

[0021] In an optional implementation, for the first category of sub-module samples that do not include storage areas among the multiple sub-module samples, the correspondence between at least one set of micro-architecture parameters and sub-module area functions can be determined based on the logic area area of ​​the first category of sub-module samples and the micro-architecture parameters of the first category of sub-module samples; for the second category of sub-module samples that include storage areas among the multiple sub-module samples, the correspondence between at least one set of micro-architecture parameters and sub-module area functions can be determined based on the storage area area and logic area of ​​the second category of sub-module samples and the micro-architecture parameters of the second category of sub-module samples; wherein the second category of sub-module samples includes at least one target sub-module sample.

[0022] In an optional implementation, for a first group of sub-module samples having micro-architecture parameters with the same name, the following operations may be performed: determining weights corresponding to a group of micro-architecture parameters based on the logical area area of ​​each first-category sub-module sample in the first group of sub-module samples; determining a sub-module area function corresponding to the group of micro-architecture parameters based on the weights corresponding to the group of micro-architecture parameters and the group of micro-architecture parameters; wherein the group of micro-architecture parameters are micro-architecture parameters of the logical area of ​​the first group of sub-module samples; and the first group of sub-module samples are any group of sub-module samples having micro-architecture parameters with the same name in the first-category sub-module samples.

[0023] In an optional implementation, for a second group of sub-module samples having micro-architecture parameters with the same name, the following operations may be performed: determining a weight corresponding to the micro-architecture parameters of the logic area based on the logic area area of ​​each second-category sub-module sample in the second group of sub-module samples; wherein the micro-architecture parameters of the logic area are the micro-architecture parameters of the logic area of ​​the second group of sub-module samples; determining a function corresponding to the micro-architecture parameters of the storage area based on the storage area area of ​​each second-category sub-module sample in the second group of sub-module samples; wherein the micro-architecture parameters of the storage area are the micro-architecture parameters of the storage area of ​​the second group of sub-module samples; determining a group of sub-module area functions corresponding to the micro-architecture parameters based on the weight corresponding to the micro-architecture parameters of the logic area and the micro-architecture parameters of the logic area, as well as the function corresponding to the micro-architecture parameters of the storage area; the group of micro-architecture parameters includes the micro-architecture parameters of the logic area and the micro-architecture parameters of the storage area, and the second group of sub-module samples is any group of sub-module samples of the second category of sub-module samples having micro-architecture parameters with the same name.

[0024] In an optional implementation, the chip area determination method may also include: determining the performance information and power consumption information of the target chip respectively according to the micro-architecture parameter table to be tested of the target chip; judging whether the determined area information, performance information or power consumption information of the target chip meets the set conditions; if the area information, performance information or power consumption information of the target chip does not meet the set conditions, redetermining the micro-architecture parameters of the target chip, and generating a new micro-architecture parameter table to be tested according to the redetermined micro-architecture parameters, and redetermining the area information, performance information and power consumption information of the target chip according to the new micro-architecture parameter table to be tested; repeating the above steps until the area information, performance information or power consumption information of the target chip finally determined meets the set conditions; using the micro-architecture parameter table to be tested of the target chip finally determined as the target micro-architecture parameter table of the target chip; outputting the target micro-architecture parameter table; the target micro-architecture parameter table is used in the production process of the target chip.

[0025] In the above implementation, the parameter table of the micro-architecture to be tested of the target chip is optimized based on the predicted area information, performance information and power consumption information, which can reduce the development workload of back-end engineers.

[0026] In a second aspect, an embodiment of the present application provides a method for constructing an area model, in which the area model includes a correspondence between multiple sets of micro-architecture parameters and sub-module area functions; the method includes: obtaining multiple chip samples, and determining multiple sub-module samples contained in the multiple chip samples; wherein each chip sample contains at least one sub-module sample; determining the logic area area and micro-architecture parameters of the multiple sub-module samples, and determining the storage area area of ​​at least one target sub-module sample; wherein at least one target sub-module sample is a sub-module sample containing a storage area among the multiple sub-module samples; constructing an area model based on the logic area area and micro-architecture parameters of the multiple sub-module samples, and the storage area area of ​​at least one target sub-module sample.

[0027] Optionally, some steps involved in this method can refer to the description of corresponding steps in the area model construction process in the first aspect, and will not be repeated here.

[0028] In a third aspect, an embodiment of the present application provides an electronic device, comprising a module for executing any one of the methods provided in the first aspect, or a module for executing any one of the methods provided in the second aspect.

[0029] In a fourth aspect, an embodiment of the present application provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program that can be run on the processor, and when the computer program is executed by the processor, the processor implements any one of the methods provided in the first aspect, or implements any one of the methods provided in the second aspect.

[0030] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute any one of the methods provided in the first aspect above, or to execute any one of the methods provided in the second aspect.

[0031] In a sixth aspect, an embodiment of the present application provides a computer program product comprising computer executable instructions, which are used to enable a computer to execute any one of the methods provided in the first aspect above, or to execute any one of the methods provided in the second aspect.

[0032] The technical effects that can be achieved in any of the second to sixth aspects mentioned above can refer to the description of the beneficial effects in the first aspect mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A flowchart of a method for constructing an area model according to an embodiment of the present application;

[0034] Figure 2 A schematic diagram of a chip sample layout according to an embodiment of the present application;

[0035] Figure 3 A schematic diagram of another chip sample layout according to an embodiment of the present application;

[0036] Figure 4 A schematic diagram of a track in a logic area of ​​a submodule sample provided in an embodiment of the present application;

[0037] Figure 5 A schematic diagram of lateral expansion of a standard logic unit provided in an embodiment of the present application;

[0038] Figure 6 A schematic diagram of determining the effective area of ​​a track provided in an embodiment of the present application;

[0039] Figure 7 A schematic diagram of another method for determining the effective area of ​​a track provided in an embodiment of the present application;

[0040] Figure 8 A schematic diagram of coloring a logic area in a submodule sample provided in an embodiment of the present application;

[0041] Fig. 9 A flowchart for determining the storage area of ​​a submodule sample provided in an embodiment of the present application;

[0042] Fig.10 A schematic diagram of a correspondence between a physical width and a logical depth provided in an embodiment of the present application;

[0043] Fig.11 A schematic diagram of a correspondence between a physical height and a logical bit width provided in an embodiment of the present application;

[0044] Fig.12 A schematic diagram of an area determination function corresponding to a micro-architecture parameter of a logic area provided in an embodiment of the present application;

[0045] Fig.13 A flowchart of a chip area determination method provided in an embodiment of the present application;

[0046] Fig.14 A flowchart of a micro-architecture parameter determination process provided in an embodiment of the present application;

[0047] Fig.15 A schematic diagram of a process for determining micro-architecture parameters provided in an embodiment of the present application;

[0048] Fig.16 A schematic diagram of the effect of a chip area determination method provided in an embodiment of the present application;

[0049] Fig.17A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0050] Fig.18 A schematic diagram of the structure of another electronic device provided in an embodiment of the present application;

[0051] Fig.19 A schematic diagram of the structure of another electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0052] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in detail below in conjunction with the accompanying drawings. The terms used in the implementation method section of the present application are only used to explain the specific embodiments of the present application, and are not intended to limit the present application.

[0053] Before introducing the specific solutions provided by the embodiments of the present application, some terms in the present application are explained to facilitate understanding by those skilled in the art, and the terms in the present application are not limited.

[0054] (1) Submodule in a chip: refers to a functional module contained in a chip, such as the instruction extraction module, instruction decoding module, arithmetic logic module, floating point module, cache module, etc. in a processor chip. The chip is generally a regular rectangle, and the area occupied by the submodule on the chip layout is generally irregular.

[0055] (2) Microarchitecture parameters: These are the circuit parameters of the processor chip of a computer device, which can include dozens of microarchitecture parameters such as cache configuration parameters and decoding unit width. Usually a chip can include multiple submodules, and each submodule corresponds to one or more microarchitecture parameters. During the chip design stage, the configuration of the corresponding submodule can be achieved by modifying the microarchitecture parameters. Different configurations will affect the area occupied by the submodule on the chip layout.

[0056] (3) Standard logic unit: a logic unit that can realize the basic functions of a circuit, such as AND gates, NAND gates and other basic units. Standard logic units are stored in a standard cell library, which can usually store hundreds of standard logic units. During the circuit design and generation process, EDA tools can convert the version code of the circuit into a chip layout based on standard logic units. Among them, EDA tools are a type of circuit design software.

[0057] In the embodiments of the present application, "multiple" refers to two or more than two. In view of this, in the embodiments of the present application, "multiple" can also be understood as "at least two". "At least one" can be understood as one or more, for example, one, two or more. For example, including at least one means including one, two or more, and there is no restriction on which ones are included. For example, including at least one of A, B and C, then A, B, C, A and B, A and C, B and C, or A and B and C may be included. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / ", unless otherwise specified, generally indicates that the previously associated objects are in an "or" relationship.

[0058] Unless otherwise specified, the ordinal numbers such as "first" and "second" mentioned in the embodiments of the present application are used to distinguish multiple objects and are not used to limit the order, timing, priority or importance of the multiple objects.

[0059] In order to produce qualified or better chip products, it is usually necessary to predict the chip area during the chip design stage. In order to improve the accuracy of the prediction results of the chip area, the embodiment of the present application provides a chip area determination method and an area model construction method. The chip area determination method and the area model construction method can be performed by an electronic device. The electronic device can be but is not limited to a computing device such as a server, a personal computer, a portable computer, a smart terminal, a desktop or an all-in-one machine. The chip area determination method and the area model construction method can be performed by the same electronic device or by two different electronic devices.

[0060] The area model is an area model used in the execution process of the chip area determination method, and the area model includes a correspondence between multiple sets of micro-architecture parameters and sub-module area functions. For ease of understanding, the area model construction method is first introduced below. Figure 1 A flow chart of a method for constructing an area model is shown. Figure 1 As shown, the method may include the following steps:

[0061] S101, an electronic device obtains a plurality of chip samples, and determines a plurality of sub-module samples included in the plurality of chip samples.

[0062] Each chip sample among the multiple chip samples may include at least one sub-module sample.

[0063] In some embodiments, the electronic device can generate multiple versions of code with different configurations based on the code bin of the chip, and each version of the code can be used to generate a chip containing several sub-modules. Then, the electronic device performs (design compiler graphical, DCG) synthesis and layout and routing on each version of the code to obtain multiple chip sample layouts. During the DCG synthesis process, partial physical implementation of the chip is considered. Each chip sample layout includes at least one sub-module, and the sub-modules included in different chip sample layouts may be different.

[0064] In the embodiment of the present application, each chip sample layout can be used as a chip sample, and each chip sample can include at least one submodule sample. Therefore, multiple chip samples can include multiple submodule samples, and each submodule sample has corresponding microarchitecture parameters. Among them, some submodule samples can only include logic areas, such as Figure 2 The submodule sample a shown in FIG. 1 ; another submodule sample may include a logic part and a memory part, such as Figure 3 The submodule sample shown in b.

[0065] S102: The electronic device determines the logical area areas of a plurality of sub-module samples.

[0066] The electronic device can determine the area of ​​the logic area of ​​each submodule sample among the multiple submodule samples by an integration method or a coloring method. Since each submodule sample occupies an irregular graphic area on the chip layout, the area of ​​the logic area of ​​the submodule sample is equivalent to the area of ​​the predicted irregular area.

[0067] For example, in some embodiments, the electronic device may determine the logical area of ​​each submodule sample by an integral method. The logical area of ​​each submodule sample in the plurality of submodule samples may include a plurality of tracks. Submodule sample a is used as an example for illustration, and submodule sample a may be understood as any submodule sample in the plurality of submodule samples. Figure 4 shows a portion of the logical area of ​​submodule sample a, Figure 4 Each row in the diagram represents a track in the logical area. Figure 4 It can be seen from FIG that the logic area of ​​the submodule sample a includes multiple tracks. The process of determining the area of ​​the logic area of ​​the submodule sample a by the integral method may include the following steps s1 to s2:

[0068] In step s1, the electronic device determines the effective area covered by the standard logic unit contained in each track in the submodule sample a.

[0069] The logic area of ​​submodule sample a includes multiple standard logic cells (std.cell). Some standard logic cells may occupy only one track, while other standard logic cells may occupy multiple tracks. If there are standard logic cells to be processed that occupy multiple tracks in the logic area of ​​submodule sample a, the standard logic cells to be processed may be cut so that each of the obtained standard logic cells occupies one track.

[0070] Taking the first track as an example, the first track can be understood as any track in the submodule sample a. The electronic device can determine the effective area covered by the standard logic unit included in the first track through the following steps S1-1 to S1-2:

[0071] S1-1: According to a set expansion coefficient, the standard logic unit included in the first track is expanded laterally or in abscissa to obtain at least one rectangular block.

[0072] The expansion coefficient is determined based on experimental data and is used to connect the standard logic cells contained in the first track into a rectangular block. Figure 5 As shown, when the expansion coefficient is 2, a standard logic unit expands laterally and its length becomes twice as long as before.

[0073] S1-2: After obtaining at least one rectangular block, the electronic device may determine the end coordinates of each rectangular block in the at least one rectangular block, and determine the effective area of ​​the first track according to the end coordinates of each rectangular block.

[0074] Exemplarily, for any one of the at least one rectangular blocks of the first track, the rectangular block is used as the first rectangular block, and the horizontal coordinate expansion values ​​of the standard logic units corresponding to the two ends of the first rectangular block can be determined respectively, and the end coordinates of the first rectangular block are determined according to the horizontal coordinate expansion values ​​of the standard logic units corresponding to the two ends of the first rectangular block and the horizontal coordinate values ​​of the two ends of the first rectangular block. After determining the end coordinates of each rectangular block in the at least one rectangular block, the electronic device can determine the effective area of ​​the first track according to the end coordinates of each rectangular block.

[0075] For example, Figure 6 As shown, in most cases, after the standard logic cells contained in the first track are expanded laterally, all gaps inside the first track can be covered, so that the originally separated rectangular blocks of standard logic cells in the first track become a continuous rectangular block, that is, the first track contains a rectangular block.

[0076] If the first track contains a rectangular block, such as Figure 6As shown, the first track only includes a rectangular block R1, and the rectangular block R1 has a left end and a right end. The left end of the rectangular block R1 corresponds to the standard logic unit u1, and the right end of the rectangular block R1 corresponds to the standard logic unit u2. According to the original length of the standard logic unit u1 and the set expansion coefficient, the horizontal coordinate expansion value of the standard logic unit u1 can be determined. For example, assuming that the original length of the standard logic unit u1 is 4 unit lengths and the set expansion coefficient is 1.5, the length of the standard logic unit u1 after expansion is 6 unit lengths, and the length of the standard logic unit u1 increases by 2 unit lengths. It can be determined that the left end of the standard logic unit u1 extends to the left by 1 unit length, and the right end of the standard logic unit u1 extends to the right by 1 unit length. Therefore, the horizontal coordinate expansion value of the standard logic unit u1 is 4*(1.5-1) / 2=1. Similarly, according to the original length of the standard logic unit u2 and the set expansion coefficient, the horizontal coordinate expansion value of the standard logic unit u2 can be determined.

[0077] The electronic device can determine the end coordinates of the rectangular block R1 according to the horizontal coordinate expansion values ​​of the standard logic units corresponding to the two ends of the rectangular block R1 and the horizontal coordinate values ​​of the two ends of the rectangular block R1. For example, assuming that the horizontal coordinate value of the left end of the rectangular block R1 is 2, the horizontal coordinate value of the right end of the rectangular block R1 is 24, the horizontal coordinate expansion value of the standard logic unit u1 corresponding to the left end of the rectangular block R1 is 1, and the horizontal coordinate expansion value of the standard logic unit u2 corresponding to the right end of the rectangular block R1 is 1.5, it can be determined that the coordinates of the left end of the rectangular block R1 are 2+1=3, and the coordinates of the right end of the rectangular block R1 are 24-1.5=22.5. According to the coordinates of the two ends of the rectangular block R1, the length of the rectangular block R1 can be determined to be 22.5-3=19.5. Assuming that the width of each track is fixed and is 1, since the first track only contains the rectangular block R1, the effective area of ​​the first track is 19.5 unit areas.

[0078] In some cases, such as Figure 7 As shown, if the distance between two adjacent standard logic cells in the first track is very far, two or more rectangular blocks may be obtained after the standard logic cells contained in the first track are expanded laterally.

[0079] If the first track contains two rectangular blocks, such as Figure 7As shown, the two rectangular blocks are R2 and R3. The left end of the rectangular block R2 corresponds to the standard logic unit u3, and the right end of the rectangular block R2 corresponds to the standard logic unit u4. The electronic device can determine the horizontal coordinate expansion value of the standard logic unit u3 according to the original length of the standard logic unit u3 and the set expansion coefficient, and can determine the horizontal coordinate expansion value of the standard logic unit u4 according to the original length of the standard logic unit u4 and the set expansion coefficient. According to the horizontal coordinate expansion values ​​of the corresponding standard logic units at the two ends of the rectangular block R2 and the horizontal coordinate values ​​of the two ends of the rectangular block R2, the end coordinates of the rectangular block R2 can be determined. The left end and the right end of the rectangular block R3 both correspond to the standard logic unit u5, and the horizontal coordinate expansion value of the standard logic unit u5 can be determined according to the original length of the standard logic unit u5 and the set expansion coefficient. According to the horizontal coordinate expansion value of the standard logic unit u5 and the horizontal coordinate values ​​of the two ends of the rectangular block R3, the end coordinates of the rectangular block R3 can be determined. It can also be said that the end coordinates of the rectangular block R3 are the coordinate values ​​of the end coordinates of the standard logic unit u5.

[0080] The electronic device can determine the area of ​​rectangular block R2 based on the coordinates of the two ends of rectangular block R2. For example, the coordinates of the two ends of R2 are 1 and 15 respectively, and the width of the first track is 1, then the area of ​​rectangular block R2 is 14 unit areas. The area of ​​rectangular block R3 can be determined based on the coordinates of the two ends of rectangular block R3. For example, the coordinates of the two ends of R3 are 30 and 34 respectively, and the width of the first track is 1, then the area of ​​rectangular block R3 is 4 unit areas. By adding the areas of rectangular blocks R2 and R3, it can be obtained that the effective area of ​​the first track is 14+4=18 unit areas.

[0081] It can be seen that if the first track contains multiple rectangular blocks, the electronic device can calculate the area of ​​each rectangular block separately according to the end coordinates of each rectangular block, and take the sum of the areas of each rectangular block in the first track as the effective area of ​​the first track.

[0082] Through the above step s1, the electronic device can determine the effective area of ​​each track in the submodule sample a. After executing step s1, the electronic device can execute step s2.

[0083] Step s2: The electronic device uses the sum of the effective areas of the multiple tracks as the logic area of ​​the submodule sample a.

[0084] In the process of executing step s2, the electronic device scans the vertical coordinates covered by the standard logic unit in the logic area of ​​the submodule sample a line by line, and accumulates the effective areas of multiple tracks to obtain the logic area area of ​​the submodule sample a. The above integration method is performed on multiple submodule samples respectively to obtain the logic area area of ​​each submodule sample.

[0085] In other embodiments, the electronic device may also determine the logical region area of ​​each submodule sample by a coloring method. Similarly, continuing to use submodule sample a as an example for explanation, submodule sample a may be understood as any submodule sample among a plurality of submodule samples. The process may include the following steps: the electronic device colors the standard logical unit contained in the logical region of submodule sample a, and determines the logical region area in submodule sample a according to the ratio of the number of pixels of the colored part in submodule sample a to the total number of pixels of the chip sample to which submodule sample a belongs, and the area of ​​the chip sample to which submodule sample a belongs.

[0086] For example, the electronic device can color the submodule sample a in the selected chip sample through an EDA tool, and the EDA tool can automatically identify the standard logic units contained in the logic area of ​​the specified submodule sample, and only color or dye the standard logic units, and do not color other parts, such as Figure 8 As shown. The electronic device saves the selected chip sample after coloring. In the selected chip sample after coloring, the pixel values ​​of each pixel point of the standard logic unit contained in the logic area of ​​the submodule sample a are the same, and the pixel values ​​of the standard logic unit contained in the logic area of ​​the submodule sample a are different from those of each pixel point in other areas of the selected chip sample. Based on the pixel value of each pixel point in the selected chip sample, the electronic device can respectively determine the total number of pixels P_core of the selected chip sample and the number of pixels P_module of the colored part in the submodule sample a. The area of ​​the selected chip sample is known, and the area of ​​the logic area in the submodule sample a can be determined according to the ratio of P_module to P_core. For example, assuming that the area of ​​the selected chip sample is C, the area of ​​the logic area in the submodule sample a is C*P_module / P_core.

[0087] By performing the above coloring process on a plurality of submodule samples respectively, the electronic device can obtain the logical region area of ​​each submodule sample.

[0088] The embodiments of the present application provide two methods for extracting the area of ​​the logic region, namely, an integration method based on the idea of ​​integration and a coloring method based on image processing. These two methods can accurately predict the area of ​​the logic region of the sub-module in the chip and help to build a high-precision area model.

[0089] S103: The electronic device determines a storage area of ​​at least one target submodule sample.

[0090] Among them, at least one target submodule sample is a submodule sample including a storage area among the multiple submodule samples.

[0091] Taking submodule sample b as an example, submodule sample b can be understood as any target submodule sample in at least one target submodule sample. For the storage area of ​​submodule sample b, the electronic device can execute the following Fig. 9 The following steps are shown:

[0092] S901, the electronic device obtains micro-architecture parameters of the storage area of ​​sub-module sample b.

[0093] S902, the electronic device determines a target logical depth and a target logical bit width corresponding to the micro-architecture parameters of the storage area according to a correspondence relationship between a plurality of pre-stored micro-architecture parameters and the logical depth and logical bit width of the storage area.

[0094] Among them, the correspondence between multiple microarchitecture parameters and the logic depth and logic bit width of the storage area is pre-established by chip design engineers based on actual measured data and can be stored in a table. The logic depth and logic bit width can be expressed as the capacity of the storage area, as shown in Table 1. Among them, DSE parameter name is the name of different microarchitecture parameters, Value is the parameter value of different microarchitecture parameters, Macro number is the number of memories, Density is the density type of the storage area, Mux is the composite multiplexer type of the storage area, and Capacity is the capacity of the storage area, which is represented by the product of the logic depth (depth) and the logic bit width (width).

[0095] Table 1

[0096]

[0097] It can be seen from Table 1 that different parameter values ​​of the microarchitecture parameters will not affect the density, memory quantity and multiplexer type of the storage area, but will affect the logic depth and logic bit width of the storage area. After obtaining the microarchitecture parameters of the storage area of ​​submodule sample b, the electronic device can determine the target logic depth and target logic bit width corresponding to the microarchitecture parameters of the storage area by querying Table 1.

[0098] S903, the electronic device determines a target physical width corresponding to the target logical depth according to a pre-stored correspondence between the logical depth and the physical width, and determines a target physical height corresponding to the target logical width according to a pre-stored correspondence between the logical bit width and the physical height.

[0099] The pre-stored corresponding relationship between the logic depth and the physical width and the pre-stored corresponding relationship between the logic bit width and the physical height are determined according to the information in the process library file lef.

[0100] In some embodiments, the electronic device can generate a lef description file of memory of different capacities through a memory compiler according to different capacity information of the storage area, obtain the physical size of the storage area of ​​different capacities, and then obtain the corresponding relationship between the capacity information and the physical size of the storage area. Among them, the capacity information of the storage area includes the logical depth and logical bit width of the storage area, and the physical size of the storage area includes the physical width and physical height of the storage area.

[0101] In other implementations, the staff can determine the corresponding relationship between the capacity information and the physical size of the storage area based on experimental data, and the electronic device can receive and save the corresponding relationship between the logical depth and physical width of the storage area, and the corresponding relationship between the logical bit width and physical height of the storage area input by the staff. Fig.10 As shown in the figure, the corresponding relationship between the logical bit width and the physical height of a storage area is as follows Fig.11 shown.

[0102] The electronic device can determine the target physical width corresponding to the target logical depth according to the pre-stored correspondence between the logical depth and the physical width, and can determine the target physical height corresponding to the target logical width according to the pre-stored correspondence between the logical bit width and the physical height.

[0103] S904: The electronic device uses the product of the target physical width and the target physical height as the storage area of ​​the submodule sample b.

[0104] Through the above process, after obtaining the micro-architecture parameters of the storage area of ​​submodule sample b, the electronic device can determine the target physical width and target physical height of submodule sample b through a table lookup process. The product of the target physical width and the target physical height is used as the storage area area of ​​submodule sample b.

[0105] By performing the above process for a plurality of submodule samples respectively, the electronic device can obtain the storage area of ​​each submodule sample.

[0106] The embodiment of the present application provides a storage area area modeling method based on a secondary lookup table, which can accurately predict the area of ​​the storage area of ​​a sub-module of a chip, improve the efficiency of storage area area prediction, and avoid frequent calls to the memory compiler.

[0107] Optionally, the embodiments of the present application do not limit the execution order of S102 and S103. For example, in some embodiments, the order of the above steps S102 and S103 can be interchanged; or the electronic device can execute the two steps at the same time.

[0108] S104, the electronic device obtains micro-architecture parameters of multiple sub-module samples, and constructs an area model according to the logic area areas and micro-architecture parameters of the multiple sub-module samples and the storage area area of ​​at least one target sub-module sample.

[0109] For the first type of sub-module samples that do not include storage areas in multiple sub-module samples, the electronic device can determine the correspondence between at least one set of micro-architecture parameters and sub-module area functions based on the logic area of ​​the first type of sub-module samples and the micro-architecture parameters of the first type of sub-module samples.

[0110] Exemplarily, for the first group of submodule samples with microarchitecture parameters of the same name, the electronic device can fit the microarchitecture parameters of the first group of submodule samples and the logical area area of ​​the first group of submodule samples to obtain a corresponding relationship between a set of microarchitecture parameters and submodule area functions. Wherein, the first group of submodule samples is any group of submodule samples with microarchitecture parameters of the same name in the first type of submodule samples, that is, the first group of submodule samples can include multiple submodule samples, and these submodule samples have microarchitecture parameters of the same name, but the values ​​of microarchitecture parameters of different submodule samples can be different. For example, submodule sample c and submodule sample e can both have microarchitecture parameter x1, but the value of microarchitecture parameter x1 of submodule sample c can be different from the value of microarchitecture parameter x1 of submodule sample e.

[0111] In some embodiments, for the first group of submodule samples, the electronic device may perform the following operations: determine a set of weights corresponding to microarchitecture parameters according to the logical area area of ​​each first-category submodule sample in the first group of submodule samples; wherein the set of microarchitecture parameters is the microarchitecture parameters of the logical area of ​​the first group of submodule samples. According to the weights corresponding to the set of microarchitecture parameters and the set of microarchitecture parameters, a submodule area function corresponding to a set of microarchitecture parameters may be determined. The submodule area function is a linear function, and the weight may also be referred to as a coefficient of the microarchitecture parameter.

[0112] For example, assuming that the micro-architecture parameter of the first group of sub-module samples is x1, through the above process, the electronic device can determine that the weight corresponding to the micro-architecture parameter x1 of the first group of sub-module samples is k1, and the sub-module area function corresponding to the micro-architecture parameter of the first group of sub-module samples can be obtained as f(x1)=k1*x1+b1. Among them, b1 is a set correction value, and the value of b1 can be 0 or not. Exemplarily, a sub-module area function can be expressed as Fig.12 The linear function shown, where k1=1415.4 and b1=0.

[0113] By repeating the above process, the electronic device can obtain sub-module area functions corresponding to multiple groups of micro-architecture parameters based on the first type of sub-module samples.

[0114] For the second type of submodule samples including the storage area in the plurality of submodule samples, the electronic device may determine the correspondence between at least one set of microarchitecture parameters and the submodule area function according to the storage area area and the logic area area of ​​the second type of submodule samples and the microarchitecture parameters of the second type of submodule samples. The second type of submodule samples includes the at least one target submodule sample mentioned above.

[0115] Exemplarily, for the second group of submodule samples with the same microarchitecture parameters, the electronic device can fit the microarchitecture parameters of the second group of submodule samples and the logic area area of ​​the second group of submodule samples, and fit the microarchitecture parameters of the second group of submodule samples and the storage area area of ​​the second group of submodule samples to obtain a set of corresponding relationships between microarchitecture parameters and submodule area functions. The second group of submodule samples is any group of submodule samples with microarchitecture parameters of the same name in the second type of submodule samples, that is, the second group of submodule samples may include multiple submodule samples, and these submodule samples have microarchitecture parameters of the same name, but the values ​​of microarchitecture parameters of different submodule samples may be different.

[0116] In some embodiments, for the second group of sub-module samples, the electronic device may perform the following operations: determine the weight corresponding to the micro-architecture parameter of the logic area according to the logic area area of ​​each second-category sub-module sample in the second group of sub-module samples; wherein the micro-architecture parameter of the logic area is the micro-architecture parameter of the logic area of ​​the second group of sub-module samples. Determine the function corresponding to the micro-architecture parameter of the storage area according to the storage area area of ​​each second-category sub-module sample in the second group of sub-module samples; wherein the micro-architecture parameter of the storage area is the micro-architecture parameter of the storage area of ​​the second group of sub-module samples. Determine a set of sub-module area functions corresponding to the micro-architecture parameters according to the weight corresponding to the micro-architecture parameter of the logic area and the micro-architecture parameter of the logic area, and the function corresponding to the micro-architecture parameter of the storage area; wherein the set of micro-architecture parameters includes the micro-architecture parameter of the logic area and the micro-architecture parameter of the storage area.

[0117] For example, assuming that the micro-architecture parameter of the second group of sub-module samples is x2, that is, the micro-architecture parameter of the logic area and the micro-architecture parameter of the storage area of ​​the second group of sub-module samples are both x2, through the above process, the electronic device can determine that the weight corresponding to the micro-architecture parameter x2 of the logic area of ​​the second group of sub-module samples is k2, and the function corresponding to the micro-architecture parameter x2 of the storage area of ​​the second group of sub-module samples is LUT(x2), and LUT() represents a table lookup operation. According to the weight corresponding to the micro-architecture parameter x2 of the logic area of ​​the second group of sub-module samples is k2, and the function corresponding to the micro-architecture parameter x2 of the storage area of ​​the second group of sub-module samples, the sub-module area function corresponding to the micro-architecture parameter of the second group of sub-module samples can be obtained as f(x2)=k2*x2+b2+LUT(x2). Among them, b2 is a set correction value, and the value of b2 can be 0 or not.

[0118] By repeating the above process, the electronic device can also obtain sub-module area functions corresponding to multiple groups of micro-architecture parameters based on the second type of sub-module samples.

[0119] The electronic device saves the sub-module area functions corresponding to the multiple groups of micro-architecture parameters obtained according to the first type of sub-module samples and the second type of sub-module samples into the area model.

[0120] The embodiment of the present application can accurately predict the area of ​​the chip without relying on the developer's familiarity with the micro-architecture and engineering experience, which can reduce human errors. The industry currently does not have a method for determining the area of ​​the logic area (floorplan) of a submodule. The embodiment of the present application proposes two area extraction methods for the first time, and finally constructs a high-precision area model for predicting the chip area.

[0121] In actual application scenarios, when it is necessary to determine the area information of the target chip to be produced, the electronic device can perform Fig.13 The process shown may include the following steps:

[0122] S1301, the electronic device obtains a micro-architecture parameter table to be tested of a target chip to be produced.

[0123] The target chip includes multiple sub-modules, and the micro-architecture parameter table to be tested includes the micro-architecture parameter to be tested of each sub-module in the multiple sub-modules.

[0124] S1302, the electronic device determines the area of ​​each sub-module in the target chip according to the micro-architecture parameters to be tested of each sub-module and a pre-built area model.

[0125] The area model includes the correspondence between multiple groups of micro-architecture parameters and sub-module area functions.

[0126] For each submodule, the electronic device can perform the following operations respectively: in the area model, find the target submodule area function corresponding to the micro-architecture parameter to be tested of the submodule; and determine the area of ​​the submodule according to the target submodule area function.

[0127] S1303: The electronic device determines area information of the target chip according to the area of ​​each submodule.

[0128] The area information of the target chip may include the area of ​​each submodule and may also include the overall area of ​​the target chip. The overall area of ​​the target chip is the sum of the areas of each submodule.

[0129] In the embodiments of the present application, the area model can be used to quickly predict the area during different types of chip design processes and efficiently evaluate the impact of microarchitecture parameters on chip area, thereby reducing the development workload of back-end engineers.

[0130] In a specific embodiment, the electronic device can adjust the micro-architecture parameters of the target chip according to the predicted area information of the target chip to optimize the target chip. Fig.14 and Fig.15 As shown, the process may include the following steps:

[0131] S1401, the electronic device obtains an initial micro-architecture parameter table of a target chip to be produced, and uses the initial micro-architecture parameter table as a micro-architecture parameter table to be tested.

[0132] The target chip includes multiple sub-modules, and the initial micro-architecture parameter table includes the micro-architecture parameters to be tested that are initially configured for each of the multiple sub-modules.

[0133] S1402, the electronic device determines PPA information of the target chip according to the micro-architecture parameter table to be tested of the target chip.

[0134] The PPA information includes power information, performance information, and area information. That is, according to the micro-architecture parameter table of the target chip to be tested, the power consumption information, performance information, and area information of the target chip are determined respectively. For example, Fig.15 As shown, the electronic device can determine the power consumption information of the target chip through the power consumption model, can determine the performance information of the target chip through the performance model, and can determine the area information of the target chip through the above-mentioned area model.

[0135] S1403, the electronic device determines whether the PPA information of the target chip meets the set conditions; if so, execute step S1405, if not, execute step S1404.

[0136] Exemplarily, the electronic device may compare the power consumption information of the target chip with a preset target power consumption value to determine whether the power consumption meets the standard, compare the performance information of the target chip with a preset target performance value to determine whether the performance meets the standard, and compare the area information of the target chip with a preset target area value to determine whether the performance meets the standard. If the power consumption information, performance information, and area information of the target chip all meet the standard, it is determined that the PPA information of the target chip meets the set condition. If at least one of the power consumption information, performance information, and area information of the target chip does not meet the standard, it is determined that the PPA information of the target chip does not meet the set condition.

[0137] S1404, the electronic device re-determines the micro-architecture parameters of the target chip, and generates a new micro-architecture parameter table to be tested according to the re-determined micro-architecture parameters. Return to step S1402.

[0138] If the PPA information of the target chip does not meet the set conditions, the electronic device can search for new micro-architecture parameters through the DSE algorithm, and generate a new micro-architecture parameter table to be tested based on the re-determined micro-architecture parameters, and redetermine the area information, performance information and power consumption information of the target chip based on the new micro-architecture parameter table to be tested.

[0139] S1405, the electronic device uses the finally determined target chip's micro-architecture parameter table to be tested as the target micro-architecture parameter table of the target chip, and outputs the target micro-architecture parameter table.

[0140] The electronic device repeatedly executes steps S1402 to S1404 until the area information, performance information or power consumption information of the target chip finally determined meets the set conditions, and uses the micro-architecture parameter table of the target chip to be tested as the target micro-architecture parameter table of the target chip, and outputs the target micro-architecture parameter table, which is used in the production process of the target chip. Exemplarily, after the target micro-architecture parameter table is output, the corresponding chip layout code can be generated according to the target micro-architecture parameter table, and the back-end DCG synthesis and layout and routing steps are completed, so that the chip manufacturer can finally produce the target chip that meets the PPA requirements.

[0141] In a specific implementation process, the constructed data set includes 55 versions of configurations with different microarchitecture parameters. For each version of the configuration, DCG synthesis and back-end layout and routing are used to obtain the actual area of ​​the chip sample. Seven configurations are selected from the 55 configurations as sample data for training. Figure 1 The area model construction method shown in the figure models the logic area and the storage area respectively, and the obtained area model is verified on the remaining 48-board configurations, that is, the area model is used to predict the area of ​​the remaining 48-board configurations respectively, and the area prediction results are obtained. The actual area of ​​the chip sample is verified with the predicted result, and the verification result is as follows Fig.16 As shown, Fig.16 The horizontal axis corresponds to the actual area of ​​the chip sample, and the vertical axis is the predicted result of the area model. Fig.16 The slash in the figure indicates that the actual area is exactly equal to the predicted area. Fig.16 The closer each point is to the diagonal line, the more accurate the prediction result is. It has been verified that the average error of the area model on the 48-version configuration is 1.39%.

[0142] The area model is applied to optimize the microarchitecture parameters of the chip. In the search iteration of the DSE algorithm, the comprehensive performance gain of a target configuration is 2.65%. The area model predicts an area gain of 4.97%, and the actual area gain is 3.15%. The purpose of saving chip area on the basis of performance improvement is achieved, and the overall area efficiency is improved by 5.98%.

[0143] Based on the same technical concept as the above embodiments, an electronic device is also provided in the embodiments of the present application. The electronic device can be used to implement the functions of any one of the methods provided in the above embodiments, and thus can achieve the beneficial effects of the above method embodiments.

[0144] In some embodiments, Fig.17 As shown, the electronic device 1700 may include a parameter acquisition module 1701 and an area determination module 1702. The electronic device 1700 may be used to implement the functions of the above chip area determination method embodiment, and thus may achieve the beneficial effects of the above chip area determination method embodiment.

[0145] Among them, the parameter acquisition module 1701 can be used to obtain the micro-architecture parameter table to be tested of the target chip to be produced. Among them, the target chip includes multiple sub-modules, and the micro-architecture parameter table to be tested includes the micro-architecture parameters to be tested of each sub-module in the multiple sub-modules. The area determination module 1702 can be used to determine the area of ​​each sub-module in the target chip according to the micro-architecture parameters to be tested of each sub-module and the pre-built area model, and determine the area information of the target chip according to the area of ​​each sub-module. The area model includes the correspondence between multiple groups of micro-architecture parameters and sub-module area functions.

[0146] In some implementations, the area determination module 1702 may be specifically used to: for each sub-module, perform the following operations respectively: in the area model, search for a target sub-module area function corresponding to the micro-architecture parameter to be tested of the sub-module, and determine the area of ​​the sub-module according to the target sub-module area function.

[0147] In some embodiments, the electronic device 1700 may further include a parameter adjustment module, which may be used to: determine the performance information and power consumption information of the target chip respectively according to the micro-architecture parameter table to be tested of the target chip; determine whether the area information, performance information or power consumption information of the determined target chip meets the set conditions; if the area information, performance information or power consumption information of the target chip does not meet the set conditions, redetermine the micro-architecture parameters of the target chip, and generate a new micro-architecture parameter table to be tested according to the redetermined micro-architecture parameters, and redetermine the area information, performance information and power consumption information of the target chip according to the new micro-architecture parameter table to be tested; repeat the above steps until the area information, performance information or power consumption information of the target chip finally determined meets the set conditions; use the micro-architecture parameter table to be tested of the target chip finally determined as the target micro-architecture parameter table of the target chip; output the target micro-architecture parameter table; the target micro-architecture parameter table is used in the production process of the target chip.

[0148] In other embodiments, Fig.18 As shown, the electronic device 1800 may include a sample acquisition module 1801 and a model construction module 1802. The electronic device 1800 may be used to implement the functions of the above area model construction method embodiment, and thus may achieve the beneficial effects of the above area model construction method embodiment.

[0149] Among them, the sample acquisition module 1801 can be used to obtain multiple chip samples and determine the multiple sub-module samples contained in the multiple chip samples. Among them, each chip sample contains at least one sub-module sample. The model construction module 1802 can be used to determine the logic area area and micro-architecture parameters of multiple sub-module samples, and determine the storage area area of ​​at least one target sub-module sample; wherein at least one target sub-module sample is a sub-module sample containing a storage area among the multiple sub-module samples; according to the logic area area and micro-architecture parameters of the multiple sub-module samples, and the storage area area of ​​at least one target sub-module sample, an area model is constructed, and the area model includes the correspondence between multiple groups of micro-architecture parameters and sub-module areas.

[0150] In some embodiments, the model building module 1802 can be specifically used to: perform the following operations for the logic area of ​​the first sub-module sample: determine the effective area covered by the standard logic unit contained in each track in the first sub-module sample respectively; take the sum of the effective areas of multiple tracks as the logic area area in the first sub-module sample; wherein the first sub-module sample is any one of the multiple sub-module samples.

[0151] In some embodiments, the model building module 1802 can be specifically used to: if there are standard logic units to be processed that occupy multiple tracks in the logic area, the standard logic units to be processed are cut, and each of the cut standard logic units occupies a track; for the first track, the following operations are performed: according to the set expansion coefficient, the standard logic units contained in the first track are expanded laterally to obtain at least one rectangular block; the end coordinates of each rectangular block in the at least one rectangular block are determined, and according to the end coordinates of each rectangular block, the effective area of ​​the first track is determined; wherein the first track is any track in the first submodule sample.

[0152] In some embodiments, the model building module 1802 can be specifically used to: perform the following operations on the first rectangular block obtained after expansion: respectively determine the horizontal coordinate expansion values ​​of the standard logic units corresponding to the two ends of the first rectangular block; determine the end coordinates of the first rectangular block according to the horizontal coordinate expansion values ​​of the standard logic units corresponding to the two ends of the first rectangular block and the horizontal coordinate values ​​of the two ends of the first rectangular block; wherein the first rectangular block is any rectangular block among at least one rectangular block.

[0153] In some embodiments, the model building module 1802 can be specifically used to: perform the following operations on the logical area of ​​the second sub-module sample: color the standard logical units contained in the logical area of ​​the second sub-module sample; determine the area of ​​the logical area in the second sub-module sample based on the ratio of the number of pixels of the colored part in the second sub-module sample to the total number of pixels of the chip sample to which the second sub-module sample belongs, and the area of ​​the chip sample to which the second sub-module sample belongs; wherein the second sub-module sample is any one of the multiple sub-module samples.

[0154] In some implementations, the model building module 1802 may be specifically used to: for the storage area of ​​the third submodule sample, perform the following operations: obtain the micro-architecture parameters of the storage area of ​​the third submodule sample; determine the target logical depth and target logical bit width corresponding to the micro-architecture parameters of the storage area according to the correspondence between the pre-stored plurality of micro-architecture parameters and the logical depth and logical bit width of the storage area;

[0155] According to the correspondence between the pre-stored logical depth and the physical width, the target physical width corresponding to the target logical depth is determined, and according to the correspondence between the pre-stored logical bit width and the physical height, the target physical height corresponding to the target logical bit width is determined; the product of the target physical width and the target physical height is used as the storage area of ​​the third sub-module sample; wherein the third sub-module sample is any one of at least one target sub-module sample.

[0156] In some embodiments, the model building module 1802 can be specifically used to: for a first type of sub-module samples that do not include a storage area among multiple sub-module samples, determine the correspondence between at least one set of micro-architecture parameters and the sub-module area function based on the logic area area of ​​the first type of sub-module samples and the micro-architecture parameters of the first type of sub-module samples; for a second type of sub-module samples that include a storage area among multiple sub-module samples, determine the correspondence between at least one set of micro-architecture parameters and the sub-module area function based on the storage area area and the logic area of ​​the second type of sub-module samples and the micro-architecture parameters of the second type of sub-module samples; the second type of sub-module samples include at least one target sub-module sample.

[0157] In some embodiments, the model building module 1802 can be specifically used to: perform the following operations for a first group of sub-module samples having micro-architecture parameters with the same name: determine a set of weights corresponding to micro-architecture parameters based on the logical area area of ​​each first-category sub-module sample in the first group of sub-module samples; a set of micro-architecture parameters are micro-architecture parameters of the logical area of ​​the first group of sub-module samples; determine a set of sub-module area functions corresponding to a set of micro-architecture parameters based on the weights corresponding to a set of micro-architecture parameters and a set of micro-architecture parameters; wherein the first group of sub-module samples are any group of sub-module samples having micro-architecture parameters with the same name in the first-category sub-module samples.

[0158] In some embodiments, the model building module 1802 can be specifically used to: perform the following operations for a second group of sub-module samples with micro-architecture parameters of the same name: determine the weight corresponding to the micro-architecture parameters of the logic area according to the logic area area of ​​each second-category sub-module sample in the second group of sub-module samples; the micro-architecture parameters of the logic area are the micro-architecture parameters of the logic area of ​​the second group of sub-module samples; determine the function corresponding to the micro-architecture parameters of the storage area according to the storage area area of ​​each second-category sub-module sample in the second group of sub-module samples; the micro-architecture parameters of the storage area are the micro-architecture parameters of the storage area of ​​the second group of sub-module samples; determine a group of sub-module area functions corresponding to the micro-architecture parameters according to the weight corresponding to the micro-architecture parameters of the logic area and the micro-architecture parameters of the logic area, and the function corresponding to the micro-architecture parameters of the storage area; a group of micro-architecture parameters includes the micro-architecture parameters of the logic area and the micro-architecture parameters of the storage area; wherein the second group of sub-module samples is any group of sub-module samples with micro-architecture parameters of the same name in the second category of sub-module samples.

[0159] Exemplarily, each of the above modules can be implemented by software or hardware.

[0160] In other embodiments, the structure of the electronic device 1900 may be as follows: Fig.19As shown, it includes a processor 1901 and a memory 1902 connected to the processor 1901. The processor 1901 and the memory 1902 can be interconnected via a bus, and the processor 1901 can serve as the main processor of the electronic device 1900, that is, the control core of the electronic device 1900. The bus can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. The specific connection medium between the above-mentioned processor 1901 and the memory 1902 is not limited in the embodiments of the present application.

[0161] The memory 1902 may include the above-mentioned memory, and the memory 1902 may be a volatile memory, such as a random access memory; the memory may also be a non-volatile memory, such as a read-only memory ROM, a flash memory, a hard disk drive (HDD) or a solid-state drive (SSD), or the memory 1902 is any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory 1902 may be a combination of the above-mentioned memories. The memory 1902 may be used to store software programs and modules.

[0162] The processor 1901 may include one or more processors. The processor 1901 executes various functional applications and data processing of the electronic device 1900 by running software programs and modules stored in the memory 1902, such as the chip area determination method and area model construction method provided in the embodiments of the present application.

[0163] It is to be understood that the structure illustrated in the embodiments of the present application does not constitute a specific limitation on the electronic device. In other embodiments of the present application, the electronic device may include more or fewer components than shown in the figure, or combine certain components, or split certain components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

[0164] The method steps in the embodiments of the present application can be implemented by hardware, or by a processor executing a computer program or instruction. The computer program or instruction can constitute a computer program product. The embodiment of the present application also provides a computer program product, including computer executable instructions. In one embodiment, the computer executable instructions are used to enable a computer to perform the functions in the above method embodiments.

[0165] The computer executable instructions may be stored in a computer readable storage medium. The present application also provides a computer readable storage medium, wherein the computer readable storage medium stores the executable instructions. In one embodiment, the computer executable instructions are used to enable a computer to execute the functions in the above method embodiment.

[0166] The computer-readable storage medium provided in the embodiments of the present application may be a random access memory (RAM), a flash memory, a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a register, a hard disk, a mobile hard disk, a CD-ROM, or any other form of computer-readable storage medium known in the art.

[0167] Computer executable instructions may be stored in a computer readable storage medium or transferred from one computer readable storage medium to another computer readable storage medium. For example, the computer program or instructions may be transferred from one website, computer, server or data center to another website, computer, server or data center by wired or wireless means. The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server or data center that integrates one or more available media. The available medium may be a magnetic medium, such as a floppy disk, a hard disk, or a magnetic tape; it may also be an optical medium, such as a digital video disc (DVD); it may also be a semiconductor medium, such as a solid state drive.

[0168] In each embodiment of the present application, if there is no special explanation and logical conflict, the terms and / or descriptions between different embodiments are consistent and can be referenced to each other, and the technical features in different embodiments can be combined to form new embodiments according to their inherent logical relationships. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, including a series of steps or units. Methods, systems, products or devices are not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0169] Although the present application has been described in conjunction with specific features and embodiments thereof, it is apparent that various modifications and combinations may be made thereto without departing from the spirit and scope of the present application. Accordingly, the present specification and the accompanying drawings are merely exemplary illustrations of the schemes defined by the appended claims, and are deemed to have covered any and all modifications, variations, combinations or equivalents within the scope of the present application.

[0170] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the scope of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A method for determining chip area, characterized in that: include: Obtaining a micro-architecture parameter table to be tested of a target chip to be produced; The target chip includes a plurality of sub-modules, and the micro-architecture parameter table to be tested includes the micro-architecture parameter to be tested of each sub-module in the plurality of sub-modules; Determining the area of ​​each submodule in the target chip according to the microarchitecture parameters to be tested of each submodule and a pre-built area model; The area model includes a correspondence between multiple groups of micro-architecture parameters and sub-module area functions; According to the area of ​​each submodule, the area information of the target chip is determined.

2. The method according to claim 1, characterized in that Determining the area of ​​each submodule in the target chip according to the micro-architecture parameters to be tested of each submodule and the pre-built area model includes: For each submodule, perform the following operations: In the area model, searching for a target submodule area function corresponding to the micro-architecture parameter to be measured of the submodule; The area of ​​the submodule is determined according to the target submodule area function.

3. The method according to claim 1 or 2, characterized in that: The area model is constructed in the following way: Acquire multiple chip samples, and determine multiple submodule samples included in the multiple chip samples; wherein each chip sample includes at least one submodule sample; Determine the logic area area and micro-architecture parameters of the plurality of sub-module samples, and determine the storage area area of ​​at least one target sub-module sample; wherein the at least one target sub-module sample is a sub-module sample including a storage area among the plurality of sub-module samples; The area model is constructed according to the logic area areas and micro-architecture parameters of the plurality of sub-module samples and the storage area area of ​​the at least one target sub-module sample.

4. The method according to claim 3, characterized in that: The logic area of ​​each submodule sample in the plurality of submodule samples includes a plurality of tracks; and determining the area of ​​the logic area of ​​the plurality of submodule samples includes: For the logic area of ​​the first submodule sample, perform the following operations: respectively determining the effective area covered by the standard logic unit contained in each track in the first submodule sample; Taking the sum of the effective areas of the plurality of tracks as the logical area in the first submodule sample; The first submodule sample is any one of the multiple submodule samples.

5. The method according to claim 4, characterized in that The respectively determining the effective area covered by the standard logic unit included in each track in the first submodule sample comprises: If there are standard logic units to be processed that occupy multiple tracks in the logic area, the standard logic units to be processed are cut, and each of the cut standard logic units occupies one track; For the first track, do the following: According to a set expansion coefficient, the standard logic unit contained in the first track is expanded laterally to obtain at least one rectangular block; Determine the end coordinates of each rectangular block in the at least one rectangular block, and determine the effective area of ​​the first track according to the end coordinates of each rectangular block; The first track is any track in the first submodule sample.

6. The method according to claim 5, characterized in that The step of determining the end coordinates of each rectangular block in the at least one rectangular block comprises: For the first rectangular block obtained after expansion, perform the following operations: respectively determining the horizontal coordinate expansion values ​​of the standard logic cells corresponding to the two ends of the first rectangular block; Determine the end coordinates of the first rectangular block according to the horizontal coordinate expansion values ​​of the standard logic units corresponding to the two ends of the first rectangular block and the horizontal coordinate values ​​of the two ends of the first rectangular block; The first rectangular block is any rectangular block among the at least one rectangular block.

7. The method according to claim 3, characterized in that The determining of the logical area of ​​the plurality of submodule samples comprises: For the logic area of ​​the second submodule sample, perform the following operations: Coloring the standard logic cells contained in the logic area of ​​the second submodule sample; Determine the area of ​​the logic region in the second submodule sample according to the ratio of the number of pixels of the colored part in the second submodule sample to the total number of pixels of the chip sample to which the second submodule sample belongs, and the area of ​​the chip sample to which the second submodule sample belongs; The second submodule sample is any one of the multiple submodule samples.

8. The method according to any one of claims 3 to 7, characterized in that: The determining of the storage area of ​​at least one target submodule sample comprises: For the storage area of ​​the third submodule sample, perform the following operations: Obtaining micro-architecture parameters of the storage area of ​​the third sub-module sample; Determining a target logic depth and a target logic bit width corresponding to the microarchitecture parameters of the storage area according to a correspondence relationship between a plurality of pre-stored microarchitecture parameters and the logic depth and logic bit width of the storage area; Determine the target physical width corresponding to the target logical depth according to the pre-stored correspondence between the logical depth and the physical width, and determine the target physical height corresponding to the target logical width according to the pre-stored correspondence between the logical bit width and the physical height; The product of the target physical width and the target physical height is used as the storage area of ​​the third submodule sample; The third submodule sample is any one of the at least one target submodule sample.

9. The method according to any one of claims 3 to 8, characterized in that: The constructing the area model according to the logic area areas and micro-architecture parameters of the plurality of sub-module samples and the storage area area of ​​the at least one target sub-module sample comprises: For a first type of submodule sample that does not include a storage area among the plurality of submodule samples, determining a correspondence between at least one set of microarchitecture parameters and a submodule area function according to a logic area of ​​the first type of submodule sample and a microarchitecture parameter of the first type of submodule sample; For the second type of sub-module samples including the storage area among the multiple sub-module samples, the correspondence between at least one set of micro-architecture parameters and the sub-module area function is determined according to the storage area area and the logic area area of ​​the second type of sub-module samples and the micro-architecture parameters of the second type of sub-module samples; the second type of sub-module samples includes the at least one target sub-module sample.

10. The method according to claim 9, characterized in that Determining the correspondence between at least one set of micro-architecture parameters and sub-module area functions according to the logic area of ​​the first type of sub-module samples and the micro-architecture parameters of the first type of sub-module samples includes: For the first set of submodule samples with microarchitectural parameters of the same name, the following operations are performed: Determine a weight corresponding to a set of micro-architecture parameters according to the logic area area of ​​each first-category sub-module sample in the first group of sub-module samples; the set of micro-architecture parameters is the micro-architecture parameters of the logic area of ​​the first group of sub-module samples; Determining a submodule area function corresponding to the set of microarchitecture parameters according to the weights corresponding to the set of microarchitecture parameters and the set of microarchitecture parameters; The first group of sub-module samples is any group of sub-module samples of the first type of sub-module samples having micro-architecture parameters with the same name.

11. The method according to claim 9, characterized in that Determining the correspondence between at least one set of micro-architecture parameters and sub-module area functions according to the storage area area and the logic area area of ​​the second-type sub-module samples and the micro-architecture parameters of the second-type sub-module samples includes: For the second set of submodule samples with microarchitectural parameters of the same name, the following operations are performed: Determine a weight corresponding to a micro-architecture parameter of the logic area according to the logic area area of ​​each second type of sub-module sample in the second group of sub-module samples; the micro-architecture parameter of the logic area is the micro-architecture parameter of the logic area of ​​the second group of sub-module samples; Determine a function corresponding to a micro-architecture parameter of a storage area according to the storage area area of ​​each second type of sub-module sample in the second group of sub-module samples; the micro-architecture parameter of the storage area is the micro-architecture parameter of the storage area of ​​the second group of sub-module samples; Determine a submodule area function corresponding to a set of microarchitecture parameters according to the weight corresponding to the microarchitecture parameters of the logic area and the microarchitecture parameters of the logic area, and the function corresponding to the microarchitecture parameters of the storage area; the set of microarchitecture parameters includes the microarchitecture parameters of the logic area and the microarchitecture parameters of the storage area; The second group of sub-module samples is any group of sub-module samples of the second type of sub-module samples having micro-architecture parameters with the same name.

12. The method according to any one of claims 1 to 11, characterized in that: The method further comprises: According to the micro-architecture parameter table to be tested of the target chip, respectively determining the performance information and power consumption information of the target chip; Determine whether the determined area information, performance information or power consumption information of the target chip meets the set conditions; if the area information, performance information or power consumption information of the target chip does not meet the set conditions, redetermine the micro-architecture parameters of the target chip, and generate a new micro-architecture parameter table to be tested according to the re-determined micro-architecture parameters, and redetermine the area information, performance information and power consumption information of the target chip according to the new micro-architecture parameter table to be tested; repeat the above steps until the area information, performance information or power consumption information of the target chip finally determined meets the set conditions; Using the finally determined micro-architecture parameter table to be tested of the target chip as the target micro-architecture parameter table of the target chip; Output the target micro-architecture parameter table; the target micro-architecture parameter table is used in the production process of the target chip.

13. A method for constructing an area model, characterized in that: The area model includes a correspondence between multiple groups of micro-architecture parameters and sub-module area functions; the method includes: Acquire multiple chip samples, and determine multiple submodule samples included in the multiple chip samples; wherein each chip sample includes at least one submodule sample; Determine the logic area area and micro-architecture parameters of the plurality of sub-module samples, and determine the storage area area of ​​at least one target sub-module sample; wherein the at least one target sub-module sample is a sub-module sample including a storage area among the plurality of sub-module samples; The area model is constructed according to the logic area areas and micro-architecture parameters of the plurality of sub-module samples and the storage area area of ​​the at least one target sub-module sample.

14. An electronic device, characterized in that: The method comprises a module for executing the method according to any one of claims 1 to 12, or a module for executing the method according to claim 13.

15. An electronic device, characterized in that: It comprises a processor and a memory, wherein the memory stores a computer program; the processor is used to read the computer program stored in the memory to execute the method according to any one of claims 1 to 13.

16. A computer-readable storage medium, characterized in that: Computer executable instructions are stored, and the computer executable instructions are used to enable a computer to execute the method according to any one of claims 1 to 13.

17. A computer program product, characterized in that The method comprises computer executable instructions, wherein the computer executable instructions are used to enable a computer to execute the method according to any one of claims 1 to 13.

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