Implementation method of fractional-order memristor Hopfield neural network circuit based on FPGA

Abstract

A method for implementing a fractional-order memristor Hopfield neural network circuit based on FPGA adopts the Grünwald‑Letnikov fractional-order derivative definition and short-term memory principle, and completes the FPGA circuit implementation of the fractional-order memristor Hopfield model through multi-segment linear fitting of the hyperbolic tangent function. The specific steps include the processing of fractional-order integrals and hyperbolic tangent functions, which are written in Verilog code and simulated in Xilinx ISE. This method combines the short-term memory principle with a resource-efficient fitting algorithm, can generate high-precision periodic and chaotic signals on FPGA, and has broad application prospects.

Description

Technical Field

[0001] The present invention relates to the field of nonlinear dynamics, and in particular to a method for realizing a fractional-order memristor Hopfield neural network circuit based on FPGA. Background Art

[0002] Hopfield neurons are the basic structure of Hopfield networks, which form a fully connected recursive network. Since the memristor technology was verified in 2008, memristors have quickly become a research hotspot in the field of neural networks due to their bionic memory characteristics and ability to simulate neuron synaptic functions. With the continuous deepening of memristor technology and neural network research, the research field of Hopfield neural networks based on memristors has ushered in rapid development.

[0003] According to the definition of fractional differential, numerical integration usually relies on approximate methods. At present, several common methods for FPGA to implement numerical calculation of fractional-order systems include prediction-correction algorithm, time-domain frequency-domain conversion method and Adomian algorithm. Time-frequency domain conversion technology usually produces large calculation errors and is not very accurate; in contrast, the Adomian decomposition method has advantages in calculation accuracy. However, the calculation is complex and consumes a lot of resources. Therefore, based on the principle of short-term memory, the calculation accuracy and resource consumption can be better balanced. FPGA technology can implement complex functions such as tanh and sinh through table lookup method, fitting function method and Cordic algorithm, which is a key step in realizing the fractional-order memristor Hopfield neuron model. Under low precision requirements, the table lookup method is an efficient choice; but under high precision, a large amount of ROM / RAM support is required. The Cordic algorithm can provide high precision, but the efficiency is low. How to optimize resource consumption to achieve a balance while ensuring accuracy is still a current challenge.

[0004] In view of the fact that existing FPGA digital technology lacks sufficient resources to realize high-precision fractional-order memristor Hopfield neuron circuits containing complex transcendental functions, the present invention aims to design an FPGA implementation method for fractional-order memristor Hopfield neuron circuits containing complex transcendental functions. Based on the short-term memory principle and multi-segment linear fitting method, only a small amount of FPGA resources are needed to solve the integration problem of high-precision fractional-order systems in FPGA devices, and then realize neural network circuits containing complex transcendental functions in FPGAs. Summary of the invention

[0005] In order to overcome the problem that the prior art cannot generate discharge signals of a fractional-order memristor Hopfield model containing complex functions with high precision and high efficiency, the present invention proposes an FPGA-based fractional-order memristor Hopfield neural network circuit implementation method to implement the fractional-order memristor Hopfield neural network circuit. Only a small amount of resources are needed to solve the problem of implementing a fractional-order memristor Hopfield neuron circuit with high precision requirements in an FPGA device, so as to better analyze the memory effect of neurons.

[0006] To achieve the above object, the technical solution adopted by the present invention is:

[0007] A method for realizing a fractional-order memristor Hopfield neural network circuit based on FPGA, the method comprising the following steps:

[0008] Step 1, based on the principle of short-term memory, rewrite the Grunwald-Letnikov expression into a finite time window form:

[0009] Rewrite the Grünwald-Letnikov fractional derivative with short-term memory into the following form:

[0010] ;

[0011] L is a finite time window. If the time step is small enough, it is used for the fractional order integral operation of a given function, and the value for a given time interval satisfies , M is the system maximum value. If the expected error is less than a predetermined positive number , Right now , then the memory duration is selected as:

[0012] ;

[0013] Due to this approximation, there will be some errors, but the upper bound of the error based on the principle of short-term memory is:

[0014] ;

[0015] Here , and when hour, , here and The integral interval of the integral gets the starting point and the end point;

[0016] Step 2, processing of complex hyperbolic tangent functions in neural networks, through piecewise approximation, data concatenation and RAM storage combined with floating point conversion;

[0017] Step 3, using Verilog programming, after the calculation is completed, the obtained value is output through the floating point converter and AD converter and displayed on the oscilloscope;

[0018] Step 4: According to the results of step 1 and step 3, a fractional-order Hopfield neural network model of coupled memristor is selected, and its mathematical expression is:

[0019] ;

[0020] in is the state variable, is the neuron activation function, is the flux of the magnetic field of the second neuron through the cell membrane, is the adjustable parameter of the memristor, It is the magnetic field induced current caused by the change of magnetic flux. is the intensity of electromagnetic radiation, is the change in magnetic flux, and is the leakage of magnetic flux, is the order of the fraction.

[0021] Further, the processing steps of the complex hyperbolic tangent function in the neural network in step 2 are:

[0022] Step 1), divide the interval according to a certain segmentation principle to obtain all the approximation points;

[0023] According to the predetermined segmentation principle, the interval is subdivided into multiple sub-intervals, and the approximation point of each interval is obtained to obtain all the straight line segments. middle k and b The value is converted into IEEE754 single-precision 32-bit data format and saved through programming software;

[0024] Step 2) Process the two sets of 32-bit data, concatenate them into 64-bit data in a specified way, and save them as a .coe file, where the high 32 bits are stored. k The value is stored in the lower 32 bits. b The value of , and then use Xilinx ise software to generate a RAM IP core from the .coe file;

[0025] Step 3), according to the data to be processed, the adjacent integer intervals are segmented, and the value of each interval is amplified by the corresponding multiple through the multiplier. Then, the single-precision IEEE 754 floating-point number is converted into a decimal number using the floating-point converter, and its integer part is taken and transmitted to the address line of the RAM for addressing, so as to obtain the high 32-bit and low 32-bit data stored in the RAM. Then, the corresponding value of the hyperbolic function is calculated through the multiplier and adder. In this process, the multiplier is used in time-sharing multiplexing mode, so that the system only consumes 1 RAM, 1 adder, 1 multiplier and 1 floating-point converter.

[0026] Further, the step 3 is specifically as follows:

[0027] Use the results obtained in step 2 to write the corresponding Verilog algorithm code in the Xilinx ISE programming environment, and perform joint simulation through Xilinx ISE and ModelSim software. The simulation results are converted into decimal data through Matlab for plotting and analysis. After confirmation, the compiled file is burned to the FPGA development board.

[0028] The advantages of the present invention are: the present invention is based on the fractional-order system processing method of the short-term memory principle, and uses a multi-segment linear fitting algorithm with low resource consumption and high efficiency to realize the model of the fractional-order memristor Hopfield neural network on the FPGA, generate high-precision periodic and chaotic signals, and can more intuitively observe the abnormal discharge behavior of the neuron circuit on the hardware device. The present invention not only provides a new idea for the FPGA implementation of the fractional-order memristor Hopfield neural network, but also provides a new idea for other FPGA designs containing fractional orders and special activation functions, which is of great significance to the disciplines of nonlinear neurons and intelligent control. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 Implement a module for the hyperbolic tangent function;

[0030] Figure 2 It is the overall module diagram of the Verilog algorithm;

[0031] Figure 3 It is the schematic diagram of the system module;

[0032] in Figure 3 (a) is the schematic diagram of the output modules of system K1 and K3. Figure 3 (b) is the schematic diagram of the output modules of system K2 and K4;

[0033] Figure 4 It is a diagram of the principle of binomial summation;

[0034] Figure 5 Flowchart for summing binomials;

[0035] Figure 6 Summing flow chart for the system;

[0036] Figure 7 This is the overall connection schematic diagram;

[0037] Figure 8 For different states Phase diagram and timing diagram of y;

[0038] in Figure 8 (a) is the yw phase diagram when q=0.95. Figure 8 (b) is the yw phase diagram when q=0.95. Figure 8 (c) in the figure is the yw phase diagram when q=0.96, (d) in the figure is the timing diagram of y when q=0.96, (e) in the figure is the yw phase diagram when q=0.99, and (f) in the figure is the timing diagram of y when q=0.99. DETAILED DESCRIPTION

[0039] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments:

[0040] The present invention relates to a method for realizing a fractional-order memristor Hopfield neuron circuit by using FPGA, which can realize high-precision complex neural network problems in FPGA by occupying only a small amount of RAM resources, and provides a design method for fractional-order memristor Hopfield neural network design in Verilog language, which can be used to simulate the discharge characteristics of neural network.

[0041] The specific steps of the algorithm are:

[0042] 1. First, we focus on the calculation problem of fractional-order memristor Hopfield neural network;

[0043] Step 1) First, the system of fractional-order Hopfield neural network defined by Grünwald-Letnikov can be rewritten as:

[0044] ;

[0045] The system step length h The value of is set to 5e-3, and the observation time t is set to 400. The initial values ​​of are all set to 0.1, and by changing the fractional order q Software simulation, observe the Hopfield neural network When the memory time is too long, its resource requirements are too large, but due to the limited computing resources of FPGA, the final memory time is determined to be The final system equation can be rewritten as:

[0046] ;

[0047] 2. Processing of hyperbolic tangent function:

[0048] Step 1), since the tanh function is an odd function and approaches 1 when the input value is greater than 8, the part of the input value exceeding 8 can be directly set to 1 through conditional judgment. For inputs in other ranges, the interval is subdivided into 500 segments, the total plan is divided into 4000 small intervals, and 4000 approximation points are calculated to improve accuracy. The negative part can use the properties of odd functions. Only the value on the positive semi-axis needs to be calculated, and the value on the negative semi-axis is processed through judgment statements. By writing a software program, Cramer's rule is used to solve the sum of all straight line segments, and the calculation results are converted into a 32-bit single-precision floating point format that complies with the IEEE 754 standard for storage.

[0049] Step 2), use software to concatenate two groups of 32-bit data into 64-bit data and save it to generate a .coe file, in which the high 32 bits are stored k The value is stored in the lower 32 bits. b The value of , and then use Xilinx ise software to generate a RAM IP core from the .coe file;

[0050] Step 3), when the adjacent integer segment interval is 500 segments, first use the multiplier to magnify the data to be processed by 500 times, then use the floating point converter to convert the single-precision IEEE 754 floating point number to a decimal number, extract its integer part and send it to the address line of the RAM for addressing. k Value and lower 32 bits b The value of the hyperbolic function can be obtained by multiplying and adding. x If it is a negative number, just convert it to a positive number, and then output The highest bit can be converted to 1. Since the multiplier adopts time-sharing multiplexing, the overall resource consumption is 1 RAM, 1 adder, 1 multiplier and 1 floating-point converter. The specific modules are as follows Figure 1 As shown:

[0051] 3. Write the corresponding Verilog algorithm according to the above mathematical expression. The algorithm module is divided into five parts. Then you can use XIlinx ise and Modelsim software for joint simulation, and use Matlab to convert the obtained data into decimal for plotting and analysis. Design the overall framework of the algorithm as follows Figure 2 shown.

[0052] The program call module mainly calculates the system value for the system module, binomial summation module and system summation module, and then passes the value to the module_DAC module to convert it into analog quantity. Among them, the system includes a floating point to decimal fixed point converter, adder, multiplier, RAM, and the system The previous term without summation is calculated. The binomial summation module calculates the binomial product including the memory length, which uses adders, multipliers, shift registers and RAM including the memory length. When the system and binomial summation are calculated, the program call module passes the calculation content of the previous two modules to the system summation module to calculate the new iterative value, and transmits the iterative value to module_DAC output. The schematic diagram of the system module is as follows Figure 3 Shown include Figure 3 (a) System K1, K3 output module schematic and Figure 3 (b) The schematic diagram of the output modules of the system K2 and K4, and the schematic diagram of the binomial summation are shown in Figure 4 As shown, the binomial summation flowchart is as follows Figure 5 As shown, the system summation flow chart is as follows Figure 6 shown.

[0053] 4. After the simulation analysis is correct, the bit file generated by the XIlinx ise software can be burned into the FPGA, and the oscilloscope can be connected to observe the waveform, such as Figure 7 shown.

[0054] The oscilloscope display of the periodic and chaotic signals of the fractional-order memristor Hopfield neural network model based on FPGA digital technology is shown in the figure below. Figure 8 Shown include Figure 8 (a) yw phase diagram when q=0.95, Figure 8 (b) yw phase diagram when q=0.95, Figure 8 (c) yw phase diagram when q=0.96, Figure 8 (d) The timing diagram of y when q=0.96, Figure 8 When (e)q=0.99, the yw phase diagram is shown in Figure 1. Figure 8 (f) Timing diagram of y when q=0.99.

[0055] 5. In addition, in order to present the above-mentioned effect of achieving high-precision fractional-order memristor Hopfield neural network with fewer resources, the superiority of the present invention can be more intuitively felt by comparing the FPGA resources of the fractional-order memristor Hopfield neural network implemented by the Adomian algorithm.

[0056] The Adomian algorithm involves breaking down the system into three different components: linear terms, nonlinear terms, and constant terms. These components are then solved separately and the results are summed.

[0057] ;

[0058] in, L , N and g They represent the linear, nonlinear and constant terms of the system function respectively. represent q Caputo differential operator of order, Represents the initial value of the k-th order.

[0059] The system is divided into linear and nonlinear parts, as well as some constant parts based on Adomian decomposition:

[0060]

[0061] In order to ensure the accuracy of the Adomian algorithm, the initial value of the system is set to:

[0062] ;

[0063] From this, we can get the second term:

[0064]

[0065] in Represents the Gamma function, and the derived iterative formula is as follows:

[0066] ;

[0067] Through the recursive formula iteration, the following items can be deduced. However, the expression is too long. The following is the system solution formula:

[0068]

[0069] The Adomian decomposition method usually requires six decompositions to achieve the required accuracy, but since the nonlinear term of this system has been decomposed four times, the data accuracy has met the requirements. Through iterative equations, based on FPGA technology, the tanh function in the system equation is subjected to the same fitting process, and it can be obtained that the FPGA resources occupied by this method are much greater than those of the algorithm of the present invention.

[0070] Table 1 Comparison of FPGA resources for implementing fractional-order systems using different methods;

[0071]

[0072] By comparing Table 1, it can be seen that the algorithm for implementing the fractional-order memristor Hopfield neural network in the present invention is far less resource-intensive than the Adomian algorithm. This method significantly reduces the reliance on hardware resources such as multipliers, dividers, and adders, optimizes resource utilization efficiency, and can meet the needs of high-precision calculations. This advantage makes it suitable for scenarios with limited hardware resources but high requirements for calculation accuracy, showing broad application prospects.

[0073] In summary, the present invention overcomes the problem that the prior art cannot meet the requirements of FPGA for high-precision and high-efficiency implementation of fractional-order memristor Hopfield neural network. It only consumes a small amount of RAM resources and can solve the problem of implementing complex fractional-order neural networks with higher precision requirements in FPGA devices.

[0074] The above description is only a preferred embodiment of the present invention and does not constitute any other form of limitation to the present invention. Any modification or equivalent change made based on the technical essence of the present invention still falls within the scope of protection required by the present invention.

Claims

1. A method for implementing a fractional-order memristor Hopfield neural network circuit based on FPGA, characterized in that: The method comprises the following steps: Step 1, based on the principle of short-term memory, rewrite the Grunwald-Letnikov expression into a finite time window form: Rewrite the Grünwald-Letnikov fractional derivative with short-term memory into the following form: ； L is a finite time window. If the time step is small enough, it is used for the fractional order integral operation of a given function, and the value for a given time interval satisfies , M is the system maximum value. If the expected error is less than a predetermined positive number , Right now , then the memory duration is selected as: ； Due to this approximation, there will be some errors, but the upper bound of the error based on the principle of short-term memory is: ； Here , and when hour, , here and The integral interval of the integral gets the starting point and the end point; Step 2, processing of complex hyperbolic tangent functions in neural networks, through piecewise approximation, data concatenation and RAM storage combined with floating point conversion; The processing steps of the complex hyperbolic tangent function in the step 2 neural network are: Step 1), divide the interval according to a certain segmentation principle to obtain all the approximation points; According to the predetermined segmentation principle, the interval is subdivided into multiple sub-intervals, and the approximation point of each interval is obtained to obtain all the straight line segments. middle k and b The value is converted into IEEE754 single-precision 32-bit data format and saved through programming software; Step 2) Process the two sets of 32-bit data, concatenate them into 64-bit data in a specified way, and save them as a .coe file, where the high 32 bits are stored. k The value is stored in the lower 32 bits. b The value of , and then use Xilinx ise software to generate a RAM IP core from the .coe file; Step 3), according to the data to be processed, the adjacent integer intervals are segmented, and the value of each interval is amplified by a corresponding multiple through a multiplier. Then, the single-precision IEEE 754 floating-point number is converted into a decimal number using a floating-point converter, and its integer part is taken and transmitted to the address line of the RAM for addressing, so as to obtain the high 32-bit and low 32-bit data stored in the RAM. Then, the corresponding value of the hyperbolic function is calculated through the multiplier and adder. In this process, the multiplier is used in a time-sharing multiplexing mode, so that the system only consumes 1 RAM, 1 adder, 1 multiplier and 1 floating-point converter; Step 3, using Verilog programming, after the calculation is completed, the obtained value is output through the floating point converter and AD converter and displayed on the oscilloscope; The step 3 is as follows: Use the results obtained in step 2 to write the corresponding Verilog algorithm code in the Xilinx ISE programming environment, and perform joint simulation through Xilinx ISE and ModelSim software. The simulation results are converted into decimal data through Matlab for plotting and analysis. After confirmation, the compiled file is burned to the FPGA development board; Step 4: According to the results of step 1 and step 3, a fractional-order Hopfield neural network model of coupled memristor is selected, and its mathematical expression is: ; in is the state variable, is the neuron activation function, is the flux of the magnetic field of the second neuron through the cell membrane, is the adjustable parameter of the memristor, It is the magnetic field induced current caused by the change of magnetic flux. is the intensity of electromagnetic radiation, is the change in magnetic flux, and is the leakage of magnetic flux, is the order of the fraction.

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