Display panel driving method, display device and display panel

Abstract

The embodiment of the invention provides a display panel driving method, a display device and a display panel.The display panel driving method comprises the steps that when a direct current (DC) dimming mode is converted into a pulse width modulation (PWM) dimming mode, an unequal-width pulse (PWM) signal is generated, the unequal-width pulse PWM signal comprises a plurality of first-type pulses and a plurality of second-type pulses, and the first-type pulses and the second-type pulses are different from each other; the first type of pulse and the second type of pulse are both first level signals, the pulse width of the first type of pulse is larger than that of the second type of pulse, and the pulse width of the first type of pulse is not smaller than the minimum level width of scanning or resetting of a pixel circuit in the display panel; and scanning each row of pixel circuits in the display panel by using the unequal-width pulse PWM signals. Through a plurality of first-class pulses and a plurality of second-class pulses included in the unequal-width pulse PWM signals, the duty ratio of PWM dimming can be improved under the condition of high-frequency PWM, and the flicker problem during switching of high-frequency PWM dimming and DC dimming is weakened.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel driving method, a display device and a display panel. Background Art

[0002] In the traditional PWM (Pulse Width Modulation) dimming scheme, when the OLED (Organic Light Emitting Diode) screen uses the PMOS (positive channel Metal Oxide Semiconductor) process, all EM (light-emitting control signals) high levels are set to be consistent with the first approximation. This setting is relatively simple to implement and easy to control logically. However, with the improvement of high-frequency PWM specifications, the implementation of the new LTPO (Low Temperature Polycrystalline Oxide) scheme (with reset in the middle holding area and limited EM width) or the reduction of the vertical resolution of some special products, the proportion of high-level EM signals increases, and the duty cycle of PWM dimming becomes smaller. In high-brightness DC dimming (changing the brightness of the screen by increasing or decreasing the power of the screen panel circuit), the proportion of high-level EM signals is very small, and the proportion of low-level signals is relatively large. Therefore, the duty cycle of DC dimming is usually very high, see Figure 3 If the duty of high-frequency PWM dimming is too small, the flicker problem will increase when switching with DC dimming during the dimming process. Summary of the invention

[0003] The purpose of the embodiments of the present application is to provide a display panel driving method, a display device and a display panel to reduce the flicker problem when switching between high-frequency PWM dimming and DC dimming. The specific technical solution is as follows:

[0004] In a first aspect, an embodiment of the present application provides a display panel driving method, the method comprising:

[0005] When converting from a direct current (DC) dimming mode to a pulse width modulation (PWM) dimming mode, generating a non-equal width pulse PWM signal, wherein the non-equal width pulse PWM signal includes a plurality of first-type pulses and a plurality of second-type pulses, the first-type pulses and the second-type pulses are both first-level signals, the pulse width of the first-type pulses is greater than the pulse width of the second-type pulses, and the pulse width of the first-type pulses is not less than the minimum level width of the pixel circuit in the display panel for scanning or resetting;

[0006] The non-uniform-width pulse PWM signal is used to scan each row of pixel circuits in the display panel.

[0007] In a possible implementation, for each frame of non-equal-width pulse PWM signal, the frame of non-equal-width pulse PWM signal includes at least two sub-timing signals; for each sub-timing signal, the sub-timing signal includes one first-type pulse and multiple second-type pulses.

[0008] In a possible implementation, the pulse width of the first type of pulse is a minimum level width for scanning or resetting a pixel circuit in the display panel, and the pulse width of the second type of pulse is a minimum width required by the timing of the display panel.

[0009] In a possible implementation manner, the timing of the reset signal, the initialization signal, the charging signal, and the reset compensation signal of the pixel circuit is within the timing of the first type of pulses.

[0010] In a possible implementation, the method further includes:

[0011] Obtaining the number of pulses in each refreshed image frame, the pulse width of the first type of pulses, the pulse width of the second type of pulses, and the timing of obtaining a reset signal, an initialization signal, a charging signal, and a reset compensation signal of the pixel circuit;

[0012] Determine the number and timing of the first type of pulses according to the timing of the reset signal, the initialization signal, the charging signal and the reset compensation signal, and the pulse width of the first type of pulses, wherein the timing of the reset signal, the initialization signal, the charging signal and the reset compensation signal is within the timing of the first type of pulses, and the timing of the first type of pulses is evenly arranged within the time of one image frame;

[0013] According to the number and timing of the first-type pulses, one image frame is divided into n segments of sub-timing signals, wherein n is the number of the first-type pulses, and for each segment of the sub-timing signal, the sub-timing signal includes a first-type pulse located at the timing head of the sub-timing signal;

[0014] According to the number of pulses, the number of the first type of pulses and the pulse width of the second type of pulses, the timing and number of the second type of pulses in each segment of the sub-timing signal are determined to obtain generation parameters of the PWM signal; wherein the generation parameters include the timing of the first type of pulses, the timing and number of the second type of pulses in each segment of the sub-timing signal, and the number of segments n of the sub-timing signal;

[0015] When the DC dimming mode is converted into the PWM dimming mode, a non-uniform width pulse PWM signal is generated, including:

[0016] When the direct current (DC) dimming mode is converted to the pulse width modulation (PWM) dimming mode, a non-uniform width pulse PWM signal is generated according to the generation parameters.

[0017] In a possible implementation manner, after scanning each row of pixel circuits in the display panel using the non-uniform-width pulse PWM signal, the method further includes:

[0018] According to a preset scanning cycle, the pulse width of the second type of pulses in the non-equal width pulse PWM signal is increased by a preset width to obtain a current PWM signal;

[0019] Scanning each row of pixel circuits in the display panel using the current PWM signal;

[0020] Return to the execution step: according to the preset scanning period, increase the pulse width of the second type of pulse in the non-equal width pulse PWM signal, or increase the pulse width of the first type of pulse and the second type of pulse in the non-equal width pulse PWM signal, to obtain the current PWM signal, until the brightness of the scanned image under the current PWM signal is the specified brightness.

[0021] In a possible implementation, the method further includes:

[0022] In the PWM dimming mode, in the first brightness scene, a second non-equal width pulse PWM signal is generated, wherein the second non-equal width pulse PWM signal includes a plurality of first type pulses and a plurality of second type pulses;

[0023] Scanning each row of pixel circuits in the display panel using the second non-uniform-width pulse PWM signal;

[0024] When the first brightness scene is switched to the second brightness scene, a third non-equal width pulse PWM signal is generated, wherein the third non-equal width pulse PWM signal includes a plurality of first type pulses and a plurality of second type pulses;

[0025] Scanning each row of pixel circuits in the display panel using the third non-uniform-width pulse PWM signal;

[0026] Among them, the brightness of the scanned image in the first brightness scene is greater than the brightness of the scanned image in the second brightness scene; the number of second-type pulses in the second non-equal-width pulse PWM signal is less than the number of second-type pulses in the third non-equal-width pulse PWM signal, and the total width of the second-type pulses in the second non-equal-width pulse PWM signal is greater than the total width of the second-type pulses in the third non-equal-width pulse PWM signal.

[0027] In a second aspect, an embodiment of the present application provides a display device, wherein the display device includes a display panel and a display driver chip:

[0028] The display panel comprises a display module, the display module comprises a plurality of pixel rows, each of the pixel rows comprises a plurality of pixel circuits;

[0029] The display driver chip is used to: generate a non-equal width pulse PWM signal when converting from a direct current (DC) dimming mode to a pulse width modulation (PWM) dimming mode, wherein the non-equal width pulse PWM signal includes a plurality of first-type pulses and a plurality of second-type pulses, the first-type pulses and the second-type pulses are both first-level signals, the pulse width of the first-type pulses is greater than the pulse width of the second-type pulses, and the pulse width of the first-type pulses is not less than the minimum level width for scanning or resetting a pixel circuit in the display panel; and scan the pixel circuits in each pixel row in the display panel using the non-equal width pulse PWM signal;

[0030] The display module is used to drive the pixel circuits in each pixel row in response to the scanning of the non-uniform width pulse PWM signal.

[0031] In a possible implementation, for each frame of non-equal-width pulse PWM signal, the frame of non-equal-width pulse PWM signal includes at least two sub-timing signals; for each sub-timing signal, the sub-timing signal includes one first-type pulse and multiple second-type pulses.

[0032] In a possible implementation, the pulse width of the first type of pulse is a minimum level width for scanning or resetting a pixel circuit in the display panel, and the pulse width of the second type of pulse is a minimum width required by the timing of the display panel.

[0033] In a possible implementation manner, the timing of the reset signal, the initialization signal, the charging signal, and the reset compensation signal of the pixel circuit is within the timing of the first type of pulses.

[0034] In one possible implementation,

[0035] The display driver chip is further used to obtain the number of pulses in each refreshed image frame, the pulse width of the first type of pulses, the pulse width of the second type of pulses, and the timing of the reset signal, initialization signal, charging signal and reset compensation signal of the pixel circuit; according to the timing of the reset signal, initialization signal, charging signal and reset compensation signal, and the pulse width of the first type of pulses, the number and timing of the first type of pulses are determined, wherein the timing of the reset signal, initialization signal, charging signal and reset compensation signal is within the timing of the first type of pulses, and the timing of the first type of pulses is evenly arranged within the time of one image frame. According to the number and timing of the first type of pulses, a frame of the image is divided into n segments of sub-timing signals, wherein n is the number of the first type of pulses, and for each segment of the sub-timing signal, the sub-timing signal includes a first type of pulse, and is located at the timing head of the sub-timing signal; according to the number of pulses, the number of the first type of pulses and the pulse width of the second type of pulses, the timing and number of the second type of pulses in each segment of the sub-timing signal are determined to obtain the generation parameters of the PWM signal; wherein the generation parameters include the timing of the first type of pulses, the timing and number of the second type of pulses in each segment of the sub-timing signal, and the segment number n of the sub-timing signal;

[0036] The display driver chip is specifically used to generate non-uniform width pulse PWM signals according to the generation parameters when converting from a direct current (DC) dimming mode to a pulse width modulation (PWM) dimming mode.

[0037] In a possible implementation manner, the display driver chip is further used for:

[0038] According to a preset scanning cycle, the pulse width of the second type of pulse in the non-equal width pulse PWM signal is increased by a preset width to obtain a current PWM signal; the current PWM signal is used to scan each row of pixel circuits in the display panel; and the execution step is returned: according to a preset scanning cycle, the pulse width of the second type of pulse in the non-equal width pulse PWM signal is increased, or the pulse widths of the first type of pulse and the second type of pulse in the non-equal width pulse PWM signal are increased to obtain the current PWM signal, until the brightness of the scanned image under the current PWM signal is the specified brightness.

[0039] In a possible implementation manner, the display driver chip is further used for:

[0040] In the PWM dimming mode, in a first brightness scene, a second non-equal-width pulse PWM signal is generated, wherein the second non-equal-width pulse PWM signal includes multiple first-type pulses and multiple second-type pulses; each row of pixel circuits in the display panel is scanned using the second non-equal-width pulse PWM signal; when the first brightness scene is switched to the second brightness scene, a third non-equal-width pulse PWM signal is generated, wherein the third non-equal-width pulse PWM signal includes multiple first-type pulses and multiple second-type pulses; each row of pixel circuits in the display panel is scanned using the third non-equal-width pulse PWM signal; wherein the brightness of the scanned image in the first brightness scene is greater than the brightness of the scanned image in the second brightness scene; the number of the second-type pulses in the second non-equal-width pulse PWM signal is less than the number of the second-type pulses in the third non-equal-width pulse PWM signal, and the total width of the second-type pulses in the second non-equal-width pulse PWM signal is greater than the total width of the second-type pulses in the third non-equal-width pulse PWM signal.

[0041] In a third aspect, an embodiment of the present application further provides a display panel, the display panel comprising:

[0042] A driving module and a display module, wherein the display module comprises a plurality of pixel rows, and each of the pixel rows comprises a plurality of pixel circuits;

[0043] The driving module is used to: generate a non-equal width pulse PWM signal when converting from a direct current (DC) dimming mode to a pulse width modulation (PWM) dimming mode, wherein the non-equal width pulse PWM signal includes a plurality of first-type pulses and a plurality of second-type pulses, the first-type pulses and the second-type pulses are both first-level signals, the pulse width of the first-type pulses is greater than the pulse width of the second-type pulses, and the pulse width of the first-type pulses is not less than the minimum level width for scanning or resetting the pixel circuit in the display panel; and use the non-equal width pulse PWM signal to scan the pixel circuits in each pixel row in the display panel;

[0044] The display module is used to drive the pixel circuits in each pixel row in response to the scanning of the non-uniform width pulse PWM signal.

[0045] Beneficial effects of the embodiments of the present application:

[0046] The embodiment of the present application provides a display panel driving method, a display device and a display panel, wherein the display panel driving method comprises: when converting from a direct current (DC) dimming mode to a pulse width modulation (PWM) dimming mode, generating a non-equal width pulse PWM signal, wherein the non-equal width pulse PWM signal comprises a plurality of first-type pulses and a plurality of second-type pulses, the first-type pulses and the second-type pulses are both first-level signals, the pulse width of the first-type pulses is greater than the pulse width of the second-type pulses, and the pulse width of the first-type pulses is not less than the minimum level width for scanning or resetting the pixel circuit in the display panel; and the non-equal width pulse PWM signal is used to scan each row of pixel circuits in the display panel. By using the plurality of first-type pulses and the plurality of second-type pulses included in the non-equal width pulse PWM signal, the duty cycle of PWM dimming can be increased in the case of high-frequency PWM, and the flickering problem when switching between high-frequency PWM dimming and DC dimming can be reduced.

[0047] Of course, implementing any product or method of the present application does not necessarily require achieving all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0049] Figure 1 It is a structural schematic diagram of a 7T1C pixel circuit in the related art;

[0050] Figure 2a It is a schematic diagram of display panel scanning in the related technology;

[0051] Figure 2b It is a schematic diagram of PWM dimming in the related technology;

[0052] Figure 2c A schematic diagram of DC dimming in the related art;

[0053] Figure 3 A timing diagram of PWM dimming and DC dimming in the related art;

[0054] Figure 4a A schematic diagram of a first flow chart of a display panel driving method provided in an embodiment of the present application;

[0055] Figure 4b A timing diagram of an EM signal for high-frequency non-equal-width pulse PWM dimming provided in an embodiment of the present application;

[0056] Figure 5 A second flow chart of the display panel driving method provided in an embodiment of the present application;

[0057] Figure 6a A third flow chart of the display panel driving method provided in the embodiment of the present application;

[0058] Figure 6b This is a schematic diagram of switching between high-frequency PWM dimming and DC dimming;

[0059] Figure 6c Another timing diagram of the EM signal of high-frequency non-equal-width pulse PWM dimming provided in an embodiment of the present application;

[0060] Figure 7 A schematic diagram of the timing of the scanning signal and the reset compensation signal of the high-frequency non-equal-width pulse PWM dimming provided in the embodiment of the present application;

[0061] Figure 8a A fourth flow chart of the display panel driving method provided in the embodiment of the present application;

[0062] Figure 8b The following is a timing diagram of PWM dimming in two different scenarios;

[0063] Fig. 9 A schematic diagram of the structure of a display device provided in an embodiment of the present application;

[0064] Fig.10 A schematic diagram of a first structure of a display panel provided in an embodiment of the present application;

[0065] Fig.11 A second structural schematic diagram of a display panel provided in an embodiment of the present application. DETAILED DESCRIPTION

[0066] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field based on the present application belong to the scope of protection of the present application.

[0067] First, a brief description is given of the display device in the related art. The display device in the related art includes a display panel and a display driver chip. The display panel includes a display module. The display module includes multiple rows of pixels, and each row of pixels includes multiple pixel circuits. The display driver chip is used to: generate an equal-width pulse PWM signal (EM signal) in a pulse width modulation PWM dimming mode, and use the equal-width pulse PWM signal to scan the pixel circuits in each pixel row in the display panel; the display driver chip is also used to: generate an EM signal with a relatively high low-level ratio in a DC dimming mode, and use the EM signal to scan the pixel circuits in each pixel row in the display panel.

[0068] Next, a brief description of PWM dimming in the related art is given. In the related art, due to the light-emitting principle and characteristics of OLED (Organic Light Emitting Diode) current drive, the corresponding current under low brightness and low grayscale is very small, the color and brightness uniformity of the picture is poor, and the color deviation and mura (the phenomenon of uneven display brightness and various traces) are serious. In order to solve the above problems, the current OLED screen in the industry will use PWM dimming at low brightness, and DC dimming can be used at high brightness (changing the brightness of the screen by increasing or decreasing the power of the screen panel circuit). However, the traditional low-frequency PWM dimming may have a bad effect on the human eye when watching the screen for a long time. In order to solve this problem, a high-frequency PWM solution has emerged in the industry. Generally speaking, the higher the PWM frequency, the less impact on the human eye, and the better eye protection. With the increase in demand and the development of technology, PWM is evolving towards higher frequencies, but for higher-frequency PWM dimming, the risk of flickering increases accordingly when switching between low-frequency PWM dimming / high-brightness DC dimming, which needs to be optimized and solved.

[0069] In order to explain the problems existing in related technologies, some basic concepts are briefly introduced as follows:

[0070] GOA signal: GOA stands for Gate Drive On Array, which is a signal used to control gate scanning. Through timing configuration, the scanning time h of each pixel row and the porch (blanking area) duration VBP (Vertical Back Porch, the back shoulder of the vertical synchronization signal, indicating the number of invalid rows after the vertical synchronization signal at the beginning of a frame of image) and VFP (Vertical Front Porch, the front shoulder of the vertical synchronization signal, indicating the number of invalid rows before the vertical synchronization signal after the end of a frame of image) can be set.

[0071] EM (PWM) signal: the signal that controls the lighting of OLED, see Figure 1The 7T1C (7 TFTs, Thin Film Transistor, 1 capacitor) pixel circuit shown in the figure, where ELVDD is the positive power supply voltage, ELVSS is the negative power supply voltage, Cst is the storage capacitor, Vdata is the data signal, Scan1, Scan2, Scan3 are the scanning signals, and Vref is the reset signal. For each pixel, after charging is completed, the driving TFT, i.e., the T3 tube, is always in the on state, and at this time, the lighting / closing of the OLED is controlled by the EM signal. The so-called DC dimming usually means that the EM signal is always in the on state, and PWM dimming means that the EM signal is turned on-off-on at a set frequency to modulate the pixel brightness.

[0072] The principle of PWM (EM) dimming: Due to the current-driven light-emitting principle of OLED, the process consistency of different pixel TFTs cannot be guaranteed at low brightness, which will cause problems such as mura and color shift due to different brightness of different pixels. Therefore, OLED basically uses PWM dimming at low brightness, that is, maintaining a certain TFT driving voltage (current) and adjusting the OLED light brightness through the EM signal duty cycle, which is the so-called bright-dark-bright-dark ratio.

[0073] Display panel Panel scanning time per line h: When the panel is working, it is usually controlled by DDIC (Display Driver IC) to drive the GOA, EM, TFT timing of the panel to complete reset, initialization, charging, light emission and other actions. The scanning of each pixel row has precise hardware timing control, and the required duration of each row can be generated by the IC internal clock setting. This duration is called row scanning h. For example, for a screen with a resolution of 1200×2800×120hz, assuming that the VFP and VBP in the inter-frame porch area total 80 h (actually it can be flexibly set according to different product requirements), then the approximate duration of h is h=1 / 120 / (2800+80)=2.894us.

[0074] In current OLED displays, the proportion of EM low-level duration is generally defined as EM duty, which is collectively referred to as duty below. It should be noted that if the OLED screen uses the PMOS process, the high level of the EM signal corresponds to the OLED being turned off, and the low level of the EM signal corresponds to the OLED being lit; if the OLED screen uses the NMOS (Negative channel-Metal-Oxide-Semiconductor) process, the high level of the EM signal corresponds to the OLED being lit, and the low level of the EM signal corresponds to the OLED being turned off, and the current OLED screens generally use the PMOS process. Calculation of duty cycle of PWM (EM): The duration of high and low levels of PWM is usually calculated by the number of h. The duration width of each EM signal black insertion (high level, turning off OLED) is x*h, and the duration width of each EM signal lighting area (effective level) is y*h. Then x+y=total number of pixel rows+VBP+VFP, EM light-emitting duty cycle duty=total duration of EM lighting area / total duration of each frame*100%=1-x*h / (total number of pixel rows+VBP+VFP)*h*100%=1-x / (total number of pixel rows+VBP+VFP)*100%. Figure 2a , Figure 2b and Figure 2c As shown, for example, based on a screen with a resolution of 1200×2800×120hz, assuming that VFP and VBP total 80 h, the duty of EM lighting is about 1-(x / (2800+80))×100%. It can be seen that the wider the EM signal black insertion in a frame of image, the smaller the duty, and the darker the screen brightness, and vice versa. The duty of the DC dimming interval can usually be above 90%, or even above 98%. Due to the increasingly higher PWM specifications and the use of LTPO, the duty of the PWM dimming interval is getting lower and lower.

[0075] OLED screens are usually scanned line by line (including reset, initialization, charging, luminescence, etc.). For each row of pixels, the reset, initialization, charging, etc. are usually completed when the first EM signal is at a high level (no luminescence). Figure 1 , the signals for reset, initialization, and charging operations require several scanning operation signals, such as Scan1, Scan2, and Scan3 (it should be noted that the scanning signals may be 2, 3, 4, or 5 signals, and the number of scanning signals in different circuit architectures is different). This requires the corresponding EM signal width to be wider in order to wrap these scanning signals within the time range. Other EM signals in the non-scanning charging interval usually meet the minimum requirements of the Panel circuit. Figure 3As shown, EM-1 is the DC EM signal waveform in the high brightness interval, and EM-2 is the EM signal waveform of the PWM in the low brightness interval. The first EM pulse duration is required to be longer. In the PWM dimming in the related art, the high level of all EM signals is usually set to be approximately consistent with the first one, because in the actual duty adjustment process, there will be certain regular fine-tuning for the width of some EM high levels. Take 12Pulse (12 pulses) at 120Hz as an example for explanation. For example, if a step is adjusted to 4h, then this 4h is usually added to the first EM high level, and the first EM high level will be 4h longer than the others; if it is adjusted to 8h, it is usually added to the first EM high level and the seventh EM high level, so the width of the first EM high level and the seventh EM high level is slightly wider. The increased EM high level duration is usually divided into 12 pulses as evenly as possible in time and scanning space. Therefore, the high level of the EM signal is approximately consistent with the first EM high level, and the difference will not be too large, and there will be no obvious special setting of a wider EM. This setting is relatively simple to implement and easy to control logically. However, with the improvement of high-frequency PWM specifications, such as 2160, 3840hz, etc., as well as the implementation of new LTPO solutions (with reset in the middle holding area and limited EM width) or the reduction in the vertical resolution of some special products, the duty of PWM dimming becomes smaller. The duty of DC dimming is usually very high at high brightness. If the high-frequency PWM dimming duty is too small, the risk of flickering increases when switching between DC dimming and PWM dimming during the dimming process. Or in some specific low-frequency PWM dimming scenarios, the proportion of high-level EM signals is smaller than that of high-frequency PWM dimming. Therefore, the duty cycle of low-frequency PWM dimming is larger than that of high-frequency PWM dimming. When switching with high-frequency PWM dimming, there will be more serious flickering problems due to the large difference in duty.

[0076] For example, see Figure 3 , if DC dimming is 1 pulse PWM, PWM dimming is 4 pulses, each PWM black insertion width is calculated as 40h, and the duration width in one frame is 2800+80=2880h, then the duty cycle of 4 pulse PWM dimming is duty=1-(40*4 / 2880)*100%=94.4%, and the duty cycle of DC dimming is duty=1-(40*1 / 2880)*100%=98.6%. The difference between the two is very small, and the flickering is weaker when switching. If PWM dimming becomes 32 pulses (or even higher), then PWM dimming duty=1-(40*32 / 2800)*100%=55.6%, and DC is still 98.6%. At this time, the flickering problem during switching is aggravated.

[0077] In order to improve the duty cycle of high-frequency PWM dimming and reduce the flickering problem when switching between high-frequency PWM dimming and DC dimming / low-frequency PWM dimming, the embodiment of the present application provides a display panel driving method, see Figure 4a , including the following steps:

[0078] Step S401, when converting from a direct current (DC) dimming mode to a pulse width modulation (PWM) dimming mode, generating a non-equal width pulse PWM signal, wherein the non-equal width pulse PWM signal includes a plurality of first-type pulses and a plurality of second-type pulses, the first-type pulses and the second-type pulses are both first-level signals, the pulse width of the first-type pulses is greater than the pulse width of the second-type pulses, and the pulse width of the first-type pulses is not less than the minimum level width for scanning or resetting a pixel circuit in the display panel.

[0079] Referring to the description in the above related art, if the OLED screen uses the PMOS process, the first level signal in step S401 is a high level signal, and if the OLED screen uses the NMOS process, the first level signal in step S401 is a low level signal. The examples and descriptions in the subsequent embodiments are based on the OLED screen using the PMOS process, and will not be described in the subsequent embodiments.

[0080] For an example, see Figure 4b , EM-3 is a schematic diagram of the EM signal waveform of low-frequency PWM dimming in the related technology, and EM-4 is a schematic diagram of the EM signal waveform of high-frequency non-equal-width pulse PWM dimming provided in an embodiment of the present application (taking the OLED screen using the PMOS process as an example). Figure 4b In the embodiment, EM-4 can be a 32-pulse high-frequency PWM timing sequence, the first EM pulse and the 17th EM pulse can be first-class pulses, the first-class pulses can be high-level signals, the pulse width of the first-class pulses is not less than the minimum level width of the pixel circuit in the display panel for scanning or resetting, in one example, the minimum level width can be 80h, which can be flexibly set according to the actual display panel product. The other 30 EM pulses can be second-class pulses, which can be high-level signals.

[0081] Step S402 : Scanning each row of pixel circuits in the display panel using the non-uniform-width pulse PWM signal.

[0082] In the embodiment of the present application, the duty cycle of PWM dimming can be increased in the case of high-frequency PWM by including multiple first-type pulses and multiple second-type pulses in the non-equal-width pulse PWM signal.

[0083] In a possible implementation, for each frame of non-equal-width pulse PWM signal, the frame of non-equal-width pulse PWM signal includes at least two sub-timing signals; for each sub-timing signal, the sub-timing signal includes one first-type pulse and multiple second-type pulses.

[0084] For an example, see Figure 4b Each frame of non-equal width pulse PWM signal may include two sections of sub-timing signals, and each section of the sub-timing signal may include 1 first type pulse and 16 second type pulses.

[0085] In a possible implementation, the pulse width of the first type of pulse is a minimum level width for scanning or resetting a pixel circuit in the display panel, and the pulse width of the second type of pulse is a minimum width required by the timing of the display panel.

[0086] For an example, see Figure 4b , the level width of the first EM pulse and the level width of the 17th EM pulse can be 80h, 85h, or 75h, which can be flexibly set according to the actual product. The level width of the other 30 EM pulses can be 16h, 4h, 8h, etc., which can be flexibly set according to the actual product. It should be noted that the above examples are for the minimum state of the first and second pulse widths (i.e., the state when PWM dimming is the brightest).

[0087] In one possible implementation, see Figure 5 ,based on Figure 4a , the display panel driving method further comprises the following steps:

[0088] Step S501 , according to a preset scanning period, the pulse width of the second type of pulses in the non-equal width pulse PWM signal is increased by a preset width to obtain a current PWM signal.

[0089] Step S502 : Scanning each row of pixel circuits in the display panel using the current PWM signal.

[0090] Step S503, return to execute step S501: according to the preset scanning cycle, increase the pulse width of the second type of pulse in the non-equal width pulse PWM signal, or increase the pulse width of the first type of pulse and the second type of pulse in the non-equal width pulse PWM signal, to obtain the current PWM signal, until the brightness of the scanned image under the current PWM signal is the specified brightness.

[0091] The PWM interval is usually duty dimming. As the brightness decreases, the high level of the second type of pulse will slowly increase. Generally, at the lowest brightness, such as 2nit, the duty will drop to about 10%. At this time, all the second type of pulses may have the same width as the first type of pulses, such as 1-80*32 / 2880=16.67%. That is, in the high-frequency PWM dimming low brightness interval, the first type of pulse and the second type of pulse may reach the same or similar width. After the first and second types of pulses reach the same or similar width, the brightness continues to decrease. These two types of pulses can be regarded as one type. As the brightness is adjusted, the EM width is adjusted according to the minimum step (for example, 4h each time).

[0092] During PWM dimming, as the brightness decreases, the EM duty will decrease accordingly, and the first and second pulse widths will increase according to certain rules. For example, according to the panel design, each time the duration increases by 4 hours, the increased EM will be evenly distributed to each EM in the duration position. In this way, at lower brightness, the first and second pulse widths may be the same or similar, which is not fixed. In an example, as the brightness decreases, in a certain state, the first and second widths reach 80 hours with adjustment. At this time, EM duty = 1-(80*32) / 2880*100% = 11.11%. Of course, if the minimum width of the first pulse is 70 hours, or lower, or the number of EM pulses is relatively small, when the first and second pulse widths reach the same, the duty is still high, such as 30%. Then, as the brightness decreases, the duty will continue to decrease, that is, the EM width continues to increase in steps of 4 hours. At this time, the first and second pulse widths will exceed the original setting of 70 hours.

[0093] In a possible implementation manner, the timing of the reset signal, the initialization signal, the charging signal, and the reset compensation signal of the pixel circuit is within the timing of the first type of pulses.

[0094] In one possible implementation, see Figure 6a ,based on Figure 4a , the display panel driving method further comprises the following steps:

[0095] Step S601, obtaining the number of pulses in each refreshed image frame, the pulse width of the first type of pulses, the pulse width of the second type of pulses, and the timing of obtaining the reset signal, initialization signal, charging signal and reset compensation signal of the pixel circuit.

[0096] Step S602, determining the number and timing of the first type of pulses according to the timing of the reset signal, initialization signal, charging signal and reset compensation signal, and the pulse width of the first type of pulses, wherein the timing of the reset signal, initialization signal, charging signal and reset compensation signal is within the timing of the first type of pulses, and the timing of the first type of pulses is evenly arranged within the time of one image frame.

[0097] Step S603, dividing an image frame into n sub-timing signals according to the number and timing of the first type of pulses, wherein n is the number of the first type of pulses, and for each sub-timing signal, the sub-timing signal includes a first type of pulse, and is located at the timing head of the sub-timing signal.

[0098] Step S604, determining the timing and quantity of the second type of pulses in each segment of the sub-timing signal according to the number of pulses, the number of the first type of pulses and the pulse width of the second type of pulses, and obtaining generation parameters of the PWM signal; wherein the generation parameters include the timing of the first type of pulses, the timing and quantity of the second type of pulses in each segment of the sub-timing signal, and the number of segments n of the sub-timing signal.

[0099] Step S605 , when the direct current (DC) dimming mode is converted to the pulse width modulation (PWM) dimming mode, a non-uniform width pulse PWM signal is generated according to the generation parameters.

[0100] In an example, based on the description of the calculation method of the PWM dimming duty cycle in the above-mentioned related technology, Figure 4bFor example, each frame of PWM signal can be divided into two sub-timing signals, each of which can include 1 first-class pulse and 16 second-class pulses, and the first-class pulse is located at the head of the timing. Therefore, EM-4 can be a 32-pulse high-frequency PWM timing, and the high-level width of the first EM pulse and the high-level width of the 17th EM pulse are set to the minimum level width required for the pixel circuit scan, which can be 80h, and the high-level widths of the other 30 EM pulses are set to the minimum width required for the display panel timing, which can be 16h. Taking a total frame length of 2900h as an example, in high-brightness DC dimming, the duty cycle duty is 1-(80*2 / 2900)*100%=94.5%, and the duty cycle duty is 1-{(80*2+16*30) / 2900}*100%=77.9% in low-brightness high-frequency PWM dimming. According to the low-brightness high-frequency PWM dimming method in the above-mentioned related technology, the duty cycle duty is calculated to be 1-{(40*32) / 2900}*100%=55.9%. It can be seen that the non-equal-width pulse PWM signal provided in the embodiment of the present application can improve the lighting duty cycle duty, reduce the difference between the duty when switching with the high-brightness DC dimming, and reduce the flickering problem when switching between high-frequency PWM dimming and DC dimming. The schematic diagram of switching between high-frequency PWM dimming and DC dimming is shown in FIG. Figure 6b As shown, nit is the unit of display brightness. Similarly, the flicker problem when switching between high-frequency PWM dimming and low-frequency PWM dimming can also be reduced.

[0101] In one example, for Figure 4b The non-equal width pulse PWM signal shown can also be divided into two equal intervals, that is, each frame of PWM signal is divided into two segments of sub-timing signals, for example, 2 pulses can be used for high-brightness DC dimming, and 24 pulses, 30 pulses or 36 pulses can be used for low-brightness high-frequency PWM dimming. The high-level width of the first EM pulse and the high-level widths of the (24 / 3)*n+1, (30 / 3)*n+1, (36 / 3)*n+1 (n=1, 2, 3...) EM pulses can be set to the minimum level width required for pixel scanning, and the high-level widths of other EM pulses can be set to the minimum width required for the display panel timing. Similarly, it can also be set to 4, 5, 6, etc. according to actual needs, and this application does not make specific restrictions on this.

[0102] It should be noted that Figure 4b It is just a schematic diagram. In actual different refresh rates, the first-class pulses can also be extended with the same equal period within the same base frequency of 120 Hz. For example, there are 2 equal-period first-class pulses within 120 Hz, and 4 equal-period first-class pulses within 60 Hz. Figure 6c As shown, other refresh rates are similar.

[0103] The PWM signal setting of non-equal width pulses can also be well combined with LTPO scanning and reset compensation, which can not only reduce the duty of high-frequency PWM, but also meet the reset and compensation timing requirements of the non-scanning area. For example, some LTPS (Low Temperature Poly-Silicon) or LTPO use 8T1C (8 TFTs, 1 capacitor) pixel circuits. After charging is completed, there will be a pair of T3 transistors (here the same) in the holding interval. Figure 1 The reset compensation operation of the 7T1C pixel circuit shown in the figure also requires a certain period of EM high level. The use of PWM signal setting with non-equal width pulses can just make the reset compensation operation be performed in these wider high level EM. Figure 7 As shown, the scanning action is completed in the first width and height level EM of each sub-timing sequence, and the reset compensation can be performed in the equally divided width and height levels EM of the holding interval.

[0104] In the above-mentioned embodiment, the non-equal width pulse PWM signal setting, the wider EM pulse is distributed at equal positions in the time domain according to a certain period, which can be well combined with some actions of the OLED that need to be reset and compensated in the holding interval. In addition, the non-equal width wider EM pulse can also be adjusted to unequal positions according to actual needs, so that the wide level EM can be distributed in different frequency domains, dispersing the frequency domain energy of black insertion, which is beneficial to eye protection.

[0105] The present application also provides a display panel driving method. Figure 8a , including the following steps:

[0106] Step S801, in a PWM dimming mode, in a first brightness scene, generating a second non-equal width pulse PWM signal, wherein the second non-equal width pulse PWM signal includes a plurality of first type pulses and a plurality of second type pulses;

[0107] Step S802, scanning each row of pixel circuits in the display panel using the second non-uniform-width pulse PWM signal;

[0108] Step S803, when the first brightness scene is switched to the second brightness scene, a third non-equal width pulse PWM signal is generated, wherein the third non-equal width pulse PWM signal includes a plurality of first type pulses and a plurality of second type pulses;

[0109] Step S804, scanning each row of pixel circuits in the display panel using the third non-uniform-width pulse PWM signal;

[0110] Among them, the brightness of the scanned image in the first brightness scene is greater than the brightness of the scanned image in the second brightness scene; the number of second-type pulses in the second non-equal-width pulse PWM signal is less than the number of second-type pulses in the third non-equal-width pulse PWM signal, and the total width of the second-type pulses in the second non-equal-width pulse PWM signal is greater than the total width of the second-type pulses in the third non-equal-width pulse PWM signal.

[0111] In addition to high-low brightness DC and high-frequency PWM switching, non-uniform EM settings can also be used in different scenarios with different PWM Pulse configurations. In an example, special scene 1 (which can be AOD, i.e. Always On Display) uses 8Pulse, and normal display scene 2 uses 32Pulse. Then both scene 1 and scene 2 use non-uniform EM settings, such as Figure 8b As shown, the duty difference when switching between two scenes of PWM dimming can also be effectively reduced, and the switching flicker can be weakened.

[0112] The present application also provides a display device. Fig. 9 , the display device includes a display panel 1 and a display driver chip 2:

[0113] The display panel 1 includes a display module 12, and the display module 12 includes a plurality of pixel rows 121, and each of the pixel rows 121 includes a plurality of pixel circuits 1211;

[0114] The display driver chip 2 is used to: generate a non-equal width pulse PWM signal when converting from a DC dimming mode to a pulse width modulation PWM dimming mode, wherein the non-equal width pulse PWM signal includes a plurality of first-type pulses and a plurality of second-type pulses, the first-type pulses and the second-type pulses are both first-level signals, the pulse width of the first-type pulses is greater than the pulse width of the second-type pulses, and the pulse width of the first-type pulses is not less than the minimum level width for scanning or resetting the pixel circuit in the display panel; and use the non-equal width pulse PWM signal to scan the pixel circuits 1211 in each pixel row 121 in the display panel;

[0115] The specific analysis is the same as above and will not be repeated here.

[0116] The display module 12 is used to drive the pixel circuits 1211 in each pixel row 121 in response to the scanning of the non-uniform-width pulse PWM signal.

[0117] The specific analysis is the same as above and will not be repeated here.

[0118] The display panel is used to receive the non-equal width pulse PWM signal timing generated by the display driver chip, and completes the timing scanning and transmission of each row of pixels through its own driving circuit, thereby realizing the timing control and driving of non-equal width pulses.

[0119] In the embodiment of the present application, the duty cycle of PWM dimming can be increased in the case of high-frequency PWM by including multiple first-type pulses and multiple second-type pulses in the non-equal-width pulse PWM signal.

[0120] In a possible implementation, for each frame of non-equal-width pulse PWM signal, the frame of non-equal-width pulse PWM signal includes at least two sub-timing signals; for each sub-timing signal, the sub-timing signal includes one first-type pulse and multiple second-type pulses.

[0121] The specific analysis is the same as above and will not be repeated here.

[0122] In a possible implementation, the pulse width of the first type of pulse is a minimum level width for scanning or resetting a pixel circuit in the display panel, and the pulse width of the second type of pulse is a minimum width required by the timing of the display panel.

[0123] The specific analysis is the same as above and will not be repeated here.

[0124] In a possible implementation manner, the timing of the reset signal, the initialization signal, the charging signal, and the reset compensation signal of the pixel circuit is within the timing of the first type of pulses.

[0125] The specific analysis is the same as above and will not be repeated here.

[0126] In one possible implementation,

[0127] The display driver chip 2 is also used to obtain the number of pulses in each refreshed image frame, the pulse width of the first type of pulses, the pulse width of the second type of pulses, and the timing of the reset signal, initialization signal, charging signal and reset compensation signal of the pixel circuit; according to the timing of the reset signal, initialization signal, charging signal and reset compensation signal, and the pulse width of the first type of pulses, the number and timing of the first type of pulses are determined, wherein the timing of the reset signal, initialization signal, charging signal and reset compensation signal is within the timing of the first type of pulses, and the timing of the first type of pulses is uniform within the time of one image frame. Arrangement; according to the number and timing of the first type of pulses, a frame of the image is divided into n segments of sub-timing signals, wherein n is the number of the first type of pulses, and for each segment of the sub-timing signal, the sub-timing signal includes a first type of pulse, and is located at the timing head of the sub-timing signal; according to the number of pulses, the number of the first type of pulses and the pulse width of the second type of pulses, the timing and number of the second type of pulses in each segment of the sub-timing signal are determined to obtain the generation parameters of the PWM signal; wherein the generation parameters include the timing of the first type of pulses, the timing and number of the second type of pulses in each segment of the sub-timing signal, and the segment number n of the sub-timing signal;

[0128] The specific analysis is the same as above and will not be repeated here.

[0129] The settings in the display driver chip are as follows: 1. According to the specification requirements, set the number of pulses of EM, such as 12Pulse, 16Pulse, 24Pulse, 32Pulse, etc.

[0130] 2. According to the entire PWM timing duration determined by the resolution and porch time, the maximum EM duty is estimated manually, such as 66.67% in the above embodiment, and the corresponding parameters are set; and the duty adjustment change rule is set (the minimum number of increased steps, such as 4h, 8h, etc., evenly distributed in different pulses), and output to the display panel's own driving circuit.

[0131] 3. Output the scan-related signals according to the expected timing, and ensure that the scan-related signals are within the expected EM high level, such as the first EM high level.

[0132] The display driver chip 2 is specifically used for generating non-uniform width pulse PWM signals according to the generation parameters when the DC dimming mode is converted to the PWM dimming mode.

[0133] The specific analysis is the same as above and will not be repeated here.

[0134] In a possible implementation manner, the display driver chip 2 is further used for:

[0135] According to a preset scanning cycle, the pulse width of the second type of pulse in the non-equal width pulse PWM signal is increased by a preset width to obtain a current PWM signal; the current PWM signal is used to scan each row of pixel circuits in the display panel; and the execution step is returned: according to a preset scanning cycle, the pulse width of the second type of pulse in the non-equal width pulse PWM signal is increased, or the pulse widths of the first type of pulse and the second type of pulse in the non-equal width pulse PWM signal are increased to obtain the current PWM signal, until the brightness of the scanned image under the current PWM signal is the specified brightness.

[0136] The specific analysis is the same as above and will not be repeated here.

[0137] The display driver chip is used to generate non-uniform width pulse PWM signals and control the pulse width change rules in the PWM signals caused by the corresponding duty changes.

[0138] In a possible implementation manner, the display driver chip 2 is further used for:

[0139] In the PWM dimming mode, in a first brightness scene, a second non-equal-width pulse PWM signal is generated, wherein the second non-equal-width pulse PWM signal includes multiple first-type pulses and multiple second-type pulses; each row of pixel circuits in the display panel is scanned using the second non-equal-width pulse PWM signal; when the first brightness scene is switched to the second brightness scene, a third non-equal-width pulse PWM signal is generated, wherein the third non-equal-width pulse PWM signal includes multiple first-type pulses and multiple second-type pulses; each row of pixel circuits in the display panel is scanned using the third non-equal-width pulse PWM signal; wherein the brightness of the scanned image in the first brightness scene is greater than the brightness of the scanned image in the second brightness scene; the number of the second-type pulses in the second non-equal-width pulse PWM signal is less than the number of the second-type pulses in the third non-equal-width pulse PWM signal, and the total width of the second-type pulses in the second non-equal-width pulse PWM signal is greater than the total width of the second-type pulses in the third non-equal-width pulse PWM signal.

[0140] The specific analysis is the same as above and will not be repeated here.

[0141] The present application also provides a display panel 3, see Fig.10 , the display panel 3 includes:

[0142] A driving module 31 and a display module 32, wherein the display module 32 includes a plurality of pixel rows 321, and each pixel row 321 includes a plurality of pixel circuits 3211;

[0143] The driving module 31 is used to: generate a non-equal width pulse PWM signal when converting from a direct current (DC) dimming mode to a pulse width modulation (PWM) dimming mode, wherein the non-equal width pulse PWM signal includes a plurality of first-type pulses and a plurality of second-type pulses, the first-type pulses and the second-type pulses are both first-level signals, the pulse width of the first-type pulses is greater than the pulse width of the second-type pulses, and the pulse width of the first-type pulses is not less than the minimum level width for scanning or resetting the pixel circuit in the display panel; and use the non-equal width pulse PWM signal to scan the pixel circuits 3211 in each pixel row 321 in the display panel;

[0144] The display module 32 is used to drive the pixel circuits 3211 in each pixel row 321 in response to the scanning of the non-uniform-width pulse PWM signal.

[0145] In one possible implementation, see Fig.11 , the display panel 3 further includes:

[0146] The driving configuration module 33 is used to obtain the number of pulses in each refreshed image frame, the pulse width of the first type of pulses, the pulse width of the second type of pulses, and the timing of the reset signal, initialization signal, charging signal and reset compensation signal of the pixel circuit; according to the timing of the reset signal, initialization signal, charging signal and reset compensation signal, and the pulse width of the first type of pulses, the number and timing of the first type of pulses are determined, wherein the timing of the reset signal, initialization signal, charging signal and reset compensation signal is within the timing of the first type of pulses, and the timing of the first type of pulses is evenly arranged within the time of one image frame. According to the number and timing of the first type of pulses, a frame of the image is divided into n segments of sub-timing signals, wherein n is the number of the first type of pulses, and for each segment of the sub-timing signal, the sub-timing signal includes a first type of pulse, and is located at the timing head of the sub-timing signal; according to the number of pulses, the number of the first type of pulses and the pulse width of the second type of pulses, the timing and number of the second type of pulses in each segment of the sub-timing signal are determined to obtain the generation parameters of the PWM signal; wherein the generation parameters include the timing of the first type of pulses, the timing and number of the second type of pulses in each segment of the sub-timing signal, and the segment number n of the sub-timing signal;

[0147] The driving module 31 is specifically used for generating a non-uniform width pulse PWM signal according to the generation parameters when the DC dimming mode is converted to the PWM dimming mode.

[0148] In a possible implementation manner, the driving module 31 is further used for:

[0149] According to a preset scanning cycle, the pulse width of the second type of pulse in the non-equal width pulse PWM signal is increased by a preset width to obtain a current PWM signal; the current PWM signal is used to scan each row of pixel circuits in the display panel; and the execution step is returned: according to a preset scanning cycle, the pulse width of the second type of pulse in the non-equal width pulse PWM signal is increased, or the pulse widths of the first type of pulse and the second type of pulse in the non-equal width pulse PWM signal are increased to obtain the current PWM signal, until the brightness of the scanned image under the current PWM signal is the specified brightness.

[0150] In the embodiment of the present application, the display panel can generate an equal-width pulse PWM signal through its own driving module, and can set the number of EM pulses in different frames, the width of the EM pulses, etc. through its own driving configuration module.

[0151] In a possible implementation manner, the driving module 31 is further used for:

[0152] In the PWM dimming mode, in a first brightness scene, a second non-equal-width pulse PWM signal is generated, wherein the second non-equal-width pulse PWM signal includes multiple first-type pulses and multiple second-type pulses; each row of pixel circuits in the display panel is scanned using the second non-equal-width pulse PWM signal; when the first brightness scene is switched to the second brightness scene, a third non-equal-width pulse PWM signal is generated, wherein the third non-equal-width pulse PWM signal includes multiple first-type pulses and multiple second-type pulses; each row of pixel circuits in the display panel is scanned using the third non-equal-width pulse PWM signal; wherein the brightness of the scanned image in the first brightness scene is greater than the brightness of the scanned image in the second brightness scene; the number of the second-type pulses in the second non-equal-width pulse PWM signal is less than the number of the second-type pulses in the third non-equal-width pulse PWM signal, and the total width of the second-type pulses in the second non-equal-width pulse PWM signal is greater than the total width of the second-type pulses in the third non-equal-width pulse PWM signal.

[0153] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0154] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0155] The above description is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are included in the protection scope of the present application.

Claims

1. A display panel driving method, characterized in that: The method comprises: When converting from a direct current (DC) dimming mode to a pulse width modulation (PWM) dimming mode, generating a non-equal width pulse PWM signal, wherein the non-equal width pulse PWM signal includes a plurality of first-type pulses and a plurality of second-type pulses, the first-type pulses and the second-type pulses are both first-level signals, the pulse width of the first-type pulses is greater than the pulse width of the second-type pulses, and the pulse width of the first-type pulses is not less than the minimum level width of the pixel circuit in the display panel for scanning or resetting; The non-uniform-width pulse PWM signal is used to scan each row of pixel circuits in the display panel.

2. The method according to claim 1, characterized in that For each frame of non-equal width pulse PWM signal, the frame of non-equal width pulse PWM signal includes at least two sections of sub-timing signals; for each section of sub-timing signal, the sub-timing signal includes one first-type pulse and multiple second-type pulses.

3. The method according to claim 1, characterized in that The pulse width of the first type of pulse is the minimum level width for scanning or resetting the pixel circuit in the display panel, and the pulse width of the second type of pulse is the minimum width required by the timing of the display panel.

4. The method according to claim 1, characterized in that: The timing of the reset signal, the initialization signal, the charging signal and the reset compensation signal of the pixel circuit is within the timing of the first type of pulses.

5. The method according to claim 1, characterized in that The method further comprises: Obtaining the number of pulses in each refreshed image frame, the pulse width of the first type of pulses, the pulse width of the second type of pulses, and the timing of obtaining a reset signal, an initialization signal, a charging signal, and a reset compensation signal of the pixel circuit; Determine the number and timing of the first type of pulses according to the timing of the reset signal, the initialization signal, the charging signal and the reset compensation signal, and the pulse width of the first type of pulses, wherein the timing of the reset signal, the initialization signal, the charging signal and the reset compensation signal is within the timing of the first type of pulses, and the timing of the first type of pulses is evenly arranged within the time of one image frame; According to the number and timing of the first-type pulses, one image frame is divided into n segments of sub-timing signals, wherein n is the number of the first-type pulses, and for each segment of the sub-timing signal, the sub-timing signal includes a first-type pulse located at the timing head of the sub-timing signal; According to the number of pulses, the number of the first type of pulses and the pulse width of the second type of pulses, the timing and number of the second type of pulses in each segment of the sub-timing signal are determined to obtain generation parameters of the PWM signal; wherein the generation parameters include the timing of the first type of pulses, the timing and number of the second type of pulses in each segment of the sub-timing signal, and the number of segments n of the sub-timing signal; When the DC dimming mode is converted into the PWM dimming mode, a non-uniform width pulse PWM signal is generated, including: When the direct current (DC) dimming mode is converted to the pulse width modulation (PWM) dimming mode, a non-uniform width pulse PWM signal is generated according to the generation parameters.

6. The method according to claim 1, characterized in that After scanning each row of pixel circuits in the display panel using the non-uniform-width pulse PWM signal, the method further includes: According to a preset scanning cycle, the pulse width of the second type of pulses in the non-equal width pulse PWM signal is increased by a preset width to obtain a current PWM signal; Scanning each row of pixel circuits in the display panel using the current PWM signal; Return to the execution step: according to the preset scanning period, increase the pulse width of the second type of pulse in the non-equal width pulse PWM signal, or increase the pulse width of the first type of pulse and the second type of pulse in the non-equal width pulse PWM signal, to obtain the current PWM signal, until the brightness of the scanned image under the current PWM signal is the specified brightness.

7. The method according to claim 1, characterized in that The method further comprises: In the PWM dimming mode, in the first brightness scene, a second non-equal width pulse PWM signal is generated, wherein the second non-equal width pulse PWM signal includes a plurality of first type pulses and a plurality of second type pulses; Scanning each row of pixel circuits in the display panel using the second non-uniform-width pulse PWM signal; When the first brightness scene is switched to the second brightness scene, a third non-equal width pulse PWM signal is generated, wherein the third non-equal width pulse PWM signal includes a plurality of first type pulses and a plurality of second type pulses; Scanning each row of pixel circuits in the display panel using the third non-uniform-width pulse PWM signal; Among them, the brightness of the scanned image in the first brightness scene is greater than the brightness of the scanned image in the second brightness scene; the number of second-type pulses in the second non-equal-width pulse PWM signal is less than the number of second-type pulses in the third non-equal-width pulse PWM signal, and the total width of the second-type pulses in the second non-equal-width pulse PWM signal is greater than the total width of the second-type pulses in the third non-equal-width pulse PWM signal.

8. A display device, characterized in that: The display device includes a display panel and a display driver chip: The display panel comprises a display module, the display module comprises a plurality of pixel rows, each of the pixel rows comprises a plurality of pixel circuits; The display driver chip is used to: generate a non-equal width pulse PWM signal when converting from a direct current (DC) dimming mode to a pulse width modulation (PWM) dimming mode, wherein the non-equal width pulse PWM signal includes a plurality of first-type pulses and a plurality of second-type pulses, the first-type pulses and the second-type pulses are both first-level signals, the pulse width of the first-type pulses is greater than the pulse width of the second-type pulses, and the pulse width of the first-type pulses is not less than the minimum level width for scanning or resetting a pixel circuit in the display panel; and scan the pixel circuits in each pixel row in the display panel using the non-equal width pulse PWM signal; The display module is used to drive the pixel circuits in each pixel row in response to the scanning of the non-uniform width pulse PWM signal.

9. The display device according to claim 8, characterized in that: For each frame of non-equal width pulse PWM signal, the frame of non-equal width pulse PWM signal includes at least two sections of sub-timing signals; for each section of sub-timing signal, the sub-timing signal includes one first-type pulse and multiple second-type pulses.

10. The display device according to claim 8, characterized in that: The pulse width of the first type of pulse is the minimum level width for scanning or resetting the pixel circuit in the display panel, and the pulse width of the second type of pulse is the minimum width required by the timing of the display panel.

11. The display device according to claim 8, characterized in that The timing of the reset signal, the initialization signal, the charging signal and the reset compensation signal of the pixel circuit is within the timing of the first type of pulses.

12. The display device according to claim 8, characterized in that The display driver chip is further used to obtain the number of pulses in each refreshed image frame, the pulse width of the first type of pulses, the pulse width of the second type of pulses, and the timing of the reset signal, initialization signal, charging signal and reset compensation signal of the pixel circuit; according to the timing of the reset signal, initialization signal, charging signal and reset compensation signal, and the pulse width of the first type of pulses, the number and timing of the first type of pulses are determined, wherein the timing of the reset signal, initialization signal, charging signal and reset compensation signal is within the timing of the first type of pulses, and the timing of the first type of pulses is evenly arranged within the time of one image frame. According to the number and timing of the first type of pulses, a frame of the image is divided into n segments of sub-timing signals, wherein n is the number of the first type of pulses, and for each segment of the sub-timing signal, the sub-timing signal includes a first type of pulse, and is located at the timing head of the sub-timing signal; according to the number of pulses, the number of the first type of pulses and the pulse width of the second type of pulses, the timing and number of the second type of pulses in each segment of the sub-timing signal are determined to obtain the generation parameters of the PWM signal; wherein the generation parameters include the timing of the first type of pulses, the timing and number of the second type of pulses in each segment of the sub-timing signal, and the segment number n of the sub-timing signal; The display driver chip is specifically used to generate non-uniform width pulse PWM signals according to the generation parameters when converting from a direct current (DC) dimming mode to a pulse width modulation (PWM) dimming mode.

13. The display device according to claim 8, characterized in that The display driver chip is also used for: According to a preset scanning cycle, the pulse width of the second type of pulses in the non-equal width pulse PWM signal is increased by a preset width to obtain a current PWM signal; and the current PWM signal is used to scan each row of pixel circuits in the display panel; Return to the execution step: according to the preset scanning period, increase the pulse width of the second type of pulse in the non-equal width pulse PWM signal, or increase the pulse width of the first type of pulse and the second type of pulse in the non-equal width pulse PWM signal, to obtain the current PWM signal, until the brightness of the scanned image under the current PWM signal is the specified brightness.

14. The display device according to claim 8, characterized in that The display driver chip is also used for: In the PWM dimming mode, in a first brightness scene, a second non-equal-width pulse PWM signal is generated, wherein the second non-equal-width pulse PWM signal includes multiple first-type pulses and multiple second-type pulses; each row of pixel circuits in the display panel is scanned using the second non-equal-width pulse PWM signal; when the first brightness scene is switched to the second brightness scene, a third non-equal-width pulse PWM signal is generated, wherein the third non-equal-width pulse PWM signal includes multiple first-type pulses and multiple second-type pulses; each row of pixel circuits in the display panel is scanned using the third non-equal-width pulse PWM signal; wherein the brightness of the scanned image in the first brightness scene is greater than the brightness of the scanned image in the second brightness scene; the number of the second-type pulses in the second non-equal-width pulse PWM signal is less than the number of the second-type pulses in the third non-equal-width pulse PWM signal, and the total width of the second-type pulses in the second non-equal-width pulse PWM signal is greater than the total width of the second-type pulses in the third non-equal-width pulse PWM signal.

15. A display panel, characterized in that: The display panel comprises: A driving module and a display module, wherein the display module comprises a plurality of pixel rows, and each pixel row comprises a plurality of pixel circuits; The driving module is used to: generate a non-equal width pulse PWM signal when converting from a direct current (DC) dimming mode to a pulse width modulation (PWM) dimming mode, wherein the non-equal width pulse PWM signal includes a plurality of first-type pulses and a plurality of second-type pulses, the first-type pulses and the second-type pulses are both first-level signals, the pulse width of the first-type pulses is greater than the pulse width of the second-type pulses, and the pulse width of the first-type pulses is not less than the minimum level width for scanning or resetting the pixel circuit in the display panel; and use the non-equal width pulse PWM signal to scan the pixel circuits in each pixel row in the display panel; The display module is used to drive the pixel circuits in each pixel row in response to the scanning of the non-uniform width pulse PWM signal.

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