Pixel circuit and control method thereof, and display panel

Abstract

This application provides a pixel circuit and its control method, as well as a display panel, relating to the field of electronic equipment technology. By adding a control sub-circuit between the driving sub-circuit of the pixel circuit and the anode of the light-emitting device, the control sub-circuit can isolate the driving sub-circuit from the anode of the light-emitting device during the threshold voltage compensation process of each node coupled to the driving sub-circuit. This prevents the voltage used for threshold voltage compensation from continuing to flow to the anode of the light-emitting device and causing leakage. In this way, the effectiveness of threshold voltage compensation for each node coupled to the driving sub-circuit can be ensured, thereby improving the light leakage problem of sub-pixels when the driving sub-circuit drives the light-emitting device to emit light, and thus improving the brightness uniformity of sub-pixels when the display panel displays sub-pixels.

Description

Technical Field

[0001] This application relates to the field of electronic device technology, and in particular to a pixel circuit and its control method, and a display panel. Background Technology

[0002] With the rapid development of electronic device technology, users' demands for the display effect of electronic device screens are constantly increasing. However, in related technologies, the display panel of electronic devices still suffers from poor uniformity of sub-pixel brightness when refreshing and displaying images. Therefore, how to design a new type of pixel circuit to improve the uniformity of sub-pixel brightness has become an urgent technical problem to be solved in the field of electronic device technology. Summary of the Invention

[0003] This application provides a pixel circuit and its control method, as well as a display panel, aimed at improving the uniformity of display brightness of sub-pixels.

[0004] To achieve the above objectives, the embodiments of this application adopt the following technical solution: by adding a control circuit between the driving sub-circuit of the pixel circuit and the first pole of the light-emitting device of the display panel, and using the control circuit to isolate the driving circuit from the first pole of the light-emitting device during the compensation phase within a frame period, the effect of threshold voltage compensation for the nodes coupled to the driving sub-circuit is ensured, the light leakage problem of sub-pixels when the pixel circuit drives the light-emitting device to emit light is improved, and the brightness uniformity of the display panel for displaying sub-pixels is improved.

[0005] In a first aspect, a pixel circuit is provided. The pixel circuit is a pixel circuit in a display panel of an electronic device, and is coupled to the light-emitting device of the display panel. Specifically, the pixel circuit may include a driving sub-circuit, a first control sub-circuit, a second control sub-circuit, and a data writing sub-circuit. The control terminal of the first control sub-circuit is coupled to a first light-emitting control line, a first terminal of the first control sub-circuit is coupled to a first voltage terminal, and a second terminal of the first control sub-circuit is coupled to a second node. The control terminal of the driving sub-circuit is coupled to the first node, a first terminal of the driving sub-circuit is coupled to the second node, and a second terminal of the driving sub-circuit is coupled to a third node. The control terminal of the second control sub-circuit is coupled to a second light-emitting control line, a first terminal of the second control sub-circuit is coupled to the third node, and a second terminal of the second control sub-circuit is coupled to the first electrode of the light-emitting device. The second electrode of the light-emitting device is coupled to the voltage terminal. Furthermore, the control terminal of the data writing sub-circuit is coupled to a data writing control line, a first terminal of the data writing sub-circuit is coupled to a light-emitting data line, and a second terminal of the data writing sub-circuit is coupled to the first node.

[0006] In this application, the first control sub-circuit connects the first voltage terminal to the second node in response to the control signal provided by the first light-emitting control line. Thus, the operating voltage provided by the first voltage terminal will perform threshold voltage compensation on the driving sub-circuit through the first control sub-circuit. The second control sub-circuit connects the third node to the first electrode of the light-emitting device in response to the control signal provided by the second light-emitting control line. However, during the compensation phase, the second light-emitting control line does not provide a control signal, so the second control sub-circuit will keep the third node disconnected from the first electrode of the light-emitting device. Therefore, the voltage used by the first voltage terminal to perform threshold voltage compensation on the driving sub-circuit will not flow out from the second terminal of the driving sub-circuit. The data writing sub-circuit connects the light-emitting data line to the first node in response to the control signal provided by the data writing control line, so that the light-emitting data line writes the data voltage to the first node. During the light-emitting stage, the first light-emitting control line provides a control signal to connect the first control sub-circuit, thereby connecting the first voltage terminal to the second node. Simultaneously, the second light-emitting control line provides a control signal to connect the second control sub-circuit, thereby connecting the third node to the first electrode of the light-emitting device. This forms a series connection of the first voltage terminal, the first control sub-circuit, the driving sub-circuit, the second control sub-circuit, the light-emitting device, and the second voltage terminal. The driving sub-circuit controls the current switch based on the data voltage at the first node, thereby generating a driving current in this path to drive the light-emitting device to emit light.

[0007] In one feasible embodiment of the first aspect, the driving sub-circuit may include at least one driving transistor for generating a driving current to drive the light-emitting device to emit light. When the driving sub-circuit includes a driving transistor, the control electrode of the driving transistor is coupled to a first node, the first electrode of the driving transistor is coupled to a second node, and the second electrode of the driving transistor is coupled to a third node. Thus, when the potential on the first node changes to a data voltage during the light-emitting phase, the driving transistor generates a driving current to drive the light-emitting device to emit light based on the data voltage.

[0008] In one feasible embodiment of the first aspect, the first control sub-circuit includes at least one first transistor. When the first control sub-circuit includes a first transistor, the control electrode of the first transistor is coupled to a first light-emitting control line, the first terminal of the first transistor is coupled to a first voltage terminal, and the second terminal of the first transistor is coupled to a second node. During the compensation phase and the light-emitting phase, the first light-emitting control line provides a control signal to the control electrode of the first transistor, and the first transistor responds to the control signal by connecting the first voltage terminal to the second node.

[0009] In one feasible embodiment of the first aspect, the second control sub-circuit includes at least one second transistor. When the second control sub-circuit includes a second transistor, the control electrode of the second transistor is coupled to a second light-emitting control line, the first electrode of the second transistor is coupled to a third node, and the second electrode of the second transistor is coupled to the first electrode of the light-emitting device. During the light-emitting phase, the second light-emitting control line provides a control signal to the control electrode of the second transistor, and the second transistor responds to the control signal by connecting the third node to the first electrode of the light-emitting device, thereby constituting a circuit consisting of a first voltage terminal, a first transistor, a driving transistor, a second transistor, a light-emitting device, and a voltage terminal.

[0010] The driving current generated by the driving transistor can then enter the light-emitting device through the second transistor. Furthermore, during the compensation phase, the second light-emitting control line does not provide a control signal to turn on the second transistor; therefore, the second transistor will remain off to disconnect the third node from the first electrode of the light-emitting device.

[0011] In one feasible embodiment of the first aspect, the data input sub-circuit includes at least one third transistor. When the data writing sub-circuit includes a third transistor, the control electrode of the third transistor is coupled to a data writing control line, the first electrode of the third transistor is coupled to a light-emitting data line, and the second electrode of the third transistor is coupled to a first node. During the data writing phase, the data writing control line provides a control signal to the control electrode of the third transistor, and the third transistor responds to the control signal to connect the light-emitting data line to the first node, so that the light-emitting data line can write data voltage to the first node.

[0012] In one feasible embodiment of the first aspect, the pixel circuit may further include a first reset sub-circuit and a second reset sub-circuit. The control terminal of the first reset sub-circuit is coupled to a first reset control line, a first terminal of the first reset sub-circuit is coupled to a first voltage line, and a second terminal of the first reset sub-circuit is coupled to a first node. The control terminal of the second reset sub-circuit is coupled to a second reset control line, a first terminal of the second reset sub-circuit is coupled to a second voltage line, and a second terminal of the second reset sub-circuit is coupled to a third node.

[0013] In this application, a first reset sub-circuit responds to a control signal provided by a first reset control line to connect a first voltage line to a first node, thereby writing a first voltage provided by the first voltage line into the first node and resetting the first node. Furthermore, a second reset sub-circuit responds to a control signal provided by a second reset control line to connect a second voltage line to a third node, thereby writing a second voltage provided by the second voltage line into the third node and resetting the third node.

[0014] In one feasible embodiment of the first aspect, the first reset sub-circuit includes at least one fourth transistor. When the first reset sub-circuit includes a fourth transistor, the control electrode of the fourth transistor is coupled to a first reset control line, the first electrode of the fourth transistor is coupled to a first voltage line, and the second electrode of the fourth transistor is coupled to a first node. During the reset phase, the first reset control line provides a control signal to the control electrode of the fourth transistor, and the fourth transistor responds to the control signal by connecting the first voltage line to the first node, so that the first voltage line writes a first voltage to the first node to reset the first node.

[0015] In one feasible embodiment of the first aspect, the second reset sub-circuit includes at least one fifth transistor. When the second reset sub-circuit includes a fifth transistor, the control electrode of the fifth transistor is coupled to a second reset control line, while the first electrode of the fifth transistor is coupled to a second voltage line, and the second electrode of the fifth transistor is coupled to a third node. During the reset phase, the second reset control line provides a control signal to the control electrode of the fifth transistor, and the fifth transistor responds to the control signal by connecting the second voltage line to the third node, so that the second voltage line writes a second voltage to the third node to reset the third node.

[0016] In one feasible embodiment of the first aspect, the pixel circuit further includes a bootstrap circuit. A first terminal of the bootstrap circuit is coupled to a first node, and a second terminal of the bootstrap circuit is coupled to a third node. When a voltage change occurs at the first node, the bootstrap circuit also raises the voltage at the third node.

[0017] In this application, when the voltage at the first node changes, the bootstrap circuit automatically raises the voltage at the third node. This allows the driving circuit to compensate for the threshold voltage remaining at the third node when generating the driving current based on the voltage at the first node during the light-emitting phase. This improves the uniformity of brightness of the light-emitting device driven by the pixel circuit.

[0018] In one feasible embodiment of the first aspect, when the bootstrap circuit includes a first capacitor, the first plate of the first capacitor is coupled to a first node, and the second plate of the first capacitor is coupled to a third node. When the voltage of the first node changes, the first capacitor automatically raises the voltage of the third node.

[0019] In one feasible embodiment of the first aspect, the pixel circuit further includes a third reset sub-circuit. The control terminal of the third reset sub-circuit is coupled to a second reset control line, a first terminal of the third reset sub-circuit is coupled to a third voltage line, and a second terminal of the third reset sub-circuit is coupled to a fourth node; the fourth node is coupled to a light-emitting device. The third reset sub-circuit responds to a control signal provided by the second reset control line to connect the third voltage line to the fourth node, thereby writing the third voltage provided by the third voltage line into the fourth node and resetting the fourth node.

[0020] In one feasible embodiment of the first aspect, the third reset sub-circuit includes at least one sixth transistor. The control electrode of the sixth transistor is coupled to a second reset control line, the first electrode of the sixth transistor is coupled to a third voltage line, and the second electrode of the sixth transistor is coupled to a fourth node. When the second reset control line provides a control signal to the control electrode of the sixth transistor, the sixth transistor, in response to the control signal, connects the third voltage line to the fourth node, thereby writing the third voltage provided by the third voltage line into the fourth node.

[0021] In one feasible embodiment of the first aspect, the pixel circuit further includes a first isolation sub-circuit, a second isolation sub-circuit, a third control sub-circuit, and a fourth reset sub-circuit. The control terminal of the third control sub-circuit is coupled to a second light-emitting control line, a first terminal of the third control sub-circuit is coupled to a first node, a second terminal of the third control sub-circuit is coupled to a fifth node, and the fifth node is coupled to a second terminal of a data writing sub-circuit. The first terminal of the first isolation sub-circuit is coupled to the fifth node, and the second terminal of the first isolation sub-circuit is coupled to a sixth node; the first terminal of the second isolation sub-circuit is coupled to the sixth node, and the second terminal of the second isolation sub-circuit is coupled to the third node. The control terminal of the fourth reset sub-circuit is coupled to a first reset control line, a first terminal of the fourth reset sub-circuit is coupled to a first voltage line, and the second terminal of the fourth reset sub-circuit is coupled to the sixth node.

[0022] In this application, the fourth reset sub-circuit, in response to the control signal provided by the first reset control line, continuously writes the first voltage provided by the first voltage line into the sixth node. The third control sub-circuit, in response to the control signal provided by the second light emission control line, connects the fifth node to the first node. The first isolation sub-circuit is located between the fifth node and the sixth node to isolate the fifth node from the sixth node. Furthermore, the second isolation sub-circuit is located between the sixth node and the third node to isolate the sixth node from the third node.

[0023] In one feasible embodiment of the first aspect, the first isolation sub-circuit includes at least one second capacitor. A first plate of the second capacitor is coupled to a fifth node, and a second plate of the second capacitor is coupled to a sixth node, thereby isolating the fifth node from the sixth node so that a first voltage written to the sixth node does not affect the data voltage written to the fifth node.

[0024] In one feasible embodiment of the first aspect, the second isolation sub-circuit includes at least one third capacitor. The first plate of the third capacitor is coupled to the sixth node, and the second plate of the third capacitor is coupled to the third node. Thus, the third capacitor also isolates the sixth node from the third node.

[0025] In one feasible embodiment of the first aspect, the third control sub-circuit includes at least one seventh transistor. The control electrode of the seventh transistor is coupled to a second light-emitting control line, the first electrode of the seventh transistor is coupled to a first node, and the second electrode of the seventh transistor is coupled to a fifth node. During the light-emitting phase, the second light-emitting control line provides a control signal to the control electrode of the seventh transistor, and the seventh transistor responds to the control signal to connect the fifth node to the first node, thereby allowing the data voltage on the fifth node to be written to the first node through the seventh transistor.

[0026] In one feasible embodiment of the first aspect, the fourth reset sub-circuit includes at least one eighth transistor. The control electrode of the eighth transistor is coupled to a first reset control line, the first electrode of the eighth transistor is coupled to a first voltage line, and the second electrode of the eighth transistor is coupled to a sixth node. During the reset phase, the first reset control line provides a control signal to the control electrode of the eighth transistor, and the eighth transistor responds to the control signal by connecting the first voltage line to the sixth node, so that the first voltage line writes a first voltage to the sixth node to reset the sixth node.

[0027] In one feasible embodiment of the first aspect, the pixel circuit further includes an energy storage sub-circuit. A first terminal of the energy storage sub-circuit is coupled to a second node, and a second terminal of the energy storage sub-circuit is coupled to a third node. Thus, the energy storage sub-circuit can maintain the potential of the second node and the potential of the third node by a preset fixed voltage.

[0028] In another feasible embodiment of the first aspect, the first terminal of the energy storage sub-circuit can also be coupled to the first voltage terminal, and the second terminal of the energy storage sub-circuit is also coupled to the third node. Based on this, the energy storage sub-circuit can proportionally raise the voltage of the third node according to the operating voltage provided by the first voltage terminal, thereby maintaining the potential of the third node.

[0029] In one feasible embodiment of the first aspect, the energy storage sub-circuit includes at least one fourth capacitor. The first plate of the fourth capacitor is coupled to the second node, and the second plate of the fourth capacitor is coupled to the third node. In this case, the fourth capacitor can simultaneously maintain the potentials of both the second and third nodes. Alternatively, the first plate of the fourth capacitor may also be coupled to a first voltage terminal, while the second plate of the fourth capacitor remains coupled to the third node. In this case, the fourth capacitor can maintain the potential of the third node.

[0030] In this application, maintaining the potentials of the second and third nodes using a fourth capacitor, or vice versa, allows control over the influence of the data voltage on the drive current generated by the driving transistor. Therefore, adjusting the size of the fourth capacitor allows adjustment of the data voltage required for the driving transistor to generate the drive current. Thus, based on the different voltage output capabilities of the light-emitting data lines on different display panels, the pixel circuit can adjust the size of the fourth capacitor to provide a compatible data voltage for the driving transistor to generate the drive current. In other words, the pixel circuit's drive current for the light-emitting device is more stable and reliable.

[0031] Secondly, a pixel circuit control method is provided, which is mainly applied to the pixel circuit described in any of the above embodiments. During a frame cycle of image refresh display on the display panel, after the pixel circuit enters the enabled state based on the working voltage provided by the first voltage terminal, during the compensation phase of the frame cycle, the first light-emitting control line provides a control signal, and the first control sub-circuit responds to the control signal by connecting the first voltage terminal to the second node. Thus, the working voltage provided by the first voltage terminal will perform threshold voltage compensation on the driving sub-circuit through the first control sub-circuit. Furthermore, during the compensation phase, the second light-emitting control line does not provide a control signal to control the second control sub-circuit to connect, so the third node remains disconnected from the first electrode of the light-emitting device. Therefore, the voltage used by the first voltage terminal to perform threshold voltage compensation on the driving sub-circuit will not flow out from the second terminal of the driving sub-circuit. Subsequently, during the data writing phase, the data writing control line provides a control signal to the control terminal of the data writing sub-circuit, and the data writing sub-circuit responds to the control signal by connecting the light-emitting data line to the first node, thereby writing the data voltage onto the first node. Subsequently, during the light-emitting stage, the first control sub-circuit provides a control signal to its control terminal, and the second light-emitting control line provides a control signal to its control terminal. Both the first and second control sub-circuits respond to their respective control signals, connecting the first voltage terminal to the second node and the third node to the first electrode of the light-emitting device, respectively. Furthermore, the driving sub-circuit generates a driving current based on the data voltage at the first node. This driving current then flows through the third node, the second control sub-circuit, and the first electrode of the light-emitting device into the device, driving it to emit light.

[0032] In this application, since the voltage used for threshold voltage compensation of the driving sub-circuit at the first voltage terminal during the compensation phase will not flow out from the second terminal of the driving sub-circuit, there will be no leakage problem at the second terminal of the driving sub-circuit during the compensation phase. Therefore, the first voltage terminal will better compensate the threshold voltage of the driving sub-circuit, thereby improving the uniformity of brightness of the light-emitting device driven by the pixel circuit. For the display panel, when using this pixel circuit to drive the light-emitting device to refresh and display image pixels, the uniformity of the display brightness of the image pixels can be effectively improved. In other words, by connecting the first voltage terminal and the second node connected to the driving sub-circuit via the first control sub-circuit during the compensation phase, and disconnecting the third node connected to the driving sub-circuit and the first electrode of the light-emitting device via the second control sub-circuit, the pixel circuit can improve the uniformity of brightness of the image pixels displayed by the display panel.

[0033] In one feasible embodiment of the second aspect, during the reset phase within a frame period, a first reset control line provides a control signal to the control terminal of a first reset sub-circuit. The first reset sub-circuit responds to the control signal to connect a first voltage line to a first node, thereby writing a first voltage provided by the first voltage line into the first node, thus resetting the first node. Furthermore, during the reset phase, a second reset control line provides a control signal to the control terminal of a second reset sub-circuit. The second reset sub-circuit responds to the control signal to connect a second voltage line to a third node, thereby writing a second voltage provided by the second voltage line into the third node, thus resetting the third node.

[0034] Furthermore, during the reset phase, the second light-emitting control line also sends a control signal to the control terminal of the second control sub-circuit. The second control sub-circuit responds to the control signal by connecting the third node to the first electrode of the light-emitting device. Thus, the second voltage written to the third node by the second voltage line is further written to the first electrode of the light-emitting device, thereby resetting the first electrode of the light-emitting device.

[0035] In this application, during the reset phase, by simultaneously resetting the first and third nodes connected to the driving sub-circuit, the residual voltage at these two nodes during the light-emitting phase can be avoided from affecting the driving current generated by the driving sub-circuit in the next frame cycle. This ensures that the driving sub-circuit can accurately generate the current to drive the light-emitting device in each frame cycle, thereby guaranteeing the stability of the light-emitting device's brightness. Furthermore, during the reset phase, the voltage written to the third node is synchronized to the first electrode of the light-emitting device to reset the first electrode as well. This avoids the residual voltage of the light-emitting device itself after the light-emitting phase ends from interfering with the light-emitting response of the driving sub-circuit in the next light-emitting phase, thereby further ensuring the stability of the light-emitting device's brightness.

[0036] In a feasible embodiment of the second aspect, when the pixel circuit includes a third reset sub-circuit, during the reset phase, the second reset control line provides a control signal to the control terminal of the third reset sub-circuit. The third reset sub-circuit responds to this control signal by controlling the third voltage line to connect with the first electrode of the light-emitting device, thereby writing the third voltage provided by the third voltage line into the first electrode of the light-emitting device and resetting the first electrode of the light-emitting device. Furthermore, when the pixel circuit includes a third reset sub-circuit, the second light-emitting control line does not provide a control signal to connect the second control sub-circuit, thus keeping the third node disconnected from the first electrode of the light-emitting device during the reset phase.

[0037] In a feasible embodiment of the second aspect, where the pixel circuit further includes a first isolation sub-circuit, a second isolation sub-circuit, a third control sub-circuit, and a fourth reset sub-circuit, the pixel circuit can perform data writing operations during the compensation phase. That is, during the compensation phase, the first reset control line provides control signals to the control terminals of the first and fourth reset sub-circuits, causing the first reset sub-circuit to continuously write the first voltage provided by the first voltage line to the first node, and the fourth reset sub-circuit to continuously write the first voltage provided by the first voltage line to the sixth node. However, since the second light-emitting control line does not provide control signals to connect the third control sub-circuit during the compensation phase, the fifth node and the first node remain disconnected during the compensation phase. Therefore, the first voltage line writing the first voltage to the first node will not affect the voltage on the fifth node. Furthermore, since the first isolation sub-circuit is located between the fifth and sixth nodes, it isolates the fifth and sixth nodes, and the second isolation sub-circuit also isolates the sixth node from the third node. Therefore, the first voltage line writing the first voltage to the sixth node will not affect the voltage on the fifth node. Therefore, during the compensation phase, the data writing sub-circuit can connect the light-emitting data line to the fifth node in response to the control signal provided by the data writing control line, so that the light-emitting data line can write the data voltage to the fifth node. Then, during the light-emitting phase, since both the first and second light-emitting control lines provide control signals, the third control sub-circuit will connect the first node to the fifth node. Thus, the data voltage at the fifth node will be transmitted to the first node through the third control sub-circuit, allowing the driving sub-circuit to generate the driving current to drive the light-emitting device. Furthermore, since the first reset control line does not provide a control signal to connect the fourth reset sub-circuit during the light-emitting phase, there will be no first voltage written by the first voltage line at the sixth node. Therefore, the first isolation sub-circuit and the second isolation sub-circuit will couple into a bootstrap sub-circuit to automatically raise the voltage at the third node when the voltage at the first node changes.

[0038] Thirdly, a display panel is provided, the display panel including a plurality of sub-pixels, each sub-pixel including a pixel circuit and a light-emitting device interconnected with each other, the pixel circuit being the pixel circuit described in any embodiment of the first aspect above.

[0039] Fourthly, a display panel is provided, comprising a plurality of sub-pixels, each sub-pixel including interconnected pixel circuitry and light-emitting devices. When the display panel is in operation, the pixel circuitry performs the method described in any embodiment of the second aspect above.

[0040] Fifthly, an electronic device is provided. The electronic device includes: a display panel, a processor, and a memory, wherein the display panel includes a plurality of sub-pixels, each sub-pixel including interconnected pixel circuitry and light-emitting devices, the pixel circuitry being as described in any embodiment of the first aspect above.

[0041] In a sixth aspect, an electronic device is provided. The electronic device includes: a display panel, a processor, and a memory, the processor being coupled to the memory; the memory is used to store computer program code; the computer program code includes computer instructions, which, when executed by the processor, cause pixel circuits in the display panel to perform the method described in any embodiment of the second aspect above.

[0042] In a seventh aspect, this application provides a computer-readable storage medium storing computer instructions that, when executed on an electronic device, cause the pixel circuitry of the display panel of the electronic device to perform the method described in any of the embodiments of the second aspect above.

[0043] Eighthly, this application provides a computer program product containing instructions that, when run on an electronic device, enable the pixel circuitry of the display panel of the electronic device to perform the method described in any of the embodiments of the second aspect above.

[0044] A ninth aspect provides an apparatus including a processor for supporting pixel circuitry of a display panel of an electronic device in implementing the functions corresponding to the method described in any embodiment of the second aspect. In one possible design, the apparatus further includes a memory for storing program instructions and data necessary for the electronic device.

[0045] The technical effects of any of the design methods in aspects three through nine can be found in the technical effects of different implementation methods in aspect two, and will not be repeated here. Attached Figure Description

[0046] Figure 1 This is a schematic diagram of a pixel circuit involved in an embodiment of this application;

[0047] Figure 2 for Figure 1 The diagram shows the transistor structure corresponding to the pixel circuit.

[0048] Figure 3 This is a schematic diagram of a pixel circuit including an energy storage sub-circuit according to an embodiment of this application;

[0049] Figure 4 for Figure 3 The diagram shows the transistor structure corresponding to the pixel circuit.

[0050] Figure 5 This is a schematic diagram of another structure of the pixel circuit including the energy storage sub-circuit involved in the embodiments of this application;

[0051] Figure 6 for Figure 5 The diagram shows the transistor structure corresponding to the pixel circuit.

[0052] Figure 7 This is a schematic diagram showing the range variation of the data voltage Vdata corresponding to the pixel circuit involved in the embodiments of this application;

[0053] Figure 8 This is a schematic diagram of the voltage across the operating voltage provided by VDD when the pixel circuit involved in the embodiment of this application generates a small driving current;

[0054] Figure 9 This is a schematic diagram of the voltage across the operating voltage provided by VDD when the pixel circuit generates the driving current in the embodiment of this application.

[0055] Figure 10 This is a schematic diagram of the voltage across the operating voltage provided by VDD when the pixel circuit involved in the embodiment of this application generates a large driving current;

[0056] Figure 11 This is a schematic diagram of the pixel circuit, including a first reset circuit and a second reset circuit, as described in an embodiment of this application.

[0057] Figure 12 for Figure 11 The diagram shows the transistor structure corresponding to the pixel circuit.

[0058] Figure 13 This is a schematic diagram of the pixel circuit including the bootstrap circuit in an embodiment of this application;

[0059] Figure 14 for Figure 13 The diagram shows the transistor structure corresponding to the pixel circuit.

[0060] Figure 15 This is a schematic diagram of the first control timing of the pixel circuit involved in an embodiment of this application;

[0061] Figure 16 This is a schematic diagram of the pixel circuit including the third reset sub-circuit in an embodiment of this application;

[0062] Figure 17 for Figure 16 The diagram shows the transistor structure corresponding to the pixel circuit.

[0063] Figure 18 This is a second control timing diagram of the pixel circuit involved in an embodiment of this application;

[0064] Figure 19 This is a schematic diagram of the pixel circuit involved in the embodiments of this application, including a third control sub-circuit, a fourth reset sub-circuit, a first isolation sub-circuit, and a second isolation sub-circuit.

[0065] Figure 20 for Figure 19 The diagram shows the transistor structure corresponding to the pixel circuit.

[0066] Figure 21 This is a schematic diagram of the third control timing of the pixel circuit involved in the embodiments of this application. Detailed Implementation

[0067] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application are within the scope of protection of this application.

[0068] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0069] In describing some embodiments, the terms "coupled," "connected," "linked," and their derivatives may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components are in direct or indirect physical contact with each other. For example, "A and B are connected" can mean that A and B are connected directly, or it can mean that A and B are connected through other components. In addition, the term "coupled" can also refer to an electrical connection that enables signal transmission.

[0070] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0071] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0072] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0073] It should be noted that all transistors involved in the embodiments of this application can be thin-film transistors (TFTs). It should be understood that, based on different design needs in practical applications, in some feasible embodiments, the transistor constituting the pixel circuit can of course also be a thin-film transistor, field-effect transistor, metal-oxide-semiconductor field-effect transistor (MOSFET), or other electronic devices with the same characteristics, other than oxide TFTs. For ease of explanation and understanding, the embodiments of this application will be described using oxide TFTs as an example. Therefore, in the embodiments of this application, the gate of the oxide TFT is collectively referred to as the control electrode, and to distinguish the two electrodes of the oxide TFT other than the gate, one electrode is referred to as the first electrode, and the other as the second electrode. For example, the first electrode of the transistor can be the drain of the oxide TFT, and the second electrode of the transistor can be the source of the oxide TFT; or, the first electrode of the transistor can also be the source of the oxide TFT, and the second electrode of the transistor can be the drain of the oxide TFT.

[0074] Furthermore, all transistors involved in the embodiments of this application can be N-type oxide TFTs. Alternatively, in the transistors involved in the embodiments of this application, the driving transistor TD used to generate the driving current is an N-type oxide TFT, while the other transistors besides the driving transistor TD are all P-type oxide TFTs. For ease of explanation and understanding, the embodiments of this application will be described below using an example where all transistors are N-type oxide TFTs. As for the implementation process of the embodiments of this application where the driving transistor TD is an N-type oxide TFT and the other transistors are P-type oxide TFTs, it is only necessary to swap the high and low levels of the control signals corresponding to the timing of the pixel circuit one by one. The remaining operations are basically the same as the operation of the pixel circuit driving the light-emitting device to emit light when all transistors are N-type oxide TFTs, as described below.

[0075] Before introducing the embodiments of this application, a brief overview of the overall concept of the technical solutions involved in the embodiments of this application will be provided here.

[0076] Nowadays, with the rapid development of electronic device technology, users' demands for the display effect of electronic device screens are constantly increasing. However, when display panels of electronic devices refresh and display images, uneven brightness of different sub-pixels in the display area often occurs, meaning the uniformity of the display panel's control over the brightness of sub-pixels is poor. To improve the uniformity of sub-pixel brightness, related technologies mainly rely on oxide TFTs to develop pixel circuits for display panels, utilizing the low leakage current characteristic of oxide TFTs to improve the uniformity of sub-pixel brightness. However, even pixel circuits developed using oxide TFTs still exhibit leakage current. Furthermore, because related technologies cannot effectively control this leakage current, the problem of poor uniformity in sub-pixel brightness persists.

[0077] To address the issue of poor brightness uniformity in sub-pixel display on display panels, this application proposes a pixel circuit and its control method. By adding a control sub-circuit between the driving sub-circuit of the pixel circuit and the anode of the light-emitting device, the control sub-circuit can isolate the driving sub-circuit from the anode of the light-emitting device during threshold voltage compensation. This prevents the voltage used for threshold voltage compensation from flowing to the anode of the light-emitting device and causing leakage. Thus, the effectiveness of threshold voltage compensation for the driving sub-circuit is ensured, improving the light leakage problem of sub-pixels and enhancing the brightness uniformity of sub-pixels when the display panel displays them.

[0078] Based on the overall concept of the technical solutions involved in the embodiments of this application, the specific implementation methods of the pixel circuit and its control method provided in the embodiments of this application will be further described in detail.

[0079] In this embodiment, the pixel circuit provided is a pixel circuit in the display panel of an electronic device. The pixel circuit is coupled to the light-emitting device of the display panel. After the pixel circuit enters the enabled state based on the working voltage provided by the power supply voltage terminal on the display panel, it generates a driving current to drive the light-emitting device to emit light. In this way, the display panel can refresh the display of sub-pixels. It should be noted that the electronic devices involved in this embodiment may include, but are not limited to, mobile phones, tablet computers, laptops, handheld computers, netbooks, personal digital assistants (PDAs), wearable electronic devices, virtual reality devices, and other terminal devices that have a display panel and have the function of refreshing and displaying images through the display panel. In addition, the light-emitting device involved in this embodiment may be an organic light-emitting diode (OLED), or it may be a light-emitting diode (LED), etc. The anode of the light-emitting device is collectively referred to as the first electrode, and the cathode of the light-emitting device is collectively referred to as the second electrode. For example, when the light-emitting device is specifically an OLED, the anode of the OLED is called the first electrode, and the cathode of the OLED is called the second electrode. Furthermore, in this embodiment, the power supply voltage terminals on the display panel include a first voltage terminal VDD and a second voltage terminal VSS, wherein the voltage value provided by the first voltage terminal VDD is higher than the voltage value provided by the second voltage terminal VSS. It should be understood that, based on different application requirements, the voltage values ​​provided by the first voltage terminal VDD and the second voltage terminal VSS can naturally be different in different implementations. This embodiment does not specifically limit the voltage values ​​provided by the first voltage terminal VDD and the second voltage terminal VSS.

[0080] Furthermore, in this embodiment, the pixel circuit control method provided is mainly applied to the pixel circuit provided in this embodiment. That is, when the display panel of an electronic device refreshes and displays any image, the pixel circuit in the display panel can execute the pixel circuit control method provided in this embodiment. Within one frame cycle of the display panel refreshing and displaying the image, firstly, in the reset phase, each node connected to the driving sub-circuit is reset, thereby eliminating the residual potential of each node after the driving sub-circuit drives the light-emitting device to emit light in the previous frame cycle, thus improving the hysteresis phenomenon when the driving sub-circuit drives the light-emitting device to emit light in the next frame cycle. Then, in the compensation phase, threshold voltage compensation is performed on the driving sub-circuit to avoid threshold voltage deviation and the brightness decay of the light-emitting device caused by voltage drop in the driving sub-circuit. Then, in the data writing phase, data voltage is written to the control terminal of the driving sub-circuit. Finally, in the light emission phase, a driving current is generated in the pixel circuit based on the data voltage at the control terminal of the driving sub-circuit to drive the light-emitting device of the display panel to emit light.

[0081] In some embodiments, the pixel circuit may include a driving sub-circuit, a first control sub-circuit, a second control sub-circuit, and a data writing sub-circuit. The driving sub-circuit may include an N-type oxide TFT. The first control sub-circuit, the second control sub-circuit, and the data writing sub-circuit may each include either an N-type oxide TFT or a P-type oxide TFT.

[0082] like Figure 1 As shown, in the pixel circuit, the control terminal of the first control sub-circuit 210 is coupled to the first light-emitting control line EM1, the first terminal of the first control sub-circuit 210 is coupled to the first voltage terminal VDD, and the second terminal of the first control sub-circuit 210 is coupled to the second node N2.

[0083] The control terminal of the drive sub-circuit 110 is coupled to the first node N1, the first terminal of the drive sub-circuit 110 is coupled to the second node N2, and the second terminal of the drive sub-circuit 110 is coupled to the third node N3.

[0084] The control terminal of the second control sub-circuit 220 is coupled to the second light-emitting control line EM2. The first terminal of the second control sub-circuit 220 is coupled to the third node N3. The second terminal of the second control sub-circuit 220 is coupled to the first electrode of the light-emitting device 310. The second electrode of the light-emitting device 310 is coupled to the second voltage terminal VSS.

[0085] The control terminal of the data writing sub-circuit 410 is coupled to the data writing control line Gate, the first terminal of the data writing sub-circuit 410 is coupled to the light-emitting data line Data, and the second terminal of the data writing sub-circuit 410 is coupled to the first node N1.

[0086] Based on this, when the pixel circuit executes the pixel circuit control method provided in the embodiments of this application, during the compensation phase within the aforementioned frame period, the first light-emitting control line EM1 provides a control signal to the control terminal of the first control sub-circuit 210, and the first control sub-circuit 210 responds to the control signal by connecting the first voltage terminal VDD with the second node N2. Furthermore, during the compensation phase, the second light-emitting control line EM2 provides a control signal to the control terminal of the second control sub-circuit 220 to control the second control sub-circuit 220 to disconnect, thereby the second control sub-circuit 220 responds to the control signal by keeping the third node N3 disconnected from the first electrode of the light-emitting device 310. Subsequently, during the data writing phase, the data writing control line Gate provides a control signal to the control terminal of the data writing sub-circuit 410, and the data writing sub-circuit 410 responds to the control signal by connecting the light-emitting data line Data with the first node N1. Subsequently, during the light-emitting stage, the first light-emitting control line EM1 provides a control signal to the control terminal of the first control sub-circuit 210, and the second light-emitting control line EM2 also provides a control signal to the control terminal of the second control sub-circuit 220. Thus, the first control sub-circuit 210, in response to the control signal provided by the first light-emitting control line EM1, connects the first voltage terminal VDD to the second node N2, and the second control sub-circuit 220, in response to the control signal provided by the second light-emitting control line EM2, connects the third node N3 to the first electrode of the light-emitting device 310, thereby forming a circuit in which the first voltage terminal VDD, the first control sub-circuit 210, the driving sub-circuit 110, the second control sub-circuit 220, the light-emitting device 310, and the second voltage terminal VSS are connected in series. In this way, the driving sub-circuit 110 can generate a driving current in the circuit by connecting the second node N2 and the third node N3. Subsequently, the light-emitting device 310 in the circuit can emit light based on this driving current.

[0087] In this embodiment, during the compensation phase, when the first voltage terminal VDD connected to the pixel circuit provides the working voltage to compensate the threshold voltage of the third node connected to the driving sub-circuit 110 through the first control sub-circuit 210, the third node N3 is disconnected from the first pole of the light-emitting device 310. Therefore, the voltage written to the third node N3 by the first voltage terminal VDD through the first control sub-circuit 210 and the driving sub-circuit 110 will not continue to flow from the third node N3 to the light-emitting device 310. That is, the third node N3 connected to the second terminal of the driving sub-circuit 110 will not experience leakage during the compensation phase. Thus, the first voltage terminal VDD will better compensate the threshold voltage of the driving sub-circuit 110, thereby improving the uniformity of the brightness of the light-emitting device driven by the pixel circuit. For the display panel, when using this pixel circuit to drive the light-emitting device to refresh the display of sub-pixels, the uniformity of the display brightness of the sub-pixels is effectively improved because the leakage problem of the pixel circuit is effectively controlled. In other words, the pixel circuit can improve the uniformity of the brightness of the display sub-pixels by connecting the first voltage terminal VDD and the second node connected by the first control sub-circuit 210 and the driving sub-circuit 110 during the compensation stage, and disconnecting the third node connected by the driving sub-circuit 110 and the first electrode of the light-emitting device 310 by the second control sub-circuit 220.

[0088] In some embodiments, the driving sub-circuit may include at least one driving transistor, which is used to control the conduction level between the first and second electrodes based on the voltage of the control electrode, thereby generating a current corresponding to the conduction level. When the driving transistor is an N-type oxide TFT, the driving transistor may specifically be an N-type LTPO transistor. Alternatively, in some other feasible embodiments, the driving transistor may specifically be an N-type indium gallium zinc oxide (IGZO) IGZO transistor. Generally, the driving transistor may be represented as a transistor DTFT or a transistor TD to distinguish it from transistors with other uses in the pixel circuit. For ease of explanation and understanding, the driving transistor included in the driving sub-circuit will be referred to as driving transistor TD in the following detailed description of the embodiments of this application.

[0089] like Figure 2 As shown, when the driving sub-circuit 110 includes a driving transistor TD, the control terminal of the driving transistor TD is coupled to the first node N1 as the control terminal of the driving sub-circuit 110, the first terminal of the driving transistor TD is coupled to the second node N2 as the first terminal of the driving sub-circuit 110, and the second terminal of the driving transistor TD is coupled to the third node N3 as the second terminal of the driving sub-circuit 110.

[0090] Thus, when the potential at the first node N1 becomes the data voltage Vdata, and both the transistor T1 connected to the second node N2 and the transistor T2 connected to the third node N3 are turned on, the driving transistor TD turns on based on the data voltage Vdata at the control electrode, so as to control the conduction between the second node N2 and the third node N3 to turn on the current switch, thereby generating a driving current for the light-emitting device 310 to emit light in the path formed by the transistor T1, the driving transistor TD, the transistor T2 and the light-emitting device 310 connected in series.

[0091] In some embodiments, the first control sub-circuit includes at least one first transistor. The first transistor may be an LTPO transistor, or it may be an IGZO transistor.

[0092] like Figure 2 As shown, when the first control sub-circuit 210 includes a first transistor T1, the control electrode of the first transistor T1 is coupled to the first light-emitting control line EM1 as the control terminal of the first control sub-circuit 210, the first electrode of the first transistor T1 is coupled to the first voltage terminal VDD as the first terminal of the first control sub-circuit 210, and the second electrode of the first transistor T1 is coupled to the second node N2 as the second terminal of the first control sub-circuit 210.

[0093] Thus, when the first light-emitting control line EM1 provides a control signal to the control electrode of the first transistor T1 to turn on the first transistor T1, the first transistor T1 responds to the control signal to turn on, connecting the first voltage terminal VDD with the second node N2. Conversely, when the first light-emitting control line EM1 provides a control signal to the control electrode of the first transistor T1 to turn off the first transistor T1, the first transistor T1 responds to the control signal to turn off, keeping the first voltage terminal VDD disconnected from the second node N2.

[0094] In some embodiments, the second control sub-circuit includes at least one second transistor. The second transistor is similar to the first transistor described above; that is, the second transistor can be an LTPO transistor or an IGZO transistor.

[0095] like Figure 2 As shown, when the second control sub-circuit 220 includes a second transistor T2, the control electrode of the second transistor T2 is coupled to the second light-emitting control line EM2 as the control terminal of the second control sub-circuit 220, while the first electrode of the second transistor T2 is coupled to the third node N3 as the first terminal of the second control sub-circuit 220, and the second electrode of the second transistor T2 is coupled to the first electrode of the light-emitting device 310 as the second terminal of the second control sub-circuit 220.

[0096] Thus, when the second light-emitting control line EM2 provides a control signal to the control electrode of the second transistor T2 to turn on the second transistor T2, the second transistor T2 responds to the control signal to turn on, thereby connecting the third node N3 with the first electrode of the light-emitting device 310. Furthermore, when the second light-emitting control line EM2 provides a control signal to the second transistor T2 to turn off the second transistor T2, the second transistor T2 responds to the control signal to turn off, thereby keeping the third node N3 disconnected from the first electrode of the light-emitting device 310.

[0097] In some embodiments, the data input sub-circuit includes at least one third transistor. Specifically, the third transistor may be an LTPO transistor, or alternatively, an IGZO transistor.

[0098] like Figure 2 As shown, when the data writing sub-circuit 410 includes a third transistor T3, the control terminal of the third transistor T3 is coupled to the data writing control line Gate as the control terminal of the data writing sub-circuit 410, the first terminal of the third transistor T3 is coupled to the light-emitting data line Data as the first terminal of the data writing sub-circuit 410, and the second terminal of the third transistor T3 is coupled to the first node N1 as the second terminal of the data writing sub-circuit 410.

[0099] Thus, when the data write control line Gate provides a control signal to the control electrode of the third transistor T3 to turn it on, the third transistor T3 responds to the control signal to turn on, connecting the light-emitting data line Data to the first node N1. Conversely, when the data write control line Gate provides a control signal to the control electrode of the third transistor T3 to turn it off, the third transistor T3 responds to the control signal to turn off, keeping the light-emitting data line Data disconnected from the first node N1.

[0100] In some embodiments, the pixel circuit further includes an energy storage sub-circuit. The energy storage sub-circuit is coupled to the second node and the third node, respectively.

[0101] like Figure 3 As shown, the first terminal of the energy storage sub-circuit 810 is coupled to the second node N2, while the second terminal of the energy storage sub-circuit 810 is coupled to the third node N3. Thus, the energy storage sub-circuit 810 can maintain the potential of the second node N2 and the potential of the third node N3 by using a pre-set fixed voltage.

[0102] In some embodiments, the energy storage subcircuit includes at least one fourth capacitor. The fourth capacitor is an energy storage capacitor. Figure 4As shown, the first terminal of the fourth capacitor Cst4 can be coupled to the second node N2, and the second terminal of the fourth capacitor Cst4 is coupled to the third node N3. In this case, by pre-calibrating the voltage value stored in the fourth capacitor Cst4 to the operating voltage value provided by the first voltage terminal VDD (or calibrating it to another voltage value), the fourth capacitor Cst4 can simultaneously maintain the potentials of both the second node N2 and the third node N3.

[0103] In other embodiments, the energy storage subcircuit is also coupled to both the first voltage terminal and the third node. For example... Figure 5 As shown, the first terminal of the energy storage sub-circuit 810 can also be coupled to the first voltage terminal VDD, and the second terminal of the energy storage sub-circuit 810 is also coupled to the third node N3. Based on this, the energy storage sub-circuit 810 can stabilize the voltage of the third node N3 according to the operating voltage provided by the first voltage terminal VDD, so as to maintain the potential of the third node N3.

[0104] In some embodiments, when the energy storage sub-circuit includes at least one fourth capacitor, such as Figure 6 As shown, the first terminal of the fourth capacitor Cst4 can also be coupled to the first voltage terminal VDD, and the second terminal of the fourth capacitor Cst4 is still coupled to the third node N3. At this time, by controlling the first voltage terminal VDD to provide the working voltage to the first terminal of the fourth capacitor Cst4, the fourth capacitor can maintain the potential of the third node N3.

[0105] In this embodiment, using the fourth capacitor Cst4 to maintain the potential of the second node N2 and the third node N3, or using the fourth capacitor to maintain the potential of the third node N3, can control the influence of the data voltage Vdata on the drive current Ids generated by the driving transistor TD. Therefore, by adjusting the size of the fourth capacitor Cst3, the data voltage Vdata required for the driving transistor TD to generate the drive current Ids can be adjusted. Figure 7 As shown, when the fourth capacitor Cst4 is increased, the overall range of the data voltage Vdata required for the driving transistor TD to generate the driving current Ids will shift to the right. Thus, based on the different voltage output capabilities of the light-emitting data lines Data on different display panels, the pixel circuit can adjust the size of the fourth capacitor Cst4 to ensure that the data voltage Vdata is compatible with the driving transistor TD to generate the driving current. In other words, the pixel circuit's generation of the driving current to drive the light-emitting device will be more stable and reliable.

[0106] Furthermore, when coupled to the first voltage terminal VDD and the third node N3 respectively via the fourth capacitor Cst4, the third node N3, acting as the drain of the driving transistor TD, can maintain a stable potential based on the constant operating voltage provided by the first voltage terminal VDD. Also, because the voltage at the first node N1 jumps from the first voltage V1 to the data voltage Vdata, the voltage at the third node N3 also jumps upwards due to capacitive coupling. Therefore, the higher the first voltage V1 provided by the first voltage line Vninit1, the smaller the difference between the first voltage V1 and the data voltage Vdata, and the smaller the upward jump in the voltage of the third node N3. Thus, by using a higher voltage for the first voltage line Vinit1, the voltage written from the first voltage terminal VDD to the third node N3 can be made lower. In this way, compared to related technologies that do not use the fourth capacitor Cst4 to maintain the potential of the third node N3, the embodiments of this application can reduce the amount of voltage jump coupling during the operation of the pixel circuit, thereby reducing voltage across voltage. For example, as... Figure 8 As shown, when the driving current generated by the driving transistor TD based on the data voltage Vdata is a small current, the operating voltage provided by the first voltage terminal VDD connected to the pixel circuit in this embodiment of the application hardly fluctuates. However, since related technologies do not employ the technique of using the fourth capacitor Cst4 to maintain the potential of the third node N3, the voltage difference of the operating voltage provided by the first voltage terminal VDD is more significant. Furthermore, as Figure 9 As shown, when the driving current generated by the driving transistor TD based on the data voltage Vdata is a medium current, the operating voltage provided by the first voltage terminal VDD connected to the pixel circuit in this embodiment of the application also shows almost no fluctuation. Related technologies do not employ the technique of using the fourth capacitor Cst4 to maintain the potential of the third node N3, and the voltage difference of the operating voltage provided by the first voltage terminal VDD is still quite significant. Furthermore, as... Figure 10 As shown, even when the driving current generated by the driving transistor TD based on the data voltage Vdata is a large current, the working voltage provided by the first voltage terminal VDD connected to the pixel circuit in this embodiment of the application changes gradually and smoothly without irregular fluctuations. The related technology does not adopt the technical solution of the fourth capacitor Cst4 to maintain the potential of the third node N3, and the voltage fluctuation of the working voltage provided by the first voltage terminal VDD is relatively difficult to control.

[0107] In some embodiments, the pixel circuit may further include a first reset sub-circuit and a second reset sub-circuit. The first reset sub-circuit is coupled to a first reset control line and a first voltage line, respectively, and is also coupled to a first node coupled to the aforementioned driving sub-circuit. The second reset sub-circuit is coupled to a second reset control line and a second voltage line, respectively, and is also coupled to a third node coupled to the aforementioned driving sub-circuit.

[0108] like Figure 11 As shown, in the pixel circuit, the control terminal of the first reset sub-circuit 510 is coupled to the first reset control line Reset1, the first terminal of the first reset sub-circuit 510 is coupled to the first voltage line Vinit1, and the second terminal of the first reset sub-circuit 510 is coupled to the first node N1.

[0109] Based on this, when the pixel circuit executes the control method of the pixel circuit provided in the embodiment of this application, during the reset phase in the above-mentioned frame period, the first reset control line Reset1 provides a control signal to the control terminal of the first reset sub-circuit 510. The first reset sub-circuit 510 responds to the control signal to control the first voltage line Vinit1 to connect with the first node N1, thereby writing a first voltage of 1 to the first node N1, thereby resetting the first node N1.

[0110] In addition, the control terminal of the second reset sub-circuit 520 is coupled to the second reset control line Reset2, the first terminal of the second reset sub-circuit 520 is coupled to the second voltage line Vinit2-1, and the second terminal of the second reset sub-circuit 520 is coupled to the third node N3.

[0111] Thus, when the pixel circuit executes the pixel circuit control method provided in the embodiments of this application, during the above-mentioned reset phase, the second reset control line Reset2 provides a control signal to the control terminal of the second reset sub-circuit 520. The second reset sub-circuit 520 responds to the control signal to control the second voltage line Vinit2-1 to connect with the third node N3, thereby causing the second voltage line Vinit2-1 to continuously write the second voltage to the third node N3, thereby resetting the third node N3.

[0112] Furthermore, when the pixel circuit executes the pixel circuit control method provided in this application embodiment, during the reset phase, the second light-emitting control line EM2 also sends a control signal to the control terminal of the second control sub-circuit 220. The second control sub-circuit 220 then responds to the control signal to control the third node N3 to connect with the first electrode of the light-emitting device. Thus, the second voltage written to the third node N3 by the second voltage line Vinit2-1 will also be further written to the first electrode of the light-emitting device, thereby resetting the first electrode of the light-emitting device.

[0113] In some embodiments, the voltage value of the first voltage provided by the first voltage line Vinit1 may be less than or equal to the voltage value of the operating voltage provided by the first voltage terminal VDD. The voltage value of the second voltage provided by the second voltage line Vinit2-1 may be less than the voltage value of the first voltage. Alternatively, in other embodiments, the voltage value of the second voltage provided by the second voltage line Vinit2-1 may be equal to the voltage value of the first voltage. It should be understood that, based on different design needs of actual applications, the voltage values ​​of the first voltage, the operating voltage, and the second voltage can all be adapted to vary depending on the type of electronic device, the type of oxide TFT used in the electronic device, and / or the type of light-emitting device used in the electronic device. That is, the embodiments of this application do not limit the specific magnitude of the operating voltage, the first voltage, the second voltage, and the third voltage mentioned below.

[0114] In this embodiment, during the reset phase, by simultaneously resetting the first and third nodes connected to the driving sub-circuit, the residual voltage of these two nodes during the light-emitting phase can be prevented from affecting the driving sub-circuit's ability to drive the light-emitting device in the next frame cycle. This ensures that the driving sub-circuit can accurately control the current development in each frame cycle to generate the current driving the light-emitting device in the pixel circuit, thereby guaranteeing the stability of the light-emitting device's brightness. Furthermore, during the reset phase, by synchronizing the voltage written to the third node to the first electrode of the light-emitting device, the first electrode of the light-emitting device is also reset. This prevents the residual voltage of the light-emitting device itself after light emission from interfering with the light emission response of the driving sub-circuit in the next light-emitting phase, further ensuring the stability of the light-emitting device's brightness.

[0115] In some embodiments, the first reset sub-circuit includes at least one fourth transistor. The fourth transistor may be an LTPO transistor, or specifically an IGZO transistor.

[0116] like Figure 12 As shown, when the first reset circuit 510 includes a fourth transistor T4, the control terminal of the fourth transistor T4 is coupled to the first reset control line Reset1 as the control terminal of the first reset circuit 510, the first terminal of the fourth transistor T4 is coupled to the first voltage line Vinit1 as the first terminal of the first reset circuit 510, and the second terminal of the fourth transistor T4 is coupled to the first node N1 as the second terminal of the first reset circuit 510.

[0117] During the reset phase, when the first reset control line Reset1 provides a control signal to the control electrode of the fourth transistor T4 to turn it on, the fourth transistor T4 responds to the control signal and turns on to connect the first voltage line Vinit1 with the first node N1. This allows the first voltage line Vinit1 to write a first voltage into the first node N1 to reset the first node N1. In this way, the residual voltage at the first node N1 after the driver sub-circuit has driven the light-emitting device to emit light in the previous frame cycle can be avoided from affecting the driving transistor TD's ability to drive the light-emitting device to emit light in the next frame cycle.

[0118] In some embodiments, the second reset circuit includes at least one fifth transistor. The fifth transistor may be an LTPO transistor, or specifically an IGZO transistor.

[0119] like Figure 12 As shown, when the second reset circuit 520 includes a fifth transistor T5, the control terminal of the fifth transistor T5 is coupled to the second reset control line Reset2 as the control terminal of the second reset circuit 520, the first terminal of the fifth transistor T5 is coupled to the second voltage line Vinit2-1 as the first terminal of the second reset circuit 520, and the second terminal of the fifth transistor T5 is coupled to the third node N3 as the second terminal of the second reset circuit 520.

[0120] During the reset phase, when the second reset control line Reset2 provides a control signal to the control electrode of the fifth transistor T5 to turn it on, the fifth transistor T5 responds to the control signal and turns on to connect the second voltage line Vinit2-1 with the third node N3. This causes the second voltage line Vinit2-1 to write the second voltage into the third node N3 to reset the third node N3. In this way, the residual voltage at the third node N3 after the driver sub-circuit drives the light-emitting device to emit light in the previous frame cycle can be avoided from affecting the driver transistor TD in driving the light-emitting device to emit light in the next frame cycle.

[0121] In some embodiments, the pixel circuit further includes a bootstrap circuit. The bootstrap circuit is coupled to the first node and the third node, respectively.

[0122] like Figure 13 As shown, the first terminal of the bootstrap circuit 610 is coupled to the first node N1, and the second terminal of the bootstrap circuit 610 is coupled to the third node N3. During the data writing phase, the data writing sub-circuit 410 responds to the control signal g provided by the data writing control line Gate, and couples the light-emitting data line Data to the first node N1. When the light-emitting data line Data writes the data voltage Vdata to the first node N1, the voltage at the first node N1 jumps compared to the reset phase, and thus the bootstrap circuit 610 also raises the voltage at the third node N3.

[0123] In some embodiments, the bootstrap circuit includes at least one first capacitor. For example... Figure 14 As shown, when the bootstrap circuit 610 includes a first capacitor Cst1, the first plate of the first capacitor Cst1 is coupled to the first node N1, and the second plate of the first capacitor Cst1 is coupled to the third node N3. In this way, when the voltage of the first node N1 rises to the data voltage, the first capacitor Cst1 can automatically raise the voltage of the third node N3.

[0124] In other embodiments, the bootstrap circuit may further include a plurality of capacitors connected in series. For example, when the bootstrap circuit includes N capacitors connected in series, the first terminal of the first capacitor Cst1, Cst2, Cst3 to CstN, serves as the first terminal of the bootstrap circuit and is coupled to the first node N1, while the second terminal of the Nth capacitor CstN serves as the second terminal of the bootstrap circuit and is coupled to the third node N3.

[0125] In some embodiments, the pixel circuit can be specifically configured as follows: Figure 15 The timing cycle shown drives the light-emitting devices of the display panel to emit light, allowing the display panel to refresh and display image pixels. Combined with... Figure 14 and Figure 15 As shown, the example is given where all the transistors in each sub-circuit of the pixel circuit are N-type oxide TFTs.

[0126] During the reset phase, the first light-emitting control line EM1 provides a low-level control signal, and the first transistor T1 remains off in response to the control signal provided by the first light-emitting control line EM1, so that the first voltage terminal VDD is disconnected from the second node N2.

[0127] The second light-emitting control line EM2 provides a high-level control signal, and the second transistor T2 turns on in response to the control signal provided by the second light-emitting control line EM2, so that the third node N3 is connected to the first pole of the light-emitting device 310.

[0128] The first reset control line Reset1 provides a high-level control signal, and the fourth transistor T4 turns on in response to the control signal provided by the first reset control line Reset1, thereby connecting the first voltage line Vinit1 with the first node N1. Thus, the first voltage line Vinit1 begins to write a first voltage to the first node N1 to reset the first node N1.

[0129] The second reset control line Reset2 provides a high-level control signal, and the fifth transistor T5 turns on in response to the control signal provided by the second reset control line Reset2, thereby connecting the second voltage line Vinit2-1 with the third node N3. Thus, the second voltage line Vinit2-1 begins to write a second voltage to the third node N3 to reset the third node N3. Furthermore, since the second transistor T2 turns on to connect the third node N3 with the first electrode of the light-emitting device 310, the voltage at the third node N3 will also be written downwards to the first electrode of the light-emitting device 310, thereby resetting the first electrode of the light-emitting device 310.

[0130] When the data write control line Gate provides a low-level control signal, the third transistor T3 remains off in response to the control signal provided by the data write control line Gate, thereby disconnecting the light-emitting data line Data from the first node N1.

[0131] In the compensation phase following the reset phase, the first light-emitting control line EM1 provides a high-level control signal. The first transistor T1 turns on in response to the control signal provided by the first light-emitting control line EM1, connecting the first voltage terminal VDD with the second node N2. Thus, the operating voltage provided by the first voltage terminal VDD is written to the third node N3 through the first transistor T1 and the driving transistor TD to compensate for the threshold voltage Vth of the third node N3.

[0132] The second light-emitting control line EM2 provides a low-level control signal, and the second transistor T2 remains off in response to the control signal provided by the second light-emitting control line EM2, so that the third node N3 is disconnected from the first electrode of the light-emitting device 310.

[0133] The first reset control line Reset1 provides a high-level control signal. The fourth transistor T4 turns on in response to the control signal provided by the first reset control line Reset1 to connect the first voltage line Vinit1 with the first node N1. Thus, the first voltage line Vinit1 also continuously writes a first voltage to the first node N1 to compensate for the threshold voltage Vth of the first node N1.

[0134] The second reset control line Reset2 provides a low-level control signal, and the fifth transistor T5 responds to the control signal provided by the second reset control line Reset2 by remaining off, so as to disconnect the second voltage line Vinit2-1 from the third node N3.

[0135] When the data write control line Gate provides a low-level control signal, the third transistor T3 remains off in response to the control signal provided by the data write control line Gate, thereby disconnecting the light-emitting data line Data from the first node N1.

[0136] During the data writing phase following the compensation phase, the first light-emitting control line EM1 provides a low-level control signal, and the first transistor T1 remains off in response to the control signal provided by the first light-emitting control line EM1, so that the first voltage terminal VDD is disconnected from the second node N2.

[0137] The second light-emitting control line EM2 provides a low-level control signal, and the second transistor T2 remains off in response to the control signal provided by the second light-emitting control line EM2, so that the third node N3 is disconnected from the first electrode of the light-emitting device 310.

[0138] The first reset control line Reset1 provides a low-level control signal, and the fourth transistor T4 remains off in response to the control signal provided by the first reset control line Reset1, so as to disconnect the first voltage line Vinit1 from the first node N1.

[0139] The second reset control line Reset2 provides a low-level control signal, and the fifth transistor T5 responds to the control signal provided by the second reset control line Reset2 by remaining off, so as to disconnect the second voltage line Vinit2-1 from the third node N3.

[0140] The data write control line Gate provides a high-level control signal, and the third transistor T3 turns on in response to the control signal provided by the data write control line Gate, so as to connect the light-emitting data line Data with the first node N1, thereby allowing the light-emitting data line Data to write the data voltage Vdata into the first node N1.

[0141] During the light-emitting stage, the first light-emitting control line EM1 provides a high-level control signal, and the first transistor T1 turns on in response to the control signal provided by the first light-emitting control line EM1 to connect the first voltage terminal VDD with the second node N2.

[0142] The second light-emitting control line EM2 provides a high-level control signal, and the second transistor T2 turns on in response to the control signal provided by the second light-emitting control line EM2, so that the third node N3 is connected to the first pole of the light-emitting device 310.

[0143] The first reset control line Reset1 provides a low-level control signal, and the fourth transistor T4 remains off in response to the control signal provided by the first reset control line Reset1, so as to disconnect the first voltage line Vinit1 from the first node N1.

[0144] The second reset control line Reset2 provides a low-level control signal, and the fifth transistor T5 responds to the control signal provided by the second reset control line Reset2 by remaining off, so as to disconnect the second voltage line Vinit2-1 from the third node N3.

[0145] Thus, a path is formed in which the first voltage terminal VDD, the first transistor T1, the second node N2, the driving transistor TD, the third node N3, the second transistor T2, the light-emitting device 310, and the second voltage terminal VSS are connected in series. The driving transistor TD controls the conduction between the second node N2 and the third node N3 based on the data voltage Vdata of the first node N1 to turn on the current switch, thereby generating a driving current in the path to drive the light-emitting device 310 to emit light, thereby driving the light-emitting device 310 to emit light.

[0146] It should be noted that during the reset phase, the voltage at the first node N1 will be reset to the first voltage V1, while the voltage at the third node N3 and the first electrode of the light-emitting device 310 will be reset to the second voltage V2-1. Furthermore, since the voltage VN1 at the first node N1 during the compensation phase is the first voltage V1 continuously written by the first voltage line Vinit1, the difference between the voltage VN1 at the first node N1 and the voltage VN3 at the third node N3 is the threshold voltage Vth of the driving transistor TD, i.e., VN1 - VN3 = Vth. Therefore, after the compensation phase ends, the voltage VN3 at the third node N3 will be written as VN1 - Vth, and VN1 is equal to the first voltage V1, thus VN3 = V1 - Vth. Moreover, since the voltage at the first node N1 jumps to Vdata during the data writing phase, the first capacitor Cst1 will automatically raise the voltage at the third node N3. That is, during the data writing phase, the voltage VN3 at the third node N3 changes from VN3 = V1 - Vth to VN3 = (Vdata - V1) * Cst1 / CN3 + V1 - Vth. Here, Cst1 is the capacitance of the first capacitor Cst1, and CN3 represents all the capacitances at the third node N3, such as... Figure 14 As shown, all the capacitances on the third node N3 include at least the sum of the capacitance of the third node N3 itself and the capacitance of the fourth capacitor Cst. Therefore, Cst1 / CN3 is the voltage division of the first capacitor Cst1 relative to the sum of all the capacitances on the third node N3.

[0147] Thus, during the light-emitting stage, the voltage Vgs = VN1 - VN3 used by the driving transistor TD to generate the driving current Ids can be transformed into Vgs = Vdata - (Vdata - V1) * Cst1 / CN3 - V1 + Vth. Substituting the voltage Vgs into the current formula Ids = K(Vgs - Vth)^2 for the driving transistor TD during the light-emitting stage, we can obtain the driving current Ids = K(Vdata - (Vdata - V1) * Cst1 / CN3 - V1)^2 generated by the driving transistor TD based on the voltage Vgs. In this way, the threshold voltage Vth is no longer present in the new current formula, and the driving current Ids is no longer affected by the threshold voltage Vth. That is, the embodiments of this application can overcome the influence of the threshold voltage Vth on the driving current and complete the compensation for the threshold voltage Vth.

[0148] It should be noted that in the above formula for obtaining the driving current Ids based on the voltage Vgs, K = 1 / 2 * μC (W / L). Here, "μC" is the transistor's process parameter, and "W / L" is the width-to-length ratio of the transistor's internal channel. Therefore, for a specific oxide TFT where "μC" and "W / L" are known, K = 1 / 2 * μC (W / L) is a constant.

[0149] In some embodiments, the pixel circuit may further include a third reset circuit. The third reset circuit is coupled to the second reset control line described above, and is also coupled to a third voltage line, and is coupled to a fourth node, which is coupled to the first electrode of the light-emitting device described above.

[0150] like Figure 16 As shown, the control terminal of the third reset sub-circuit 530 is coupled to the second reset control line Reset2, the first terminal of the third reset sub-circuit 530 is coupled to the third voltage line Vinit2, and the second terminal of the third reset sub-circuit 530 is coupled to the fourth node N4. Thus, when the pixel circuit executes the pixel circuit control method provided in this embodiment, during the reset phase, the second reset control line Reset2 provides a control signal to the control terminal of the third reset sub-circuit 530. The third reset sub-circuit 530 responds to this control signal to connect the third voltage line Vinit2 to the fourth node N4, thereby allowing the third voltage line Vinit2 to write the third voltage to the fourth node N4. Since the fourth node N4 is coupled to the first electrode of the light-emitting device 310, the third voltage will be further written to the first electrode of the light-emitting device 310, thereby resetting the first electrode of the light-emitting device 310.

[0151] It should be noted that the voltage value of the third voltage can be the same as the voltage value of the second voltage mentioned above. For example, the voltage value of the third voltage is equal to the voltage value of the second voltage, which is -3 volts (V). Alternatively, the voltage value of the third voltage can also be greater than the voltage value of the second voltage. For example, the voltage value of the third voltage is equal to -3V, while the voltage value of the second voltage is -2V. It should be understood that, based on different design needs in practical applications, the voltage values ​​of the third voltage and the second voltage can of course be other values ​​not listed here in different feasible implementations. This application does not limit the specific values ​​of the third voltage and the second voltage. As long as the voltage value of the third voltage is equal to the voltage value of the second voltage, or the voltage value of the third voltage is slightly greater than the voltage value of the second voltage, and conforms to the technical concept of this application, it should be included within the protection scope of this application.

[0152] Furthermore, when the pixel circuit includes a third reset sub-circuit 530, during the reset phase, the second light emission control line EM2 provides a control signal to the control terminal of the second control sub-circuit 220 to control the second control sub-circuit 220 to shut down, so that the second control sub-circuit 220 remains shut down during the reset phase in response to the control signal, thereby disconnecting the third node N3 from the fourth node N4.

[0153] In some embodiments, the third reset circuit includes at least one sixth transistor. The sixth transistor may be an LTPO transistor, or it may be an IGZO transistor.

[0154] like Figure 17 As shown, the control terminal of the sixth transistor T6 is coupled to the second reset control line Reset2 as the control terminal of the third reset circuit 530. The first terminal of the sixth transistor T6 is coupled to the third voltage line Vinit2 as the first terminal of the third reset circuit 530, while the second terminal of the sixth transistor T6 is coupled to the fourth node N4 as the second terminal of the third reset circuit 530. The fourth node N4 is coupled to the first terminal of the light-emitting device 310. When the second reset control line Reset2 provides a control signal to the control terminal of the sixth transistor T6 to turn on the sixth transistor T6, the sixth transistor T6 responds to the control signal and turns on, connecting the third voltage line Vinit2 with the fourth node N4. This allows the third voltage line Vinit2 to write the third voltage V2 into the fourth node N4 and further into the first terminal of the light-emitting device 310.

[0155] In some embodiments, the pixel circuit may also be specifically configured as follows: Figure 18 The timing cycle shown drives the light-emitting devices of the display panel to emit light, allowing the display panel to refresh and display image pixels. Combined with... Figure 17 and Figure 18As shown, the example will still be taken where the transistors in each sub-circuit of the pixel circuit are all N-type oxide TFTs.

[0156] During the reset phase, the first light-emitting control line EM1 provides a low-level control signal, and the first transistor T1 remains off in response to the control signal provided by the first light-emitting control line EM1, so that the first voltage terminal VDD is disconnected from the second node N2.

[0157] The second light-emitting control line EM2 provides a low-level control signal, and the second transistor T2 remains off in response to the control signal provided by the second light-emitting control line EM2, so that the third node N3 is disconnected from the first electrode of the light-emitting device 310.

[0158] The first reset control line Reset1 provides a high-level control signal, and the fourth transistor T4 turns on in response to the control signal provided by the first reset control line Reset1, thereby connecting the first voltage line Vinit1 with the first node N1. Thus, the first voltage line Vinit1 begins to write a first voltage to the first node N1 to reset the first node N1.

[0159] The second reset control line Reset2 provides a high-level control signal, and the fifth transistor T5 turns on in response to the control signal provided by the second reset control line Reset2, connecting the second voltage line Vinit2-1 to the third node N3. Thus, the second voltage line Vinit2-1 begins to write a second voltage to the third node N3 to reset the third node N3. Furthermore, the sixth transistor T6 also turns on in response to the control signal provided by the second reset control line Reset2, connecting the third voltage line Vinit2 to the fourth node N4. The fourth node N4 is coupled to the first terminal of the light-emitting device 310, and thus, the third voltage line Vinit2 begins to write a third voltage V2 to the first terminal of the light-emitting device 310 to reset the first terminal of the light-emitting device 310.

[0160] When the data write control line Gate provides a low-level control signal, the third transistor T3 remains off in response to the control signal provided by the data write control line Gate, thereby disconnecting the light-emitting data line Data from the first node N1.

[0161] It should be noted that the pixel circuit is based on Figure 18 When the timing-driven light-emitting device shown emits light, except for the reset phase and the above-mentioned sequence... Figure 15 Apart from the difference in light emission from the timing-driven light-emitting device shown, the pixel circuit performs the same operation as described above in the other light emission, compensation, and data writing stages. Therefore, the same content will not be described again here.

[0162] In some embodiments, the pixel circuit further includes a first isolation sub-circuit, a second isolation sub-circuit, a third control sub-circuit, and a fourth reset sub-circuit. The third control sub-circuit is coupled to the second light-emitting control line to share the control signal provided by the second light-emitting control line. Furthermore, the third control sub-circuit is coupled to both the first node and the fifth node (the fifth node is coupled to the data writing sub-circuit); the first isolation sub-circuit is coupled to both the fifth node and the sixth node to isolate the fifth node from the sixth node. The second isolation sub-circuit is coupled to both the sixth node and the third node to isolate the sixth node from the third node. The fourth reset sub-circuit is coupled to the first reset control line, the first voltage line, and the sixth node.

[0163] like Figure 19 As shown, the control terminal of the third control sub-circuit 230 is coupled to the second light-emitting control line EM2, the first terminal of the third control sub-circuit 230 is coupled to the first node N1, the second terminal of the third control sub-circuit 230 is coupled to the fifth node N5, and the fifth node N5 is coupled to the second terminal of the data writing sub-circuit 410. Furthermore, the first terminal of the first isolation sub-circuit 710 is coupled to the fifth node N5, and the second terminal of the first isolation sub-circuit 710 is coupled to the sixth node N6; the first terminal of the second isolation sub-circuit 720 is coupled to the sixth node N6, and the second terminal of the second isolation sub-circuit 720 is coupled to the third node N3. Finally, the control terminal of the fourth reset sub-circuit 540 is coupled to the first reset control line Reset1, the first terminal of the fourth reset sub-circuit 540 is coupled to the first voltage line Vnint1, and the second terminal of the fourth reset sub-circuit 540 is coupled to the sixth node N6.

[0164] Thus, when the pixel circuit executes the pixel circuit control method provided in this application embodiment, the pixel circuit can perform data writing operations during the compensation phase. That is, since the third control sub-circuit 230 controls the fifth node N5 to connect with the first node N1 in response to the control signal em2 provided by the second light-emitting control line EM2, during the compensation phase, the third control sub-circuit 230 remains closed in response to the control signal provided by the second light-emitting control line EM2, thereby keeping the fifth node N5 and the first node N1 disconnected during the compensation phase. Therefore, during the compensation phase, the first voltage line Vinit1 writes the first voltage to the first node N1 without affecting the voltage on the fifth node. Moreover, the first reset control line Reset1 still provides a control signal to turn on the control sub-circuit during the compensation phase, so that the fourth reset sub-circuit 540 will also turn on in response to the control signal provided by the first reset control line Reset1, so that the first voltage line Vinit1 continuously writes the first voltage at the sixth node N6. However, since the first isolation sub-circuit 710 is located between the fifth node N5 and the sixth node N6, it isolates the fifth and sixth nodes. Therefore, the first voltage line Vinit1 writing the first voltage to the sixth node N6 will not affect the voltage on the fifth node. Thus, the data write control line Gate can provide a control signal to turn on the control sub-circuit during the compensation phase, causing the data write sub-circuit 410 to turn on in response to the control signal provided by the data write control line Gate, connecting the light-emitting data line Data to the fifth node N5, thereby allowing the light-emitting data line Data to write the data voltage Vdata to the fifth node N5. Afterwards, during the light-emitting phase, since the first light-emitting control line EM1 and the second light-emitting control line EM2 each provide a control signal to turn on the control sub-circuit, the third control sub-circuit 230 turns on in response to the control signal provided by the second light-emitting control line EM2, connecting the first node N1 and the fifth node N5. Thus, the data voltage Vdata on the fifth node N5 will be transmitted to the first node N1 through the third control sub-circuit 230, so that the potential of the driving sub-circuit 110 on the first node N1 becomes the data voltage Vdata. When both the first control sub-circuit and the second control sub-circuit are turned on, the second node N2 and the third node N3 are turned on based on the data voltage Vdata to turn on the current switch, thereby generating a driving current in the path to drive the light-emitting device 310 to emit light.Furthermore, since the first reset control line Reset1 and the second reset control line Reset2 do not provide control signals to turn on the control sub-circuit during the light-emitting stage, the fourth reset sub-circuit 540 will remain closed during the light-emitting stage to disconnect the sixth node N6 from the first voltage line Vinit1. As a result, since there is no longer a first voltage input between the first isolation sub-circuit 710 and the second isolation sub-circuit 720, the first isolation sub-circuit 710 and the second isolation sub-circuit 720 will couple into a bootstrap sub-circuit, thereby automatically boots up the voltage at the third node N3 when the voltage at the first node N1 jumps to Vdata.

[0165] In some embodiments, the first isolation sub-circuit includes at least one second capacitor. For example... Figure 20 As shown, the first plate of the second capacitor Cst2 is coupled to the fifth node N5, and the second plate of the second capacitor Cst2 is coupled to the sixth node N6. Thus, the second capacitor Cst2 can isolate the fifth node N5 and the sixth node N6, so that the first voltage V1 written to the sixth node N6 will not affect the data voltage Vdata written to the fifth node N5.

[0166] In some embodiments, the second isolation sub-circuit includes at least one third capacitor. For example... Figure 20 As shown, the first plate of the third capacitor Cst3 is coupled to the sixth node N6, and the second plate of the third capacitor Cst3 is coupled to the third node N3. Thus, the third capacitor Cst can also isolate the sixth node N6 from the third node N3, so that when the first voltage line Vinit1 writes the first voltage V1 to reset the sixth node N6, the first voltage V1 of the sixth node N1 will not affect the second voltage line V2-1 writing the second voltage V2-1 on the third node N3.

[0167] In some embodiments, the third control sub-circuit includes at least one seventh transistor. The seventh transistor is the same as the first to sixth transistors described above; that is, the seventh transistor may be an LTPO transistor or an IGZO transistor.

[0168] like Figure 20As shown, the control electrode of the seventh transistor T7 is coupled to the second light-emitting control line EM2 as the control terminal of the third control sub-circuit 230. The first electrode of the seventh transistor T7 is coupled to the first node N1 as the first terminal of the third control sub-circuit 230, and the second electrode of the seventh transistor T7 is coupled to the fifth node N5 as the second terminal of the third control sub-circuit 230. During the light-emitting stage, when the second light-emitting control line EM2 provides a control signal to the control electrode of the seventh transistor T7 to control the seventh transistor T7 to turn on, the seventh transistor T7 responds to the control signal to turn on, thereby connecting the fifth node N5 and the first node N1. Thus, the data voltage Vdata on the fifth node N5 can be written to the first node N1 through the seventh transistor T7.

[0169] In some embodiments, the fourth reset circuit includes at least one eighth transistor. The eighth transistor may be an LTPO transistor, or it may be an IGZO transistor.

[0170] like Figure 20 As shown, the control electrode of the eighth transistor T8 is coupled to the first reset control line Reset1 as the control terminal of the fourth reset sub-circuit 540. The first electrode of the eighth transistor T8 is coupled to the first voltage line Vinit1 as the first terminal of the fourth reset sub-circuit 540. The second electrode of the eighth transistor T8 is coupled to the sixth node N6 as the second terminal of the fourth reset sub-circuit 540. During the reset phase, when the first reset control line Reset1 provides a control signal to the control electrode of the eighth transistor T8 to turn on the eighth transistor T8, the eighth transistor T8 responds to the control signal and turns on to connect the first voltage line Vinit1 with the sixth node N6, so that the first voltage line Vinit1 can write the first voltage V1 into the sixth node N6 to reset the sixth node N6.

[0171] In some embodiments, the pixel circuit may also be specifically configured as follows: Figure 21 The timing cycle shown drives the light-emitting devices of the display panel to emit light, allowing the display panel to refresh and display image pixels. Combined with... Figure 20 and Figure 21 As shown, the example will still be taken where the transistors in each sub-circuit of the pixel circuit are all N-type oxide TFTs.

[0172] During the data writing phase, the first light-emitting control line EM1 provides a low-level control signal, and the first transistor T1 remains off in response to the control signal provided by the first light-emitting control line EM1, so that the first voltage terminal VDD is disconnected from the second node N2.

[0173] The second light-emitting control line EM2 provides a low-level control signal, and the second transistor T2 remains off in response to the control signal provided by the second light-emitting control line EM2, thereby disconnecting the third node N3 from the fourth node N4. Furthermore, the seventh transistor T7 also remains off in response to the control signal provided by the second light-emitting control line EM2, thereby disconnecting the first node N1 from the fifth node N5.

[0174] The first reset control line Reset1 provides a high-level control signal, and the fourth transistor T4 turns on in response to the control signal provided by the first reset control line Reset1, connecting the first voltage line Vinit1 to the first node N1. Thus, the first voltage line Vinit1 begins to write a first voltage to the first node N1 to perform threshold voltage compensation. Furthermore, the eighth transistor T8 turns on in response to the control signal provided by the first reset control line Reset1, connecting the first voltage line Vinit1 to the sixth node N6. Thus, the first voltage line Vinit1 begins to continuously write a first voltage to the sixth node N6.

[0175] The second reset control line Reset2 provides a low-level control signal, and the fifth transistor T5 responds to the control signal provided by the second reset control line Reset2 by remaining off, so as to disconnect the second voltage line Vinit2-1 from the third node N3.

[0176] The data write control line Gate provides a high-level control signal, and the third transistor T3 turns on in response to the control signal provided by the data write control line Gate, so as to connect the light-emitting data line Data with the fifth node N5, thereby allowing the light-emitting data line Data to write the data voltage Vdata into the fifth node N5.

[0177] Subsequently, during the light-emitting stage, the first light-emitting control line EM1 provides a high-level control signal, and the first transistor T1 turns on in response to the control signal provided by the first light-emitting control line EM1 to connect the first voltage terminal VDD with the second node N2.

[0178] The second light-emitting control line EM2 provides a high-level control signal. The second transistor T2 turns on in response to this control signal, connecting the third node N3 and the fourth node N4, and thus connecting them to the first electrode of the light-emitting device 310. Furthermore, the seventh transistor T7 also turns on in response to the control signal from the second light-emitting control line EM2, connecting the first node N1 and the fifth node N5. This allows the data voltage Vdata on the fifth node N5 to be written down to the first node N1.

[0179] The first reset control line Reset1 provides a low-level control signal, and the fourth transistor T4 remains off in response to the control signal provided by the first reset control line Reset1, thereby disconnecting the first voltage line Vinit1 from the first node N1. Furthermore, the eighth transistor T8 also remains off in response to the control signal provided by the first reset control line Reset1, thereby disconnecting the first voltage line Vinit1 from the sixth node N6.

[0180] The second reset control line Reset2 provides a low-level control signal, and the fifth transistor T5 responds to the control signal provided by the second reset control line Reset2 by remaining off, so as to disconnect the second voltage line Vinit2-1 from the third node N3.

[0181] Thus, a path is formed in which the first voltage terminal VDD, the first transistor T1, the second node N2, the driving transistor TD, the third node N3, the second transistor T2, the light-emitting device 310, and the second voltage terminal VSS are connected in series. The driving transistor TD controls the conduction between the second node N2 and the third node N3 based on the data voltage Vdata of the first node N1 to turn on the current switch, thereby generating a driving current in the path to drive the light-emitting device 310 to emit light, thereby driving the light-emitting device 310 to emit light.

[0182] It should be noted that the pixel circuit is based on Figure 21 When the timing-driven light-emitting device emits light, except for the data writing stage and the light-emitting stage, it follows the same procedure as described above. Figure 18 Aside from the difference in light emission from the timing-driven light-emitting devices shown, the pixel circuit operates in the same way as described above during the remaining compensation and reset phases. Figure 18 The method for driving the light-emitting device to emit light according to the timing shown is the same, and the same content will not be described again here. In addition, the data writing stage is between the compensation stage, that is, the start time of the data writing stage is later than the start time of the compensation stage, but the end time of the data writing stage is earlier than the end time of the compensation stage.

[0183] In this embodiment, by adding a seventh transistor T7 between the first node N1 and the fifth node N5, and keeping the seventh transistor T7 off during the compensation phase to disconnect the first node N1 and the fifth node N5, the first voltage line Vinit1 writes the first voltage to the first node N1 without affecting the data voltage Vdata written by the light-emitting data line Data to the fifth node N5. Furthermore, by adding a second capacitor Cst2 between the fifth node N5 and the sixth node N6, and a third capacitor Cst3 between the sixth node N6 and the third node N3, and adding an eighth transistor T8 to the sixth node N6 and turning it on during the compensation phase, the first voltage is continuously written to the sixth node N6. This ensures that the first voltage line Vinit1 writes the first voltage to the sixth node N6 without affecting the data voltage Vdata written by the light-emitting data line Data to the fifth node N5. This allows the pixel circuit to perform data writing operations during the compensation phase, thereby improving the efficiency of the pixel circuit driving the light-emitting device to emit light.

[0184] Furthermore, in this embodiment, since the fourth reset sub-circuit 540 remains closed during the light-emitting phase to disconnect the sixth node N6 from the first voltage line Vinit1, the second capacitor Cst2 and the third capacitor Cst3 are coupled into a single capacitor to automatically raise the voltage at the third node N3 when the voltage at the first node N1 transitions to the data voltage Vdata. Thus, by automatically raising the voltage at the third node N3 when the voltage at the first node N1 transitions, the driving sub-circuit can eliminate the threshold voltage at the third node N3 when it conducts the second node N2 and the third node N3 to generate the driving current based on the data voltage Vdata at the first node N1 during the light-emitting phase, thereby compensating for the threshold voltage.

[0185] In some embodiments, this application provides a display panel, which includes a plurality of sub-pixels. Each sub-pixel includes a pixel circuit and a light-emitting device that are interconnected. The pixel circuit is as described in the above embodiments.

[0186] In some embodiments, this application provides a display panel including a plurality of sub-pixels, each sub-pixel including interconnected pixel circuits and light-emitting devices. When the display panel is in operation, the pixel circuits on the display panel execute the pixel circuit control methods described in the above embodiments.

[0187] In some embodiments, this application provides an electronic device that implements the control method for the pixel circuit described in the various embodiments above. This function can be implemented in hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above-described function.

[0188] In the embodiments of this application, the electronic devices provided in the embodiments of this application may include, but are not limited to, mobile phones, tablet computers, laptops, handheld computers, netbooks, personal digital assistants (PDAs), wearable electronic devices, virtual reality devices, and other terminal devices with their own display panels.

[0189] In some embodiments, this application provides an electronic device, including: a display panel, a processor, and a memory; the display panel includes a plurality of sub-pixels, each sub-pixel including a pixel circuit and a light-emitting device interconnected thereto, the pixel circuit being as described in various embodiments.

[0190] In some embodiments, this application provides an electronic device, including: a display panel, a processor, and a memory; the memory is used to store computer program code, the computer program code including computer execution instructions, and when the electronic device is running, the processor executes the computer execution instructions to cause the pixel circuit on the display panel of the electronic device to perform the pixel circuit control method as described in the above embodiments.

[0191] In some embodiments, this application provides an electronic device, including: a processor; the processor is configured to be coupled to a memory, and after reading instructions from the memory, execute the pixel circuit control method described in the above embodiments according to the instructions.

[0192] In some embodiments, this application provides a computer-readable storage medium including computer instructions that, when executed on an electronic device, cause the pixel circuit of the display panel of the electronic device to perform the pixel circuit control method described above.

[0193] In some embodiments, this application provides a computer-readable storage medium including computer instructions that, when executed on an electronic device, cause the pixel circuit of the display panel of the electronic device to perform the pixel circuit control method described above.

[0194] In some embodiments, this application provides a computer program product that, when run on an electronic device, causes the pixel circuit of the display panel of the electronic device to execute the pixel circuit control method described in the above embodiments.

[0195] In some embodiments, this application provides a computer program product that, when run on an electronic device, causes the pixel circuit of the display panel of the electronic device to execute the pixel circuit control method described in the above embodiments.

[0196] In some embodiments, this application provides an apparatus including a display panel and a processor. The display panel includes a plurality of sub-pixels, each sub-pixel including interconnected pixel circuits and light-emitting devices, the pixel circuits being as described in the various embodiments. Furthermore, the processor of the apparatus supports the pixel circuits of the display panel in implementing the functions corresponding to the control methods for the pixel circuits described in the various embodiments. In one possible design, the apparatus further includes a memory for storing necessary program instructions and data of the electronic device.

[0197] Through the above description of the embodiments, those skilled in the art can clearly understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0198] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A pixel circuit, characterized in that, The pixel circuit is coupled to the light-emitting device, and the pixel circuit includes: a driving sub-circuit, a first control sub-circuit, a second control sub-circuit, and a data writing sub-circuit; The first control sub-circuit is used to be coupled to the first light-emitting control line and the first voltage terminal respectively, and the first control sub-circuit is also coupled to the second node; the first control sub-circuit is configured to control the first voltage terminal to connect to the second node in response to the control signal provided by the first light-emitting control line. The second control sub-circuit is used to couple to the second light-emitting control line and the light-emitting device respectively, and the light-emitting device is also coupled to the second voltage terminal; the voltage value provided by the second voltage terminal is lower than the voltage value provided by the first voltage terminal; The second control sub-circuit is also coupled to the third node. The second control sub-circuit is configured to control the third node to connect or disconnect from the light-emitting device in response to the control signal provided by the second light-emitting control line. The data writing sub-circuit is used to be coupled to the data writing control line and the light-emitting data line respectively, and the data writing sub-circuit is also coupled to the first node; the data writing sub-circuit is configured to control the light-emitting data line to connect to the first node in response to the control signal provided by the data writing control line. The driving sub-circuit is coupled to the first node, the second node and the third node respectively. The driving sub-circuit is configured to control the connection between the second node and the third node based on the potential of the first node; and to generate a driving current to drive the light-emitting device when the first control sub-circuit controls the first voltage terminal to be connected to the second node and the second control sub-circuit controls the third node to be connected to the light-emitting device. The process includes at least a compensation phase, a data writing phase, and a light emission phase within one frame period. During the compensation phase, the first control sub-circuit responds to a control signal provided by the first light emission control line, controlling the first voltage terminal to connect with the second node; the second control sub-circuit responds to a control signal provided by the second light emission control line, controlling the third node to disconnect from the light-emitting device. During the data writing phase, the data writing sub-circuit responds to a control signal provided by the data writing control line, controlling the light emission data line to connect with the first node. During the light emission phase, the first control sub-circuit responds to a control signal provided by the first light emission control line, controlling the first voltage terminal to connect with the second node; the second control sub-circuit responds to a control signal provided by the second light emission control line, controlling the third node to connect with the light-emitting device; and the driving sub-circuit controls the connection between the second node and the third node based on the potential of the first node, generating a driving current to drive the light-emitting device.

2. The pixel circuit according to claim 1, characterized in that, The driving sub-circuit includes a driving transistor; The control electrode of the driving transistor is coupled to the first node, the first electrode of the driving transistor is coupled to the second node, and the second electrode of the driving transistor is coupled to the third node; the driving transistor is configured to control the connection between the second node and the third node based on the potential of the first node to generate the driving current; The driving transistor is an N-type low-temperature polycrystalline silicon oxide (LTPO) transistor, or the driving transistor is an N-type indium gallium zinc oxide (IGZO) transistor.

3. The pixel circuit according to claim 1 or 2, characterized in that, The first control sub-circuit includes a first transistor; The control electrode of the first transistor is coupled to the first light-emitting control line, the first electrode of the first transistor is coupled to the first voltage terminal, and the second electrode of the first transistor is coupled to the second node; the first transistor is configured to connect the first voltage terminal and the second node in response to a control signal provided by the first light-emitting control line.

4. The pixel circuit according to claim 3, characterized in that, The second control sub-circuit includes a second transistor; The control electrode of the second transistor is coupled to the second light-emitting control line, the first electrode of the second transistor is coupled to the third node, and the second electrode of the second transistor is coupled to the light-emitting device; the second transistor is configured to connect the third node and the light-emitting device in response to a control signal provided by the second light-emitting control line.

5. The pixel circuit according to claim 4, characterized in that, The data writing sub-circuit includes a third transistor; The control electrode of the third transistor is coupled to the data write control line, the first electrode of the third transistor is coupled to the light-emitting data line, and the second electrode of the third transistor is coupled to the first node; the third transistor is configured to connect the light-emitting data line and the first node in response to a control signal provided by the data write control line.

6. The pixel circuit according to claim 5, characterized in that, The pixel circuit further includes: a first reset circuit and a second reset circuit; The first reset sub-circuit is used to be coupled to the first reset control line and the first voltage line respectively, and the first reset sub-circuit is also coupled to the first node; the first reset sub-circuit is configured to control the first voltage line to connect to the first node in response to the control signal provided by the first reset control line. The second reset sub-circuit is used to couple to the second reset control line and the second voltage line respectively, and the second reset sub-circuit is also coupled to the third node; the second reset sub-circuit is configured to control the second voltage line to connect to the third node in response to a control signal provided by the second reset control line.

7. The pixel circuit according to claim 6, characterized in that, The first reset circuit includes a fourth transistor; The control electrode of the fourth transistor is coupled to the first reset control line, the first electrode of the fourth transistor is coupled to the first voltage line, and the second electrode of the fourth transistor is coupled to the first node; the fourth transistor is configured to connect the first voltage line and the first node in response to a control signal provided by the first reset control line.

8. The pixel circuit according to claim 6 or 7, characterized in that, The second reset circuit includes a fifth transistor; The control electrode of the fifth transistor is coupled to the second reset control line, the first electrode of the fifth transistor is coupled to the second voltage line, and the second electrode of the fifth transistor is coupled to the third node; the fifth transistor is configured to connect the second voltage line and the third node in response to a control signal provided by the second reset control line.

9. The pixel circuit according to claim 8, characterized in that, The pixel circuit further includes: a third reset sub-circuit; The third reset circuit is used to couple to the second reset control line and the third voltage line respectively. The third reset circuit is also coupled to the fourth node, which is used to couple to the light-emitting device. The third reset circuit is configured to control the third voltage line to connect to the fourth node in response to a control signal provided by the second reset control line.

10. The pixel circuit according to claim 9, characterized in that, The third reset circuit includes a sixth transistor; The control electrode of the sixth transistor is coupled to the second reset control line, the first electrode of the sixth transistor is coupled to the third voltage line, and the second electrode of the sixth transistor is coupled to the fourth node; the sixth transistor is configured to connect the third voltage line and the fourth node in response to a control signal provided by the second reset control line.

11. The pixel circuit according to claim 10, characterized in that, The pixel circuit further includes: a bootstrap circuit; The bootstrap circuit is coupled to the first node and the third node respectively; the bootstrap circuit is configured to bootstrap the voltage of the third node in response to a voltage jump in the first node.

12. The pixel circuit according to claim 11, characterized in that, The bootstrap circuit includes a first capacitor; The first plate of the first capacitor is coupled to the first node, and the second plate of the first capacitor is coupled to the third node; the first capacitor is configured to raise the voltage of the third node in response to a voltage jump at the first node.

13. The pixel circuit according to claim 12, characterized in that, The pixel circuit further includes: a first isolation sub-circuit, a second isolation sub-circuit, a third control sub-circuit, and a fourth reset sub-circuit; The third control sub-circuit is used to couple with the second light-emitting control line. The third control sub-circuit is also coupled with the first node and the fifth node respectively. The fifth node is used to couple with the data writing sub-circuit. The third control sub-circuit is configured to control the fifth node to connect with the first node in response to the control signal provided by the second light-emitting control line. The first isolation sub-circuit is coupled to the fifth node and the sixth node respectively, and the first isolation sub-circuit is configured to isolate the fifth node from the sixth node; The second isolation sub-circuit is coupled to the sixth node and the third node respectively, and the second isolation sub-circuit is configured to isolate the sixth node from the third node; The fourth reset sub-circuit is used to couple to the first reset control line and the first voltage line respectively, and the fourth reset sub-circuit is coupled to the sixth node; the fourth reset sub-circuit is configured to control the first voltage line to connect to the sixth node in response to the control signal provided by the first reset control line.

14. The pixel circuit according to claim 13, characterized in that, During the reset and compensation phases within a frame period, the fourth reset sub-circuit is used to control the first voltage line to connect with the sixth node in response to the control signal provided by the first reset control line; during the data writing phase, the data writing sub-circuit is used to control the light-emitting data line to connect with the fifth node in response to the control signal provided by the data writing control line; the data writing phase is between the start and end times of the compensation phase; during the light-emitting phase, the third control sub-circuit is used to control the fifth node to connect with the first node in response to the control signal provided by the second light-emitting control line.

15. The pixel circuit according to claim 13 or 14, characterized in that, The first isolation sub-circuit includes a second capacitor; The first plate of the second capacitor is coupled to the fifth node, and the second plate of the second capacitor is coupled to the sixth node; the second capacitor is configured to isolate the fifth node from the sixth node.

16. The pixel circuit according to claim 15, characterized in that, The second isolation sub-circuit includes a third capacitor; The first plate of the third capacitor is coupled to the sixth node, and the second plate of the third capacitor is coupled to the third node; the third capacitor is configured to isolate the sixth node from the third node.

17. The pixel circuit according to claim 16, characterized in that, The third control sub-circuit includes a seventh transistor; The control electrode of the seventh transistor is coupled to the second light-emitting control line, the first electrode of the seventh transistor is coupled to the first node, and the second electrode of the seventh transistor is coupled to the fifth node; the seventh transistor is configured to connect the fifth node and the first node in response to a control signal provided by the second light-emitting control line.

18. The pixel circuit according to claim 17, characterized in that, The fourth reset circuit includes an eighth transistor; The control electrode of the eighth transistor is coupled to the first reset control line, the first electrode of the eighth transistor is coupled to the first voltage line, and the second electrode of the eighth transistor is coupled to the sixth node; the eighth transistor is configured to connect the first voltage line and the sixth node in response to a control signal provided by the first reset control line.

19. The pixel circuit according to claim 18, characterized in that, The pixel circuit further includes: an energy storage sub-circuit; The energy storage sub-circuit is coupled to the second node and the third node respectively, and the energy storage sub-circuit is configured to maintain the potential of the second node and the third node; Alternatively, the energy storage sub-circuit is coupled to the first voltage terminal and the third node respectively, and the energy storage sub-circuit is configured to maintain the potential of the third node.

20. The pixel circuit according to claim 19, characterized in that, The energy storage sub-circuit includes a fourth capacitor; The first terminal of the fourth capacitor is coupled to the second node, and the second terminal of the fourth capacitor is coupled to the third node; the fourth capacitor is configured to maintain the potential of the second node and the third node. Alternatively, the first terminal of the fourth capacitor is coupled to the first voltage terminal, and the second terminal of the fourth capacitor is coupled to the third node; the fourth capacitor is configured to maintain the potential of the third node.

21. A method for controlling a pixel circuit, characterized in that, The control method is applied to a pixel circuit, which includes a driving sub-circuit, a first control sub-circuit, a second control sub-circuit, and a data writing sub-circuit; the first control sub-circuit is used to be coupled to a first light-emitting control line and a first voltage terminal respectively, and the first control sub-circuit is coupled to a second node. The second control sub-circuit is used to couple to the second light-emitting control line and the light-emitting device respectively, and the light-emitting device is coupled to the second voltage terminal; The voltage value provided by the second voltage terminal is less than the voltage value provided by the first voltage terminal; The second control sub-circuit is coupled to the third node; the data writing sub-circuit is used to be coupled to the data writing control line and the light emission data line respectively, and the data writing sub-circuit is coupled to the first node; the driving sub-circuit is coupled to the first node, the second node and the third node respectively. The control method includes at least a compensation phase, a data writing phase, and a light emission phase within a frame period; the control method includes: During the compensation phase, the first control sub-circuit responds to the control signal provided by the first light-emitting control line by controlling the first voltage terminal to connect with the second node, and the second control sub-circuit responds to the control signal provided by the second light-emitting control line by controlling the third node to disconnect from the light-emitting device. During the data writing phase, the data writing sub-circuit responds to the control signal provided by the data writing control line and controls the light-emitting data line to connect with the first node; During the light-emitting phase, the first control sub-circuit responds to the control signal provided by the first light-emitting control line and controls the first voltage terminal to connect with the second node. The second control sub-circuit responds to the control signal provided by the second light-emitting control line and controls the third node to connect with the light-emitting device. The driving sub-circuit controls the second node and the third node to connect based on the potential of the first node, thereby generating a driving current to drive the light-emitting device.

22. The pixel circuit control method according to claim 21, characterized in that, The pixel circuit further includes: a first isolation sub-circuit, a second isolation sub-circuit, a third control sub-circuit, and a fourth reset sub-circuit; the third control sub-circuit is coupled to the second light-emitting control line, and is coupled to the first node and the fifth node respectively; the fifth node is coupled to the data writing sub-circuit; the first isolation sub-circuit is coupled to the fifth node and the sixth node respectively; the second isolation sub-circuit is coupled to the sixth node and the third node respectively; the fourth reset sub-circuit is coupled to the first reset control line and the first voltage line respectively, and is coupled to the sixth node; The method further includes: During the reset and compensation phases within a frame period, the fourth reset sub-circuit responds to the control signal provided by the first reset control line and controls the first voltage line to connect with the sixth node. During the data writing phase, the data writing sub-circuit responds to the control signal provided by the data writing control line and controls the light-emitting data line to connect with the fifth node; the data writing phase is between the start and end times of the compensation phase. During the light-emitting phase, the third control sub-circuit responds to the control signal provided by the second light-emitting control line and controls the fifth node to connect with the first node.

23. A display panel, characterized in that, The display panel includes a plurality of sub-pixels, each sub-pixel including a pixel circuit and a light-emitting device connected to each other, wherein the pixel circuit is the pixel circuit as described in any one of claims 1 to 20.

24. An electronic device, characterized in that, The electronic device includes: a display panel, a processor, and a memory; the display panel includes a plurality of sub-pixels, each sub-pixel including interconnected pixel circuits and light-emitting devices, the pixel circuits being pixel circuits as claimed in any one of claims 1 to 20; and / or, the electronic device includes: a display panel, a processor, and a memory, the processor being coupled to the memory; the memory being used to store computer program code; the computer program code including computer instructions, which, when executed by the processor, cause the pixel circuits to perform the control method for the pixel circuits as claimed in any one of claims 21 to 22.

25. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes computer instructions that, when executed on an electronic device, cause the pixel circuitry of the display panel of the electronic device to perform the pixel circuitry control method as described in any one of claims 21-22.

26. A computer program product, characterized in that, The computer program product includes computer instructions that, when executed on an electronic device, cause the pixel circuit of the display panel of the electronic device to perform the pixel circuit control method as described in any one of claims 21-22.

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