Memory device performing timing bias and offset calibration

Abstract

The memory device includes a data input / output (I / O) pin, an output driver, a multi-level receiver, and a calibrator. The output driver is connected to the data I / O pin and generates an internal input signal based on a first clock signal. The multi-stage receiver is connected to the data I / O pin and includes a plurality of samplers. The plurality of samplers generate a plurality of decision signals by sampling an internal input signal based on a reference voltage and a second clock signal. The calibrator detects and compensates for at least one of timing deviations and offsets associated with the plurality of samplers based on the plurality of decision signals. The internal input signal is a multi-level signal having three or more voltage levels different from each other.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0086319 filed on July 4, 2023 in the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Example embodiments relate generally to a semiconductor integrated circuit, and more particularly, to a memory device that performs timing skew and offset calibration. Background Art

[0004] Semiconductor memory devices can be divided into two categories according to whether they retain stored data when disconnected from power. These categories include volatile memory devices, which lose stored data when disconnected from power, and nonvolatile memory devices, which retain stored data when disconnected from power. Although volatile memory devices can perform read and write operations at high speeds, the contents stored therein may be lost when power is turned off. Since nonvolatile memory devices retain the contents stored therein even when power is turned off, they can be used to store data that needs to be retained.

[0005] Recently, as the performance of semiconductor memory devices has been improved, the communication speed (or interface speed) between a memory controller and the semiconductor memory devices has also been increased. Therefore, multi-level signaling that transmits a plurality of bits during one unit interval (UI) has been studied. Summary of the invention

[0006] At least one example embodiment of the present disclosure provides a memory device capable of effectively calibrating timing deviation and offset internally without external input while receiving a signal based on a multi-level signaling scheme.

[0007] At least one example embodiment of the present disclosure provides a memory device capable of effectively calibrating timing deviation and offset internally without external input while receiving a signal based on a non-return-to-zero (NRZ) scheme.

[0008] According to an example embodiment, a memory device includes a data input / output (I / O) pin, an output driver, a multi-level receiver, and a calibrator. The output driver is connected to the data I / O pin and generates an internal input signal based on a first clock signal. The multi-level receiver is connected to the data I / O pin and includes a plurality of samplers. The plurality of samplers generate a plurality of decision signals by sampling the internal input signal based on a reference voltage and a second clock signal. The calibrator detects and compensates for at least one of a timing deviation and an offset associated with the plurality of samplers based on the plurality of decision signals. The internal input signal is a multi-level signal having three or more voltage levels different from each other.

[0009] According to an example embodiment, a memory device includes a data input / output (I / O) pin, an output driver, a receiver, and a calibrator. The output driver is connected to the data I / O pin and generates an internal input signal based on a first clock signal. The receiver is connected to the data I / O pin and includes a plurality of samplers. The plurality of samplers generate a plurality of decision signals by sampling the internal input signal based on a reference voltage and a plurality of second clock signals whose phases overlap. The calibrator detects and compensates for an offset associated with the plurality of samplers based on the plurality of decision signals. The internal input signal is a non-return-to-zero (NRZ) signal having two voltage levels different from each other.

[0010] According to an example embodiment, a memory device includes a data input / output (I / O) pin, an output driver, a multi-stage receiver, and a calibrator. The output driver is connected to the data I / O pin and generates an internal input signal based on a first clock signal. The multi-stage receiver is connected to the data I / O pin and includes a plurality of samplers. The plurality of samplers generate a plurality of decision signals by sampling the internal input signal based on a reference voltage and a second clock signal. The calibrator detects and compensates for at least one of the timing deviation and offset associated with the plurality of samplers based on the plurality of decision signals. The plurality of samplers include a first sampler, a second sampler, a third sampler, a fourth sampler, a fifth sampler, and a sixth sampler. The first sampler generates a first decision signal by sampling the internal input signal based on a reference voltage and a first sub-clock signal. The second sampler generates a second decision signal by sampling the internal input signal based on a reference voltage and a second sub-clock signal. The third sampler generates a third decision signal by sampling the internal input signal based on a reference voltage and a third sub-clock signal. The fourth sampler generates a fourth decision signal by sampling the internal input signal based on a reference voltage and a fourth sub-clock signal. The fifth sampler generates a fifth decision signal by sampling an internal input signal based on a reference voltage and a fifth sub-clock signal. The sixth sampler generates a sixth decision signal by sampling an internal input signal based on a reference voltage and a sixth sub-clock signal. The first sub-clock signal to the sixth sub-clock signal are generated based on the second clock signal. The phases of the first sub-clock signal to the fourth sub-clock signal partially overlap with each other, and the phases of the first sub-clock signal, the fifth sub-clock signal and the sixth sub-clock signal are the same as each other. The calibrator includes a first offset control unit and a first delay control unit. The first offset control unit determines that an offset associated with the first sampler has occurred in response to the logic level of the first decision signal being different from the logic level of each of the second decision signal, the third decision signal and the fourth decision signal, and adjusts the output level of the first sampler. The first delay control unit determines that a timing deviation associated with the first sampler has occurred in response to the logic level of the first decision signal being different from the logic level of each of the fifth decision signal and the sixth decision signal, and adjusts the phase of the first sub-clock signal.

[0011] In a memory device according to an example embodiment, a self-calibration operation may be performed using an internal input signal generated from an output driver. For example, a self-calibration operation may be performed internally without an external input signal. Therefore, timing deviations and / or offsets associated with multiple samplers may be effectively compensated, and the memory device may have a relatively improved or enhanced DQ margin. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Illustrative, non-limiting example embodiments will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0013] Figure 1 is a block diagram illustrating a memory device according to example embodiments.

[0014] Figure 2A and Figure 2B is a block diagram illustrating an example of a calibrator included in a memory device according to example embodiments.

[0015] Figure 3A and Figure 3B is a block diagram illustrating a memory device according to example embodiments.

[0016] Figure 4A and Figure 4B is a diagram for describing multi-level signals input to or output from a memory device according to example embodiments.

[0017] Figure 5 is a diagram showing a method according to an example embodiment Figure 1 A block diagram of an example of a memory device.

[0018] Figure 6 , Fig. 7A , Figure 7B , Figure 7C , Fig.7D , Figure 8 , Fig. 9A and Fig. 9B is used to describe the Figure 5 A diagram of the operation of a memory device.

[0019] Fig. 10A and Fig. 10B is a diagram showing a method according to an example embodiment Figure 1 A block diagram of an example of a memory device.

[0020] Fig.11 , Fig.12 , Fig.13A and Fig. 13B is used to describe the Fig. 10A and Fig. 10B A diagram of the operation of a memory device.

[0021] Fig.14 is used to describe the Figure 5 , Fig. 10A and Fig. 10B A diagram of the operation of a memory device.

[0022] Fig.15 is a block diagram illustrating a memory device according to example embodiments.

[0023] Fig.16is a block diagram illustrating an example of a calibrator included in a memory device according to example embodiments.

[0024] Fig.17A and Fig. 17B is a block diagram illustrating a memory device according to example embodiments.

[0025] Fig.18 is a diagram for describing an NRZ signal input to or output from a memory device according to example embodiments.

[0026] Fig.19 is a diagram showing a method according to an example embodiment Fig.15 A block diagram of an example of a memory device.

[0027] Fig. 20 is a block diagram illustrating a memory system according to example embodiments.

[0028] Fig.21A and Fig. 21B is a diagram showing a method according to an example embodiment Fig. 20 A block diagram of an example of a memory system.

[0029] Fig. 22 is a block diagram illustrating an example of a memory device included in a memory system according to example embodiments.

[0030] Fig.23 is a flowchart illustrating a method of operating a memory device according to example embodiments. DETAILED DESCRIPTION

[0031] Various example embodiments will be more fully described with reference to the accompanying drawings showing embodiments. However, the present disclosure can be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. In this application, the same reference numerals refer to the same elements.

[0032] Figure 1 is a block diagram illustrating a memory device according to example embodiments.

[0033] Reference Figure 1 , the memory device 1000 includes a data input / output (I / O) pin 1010 , an output driver 1100 , a multi-stage receiver 1200 , and a calibrator 1300 .

[0034] In some example embodiments, the memory device 1000 may operate based on a multi-level signaling scheme. For example, in a normal operation mode, the output driver 1100 may generate a multi-level signal based on multi-bit data, and the multi-level receiver 1200 may generate a plurality of decision signals for generating multi-bit data based on the multi-level signal. For example, the multi-level signal may have one of three or more voltage levels that are different from each other during one unit interval (UI), and the multi-bit data may include two or more bits that are different from each other. Figure 3A and Figure 3B A detailed operation of the memory device 1000 in the normal operation mode is described.

[0035] In some example embodiments, the memory device 1000 may operate in a calibration mode (or compensation mode) different from a normal operation mode. For example, the memory device 1000 may include a calibrator 1300 for performing operations in the calibration mode. For example, in the calibration mode, the calibrator 1300 may detect and compensate (or calibrate or correct) at least one of a timing deviation and an offset associated with (or related to) the multi-stage receiver 1200. Figure 1 Detailed operation of the memory device 1000 in the calibration mode is shown.

[0036] The output driver 1100 is connected to the data I / O pin 1010 and generates an internal input signal IS_CAL based on the first clock signal OSC_CLK. For example, although not shown in detail, the output driver 1100 may include at least one p-type metal oxide semiconductor (PMOS) transistor and at least one n-type metal oxide semiconductor (NMOS) transistor. At least one PMOS transistor may be connected between a power supply voltage and an output node, and at least one NMOS transistor may be connected between an output node and a ground voltage. For example, the output driver 1100 may be referred to as an off-chip driver (OCD).

[0037] The multi-stage receiver 1200 is connected to the data I / O pin 1010 and includes a plurality of samplers 1210. The plurality of samplers 1210 generate a plurality of decision signals DCS_CAL by sampling an internal input signal IS_CAL based on a reference voltage VREF_CAL and a phase-adjusted (or delay-adjusted) second clock signal S_CLK' adjusted based on a second clock signal S_CLK different from the first clock signal OSC_CLK. Herein, the phase of the phase-adjusted second clock signal S_CLK' may be the same as the phase of the second clock signal S_CLK before the second clock signal is adjusted. For example, unlike in the normal operating mode, all of the plurality of samplers 1210 may operate using the same reference voltage (e.g., reference voltage VREF_CAL) in the calibration mode.

[0038] Will refer to Figure 5 , Fig. 10A and Fig. 10B A detailed configuration of the multi-stage receiver 1200 is described.

[0039] In some example embodiments, when a calibration operation is performed in a calibration mode, both the output driver 1100 and the multi-stage receiver 1200 may be enabled (or activated) and operated.

[0040] In some example embodiments, as will be referred to Figure 6 , Fig. 7A , Figure 7B , Figure 7C and Fig.7D As described above, the internal input signal IS_CAL may have a variable level (e.g., a variable voltage level), and the reference voltage VREF_CAL may have a fixed level (e.g., a fixed voltage level). In other words, the sampling operation may be performed while fixing the level of the reference voltage VREF_CAL and changing the level of the internal input signal IS_CAL. In some example embodiments, as will be described with reference to Fig.14 As described above, the internal input signal IS_CAL may have a fixed level, and the reference voltage VREF_CAL may have a variable level. In other words, the sampling operation may be performed while fixing the level of the internal input signal IS_CAL and changing the level of the reference voltage VREF_CAL.

[0041] The calibrator 1300 detects and compensates for at least one of a timing deviation and an offset associated with the plurality of samplers 1210 based on the plurality of decision signals DCS_CAL. Fig. 9A and Fig. 9B As described above, the timing deviation may represent or indicate a time error (or difference) for the outputs of the plurality of samplers 1210 and / or a time error for the phase-adjusted second clock signal S_CLK' provided to the plurality of samplers 1210. Fig.13A and Fig. 13B As described, the offset may represent or indicate an error (or difference) in output levels (eg, voltage levels) of the outputs of the plurality of samplers 1210 .

[0042] Will refer to Figure 2A , Figure 2B , Figure 5 , Fig. 10A and Fig. 10B The detailed configuration of the calibrator 1300 is described.

[0043] The data I / O pin 1010 is connected to the output driver 1100 and the multi-stage receiver 1200. For example, the pin may be a contact pad or a contact pin, but example embodiments are not limited thereto.

[0044] In some example embodiments, in the calibration mode, at least one of a timing deviation and an offset associated with the plurality of samplers 1210 may be detected and compensated using only the internal input signal IS_CAL without an external input signal received from the outside (e.g., from an external device) through the data I / O pin 1010. For example, in the calibration mode, the data I / O pin 1010 may have a high impedance (Hi-Z) state to prevent reception of an external input signal.

[0045] The memory device 1000 according to example embodiments may perform a self-calibration operation using an internal input signal IS_CAL generated from the output driver 1100. For example, the self-calibration operation may be performed internally without an external input signal. Therefore, the timing deviation and / or offset associated with the plurality of samplers 1210 may be effectively compensated, and the memory device 1000 may have a relatively improved or enhanced DQ margin.

[0046] Figure 2A and Figure 2B is a block diagram illustrating a calibrator included in a memory device according to example embodiments.

[0047] Reference Figure 2A , the calibrator 1302 may include a timing deviation detection circuit 1304 and a plurality of delay control units 1306 . Figure 2A An example of the calibrator 1302 detecting and compensating for timing deviations associated with the plurality of samplers 1210 is shown.

[0048] The timing deviation detection circuit 1304 may detect timing deviations associated with the plurality of samplers 1210 based on the plurality of decision signals DCS_CAL, and may generate a plurality of delay control signals DCON for controlling the plurality of delay control units 1306 .

[0049] The plurality of delay control units 1306 can compensate for the timing deviation associated with the plurality of samplers 1210 by adjusting the phase of the second clock signal S_CLK based on the plurality of delay control signals DCON, and can generate a phase-adjusted (or delay-adjusted) second clock signal S_CLK'. For example, the number of the plurality of delay control units 1306 can be substantially equal to the number of the plurality of samplers 1210. For example, the plurality of samplers 1210 can operate based on the phase-adjusted second clock signal S_CLK'.

[0050] Reference Figure 2B, the calibrator 1312 may include an offset detection circuit 1314 and a plurality of offset control units 1316 . Figure 2B An example is shown in which the calibrator 1312 detects and compensates for offsets associated with the plurality of samplers 1210 .

[0051] The offset detection circuit 1314 may detect offsets associated with the plurality of samplers 1210 based on the plurality of decision signals DCS_CAL, and may generate a plurality of offset control signals OCON for controlling the plurality of offset control units 1316 .

[0052] The plurality of offset control units 1316 may compensate for offsets associated with the plurality of samplers 1210 based on the plurality of offset control signals OCON. For example, the number of the plurality of offset control units 1316 may be substantially equal to the number of the plurality of samplers 1210. For example, each of the plurality of offset control units 1316 may be included in a corresponding one of the plurality of samplers 1210.

[0053] In some example embodiments, the calibrator may include Figure 2A The timing deviation detection circuit 1304 and the plurality of delay control units 1306 in the Figure 2B The calibrator can detect and compensate for both timing deviation and offset associated with the plurality of samplers 1210 by using the offset detection circuit 1314 and the plurality of offset control units 1316. In other words, the calibrator can detect and compensate for both timing deviation and offset associated with the plurality of samplers 1210.

[0054] Figure 3A and Figure 3B is a block diagram illustrating a memory device according to an example embodiment. Figure 1 Duplicate description.

[0055] Reference Figure 3A and Figure 3B , illustrating the operation of the memory device 1000 in a normal operation mode.

[0056] like Figure 3A As shown in FIG. 1 , in the normal operation mode after the calibration mode, the memory device 1000 may perform a data output operation. For example, the output driver 1100 may generate a multi-level output signal ML_OUT based on the multi-bit data MBDAT and may output the multi-level output signal ML_OUT through the data I / O pin 1010 .

[0057] In some example embodiments, the data output operation may be at least a part of a data read operation of the memory device 1000. For example, when performing a data read operation, the data output operation may be to read data from a memory cell array (eg, Fig. 22The multi-bit data MBDAT read from the memory bank arrays 280a to 280d in the memory bank arrays 280a to 280d is output to an external device (eg, Fig. 20 Operation of the memory controller 20).

[0058] like Figure 3B As shown in , in the normal operation mode after the calibration mode, the memory device 1000 can perform a data receiving operation. For example, a multi-level input signal ML_IN can be received through the data I / O pin 1010, and a plurality of samplers 1210 included in the multi-level receiver 1200 can generate a plurality of decision signals DCS_ML by sampling the multi-level input signal ML_IN based on a plurality of reference voltages VREF_ML and a second clock signal S_CLK' adjusted in phase. The plurality of reference voltages VREF_ML may be different from each other. For example, unlike in the calibration mode, at least some of the plurality of samplers 1210 may operate using different reference voltages (e.g., a plurality of reference voltages VREF_ML) in the normal operation mode.

[0059] In some example embodiments, the data receiving operation may be at least a part of the data writing operation of the memory device 1000. For example, when performing the data writing operation, the data receiving operation may be an operation of receiving a multi-level input signal ML_IN corresponding to multi-bit data to be written in the memory cell array from an external device.

[0060] In some example embodiments, when a data output operation or a data receiving operation is performed in a normal operation mode, one of the output driver 1100 and the multi-stage receiver 1200 may be enabled (or activated) and operated. Figure 3A When performing a data output operation as shown in , the output driver 1100 may be enabled and the multi-stage receiver 1200 may be disabled (or deactivated). Figure 3B When performing a data receiving operation as shown in , the multi-stage receiver 1200 may be enabled and the output driver 1100 may be disabled. In some example embodiments, when performing a data output operation or a data receiving operation in a normal operation mode, the calibrator 1300 may be disabled. Figure 3A and Figure 3B In the figure, disabled components are shown with dashed lines.

[0061] In some example embodiments, the operation mode of the memory device 1000 may be set externally (eg, based on external control). For example, when a Fig. 20 When the memory controller 20 in the memory device 1000 receives the calibration mode entry command, the memory device 1000 may operate in the calibration mode and may perform Figure 1For example, when receiving a write command or a read command from an external device, the memory device 1000 may perform a data write operation or a data read operation, and may perform Figure 3A The data output operation shown in Figure 3B The data receiving operation shown in .

[0062] In some example embodiments, the operation mode of the memory device 1000 may be set internally (eg, by itself). For example, in each predetermined cycle or when a predetermined operating environment is satisfied, the memory device 1000 may operate in a calibration mode and may perform Figure 1 The calibration operation shown in .

[0063] The memory device 1000 according to the example embodiment can be operated based on a multi-level signaling scheme. The multi-level signaling scheme can be used as a means to compress the bandwidth required to send data at a given bit rate. In a simple binary scheme, two single symbols (usually two voltage levels) can be used to represent "1" and "0", and therefore, the symbol rate can be equal to the bit rate. In contrast, the principle of the multi-level signaling scheme can use a larger alphabet of m symbols to represent data, so that each symbol can represent more than one bit of data. As a result, the number of symbols that need to be sent can be less than the number of bits (for example, the symbol rate can be less than the bit rate), and therefore, the bandwidth can be compressed. The alphabet of symbols can be composed of multiple different voltage levels. For example, in a four-level scheme, a group of two data bits can be mapped to one of four symbols. For each pair of data bits, only one symbol needs to be sent, so the symbol rate can be half the bit rate.

[0064] In other words, a multi-level signaling scheme can be used to increase the data transmission (or transfer) rate without increasing the frequency of data transmission and / or the transmission power of the data being communicated. An example of one type of multi-level signaling scheme is a pulse amplitude modulation (PAM) scheme, in which a unique symbol of a multi-level signal can represent multiple bits of data. The number of possible pulse amplitudes in a digital PAM scheme can be some power of two. For example, in a 4-level PAM (e.g., in PAM4), there can be 2 2 possible discrete pulse amplitudes, in 8-level PAM (e.g., in PAM8) there can be 2 3 possible discrete pulse amplitudes, and in 16-level PAM (e.g., in PAM16) there can be 2 4 However, example embodiments are not limited thereto, and example embodiments may be applied or used for an X-level PAM (eg, PAM(X)) having X possible pulse amplitudes, where X is a positive integer greater than or equal to three.

[0065] Figure 4A and Figure 4B is a diagram for describing multi-level signals input to or output from a memory device according to example embodiments.

[0066] Figure 4A An ideal eye diagram of a data signal (eg, a PAM4 signal) generated based on a 4-level scheme (eg, a PAM4 scheme) as an example of a multi-level signaling scheme (eg, a PAM scheme) is shown. Figure 4B By simplifying Figure 4A For example, Figure 4A and Figure 4B The PAM4 signal can be Figure 3A The multi-level output signal ML_OUT in Figure 3B Example of a multi-level input signal ML_IN in FIG.

[0067] Reference Figure 4A , eye diagrams can be used to indicate signal quality in high-speed transmission. For example, an eye diagram can represent four symbols of a signal (e.g., "00", "01", "10", and "11"), and each of the four symbols can be represented by a corresponding one of different voltage levels (e.g., voltage amplitudes) VL11, VL12, VL13, and VL14. Eye diagrams can be used to provide a healthy visual indication of signal integrity and can indicate the noise margin of a data signal.

[0068] To generate an eye diagram, an oscilloscope or other computing device may sample a digital signal according to a sampling period SP (e.g., a unit interval or a bit period). The sampling period SP may be defined by a clock signal associated with the transmission of the measured signal. The oscilloscope or other computing device may measure the voltage level of the signal during the sampling period SP to form a plurality of traces TRC. Various characteristics associated with the measured signal may be determined by superimposing a plurality of traces TRC.

[0069] The eye diagram can be used to identify multiple characteristics of the communication signal (such as jitter, crosstalk, electromagnetic interference (EMI), signal loss, signal-to-noise ratio (SNR), other characteristics, or combinations thereof). For example, the width W of the eye in the eye diagram can be used to indicate the timing synchronization of the measured signal or the jitter effect of the measured signal. For example, the eye diagram can indicate an eye opening OP, which represents the peak-to-peak voltage difference between various voltage levels VL11, VL12, VL13, and VL14. The eye opening OP can be related to the voltage margin used to distinguish between different voltage levels VL11, VL12, VL13, and VL14 of the measured signal.

[0070] Reference Figure 4B, showing different first voltage levels VL11, second voltage levels VL12, third voltage levels VL13, and fourth voltage levels VL14 of the data signal as the PAM4 signal, and showing different first reference levels VLREF_H, second reference levels VLREF_M, and third reference levels VLREF_L for sensing or detecting the levels of the data signal. For example, the number of reference levels may be one less than the number of voltage levels of the data signal.

[0071] The fourth voltage level VL14, which is the highest voltage level among the voltage levels VL11, VL12, VL13, and VL14, may be higher than the third voltage level VL13, the third voltage level VL13 may be higher than the second voltage level VL12, and the second voltage level VL12 may be higher than the first voltage level VL11, which is the lowest voltage level among the voltage levels VL11, VL12, VL13, and VL14. In addition, the first reference level VLREF_H may be a voltage level between the third voltage level VL13 and the fourth voltage level VL14, the second reference level VLREF_M may be a voltage level between the second voltage level VL12 and the third voltage level VL13, and the third reference level VLREF_L may be a voltage level between the first voltage level VL11 and the second voltage level VL12. The voltage level (e.g., sign) of the data signal may be decided or determined based on the result of comparing the data signal with the reference levels VLREF_H, VLREF_M, and VLREF_L.

[0072] For example, when Figure 3B When the multi-level input signal ML_IN in is a PAM4 signal, the multiple reference voltages VREF_ML used by the multiple samplers 1210 may include a first reference voltage having a first reference level VLREF_H, a second reference voltage having a second reference level VLREF_M, and a third reference voltage having a third reference level VLREF_L.

[0073] Hereinafter, example embodiments will be described in detail based on the PAM4 scheme. However, example embodiments are not limited thereto, and example embodiments may be applied to or used in a PAM(K) scheme having K possible pulse amplitudes.

[0074] Figure 5 is a diagram showing a method according to an example embodiment Figure 1 A block diagram of an example of a memory device.

[0075] Reference Figure 5 , the memory device 1000a may include a data I / O pin 1010, an output driver 1100, a multi-stage receiver 1200a, and a calibrator 1300a.

[0076] The data I / O pins 1010 and output drivers 1100 can be connected to the reference Figure 1 The data I / O pins 1010 and output drivers 1100 described above are substantially the same and the descriptions thereof will be omitted. Figure 1 Duplicate description.

[0077] The multi-stage receiver 1200 a may include a first sampler 1220 , a second sampler 1230 , and a third sampler 1240 .

[0078] The first sampler 1220 may generate a first decision signal D0 by sampling an internal input signal IS_CAL based on a reference voltage VREF_CAL and a phase-adjusted second clock signal S_CLK_D0'. The second sampler 1230 may generate a second decision signal D1 by sampling an internal input signal IS_CAL based on a reference voltage VREF_CAL and a phase-adjusted second clock signal S_CLK_D1'. The third sampler 1240 may generate a third decision signal D2 by sampling an internal input signal IS_CAL based on a reference voltage VREF_CAL and a phase-adjusted second clock signal S_CLK_D2'. As described above, in the calibration mode, all of the first sampler 1220, the second sampler 1230, and the third sampler 1240 may operate using the same reference voltage (e.g., reference voltage VREF_CAL).

[0079] The calibrator 1300 a may include a first delay control unit ( DCC1 ) 1320 , a second delay control unit ( DCC2 ) 1330 , a third delay control unit ( DCC3 ) 1340 , and a control circuit 1350 .

[0080] The first delay control unit 1320 may generate a phase-adjusted second clock signal S_CLK_D0' provided to the first sampler 1220 by adjusting the phase of the second clock signal S_CLK based on the first delay control signal DCON1. ​​The second delay control unit 1330 may generate a phase-adjusted second clock signal S_CLK_D1' provided to the second sampler 1230 by adjusting the phase of the second clock signal S_CLK based on the second delay control signal DCON2. The third delay control unit 1340 may generate a phase-adjusted second clock signal S_CLK_D2' provided to the third sampler 1240 by adjusting the phase of the second clock signal S_CLK based on the third delay control signal DCON3. The control circuit 1350 may generate a first delay control signal DCON1, a second delay control signal DCON2, and a third delay control signal DCON3 based on the first decision signal D0, the second decision signal D1, and the third decision signal D2. For example, each of the first delay control signal DCON1, the second delay control signal DCON2, and the third delay control signal DCON3 may have an initial value before performing a calibration operation.

[0081] The calibrator 1300a can detect and compensate for the timing deviation associated with the first sampler 1220, the second sampler 1230, and the third sampler 1240, and can correspond to Figure 2A For example, the control circuit 1350 may correspond to Figure 2A The timing deviation detection circuit 1304 in the embodiment of the present invention, and the first delay control unit 1320, the second delay control unit 1330 and the third delay control unit 1340 may correspond to Figure 2A Multiple delay control units 1306 in.

[0082] Although not shown in detail, Figure 3B In the normal operation mode, the first sampler 1220 can use Figure 4B The second sampler 1230 may use a first reference voltage having a first reference level VLREF_H in the multi-level input signal ML_IN to sample the multi-level input signal ML_IN. Figure 4B The third sampler 1240 may use a second reference voltage having a second reference level VLREF_M in the multi-level input signal ML_IN to sample the multi-level input signal ML_IN. Figure 4BThe multi-level input signal ML_IN is sampled by the third reference voltage of the third reference level VLREF_L in the sampling operation, and the voltage level of the multi-level input signal ML_IN can be determined, and the multi-level data corresponding to the multi-level input signal ML_IN can be generated based on the decision signals D0, D1 and D2 generated by the result of the sampling operation. For example, when the voltage level of the multi-level input signal ML_IN is higher than all of the first reference level VLREF_H, the second reference level VLREF_M and the third reference level VLREF_L, it can be determined that the multi-level input signal ML_IN has a voltage level VL14, and the multi-level data "11" corresponding to the voltage level VL14 can be generated.

[0083] Figure 6 , Fig. 7A , Figure 7B , Figure 7C , Fig.7D , Figure 8 , Fig. 9A and Fig. 9B is used to describe the Figure 5 A diagram of the operation of a memory device.

[0084] Reference Figure 6 , showing example waveforms of the first clock signal OSC_CLK, the internal input signal IS_CAL, and the second clock signal S_CLK.

[0085] The internal input signal IS_CAL may be generated by driving (eg, triggering) the output driver 1100 based on the first clock signal OSC_CLK. Therefore, the period T1 (or frequency) of the first clock signal OSC_CLK and the period (or frequency) of the internal input signal IS_CAL may be substantially equal to each other.

[0086] The internal input signal IS_CAL may be sampled based on the second clock signal S_CLK. In other words, the second clock signal S_CLK may be used as a sampling clock for the internal input signal IS_CAL. Therefore, the frequency of the second clock signal S_CLK may be higher than the frequency of the internal input signal IS_CAL (e.g., the frequency of the first clock signal OSC_CLK), and the period T2 of the second clock signal S_CLK may be shorter than the period of the internal input signal IS_CAL (e.g., the period T1 of the first clock signal OSC_CLK). For example, if the frequency of the internal input signal IS_CAL (e.g., the frequency of the first clock signal OSC_CLK) is defined by f, where f is a positive real number, and the frequency of the second clock signal S_CLK may be higher than 2f.

[0087] Reference Fig. 7A, illustrating an example operation of sampling the internal input signal IS_CAL using the reference voltage VREF_CAL and the second clock signal S_CLK.

[0088] The internal input signal IS_CAL may swing between the level of the power supply voltage VDD and the level of the ground voltage VSS, and the reference voltage VREF_CAL may have a reference level VLREF_CAL. For example, the level of the power supply voltage VDD and the level of the ground voltage VSS may correspond to Figure 4A and Figure 4B The voltage level VL14 and the voltage level VL11 in the reference level VLREF_CAL may correspond to Figure 4B For example, the reference level VLREF_CAL may be approximately VDD / 2.

[0089] At each of the sampling time points ts11, ts12, ts13, ts14, ts15, ts16, ts17, and ts18, the first sampler 1220, the second sampler 1230, and the third sampler 1240 may generate a first decision signal D0, a second decision signal D1, and a third decision signal D2, respectively, by comparing the level of the internal input signal IS_CAL with the reference level VLREF_CAL. For example, at the sampling time points ts11, ts12, ts13, and ts14, the level of the internal input signal IS_CAL may be higher than the reference level VLREF_CAL, and therefore, the first sampler 1220 may generate a first decision signal D0 having a value of "1". For example, at the sampling time points ts15, ts16, ts17, and ts18, the level of the internal input signal IS_CAL may be lower than the reference level VLREF_CAL, and thus, the first sampler 1220 may generate the first decision signal D0 having a value of '0'.

[0090] In some example embodiments, the above-described sampling operation may be performed based on a rising edge or a falling edge of the second clock signal S_CLK, and thus, the sampling time points ts11, ts12, ts13, ts14, ts15, ts16, ts17, and ts18 may correspond to a rising edge or a falling edge of the second clock signal S_CLK. In some example embodiments, the above-described sampling operation may be performed based on both a rising edge and a falling edge of the second clock signal S_CLK, and thus, the sampling time points ts11, ts12, ts13, ts14, ts15, ts16, ts17, and ts18 may correspond to both a rising edge and a falling edge of the second clock signal S_CLK.

[0091] Reference Figure 7B , shown in Fig. 7AAn example of timing deviation occurs in the example of .

[0092] As reference Fig. 7A As described above, in a normal case where a timing deviation does not occur, at the sampling time point ts15, the level of the internal input signal IS_CAL may be lower than the reference level VLREF_CAL, and thus the first sampler 1220 may generate the first decision signal D0 having a value of "0". Figure 7B When a timing deviation occurs as shown in (for example, before calibration is performed, when the phase of the phase-adjusted second clock signal S_CLK_D0' provided to the first sampler 1220 is ahead), a sampling operation may be performed at a sampling time point ts15' prior to the sampling time point ts15. At the sampling time point ts15', the level of the internal input signal IS_CAL may be higher than the reference level VLREF_CAL, and thus, the first sampler 1220 may generate a first decision signal D0 having a value of "1". In this case, after calibration is performed, the calibrator 1300 or 1300a may generate a phase-adjusted second clock signal S_CLK_D0', and a sampling operation may be performed at the sampling time point ts15, so that the first sampler 1220 may generate a first decision signal D0 having a value of "0".

[0093] Reference Figure 7C , showing an example operation of sampling the internal input signal IS_CAL using the reference voltage VREF_CAL and the second clock signal S_CLK. Fig. 7A Duplicate description.

[0094] At each of the sampling time points ts21, ts22, ts23, ts24, ts25, ts26, ts27, and ts28, the first sampler 1220, the second sampler 1230, and the third sampler 1240 may generate a first decision signal D0, a second decision signal D1, and a third decision signal D2, respectively, by comparing the level of the internal input signal IS_CAL with the reference level VLREF_CAL. For example, at the sampling time points ts21, ts22, ts23, ts24, and ts25, the level of the internal input signal IS_CAL may be higher than the reference level VLREF_CAL, and therefore, the first sampler 1220 may generate a first decision signal D0 having a value of "1". For example, at the sampling time points ts26, ts27, and ts28, the level of the internal input signal IS_CAL may be lower than the reference level VLREF_CAL, and thus, the first sampler 1220 may generate the first decision signal D0 having a value of "0".

[0095] Reference Fig.7D , shown in Figure 7CAn example of timing deviation occurs in the example of .

[0096] As reference Figure 7C As described above, in a normal case where a timing deviation does not occur, at the sampling time point ts25, the level of the internal input signal IS_CAL may be higher than the reference level VLREF_CAL, and therefore, the first sampler 1220 may generate the first decision signal D0 having a value of "1". Fig.7D When a timing deviation occurs as shown in (for example, before calibration is performed, when the phase of the phase-adjusted second clock signal S_CLK_D0' provided to the first sampler 1220 lags behind), a sampling operation may be performed at a sampling time point ts25' after the sampling time point ts25. At the sampling time point ts25', the level of the internal input signal IS_CAL may be lower than the reference level VLREF_CAL, and thus, the first sampler 1220 may generate a first decision signal D0 having a value of "0". In this case, after calibration is performed, the calibrator 1300 or 1300a may generate a phase-adjusted second clock signal S_CLK_D0', and a sampling operation may be performed at the sampling time point ts25, so that the first sampler 1220 may generate a first decision signal D0 having a value of "1".

[0097] Therefore, it can be determined whether a timing deviation has occurred by performing a sampling operation using the first sampler 1220, the second sampler 1230, and the third sampler 1240 based on the same internal input signal IS_CAL and the same reference voltage VREF_CAL. For example, when the value of one of the first decision signal D0, the second decision signal D1, and the third decision signal D2 generated from the first sampler 1220, the second sampler 1230, and the third sampler 1240 is different from the values ​​of the remaining decision signals, it can be determined that a timing deviation has occurred. Figure 7B or Fig.7D The timing deviation shown in .

[0098] Reference Figure 8 , shows an example of values ​​(eg, logic levels) of the first decision signal D0, the second decision signal D1, and the third decision signal D2 generated as a result of the sampling operation in the calibration mode.

[0099] When only the third decision signal D2 has a value of "1" among the first decision signal D0, the second decision signal D1, and the third decision signal D2, and the first decision signal D0 and the second decision signal D1 have a value of "0", it can be determined that a signal has occurred on the third sampler 1240. Figure 7B1240) (e.g., the phase of the phase-adjusted second clock signal S_CLK_D2' provided to the third sampler 1240 leads). Therefore, the third delay control signal DCON3 and the third delay control unit 1340 may be used to adjust (e.g., delay) the phase of the phase-adjusted second clock signal S_CLK_D2' provided to the third sampler 1240. As a result, the phase of the phase-adjusted second clock signal S_CLK_D2' provided to the third sampler 1240 may match (or coincide with) the phase-adjusted second clock signals S_CLK_D0' and S_CLK_D1' provided to the first sampler 1220 and the second sampler 1230, and the timing deviation may be compensated or calibrated.

[0100] Similarly, when only the second decision signal D1 has a value of "1" and the first decision signal D0 and the third decision signal D2 have a value of "0", it can be determined that a signal has occurred on the second sampler 1230. Figure 7B 1220) and thus, the second delay control signal DCON2 and the second delay control unit 1330 may be used to adjust the phase of the phase-adjusted second clock signal S_CLK_D1' provided to the second sampler 1230. When only the first decision signal D0 has a value of "1" and the second decision signal D1 and the third decision signal D2 have a value of "0", it can be determined that a signal has occurred on the first sampler 1220. Figure 7B (eg, the phase-adjusted second clock signal S_CLK_D0′ provided to the first sampler 1220 is ahead), and therefore, the first delay control signal DCON1 and the first delay control unit 1320 may be used to adjust the phase-adjusted second clock signal S_CLK_D0′ provided to the first sampler 1220.

[0101] When only the first decision signal D0 has a value of "0" among the first decision signal D0, the second decision signal D1, and the third decision signal D2, and the second decision signal D1 and the third decision signal D2 have a value of "1", it can be determined that a signal has occurred on the first sampler 1220. Fig.7D, for example, the phase-adjusted second clock signal S_CLK_D0' provided to the first sampler 1220 lags behind. Therefore, the first delay control signal DCON1 and the first delay control unit 1320 may be used to adjust (e.g., pull forward) the phase-adjusted second clock signal S_CLK_D0' provided to the first sampler 1220. As a result, the phase-adjusted second clock signal S_CLK_D0 provided to the first sampler 1220 may match the phase-adjusted second clock signals S_CLK_D1' and S_CLK_D2' provided to the second sampler 1230 and the third sampler 1240, and the timing deviation may be compensated.

[0102] Similarly, when only the second decision signal D1 has a value of "0" and the first decision signal D0 and the third decision signal D2 have a value of "1", it can be determined that a signal has occurred on the second sampler 1230. Fig.7D 1240) and thus, the second delay control signal DCON2 and the second delay control unit 1330 may be used to adjust the phase of the phase-adjusted second clock signal S_CLK_D1' provided to the second sampler 1230. When only the third decision signal D2 has a value of "0" and the first decision signal D0 and the second decision signal D1 have a value of "1", it can be determined that a signal has occurred on the third sampler 1240. Fig.7D The timing deviation shown in (e.g., the phase of the phase-adjusted second clock signal S_CLK_D2' provided to the third sampler 1240 lags behind), and therefore, the phase of the phase-adjusted second clock signal S_CLK_D2' provided to the third sampler 1240 can be adjusted using the third delay control signal DCON3 and the third delay control unit 1340.

[0103] In other words, the clock deviation direction may be detected, determined, and compensated by driving the first sampler 1220 , the second sampler 1230 , and the third sampler 1240 .

[0104] When all of the first decision signal D0, the second decision signal D1, and the third decision signal D2 have a value of "1", or when all of the first decision signal D0, the second decision signal D1, and the third decision signal D2 have a value of "0", it can be determined that there is no timing deviation on the first sampler 1220, the second sampler 1230, and the third sampler 1240, for example, the phase-adjusted second clock signals S_CLK_D0', S_CLK_D1', and S_CLK_D2' provided to the first sampler 1220, the second sampler 1230, and the third sampler 1240 are matched or the same. In this case, the calibration operation may not be performed.

[0105] Although the example embodiment is described based on an example of adjusting the phase of the clock signal corresponding to the decision signal having a different value when the value of one of the first decision signal D0, the second decision signal D1, and the third decision signal D2 is different from the values ​​of the remaining decision signals, the example embodiment is not limited thereto. For example, one of the first decision signal D0, the second decision signal D1, and the third decision signal D2 may be set as a reference value, and the phase of the clock signal corresponding to the decision signal other than the reference value of one of the first decision signal D0, the second decision signal D1, and the third decision signal D2 may be adjusted. For example, when the first decision signal D0 is set as a reference value, and when the value of at least one of the second decision signal D1 and the third decision signal D2 is different from the value of the first decision signal D0, at least one of the phase-adjusted second clock signals S_CLK_D1' and S_CLK_D2' may be adjusted. For example, when the first decision signal D0 has a value of "0" and the second decision signal D1 and the third decision signal D2 have a value of "1", or when the first decision signal D0 has a value of "1" and the second decision signal D1 and the third decision signal D2 have a value of "0", the phase-adjusted second clock signals S_CLK_D1' and S_CLK_D2' can be adjusted instead of adjusting the phase of the phase-adjusted second clock signal S_CLK_D0', and thus the timing deviation can be compensated.

[0106] Reference Fig. 9A and Fig. 9B , shows an example of the output of the first sampler 1220, the second sampler 1230, and the third sampler 1240. For example, in Fig. 9A and Fig. 9B The eye diagram or effective window of the first decision signal D0, the second decision signal D1 and the third decision signal D2 is shown in FIG. Fig. 9A and Fig. 9B Among the plurality of rectangular blocks in FIG. 1 , the shaded rectangular blocks represent valid regions or pass regions where data is determined to be valid, and the empty rectangular blocks represent invalid regions or fail regions where data is determined to be invalid.

[0107] like Fig. 9A As shown in , before performing the calibration operation, the eye diagrams EYE_D0_BC, EYE_D1_BC and EYE_D2_BC of the first decision signal D0, the second decision signal D1 and the third decision signal D2 may not be aligned relative to the sampling time point t1, and there may be timing deviations, timing mismatches (or inconsistencies) and / or timing errors.

[0108] like Fig. 9BAs shown in , after performing the calibration operation, the eye diagrams EYE_D0_AC, EYE_D1_AC and EYE_D2_AC of the first decision signal D0, the second decision signal D1 and the third decision signal D2 can be aligned relative to the sampling time point t2, and the timing deviation can be removed or eliminated, and the DQ margin can be improved or enhanced.

[0109] Fig. 10A and Fig. 10B is a diagram showing a method according to an example embodiment Figure 1 A block diagram of an example of a memory device.

[0110] Reference Fig. 10A and Fig. 10B , the memory device 1000b includes a data I / O pin 1010, an output driver 1100, a multi-stage receiver 1200b, and a calibrator 1300b.

[0111] The data I / O pins 1010 and output drivers 1100 can be connected to the reference Figure 1 The data I / O pins 1010 and output drivers 1100 described above are substantially the same and the descriptions thereof will be omitted. Figure 1 Duplicate description.

[0112] The multi-stage receiver 1200 b may include a first sampler 1221 , a second sampler 1223 , a third sampler 1225 , and a fourth sampler 1227 .

[0113] The first sampler 1221, the second sampler 1223, the third sampler 1225, and the fourth sampler 1227 may operate based on the sampler clock signal S_CLK_D0. The sampler clock signal S_CLK_D0 may be generated from the second clock signal S_CLK and include a first sub-clock signal S_CLK0_D0, a second sub-clock signal S_CLK1_D0, a third sub-clock signal S_CLK2_D0, and a fourth sub-clock signal S_CLK3_D0 whose phases partially overlap. In some implementations, the phases of the first sub-clock signal S_CLK0_D0 to the fourth sub-clock signal S_CLK3_D0 may be the same as each other. The first sampler 1221, the second sampler 1223, the third sampler 1225, and the fourth sampler 1227 may correspond to Figure 5 The first sampler 1220 in.

[0114] The first sampler 1221 may generate a first decision signal D0_0 by sampling the internal input signal IS_CAL based on the reference voltage VREF_CAL and the first sub-clock signal S_CLK0_D0. The second sampler 1223 may generate a second decision signal D0_1 by sampling the internal input signal IS_CAL based on the reference voltage VREF_CAL and the second sub-clock signal S_CLK1_D0. The third sampler 1225 may generate a third decision signal D0_2 by sampling the internal input signal IS_CAL based on the reference voltage VREF_CAL and the third sub-clock signal S_CLK2_D0. The fourth sampler 1227 may generate a fourth decision signal D0_3 by sampling the internal input signal IS_CAL based on the reference voltage VREF_CAL and the fourth sub-clock signal S_CLK3_D0.

[0115] The calibrator 1300 b may include a first offset control unit ( OCC1 - 1 ) 1321 , a second offset control unit ( OCC1 - 2 ) 1323 , a third offset control unit ( OCC1 - 3 ) 1325 , a fourth offset control unit ( OCC1 - 4 ) 1327 , and a first control circuit 1351 .

[0116] The first offset control unit 1321 may be included in the first sampler 1221, and may adjust the output level of the first sampler 1221 based on the first offset control signal OCON1_1. The second offset control unit 1323 may be included in the second sampler 1223, and may adjust the output level of the second sampler 1223 based on the second offset control signal OCON1_2. The third offset control unit 1325 may be included in the third sampler 1225, and may adjust the output level of the third sampler 1225 based on the third offset control signal OCON1_3. The fourth offset control unit 1327 may be included in the fourth sampler 1227, and may adjust the output level of the fourth sampler 1227 based on the fourth offset control signal OCON1_4. The first control circuit 1351 may generate first, second, third, and fourth offset control signals OCON1_1, OCON1_2, OCON1_3, and OCON1_4 based on the first, second, third, and fourth decision signals D0_0, D0_1, D0_2, and D0_3.

[0117] The multi-stage receiver 1200b may further include a fifth sampler 1231, a sixth sampler 1233, a seventh sampler 1235, an eighth sampler 1237, a ninth sampler 1241, a tenth sampler 1243, an eleventh sampler 1245, and a twelfth sampler 1247. The calibrator 1300b may further include a fifth offset control unit 1331, a ninth offset control unit 1341, a second control circuit 1353, and a third control circuit 1355. Although not shown in detail, the calibrator 1300b may further include a sixth offset control unit, a seventh offset control unit, an eighth offset control unit, a ninth offset control unit, a tenth offset control unit, an eleventh offset control unit, and a twelfth offset control unit.

[0118] The fifth sampler 1231, the sixth sampler 1233, the seventh sampler 1235, and the eighth sampler 1237 may operate based on the sampler clock signal S_CLK_D1 and may correspond to Figure 5 The second sampler 1230 in the sampler clock signal S_CLK_D0. Like the sampler clock signal S_CLK_D0, the sampler clock signal S_CLK_D1 may include a fifth sub-clock signal, a sixth sub-clock signal, a seventh sub-clock signal, and an eighth sub-clock signal whose phases partially overlap. The fifth sampler 1231, the sixth sampler 1233, the seventh sampler 1235, and the eighth sampler 1237 may generate a fifth decision signal D1_0, a sixth decision signal D1_1, a seventh decision signal D1_2, and an eighth decision signal D1_3 by sampling the internal input signal IS_CAL based on the reference voltage VREF_CAL and the fifth sub-clock signal, the sixth sub-clock signal, the seventh sub-clock signal, and the eighth sub-clock signal, respectively. The fifth offset control unit 1331 may be included in the fifth sampler 1231, and may adjust the output level of the fifth sampler 1231 based on the fifth offset control signal OCON2_1. The sixth offset control unit, the seventh offset control unit, and the eighth offset control unit may be included in the sixth sampler 1233, the seventh sampler 1235, and the eighth sampler 1237, respectively, and may adjust the output levels of the sixth sampler 1233, the seventh sampler 1235, and the eighth sampler 1237 based on the sixth offset control signal OCON2_2, the seventh offset control signal OCON2_3, and the eighth offset control signal OCON2_4, respectively. The second control circuit 1353 may generate the fifth offset control signal OCON2_1, the sixth offset control signal OCON2_2, the seventh offset control signal OCON2_3, and the eighth offset control signal OCON2_4 based on the fifth decision signal D1_0, the sixth decision signal D1_1, the seventh decision signal D1_2, and the eighth decision signal D1_3.

[0119] The ninth sampler 1241, the tenth sampler 1243, the eleventh sampler 1245, and the twelfth sampler 1247 may operate based on the sampler clock signal S_CLK_D2 and may correspond to Figure 5 The third sampler 1240 in the embodiment. Like the sampler clock signal S_CLK_D0, the sampler clock signal S_CLK_D2 may include a ninth sub-clock signal, a tenth sub-clock signal, an eleventh sub-clock signal, and a twelfth sub-clock signal whose phases partially overlap. The ninth sampler 1241, the tenth sampler 1243, the eleventh sampler 1245, and the twelfth sampler 1247 may generate a ninth decision signal D2_0, a tenth decision signal D2_1, an eleventh decision signal D2_2, and a twelfth decision signal D2_3, respectively, by sampling the internal input signal IS_CAL based on the reference voltage VREF_CAL and the ninth sub-clock signal, the tenth sub-clock signal, the eleventh sub-clock signal, and the twelfth sub-clock signal, respectively. The ninth offset control unit 1341 may be included in the ninth sampler 1241, and may adjust the output level of the ninth sampler 1241 based on the ninth offset control signal OCON3_1. The tenth offset control unit, the eleventh offset control unit, and the twelfth offset control unit may be included in the tenth sampler 1243, the eleventh sampler 1245, and the twelfth sampler 1247, respectively, and may adjust the output levels of the tenth sampler 1243, the eleventh sampler 1245, and the twelfth sampler 1247 based on the tenth offset control signal OCON3_2, the eleventh offset control signal OCON3_3, and the twelfth offset control signal OCON3_4, respectively. The third control circuit 1355 may generate the ninth offset control signal OCON3_1, the tenth offset control signal OCON3_2, the eleventh offset control signal OCON3_3, and the twelfth offset control signal OCON3_4 based on the ninth decision signal D2_0, the tenth decision signal D2_1, the eleventh decision signal D2_2, and the twelfth decision signal D2_3.

[0120] The calibrator 1300b can detect and compensate for the offsets associated with the first sampler 1221, the second sampler 1223, the third sampler 1225, and the fourth sampler 1227, can detect and compensate for the offsets associated with the fifth sampler 1231, the sixth sampler 1233, the seventh sampler 1235, and the eighth sampler 1237, can detect and compensate for the offsets associated with the ninth sampler 1241, the tenth sampler 1243, the eleventh sampler 1245, and the twelfth sampler 1247, and can correspond to Figure 2B For example, control circuits 1351, 1353, and 1355 may correspond to Figure 2BThe offset detection circuit 1314 in the embodiment, and the offset control units 1321, 1323, 1325, 1327, 1331 and 1341 may correspond to Figure 2B Multiple offset control units 1316 in.

[0121] Although not shown in detail, Figure 3B In the normal operation mode, the first sampler 1221, the second sampler 1223, the third sampler 1225 and the fourth sampler 1227 can use Figure 4B The first reference voltage with the first reference level VLREF_H in the multi-level input signal ML_IN is sampled, and the fifth sampler 1231, the sixth sampler 1233, the seventh sampler 1235 and the eighth sampler 1237 can use Figure 4B The ninth sampler 1241, the tenth sampler 1243, the eleventh sampler 1245 and the twelfth sampler 1247 can use the second reference voltage with the second reference level VLREF_M in the multi-level input signal ML_IN to sample. Figure 4B The multi-level input signal ML_IN is sampled by a third reference voltage having a third reference level VLREF_L in the multi-level input signal ML_IN, and the voltage level of the multi-level input signal ML_IN can be determined, and multi-level data corresponding thereto can be generated based on decision signals D0_0, D0_1, D0_2, D0_3, D1_0, D1_1, D1_2, D1_3, D2_0, D2_1, D2_2 and D2_3 generated as a result of the sampling operation.

[0122] Fig.11 , Fig.12 , Fig.13A and Fig. 13B is used to describe the Fig. 10A and Fig. 10B A diagram of the operation of a memory device.

[0123] Reference Fig.11 , example waveforms of four sub-clock signals S_CLK0 , S_CLK1 , S_CLK2 , and S_CLK3 included in each of the sampler clock signals S_CLK_D0 , S_CLK_D1 , and S_CLK_D2 are shown.

[0124] The first sub-clock signal S_CLK0 can be Figure 6The second clock signal S_CLK in the sampler clock signal is substantially the same. Among the first to fourth sub-clock signals S_CLK0, S_CLK1, S_CLK2 and S_CLK3, two adjacent sub-clock signals of high level (for example, the first sub-clock signal S_CLK0 and the second sub-clock signal S_CLK1) may partially overlap. For example, the second to fourth sub-clock signals S_CLK1, S_CLK2 and S_CLK3 may have a phase difference of about 90 degrees, about 180 degrees and about 270 degrees with the first sub-clock signal S_CLK0, respectively. For example, each of the sampler clock signals S_CLK_D0, S_CLK_D1 and S_CLK_D2 may be referred to as a 4-phase clock signal.

[0125] Reference Fig. 7A and Fig.12 , shows an example of values ​​(eg, logic levels) of a first decision signal D0_0 , a second decision signal D0_1 , a third decision signal D0_2 , and a fourth decision signal D0_3 generated as a result of a sampling operation in a calibration mode.

[0126] Whether an offset has occurred can be determined by performing a sampling operation based on the same internal input signal IS_CAL and the same reference voltage VREF_CAL using the first sampler 1221, the second sampler 1223, the third sampler 1225, and the fourth sampler 1227. For example, when the value of one of the first decision signal D0_0, the second decision signal D0_1, the third decision signal D0_2, and the fourth decision signal D0_3 generated from the first sampler 1221, the second sampler 1223, the third sampler 1225, and the fourth sampler 1227 is different from the values ​​of the remaining decision signals, it can be determined that an offset has occurred.

[0127] For example, in a normal case where no offset occurs, at sampling time points ts11, ts12, ts13 and ts14, the level of the internal input signal IS_CAL can be higher than the reference level VLREF_CAL, and therefore, the first sampler 1221, the second sampler 1223, the third sampler 1225 and the fourth sampler 1227 can generate a first decision signal D0_0, a second decision signal D0_1, a third decision signal D0_2 and a fourth decision signal D0_3 having a value of "1". Similarly, at sampling time points ts15, ts16, ts17 and ts18, the level of the internal input signal IS_CAL can be lower than the reference level VLREF_CAL, and therefore, the first sampler 1221, the second sampler 1223, the third sampler 1225 and the fourth sampler 1227 can generate a first decision signal D0_0, a second decision signal D0_1, a third decision signal D0_2 and a fourth decision signal D0_3 with a value of "0".

[0128] On the other hand, when only the third decision signal D0_2 has a value of "0" and the first decision signal D0_0, the second decision signal D0_1 and the fourth decision signal D0_3 have a value of "1" at the sampling time point ts14, it can be determined that an offset associated with the third sampler 1225 occurs, and therefore, the output level of the third sampler 1225 can be adjusted using the third offset control signal OCON1_3 and the third offset control unit 1325.

[0129] In other words, the offset direction can be detected, determined and compensated by driving the first sampler 1221, the second sampler 1223, the third sampler 1225 and the fourth sampler 1227 and by comparing the output averages of the first sampler 1221, the second sampler 1223, the third sampler 1225 and the fourth sampler 1227.

[0130] Although the example embodiment is described based on an example of adjusting the output level of the sampler corresponding to the decision signal having a different value when the value of one of the first decision signal D0_0, the second decision signal D0_1, the third decision signal D0_2, and the fourth decision signal D0_3 is different from the value of the remaining decision signals, the example embodiment is not limited thereto. For example, one of the first decision signal D0_0, the second decision signal D0_1, the third decision signal D0_2, and the fourth decision signal D0_3 may be set as a reference value, and the output level of the sampler corresponding to the decision signal other than the reference value may be adjusted. For example, when the third decision signal D0_2 is set as a reference value, and when the value of at least one of the first decision signal D0_0, the second decision signal D0_1, and the fourth decision signal D0_3 is different from the value of the third decision signal D0_2, at least one of the output levels of the first sampler 1221, the second sampler 1223, and the fourth sampler 1227 may be adjusted. For example, when the third decision signal D0_2 has a value of "1" and the first decision signal D0_0, the second decision signal D0_1 and the fourth decision signal D0_3 have a value of "1", the output levels of the first sampler 1221, the second sampler 1223 and the fourth sampler 1227 can be adjusted without adjusting the output level of the third sampler 1225, and therefore, the offset can be compensated.

[0131] Although not shown in detail, the above-mentioned offset detection and calibration operations may also be performed on the fifth sampler 1231, the sixth sampler 1233, the seventh sampler 1235 and the eighth sampler 1237, and the above-mentioned offset detection and calibration operations may also be performed on the ninth sampler 1241, the tenth sampler 1243, the eleventh sampler 1245 and the twelfth sampler 1247.

[0132] Reference Fig.13Aand Fig. 13B , shows an example of the output of the first sampler 1221, the second sampler 1223, the third sampler 1225, and the fourth sampler 1227. For example, in Fig.13A and Fig. 13B Graphs 1 and 2 show eye diagrams or valid windows of the first decision signal D0_0 , the second decision signal D0_1 , the third decision signal D0_2 , and the fourth decision signal D0_3 .

[0133] like Fig.13A As shown in , before the calibration operation is performed, the eye diagrams EYE_D0_0_BC, EYE_D0_1_BC, and EYE_D0_3_BC of the first decision signal D0_0, the second decision signal D0_1, and the fourth decision signal D0_3 may be different from the eye diagram EYE_D0_2_BC of the second decision signal D0_2. For example, the output average levels VLA of the first decision signal D0_0, the second decision signal D0_1, and the fourth decision signal D0_3 and the output average level VLB of the third decision signal D0_2 may be different from each other, and there may be an offset mismatch (or inconsistency) and / or an offset error.

[0134] like Fig. 13B As shown in, after performing the calibration operation, the eye diagrams EYE_D0_0_AC, EYE_D0_1_AC, EYE_D0_2_AC, and EYE_D0_3_AC of the first decision signal D0_0, the second decision signal D0_1, the third decision signal D0_2, and the fourth decision signal D0_3 may be substantially the same as each other. For example, the output average levels VLA of the first decision signal D0_0, the second decision signal D0_1, the third decision signal D0_2, and the fourth decision signal D0_3 may be substantially the same as each other, and the offset and DQ margin may be improved or enhanced.

[0135] In some example embodiments, the calibrator 1300b included in the memory device 1000b may additionally perform a reference Figure 5 , Figure 6 , 7A to 7D , Figure 8 , Fig. 9A and Fig. 9B In other words, when a timing deviation has occurred between the first group of samplers 1221, 1223, 1225 and 1227, the second group of samplers 1231, 1233, 1235 and 1237, and the third group of samplers 1241, 1243, 1245 and 1247, the calibrator 1300b can also compensate for the timing deviation.

[0136] Fig.14 is used to describe the Figure 5 , Fig. 10A and Fig. 10B A diagram of the operation of a memory device.

[0137] Reference Fig.14 , showing an example operation of sampling the internal input signal IS_CAL using the reference voltage VREF_CAL and the second clock signal S_CLK. Fig. 7A , Figure 7B , Figure 7C and Fig.7D Unlike the example of , the internal input signal IS_CAL may be sampled using the internal input signal IS_CAL having a fixed level and the reference voltage VREF_CAL having a variable level, and then, a calibration operation may be performed based on a result of the sampling operation.

[0138] Fig.15 is a block diagram illustrating a memory device according to an example embodiment. Figure 1 Duplicate description.

[0139] Reference Fig.15 , the memory device 2000 includes a data I / O pin 2010 , an output driver 2100 , a receiver 2200 , and a calibrator 2300 .

[0140] In some example embodiments, the memory device 2000 may operate based on a non-return-to-zero (NRZ) scheme. For example, in a normal operation mode, the output driver 2100 may generate an NRZ signal based on single-bit data, and the receiver 2200 may generate a plurality of decision signals for generating single-bit data based on the NRZ signal. For example, the NRZ signal may have one of two voltage levels different from each other during one unit interval, and the single-bit data may include one bit. Fig.17A and Fig. 17B A detailed operation of the memory device 2000 in the normal operation mode is described.

[0141] In some example embodiments, the memory device 2000 may operate in a calibration mode different from a normal operation mode. For example, the memory device 2000 may include a calibrator 2300 for performing operations in the calibration mode. For example, in the calibration mode, the calibrator 2300 may detect and compensate for an offset associated with the receiver 2200. Fig.15 Detailed operation of the memory device 2000 in the calibration mode is shown.

[0142] The output driver 2100 is connected to the data I / O pin 2010 and generates an internal input signal IS_CAL based on the first clock signal OSC_CLK.

[0143] The receiver 2200 is connected to the data I / O pin 2010 and includes a plurality of samplers 2210. The plurality of samplers 2210 generates a plurality of decision signals DCS_CAL by sampling the internal input signal IS_CAL based on the reference voltage VREF and the second clock signal S_CLK. Fig.11 As described, the second clock signal S_CLK may include a plurality of sub-clock signals whose phases partially overlap.

[0144] In some example embodiments, when a calibration operation is performed in a calibration mode, both the output driver 2100 and the receiver 2200 may be enabled and operated.

[0145] The calibrator 2300 detects and compensates for offsets associated with the plurality of samplers 2210 based on the plurality of decision signals DCS_CAL.

[0146] In some example embodiments, in the calibration mode, offsets associated with the plurality of samplers 2210 may be detected and compensated using only the internal input signal IS_CAL without an external input signal received from the outside (e.g., from an external device) through the data I / O pin 2010. For example, in the calibration mode, the data I / O pin 2010 may have a high impedance state to prevent reception of an external input signal.

[0147] Fig.16 is a block diagram showing an example of a calibrator included in a memory device according to an example embodiment. Figure 2B Duplicate description.

[0148] Reference Fig.16 , the calibrator 2312 may include an offset detection circuit 2314 and a plurality of offset control units 2316. The offset detection circuit 2314 and the plurality of offset control units 2316 may be respectively connected to Figure 2B The offset detection circuit 1314 and the plurality of offset control units 1316 in the embodiment are substantially the same.

[0149] Fig.17A and Fig. 17B is a block diagram illustrating a memory device according to an example embodiment. Figure 3A , Figure 3B and Fig.15 Duplicate description.

[0150] Reference Fig.17A and Fig. 17B , illustrating the operation of the memory device 2000 in a normal operation mode.

[0151] like Fig.17AAs shown in FIG. 2 , in the normal operation mode after the calibration mode, the memory device 2000 may perform a data output operation. For example, the output driver 2100 may generate an NRZ output signal NRZ_OUT based on the single-bit data SBDAT, and may output the NRZ output signal NRZ_OUT through the data I / O pin 2010 .

[0152] like Fig. 17B As shown in , in the normal operation mode after the calibration mode, the memory device 2000 can perform a data receiving operation. For example, the NRZ input signal NRZ_IN can be received through the data I / O pin 2010, and the plurality of samplers 2210 included in the receiver 2200 can generate a plurality of decision signals DCS_NRZ by sampling the NRZ input signal NRZ_IN based on the reference voltage VREF and the second clock signal S_CLK. The plurality of samplers 2210 can operate using the same reference voltage (e.g., reference voltage VREF) in the calibration mode and the normal operation mode.

[0153] In some example embodiments, when a data output operation or a data receiving operation is performed in a normal operation mode, one of the output driver 2100 and the multi-stage receiver 2200 may be enabled and operated. In some example embodiments, when a data output operation or a data receiving operation is performed in a normal operation mode, the calibrator 2300 may be disabled.

[0154] Fig.18 is a diagram for describing an NRZ signal input to or output from a memory device according to example embodiments.

[0155] Reference Fig.18 , shows an ideal eye diagram of a data signal (eg, an NRZ signal) generated based on an NRZ scheme as an example of a 2-level signaling scheme. For example, Fig.18 The NRZ signal can be Fig.17A The NRZ output signal NRZ_OUT in Fig. 17B Example of an NRZ input signal NRZ_IN in FIG.

[0156] Eye diagrams can be used to indicate signal quality in high-speed transmissions. For example, Fig.18 The eye diagram in FIG. 1 may represent two symbols (e.g., "0" and "1") of a signal, and each of the two symbols may be represented by a corresponding one of different voltage levels (e.g., voltage amplitudes) VL21 and VL22. The reference level VLREF may be a voltage level between the voltage levels VL21 and VL22. The voltage level (e.g., symbol) of the data signal may be decided or determined based on a result of comparing the data signal with the reference level VLREF.

[0157] In some example embodiments, the voltage levels VL21 and VL22 and the reference level VLREF may be respectively Figure 4A and Figure 4B The voltage levels VL11 and VL14 in FIG. 1 and the second reference level VLREF_M are substantially the same. However, example embodiments are not limited thereto.

[0158] Fig.19 is a diagram showing a method according to an example embodiment Fig.15 The following are block diagrams of examples of memory devices. Fig. 10A and Fig. 10B Duplicate description.

[0159] Reference Fig.19 , the memory device 2000a includes a data I / O pin 2010, an output driver 2100, a receiver 2200a, and a calibrator 2300a.

[0160] The data I / O pins 2010 and output drivers 2100 can be connected to the reference Fig.15 The data I / O pins 2010 and output drivers 2100 described above are substantially the same and the descriptions thereof will be omitted. Fig.15 Duplicate description.

[0161] The receiver 2200a may include a first sampler 2221, a second sampler 2223, a third sampler 2225, and a fourth sampler 2227. The first sampler 2221, the second sampler 2223, the third sampler 2225, and the fourth sampler 2227 may generate a first decision signal D_0, a second decision signal D_1, a third decision signal D_2, and a fourth decision signal D_3 by sampling an internal input signal IS_CAL based on a reference voltage VREF and sub-clock signals S_CLK0, S_CLK1, S_CLK2, and S_CLK3 whose phases partially overlap.

[0162] The calibrator 2300a may include a first offset control unit 2321 and a control circuit 2351. Although not shown in detail, the calibrator 2300a may further include a second offset control unit, a third offset control unit, and a fourth offset control unit. The first offset control unit 2321 may be included in the first sampler 2221, and may adjust the output level of the first sampler 2221 based on the first offset control signal OCON_1. The second offset control unit, the third offset control unit, and the fourth offset control unit may be included in the second sampler 2223, the third sampler 2225, and the fourth sampler 2227, respectively, and may adjust the output levels of the second sampler 2223, the third sampler 2225, and the fourth sampler 2227 based on the second offset control signal OCON_2, the third offset control signal OCON_3, and the fourth offset control signal OCON_4, respectively. The control circuit 2351 may generate a first offset control signal OCON_1 , a second offset control signal OCON_2 , a third offset control signal OCON_3 , and a fourth offset control signal OCON_4 based on the first decision signal D_0 , the second decision signal D_1 , the third decision signal D_2 , and the fourth decision signal D_3 .

[0163] Samplers 2221, 2223, 2225, and 2227, offset control unit 2321, control circuit 2351, sub-clock signals S_CLK0, S_CLK1, S_CLK2, and S_CLK3, decision signals D_0, D_1, D_2, and D_3, and offset control signals OCON_1, OCON_2, OCON_3, and OCON_4 may correspond to Fig. 10A and Fig. 10B The samplers 1221, 1223, 1225 and 1227, the offset control unit 1321, the control circuit 1351, the sub-clock signals S_CLK0_D0, S_CLK1_D0, S_CLK2_D0 and S_CLK3_D0, the decision signals D0_0, D0_1, D0_2 and D0_3, and the offset control signals OCON1_1, OCON1_2, OCON1_3 and OCON1_4. The receiver 2200a and the calibrator 2300a can perform the same operation as the reference. Fig.11 , Fig.12 , Fig.13A and Fig. 13B The offset calibration operation described is similar to the offset calibration operation.

[0164] Fig. 20 is a block diagram illustrating a memory system according to example embodiments.

[0165] Reference Fig. 20, the memory system 10 includes a memory controller 20 and a memory device 40. The memory system 10 may further include a plurality of signal lines 30 electrically connecting the memory controller 20 to the memory device 40.

[0166] The memory device 40 is controlled by the memory controller 20. For example, based on a request from a host (not shown), the memory controller 20 may store (e.g., write or program) data into the memory device 40 or may retrieve (e.g., read or sense) data from the memory device 40.

[0167] The plurality of signal lines 30 may include a control line, a command line, an address line, a data input / output (I / O) line, and a power line. The memory controller 20 may transmit a command CMD, an address ADDR, and a control signal CTRL to the memory device 40 via the command line, the address line, and the control line, may exchange a data signal DS with the memory device 40 via the data I / O line, and may transmit a power supply voltage PWR to the memory device 40 via the power line. For example, the data signal DS may be a multi-level signal or an NRZ signal transmitted and / or received according to an example embodiment. Although Fig. 20 Although not shown in the figure, the plurality of signal lines 30 may further include a DQS line for transmitting a data strobe signal (DQS) signal.

[0168] Fig.21A and Fig. 21B is a diagram showing a method according to an example embodiment Fig. 20 A block diagram of an example of a memory system.

[0169] Reference Fig.21A and Fig. 21B The memory system 11 includes a memory controller 21, a memory device 41, and a plurality of channels 31a, 31b, and 31c. For example, the number of channels 31a, 31b, and 31c may be N, where N is a positive integer greater than or equal to two.

[0170] Memory controller 21 may include multiple transmitters 25a, 25b and 25c, multiple receivers 27a, 27b and 27c, and multiple data I / O pads 29a, 29b and 29c. Memory device 41 may include multiple transmitters 45a, 45b and 45c, multiple receivers 47a, 47b and 47c, and multiple data I / O pads 49a, 49b and 49c.

[0171] Each of the plurality of transmitters 25a, 25b, 25c, 45a, 45b, and 45c may generate a multi-level signal or an NRZ signal. In an exemplary embodiment, each of the plurality of transmitters 25a, 25b, 25c, 45a, 45b, and 45c may adopt Figure 1 , Figure 5 , Fig. 10A , Fig.15 and Fig.19 Each of the plurality of receivers 27a, 27b, 27c, 47a, 47b, and 47c may receive a multilevel signal or an NRZ signal. In an exemplary embodiment, each of the plurality of receivers 27a, 27b, 27c, 47a, 47b, and 47c may adopt Figure 1 , Figure 5 , Fig. 10A , Fig.15 and Fig.19 The memory controller 21 and / or the memory device 41 may include the above-mentioned method for compensating for at least one of the timing deviation and offset according to the example embodiment. Figure 1 , Figure 2A , Figure 2B , Figure 5 , Fig. 10A , Fig.15 , Fig.16 and Fig.19 One of the calibrators described in .

[0172] Each of the multiple data I / O pads 29a, 29b, 29c, 49a, 49b and 49c can be connected to a corresponding one of the multiple transmitters 25a, 25b, 25c, 45a, 45b and 45c and a corresponding one of the multiple receivers 27a, 27b, 27c, 47a, 47b and 47c.

[0173] A plurality of channels 31a, 31b, and 31c may connect the memory controller 21 with the memory device 41. Each of the plurality of channels 31a, 31b, and 31c may be connected to a corresponding one of the plurality of transmitters 25a, 25b, and 25c and a corresponding one of the plurality of receivers 27a, 27b, and 27c through a corresponding one of the plurality of data I / O pads 29a, 29b, and 29c. Similarly, each of the plurality of channels 31a, 31b, and 31c may be connected to a corresponding one of the plurality of transmitters 45a, 45b, and 45c and a corresponding one of the plurality of receivers 47a, 47b, and 47c through a corresponding one of the plurality of data I / O pads 49a, 49b, and 49c. A multilevel signal or an NRZ signal may be transmitted through each of the plurality of channels 31a, 31b, and 31c.

[0174] Fig.21A4 shows an operation of transmitting data from the memory controller 21 to the memory device 41. For example, the transmitter 25a may generate a data signal DS11 based on the input data DAT11, may transmit the data signal DS11 from the memory controller 21 to the memory device 41 through the channel 31a, and the receiver 47a may receive the data signal DS11 to obtain the output data ODAT11 corresponding to the input data DAT11. Similarly, the transmitter 25b may generate a data signal DS21 based on the input data DAT21, may transmit the data signal DS21 to the memory device 41 through the channel 31b, and the receiver 47b may receive the data signal DS21 to obtain the output data ODAT21 corresponding to the input data DAT21. The transmitter 25c may generate a data signal DSN1 based on the input data DATN1, may transmit the data signal DSN1 to the memory device 41 through the channel 31c, and the receiver 47c may receive the data signal DSN1 to obtain the output data ODATN1 corresponding to the input data DATN1. For example, the input data DAT11 , DAT21 , and DATN1 may be write data to be stored in the memory device 41 , and a write command and a write address for storing the write data may be provided to the memory device 41 together with the write data.

[0175] Fig. 21B 1 shows an operation of transmitting data from the memory device 41 to the memory controller 21. For example, the transmitter 45a can generate a data signal DS12 based on the input data DAT12, can transmit the data signal DS12 from the memory device 41 to the memory controller 21 through the channel 31a, and the receiver 27a can receive the data signal DS12 to obtain the output data ODAT12 corresponding to the input data DAT12. Similarly, the transmitter 45b can generate a data signal DS22 based on the input data DAT22, can transmit the data signal DS22 to the memory controller 21 through the channel 31b, and the receiver 27b can receive the data signal DS22 to obtain the output data ODAT22 corresponding to the input data DAT22. The transmitter 45c can generate a data signal DSN2 based on the input data DATN2, can transmit the data signal DSN2 to the memory controller 21 through the channel 31c, and the receiver 27c can receive the data signal DSN2 to obtain the output data ODATN2 corresponding to the input data DATN2. For example, the input data DAT12 , DAT22 , and DATN2 may be read data retrieved from the memory device 41 , and a read command and a read address for retrieving the read data may be provided to the memory device 41 .

[0176] Fig. 22 is a block diagram illustrating an example of a memory device included in a memory system according to example embodiments.

[0177] Reference Fig. 22 , the memory device 200 includes a control logic 210, a refresh control circuit 215, an address register 220, a bank control logic 230, a row address multiplexer (RA MUX) 240, a column address (CA) latch 250, a row decoder, a column decoder, a memory cell array, a sense amplifier unit, an input / output (I / O) gating circuit 290, a data I / O buffer 295, and a data I / O pad 299. In some example embodiments, the memory device 200 may be, for example, a volatile memory device. For example, the memory device 200 may be one of various volatile memory devices (such as a dynamic random access memory (DRAM)).

[0178] The memory cell array may include a plurality of memory cells. The memory cell array may include a plurality of memory cell arrays, for example, first to fourth memory cell arrays 280a, 280b, 280c, and 280d. The row decoder may include a plurality of memory cell row decoders, for example, first to fourth memory cell row decoders 260a, 260b, 260c, and 260d are connected to the first to fourth memory cell arrays 280a, 280b, 280c, and 280d, respectively. The column decoder may include a plurality of memory cell column decoders, for example, first to fourth memory cell column decoders 270a, 270b, 270c, and 270d are connected to the first to fourth memory cell arrays 280a, 280b, 280c, and 280d, respectively. The sense amplifier unit may include a plurality of bank sense amplifiers, for example, first to fourth bank sense amplifiers 285a, 285b, 285c, and 285d connected to first to fourth bank arrays 280a, 280b, 280c, and 280d, respectively.

[0179] The first memory bank array 280a to the fourth memory bank array 280d, the first memory bank row decoders 260a to the fourth memory bank row decoders 260d, the first memory bank column decoders 270a to the fourth memory bank column decoders 270d, and the first memory bank sense amplifiers 285a to the fourth memory bank sense amplifiers 285d may form the first memory bank to the fourth memory bank, respectively. For example, a first memory cell array 280a, a first memory cell row decoder 260a, a first memory cell column decoder 270a and a first memory cell read amplifier 285a may form a first memory cell; a second memory cell array 280b, a second memory cell row decoder 260b, a second memory cell column decoder 270b and a second memory cell read amplifier 285b may form a second memory cell; a third memory cell array 280c, a third memory cell row decoder 260c, a third memory cell column decoder 270c and a third memory cell read amplifier 285c may form a third memory cell; and a fourth memory cell array 280d, a fourth memory cell row decoder 260d, a fourth memory cell column decoder 270d and a fourth memory cell read amplifier 285d may form a fourth memory cell.

[0180] The address register 220 can be obtained from a memory controller (e.g., Fig. 20 The memory controller 20 in the memory controller 20 receives an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR. The address register 220 can provide the received bank address BANK_ADDR to the bank control logic 230, can provide the received row address ROW_ADDR to the row address multiplexer 240, and can provide the received column address COL_ADDR to the column address latch 250.

[0181] The bank control logic 230 may generate a bank control signal in response to receiving the bank address BANK_ADDR. One of the first to fourth bank row decoders 260a to 260d corresponding to the received bank address BANK_ADDR may be activated in response to the bank control signal generated by the bank control logic 230, and one of the first to fourth bank column decoders 270a to 270d corresponding to the received bank address BANK_ADDR may be activated in response to the bank control signal generated by the bank control logic 230.

[0182] The refresh control circuit 215 may generate a refresh address REF_ADDR in response to the receipt of a refresh command or the entry of any self-refresh mode. For example, the refresh control circuit 215 may include a refresh counter configured to sequentially change the refresh address REF_ADDR from the first address of the memory cell array to the last address of the memory cell array. The refresh control circuit 215 may receive a control signal from the control logic 210.

[0183] The row address multiplexer 240 may receive a row address ROW_ADDR from the address register 220, and may receive a refresh address REF_ADDR from the refresh control circuit 215. The row address multiplexer 240 may selectively output the row address ROW_ADDR or the refresh address REF_ADDR. The row address RA (e.g., the row address ROW_ADDR or the refresh address REF_ADDR) output from the row address multiplexer 240 may be applied to the first to fourth bank row decoders 260a to 260d.

[0184] An activated one of the first to fourth bank row decoders 260a to 260d may decode the row address output from the row address multiplexer 240 and may activate a word line corresponding to the row address. For example, the activated bank row decoder may apply a word line driving voltage to the word line corresponding to the row address.

[0185] The column address latch 250 may receive the column address COL_ADDR from the address register 220 and may temporarily store the received column address COL_ADDR. The column address latch 250 may apply the temporarily stored or received column address COL_ADDR′ to the first to fourth bank column decoders 270a to 270d.

[0186] An activated one of the first to fourth bank column decoders 270 a to 270 d may decode the column address COL_ADDR output from the column address latch 250 and may control the I / O gating circuit 290 to output data corresponding to the column address COL_ADDR.

[0187] The I / O gating circuit 290 may include a circuit for gating I / O data. For example, although not shown, the I / O gating circuit 290 may include an input data mask logic, a read data latch for storing data output from the first memory bank array 280a to the fourth memory bank array 280d, and a write driver for writing data to the first memory bank array 280a to the fourth memory bank array 280d.

[0188] The data DQ to be read from one of the first to fourth memory arrays 280a to 280d may be read by a sense amplifier coupled to one memory array and may be stored in a read data latch. The data DQ stored in the read data latch may be provided to a memory controller via a data I / O buffer 295 and a data I / O pad 299. The data DQ received via the data I / O pad 299 to be written to one of the first to fourth memory arrays 280a to 280d may be provided from the memory controller to the data I / O buffer 295. The data DQ received via the data I / O pad 299 and provided to the data I / O buffer 295 may be written to one memory array via a write driver in the I / O gating circuit 290. For example, the data I / O buffer 295 may include an output driver OD and a receiver RCV, and may use a calibrator CAL according to an example embodiment to compensate for at least one of a timing deviation and an offset. In an example embodiment, the output driver OD, the receiver RCV, and the calibrator CAL of the memory device 200 may correspond to Figure 1 , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 5 , Fig. 10A , Fig. 10B , Fig.15 , Fig.16 , Fig.17A , Fig. 17B and Fig.19 output drivers, multi-stage receivers and calibrators.

[0189] The control logic 210 may control the operation of the memory device 200. For example, the control logic 210 may generate a control signal for the memory device 200 to perform a data write operation or a data read operation. The control logic 210 may include a command decoder 211 that decodes a command CMD received from a memory controller, and a mode register 212 that sets an operation mode of the memory device 200.

[0190] Although the memory device included in the memory system according to the example embodiments is described based on DRAM, the memory device according to the example embodiments may be any volatile memory device and / or any nonvolatile memory device, for example, a static random access memory (SRAM), a flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a nano floating gate memory (NFGM), a polymer random access memory (PoRAM), a magnetic random access memory (MRAM), a ferroelectric random access memory (FRAM), a thyristor random access memory (TRAM), etc.

[0191] Fig.23 is a flowchart illustrating a method of operating a memory device according to example embodiments.

[0192] Reference Fig.23 In a method of operating a memory device according to an example embodiment, an internal input signal is generated based on a first clock signal (operation S100), a plurality of decision signals are generated by sampling the internal input signal based on a reference voltage and a second clock signal (operation S200), and at least one of a timing deviation and an offset associated with a plurality of samplers is detected and compensated based on the plurality of decision signals (operation S300). For example, the memory device may be as described with reference to Figure 1 , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5 , Figure 6 , 7A to 7D , Figure 8 , Fig. 9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11 , Fig.12 , Fig.13A , Fig. 13B and Fig.14 The memory device described herein may be a memory device based on a multi-level signal operation, or ... Fig.15 , Fig.16 , Fig.17A , Fig. 17B , Fig.18 and Fig.19 A memory device operating based on NRZ signals is described.

[0193] Example embodiments may be applied to various electronic devices and systems including memory devices. For example, example embodiments may be applied to systems such as personal computers (PCs), server computers, data centers, workstations, mobile phones, smart phones, tablet computers, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, portable game consoles, music players, video cameras, video players, navigation devices, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-book readers, virtual reality (VR) devices, augmented reality (AR) devices, robotic devices, drones, etc.

[0194] The above is an illustration of example embodiments and should not be construed as limiting thereof. Although some example embodiments have been described, those skilled in the art will readily appreciate that many modifications may be made in the example embodiments without materially departing from the novel teachings and advantages of the example embodiments. Therefore, all such modifications are intended to be included within the scope of the example embodiments defined in the claims. Therefore, it will be understood that the above is an illustration of various example embodiments and is not to be construed as being limited to the specific example embodiments disclosed, and modifications to the disclosed example embodiments as well as other example embodiments are intended to be included within the scope of the appended claims.

Claims

1. A memory device, comprising: Data input / output pins; an output driver connected to the data input / output pin and configured to generate an internal input signal based on a first clock signal; a multi-stage receiver connected to the data input / output pin, the multi-stage receiver comprising a plurality of samplers configured to generate a plurality of decision signals by sampling the internal input signal based on a reference voltage and a second clock signal; as well as a calibrator configured to detect and compensate for at least one of a timing deviation and an offset associated with the plurality of samplers based on the plurality of decision signals, The internal input signal is a multi-level signal having three or more voltage levels different from each other.

2. The memory device according to claim 1, wherein: In a calibration mode of the memory device, the memory device is configured such that the calibrator detects and compensates for at least one of the timing deviation and the offset associated with the plurality of samplers in the absence of an external input signal received from an external device through the data input / output pin.

3. The memory device according to claim 2, wherein: In the calibration mode, the data input / output pin has a high impedance state.

4. The memory device according to claim 2, wherein: In a normal operation mode of the memory device after the calibration mode, the memory device is configured such that the plurality of samplers samples a multi-level input signal received through the data input / output pin based on a plurality of reference voltages different from each other.

5. The memory device according to claim 1, wherein: The calibrator comprises: a timing deviation detection circuit configured to detect the timing deviation associated with the plurality of samplers based on the plurality of decision signals; and A plurality of delay control units are configured to generate a plurality of third clock signals based on the second clock signal and to compensate for the timing deviation associated with the plurality of samplers by adjusting the phase of the second clock signal.

6. The memory device according to claim 1, wherein: The calibrator comprises: an offset detection circuit configured to detect the offset associated with the plurality of samplers based on the plurality of decision signals; and A plurality of offset control units are configured to compensate for the offsets associated with the plurality of samplers.

7. The memory device according to claim 1, wherein: The multi-level signal includes a first voltage level, a second voltage level, a third voltage level, and a fourth voltage level that are different from each other.

8. The memory device according to claim 7, wherein: The multi-stage receiver comprises: a first sampler configured to generate a first decision signal by sampling the internal input signal based on the reference voltage and a first sub clock signal generated from the second clock signal; a second sampler configured to generate a second decision signal by sampling the internal input signal based on the reference voltage and a second sub clock signal generated from the second clock signal; and A third sampler is configured to generate a third decision signal by sampling the internal input signal based on the reference voltage and a third sub clock signal generated from the second clock signal.

9. The memory device according to claim 8, wherein: The calibrator comprises: a first delay control unit configured to generate the first sub-clock signal by adjusting a phase of the second clock signal based on a first delay control signal, and provide the first sub-clock signal to the first sampler; a second delay control unit configured to generate the second sub-clock signal by adjusting a phase of the second clock signal based on a second delay control signal, and provide the second sub-clock signal to the second sampler; a third delay control unit configured to generate the third sub clock signal by adjusting the phase of the second clock signal based on a third delay control signal, and provide the third sub clock signal to the third sampler; and A control circuit is configured to generate the first delay control signal, the second delay control signal, and the third delay control signal based on the first decision signal, the second decision signal, and the third decision signal, respectively.

10. The memory device according to claim 9, wherein: In response to the logic level of the first decision signal being different from the logic levels of the second decision signal and the third decision signal, the memory device is configured such that: The first delay control unit provides the first sub-clock signal to the first sampler by adjusting the phase of the second clock signal based on the first delay control signal, or The second delay control unit and the third delay control unit provide the second sub clock signal and the third sub clock signal to the second sampler and the third sampler by adjusting the phase of the second clock signal based on the second delay control signal and the third delay control signal, respectively.

11. The memory device according to claim 8, wherein: In a normal operation mode of the memory device, the memory device is configured so that the first sampler, the second sampler, and the third sampler respectively sample a multi-level input signal received through the data input / output pin based on a first reference voltage, a second reference voltage, and a third reference voltage that are different from each other.

12. The memory device according to claim 8, wherein: Phases of the first to third sub-clock signals partially overlap with each other.

13. The memory device according to claim 7, wherein: The multi-stage receiver comprises: a first sampler configured to generate a first decision signal by sampling the internal input signal based on the reference voltage and a first sub clock signal; a second sampler configured to generate a second decision signal by sampling the internal input signal based on the reference voltage and a second sub-clock signal; a third sampler configured to generate a third decision signal by sampling the internal input signal based on the reference voltage and a third sub clock signal; and A fourth sampler is configured to generate a fourth decision signal by sampling the internal input signal based on the reference voltage and a fourth sub clock signal.

14. The memory device according to claim 13, wherein: The calibrator comprises: a first offset control unit included in the first sampler and configured to adjust an output level of the first sampler based on a first offset control signal; a second offset control unit included in the second sampler and configured to adjust an output level of the second sampler based on a second offset control signal; a third offset control unit included in the third sampler and configured to adjust an output level of the third sampler based on a third offset control signal; a fourth offset control unit included in the fourth sampler and configured to adjust an output level of the fourth sampler based on a fourth offset control signal; and A control circuit is configured to generate the first offset control signal, the second offset control signal, the third offset control signal and the fourth offset control signal based on the first decision signal, the second decision signal, the third decision signal and the fourth decision signal, respectively.

15. The memory device of claim 14, wherein: In response to the logic level of the first decision signal being different from the logic levels of the second decision signal, the third decision signal, and the fourth decision signal, the memory device is configured such that: The first offset control unit adjusts the output level of the first sampler based on the first offset control signal, or The second offset control unit, the third offset control unit, and the fourth offset control unit adjust output levels of the second sampler, the third sampler, and the fourth sampler based on the second offset control signal, the third offset control signal, and the fourth offset control signal, respectively.

16. The memory device of claim 13, wherein: In a normal operation mode of the memory device, the memory device is configured such that the first sampler, the second sampler, the third sampler, and the fourth sampler sample a multi-level input signal received through the data input / output pin based on a first reference voltage.

17. The memory device of claim 1, wherein: The plurality of samplers are configured to sample the internal input signal based on the internal input signal having a fixed level and the reference voltage having a variable level.

18. A memory device comprising: Data input / output pins; an output driver connected to the data input / output pin and configured to generate an internal input signal based on a first clock signal; a receiver connected to the data input / output pin, the receiver comprising a plurality of samplers configured to generate a plurality of decision signals by sampling the internal input signal based on a reference voltage and a plurality of second clock signals whose phases partially overlap; as well as a calibrator configured to detect and compensate for offsets associated with the plurality of samplers based on the plurality of decision signals, The internal input signal is a non-return-to-zero signal having two voltage levels different from each other.

19. The memory device of claim 18, wherein: The memory device is configured such that: In a calibration mode of the memory device, the calibrator detects and compensates for the offset associated with the plurality of samplers in the absence of an external input signal received from an external device through the data input / output pin, and In a normal operation mode of the memory device after the calibration mode, the output driver generates a non-return-to-zero output signal output through the data input / output pin, and the plurality of samplers samples a non-return-to-zero input signal received through the data input / output pin based on the reference voltage.

20. A memory device comprising: Data input / output pins; an output driver connected to the data input / output pin and configured to generate an internal input signal based on a first clock signal; a multi-stage receiver connected to the data input / output pin, the multi-stage receiver comprising a plurality of samplers configured to generate a plurality of decision signals by sampling the internal input signal based on a reference voltage and a second clock signal; as well as a calibrator configured to detect and compensate for at least one of a timing deviation and an offset associated with the plurality of samplers based on the plurality of decision signals, Wherein, the plurality of samplers include: a first sampler configured to generate a first decision signal by sampling the internal input signal based on the reference voltage and a first sub clock signal; a second sampler configured to generate a second decision signal by sampling the internal input signal based on the reference voltage and a second sub-clock signal; a third sampler configured to generate a third decision signal by sampling the internal input signal based on the reference voltage and a third sub clock signal; a fourth sampler configured to generate a fourth decision signal by sampling the internal input signal based on the reference voltage and a fourth sub clock signal; a fifth sampler configured to generate a fifth decision signal by sampling the internal input signal based on the reference voltage and a fifth sub clock signal; and a sixth sampler configured to generate a sixth decision signal by sampling the internal input signal based on the reference voltage and a sixth sub-clock signal, wherein the first sub-clock signal to the sixth sub-clock signal are generated based on the second clock signal, wherein the phases of the first to fourth sub-clock signals partially overlap with each other, and the phases of the first, fifth and sixth sub-clock signals are identical to each other, and Wherein, the calibrator comprises: a first offset control unit configured to determine that an offset associated with the first sampler has occurred, and adjust an output level of the first sampler in response to a logic level of the first decision signal being different from a logic level of each of the second decision signal, the third decision signal, and the fourth decision signal; and A first delay control unit is configured to determine that a timing deviation associated with the first sampler has occurred, and adjust a phase of the first sub-clock signal in response to a logic level of the first decision signal being different from a logic level of each of the fifth decision signal and the sixth decision signal.

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