Self-termination write circuit and magnetic memory device

Abstract

The invention provides a self-termination write-in circuit, which is used for writing a magnetic storage unit from an anti-parallel state to a parallel state, and comprises a time delay unit for outputting a signal of a first end from a second end after preset time delay; the first / second input end of the first AND gate is electrically connected with the second / one end of the delay unit; the first input end of the second AND gate is electrically connected with the output end of the first AND gate; the comparator is used for comparing the bit line voltage and the reference voltage and is enabled by the output signal of the second AND gate; the pull-up MOS tube is used for pulling up the output end of the comparator and is controlled by an output signal of the first AND gate; the output end of the latch is electrically connected with the second end of the pull-up MOS tube; the first input end of the third AND gate is electrically connected with the output end of the latch, the second input end of the third AND gate is electrically connected with the first end of the delay unit, the first input end of the third AND gate is further electrically connected with the second input end of the second AND gate, and the output end of the third AND gate is used for outputting a driving signal and controlling a write driving circuit to write the magnetic storage unit from the anti-parallel state to the parallel state.

Description

Technical Field

[0001] The present invention relates to the field of magnetic storage technology, and in particular to a self-termination writing circuit and a magnetic storage device. Background Art

[0002] When performing a write operation, the magnetic storage device usually writes to the entire address. Some of the stored data in the magnetic storage device may be the same as the data to be written, and no write operation is required. By omitting the write operation for these units that do not require write operations, the power consumption of the chip can be reduced, the number of device writes can be reduced, and the life of the magnetic storage device can be increased.

[0003] In order to reduce the number of write times, a read-verify-write technology can be introduced. The data is judged before writing. If the stored data and the written data are consistent, the write operation is terminated. If writing is required, low voltage is used for writing first, and reading is performed after the write operation is completed. If the data has been written, the write operation is completed. If the data has not been written, the write operation voltage is raised and a second write is performed. This is repeated in sequence until the array is completely written.

[0004] In the current write termination technology, since the array must be read and verified before each write operation, and multiple write operations are required, a single write cycle is actually composed of several groups of write operations and read operations. The write time will be very long, reducing the chip operating frequency and the write speed becomes very slow. Summary of the invention

[0005] The self-terminating write circuit and magnetic storage device provided by the present invention can effectively terminate invalid write operations without performing additional reading.

[0006] In a first aspect, the present invention provides a self-terminating write circuit for writing a magnetic storage unit from an antiparallel state to a parallel state, the circuit comprising:

[0007] A delay unit, used to output a signal input from the first end from the second end after a predetermined delay;

[0008] A first AND gate, wherein a first input terminal of the first AND gate is electrically connected to a second terminal of the delay unit; and a second input terminal of the first AND gate is electrically connected to a first terminal of the delay unit;

[0009] a second AND gate, wherein a first input terminal of the second AND gate is electrically connected to an output terminal of the first AND gate;

[0010] A comparator, wherein an enable terminal of the comparator is electrically connected to an output terminal of the second AND gate, a first input terminal of the comparator is electrically connected to a bit line of the magnetic storage unit, and a second input terminal of the comparator is electrically connected to a reference voltage source corresponding to the magnetic storage unit;

[0011] A pull-up MOS transistor, wherein the gate of the pull-up MOS transistor is electrically connected to the first input terminal of the second AND gate, the first terminal of the pull-up MOS transistor is electrically connected to the pull-up voltage source, and the second terminal of the pull-up MOS transistor is electrically connected to the output terminal of the comparator;

[0012] A latch, wherein an output end of the latch is electrically connected to the second end of the pull-up MOS tube;

[0013] A third AND gate, wherein the first input terminal of the third AND gate is electrically connected to the output terminal of the latch, the second input terminal of the third AND gate is electrically connected to the first terminal of the delay unit, the first input terminal of the third AND gate is also electrically connected to the second input terminal of the second AND gate, and the output terminal of the third AND gate is used to output a drive signal to control a write drive circuit that writes the magnetic storage unit from an antiparallel state to a parallel state.

[0014] Optionally, the difference between the voltage of the reference voltage source received at the second input terminal of the comparator and the first voltage output by the antiparallel magnetic storage unit is a first difference voltage; the difference between the voltage of the reference voltage source received at the second input terminal of the comparator and the second voltage output by the parallel magnetic storage unit is a second difference voltage; and the first difference voltage is less than the second difference voltage.

[0015] Optionally, the preset delay of the delay unit is not greater than a write pulse width for writing the magnetic storage unit from an antiparallel state to a parallel state.

[0016] Optionally, the preset delay of the delay unit is not less than the time difference from power-on to bit line voltage stabilization of the magnetic storage unit.

[0017] In a second aspect, the present invention provides a self-terminating write circuit for writing a magnetic storage unit from a parallel state to an anti-parallel state, the circuit comprising:

[0018] A delay unit, used to output a signal input from the first end from the second end after a predetermined delay;

[0019] A first AND gate, wherein a first input terminal of the first AND gate is electrically connected to a second terminal of the delay unit; and a second input terminal of the first AND gate is electrically connected to a first terminal of the delay unit;

[0020] a second AND gate, wherein a first input terminal of the second AND gate is electrically connected to an output terminal of the first AND gate;

[0021] A comparator, wherein an enable terminal of the comparator is electrically connected to an output terminal of the second AND gate, a first input terminal of the comparator is electrically connected to a source line of the magnetic storage unit, and a second input terminal of the comparator is electrically connected to a reference voltage source corresponding to the magnetic storage unit;

[0022] A pull-down MOS transistor, wherein a first end of the pull-down MOS transistor is electrically connected to a pull-down voltage source, and a second end of the pull-down MOS transistor is electrically connected to an output end of the comparator;

[0023] A first inverter, wherein an input end of the first inverter is electrically connected to the second end of the delay unit, and an output end of the first inverter is electrically connected to the gate of the pull-down MOS tube;

[0024] A latch, wherein an output end of the latch is electrically connected to the second end of the pull-down MOS tube;

[0025] a second inverter, wherein an input terminal of the second inverter is electrically connected to an output terminal of the latch;

[0026] A third AND gate, wherein the first input terminal of the third AND gate is electrically connected to the output terminal of the second inverter, the second input terminal of the third AND gate is electrically connected to the first terminal of the delay unit, the first input terminal of the third AND gate is also electrically connected to the second input terminal of the second AND gate, and the output terminal of the third AND gate is used to output a drive signal to control the write drive circuit of the magnetic storage unit from the parallel state to the anti-parallel state.

[0027] Optionally, the difference between the voltage of the reference voltage source received by the second input terminal of the comparator and the first voltage output by the parallel magnetic storage unit is a first difference voltage; the difference between the voltage of the reference voltage source received by the second input terminal of the comparator and the second voltage output by the anti-parallel magnetic storage unit is a second difference voltage; and the first difference voltage is less than the second difference voltage.

[0028] Optionally, the preset delay of the delay unit is not greater than a write pulse width for writing the antiparallel state of the magnetic storage unit to the parallel state.

[0029] Optionally, the preset delay of the delay unit is not less than the time difference from power-on to source line voltage stabilization of the magnetic storage unit.

[0030] In a third aspect, the present invention provides a magnetic storage device, comprising:

[0031] A magnetic storage unit, comprising a magnetic tunnel junction and a selection MOS tube, wherein a first end of the magnetic tunnel junction is electrically connected to a drain of the selection MOS tube, a second end of the magnetic tunnel junction is electrically connected to a bit line, a source of the selection MOS tube is electrically connected to a source line, and a gate of the selection MOS tube is electrically connected to a word line;

[0032] A first write drive circuit is electrically connected to the bit line of the magnetic storage unit, and the first write drive circuit is used to write the magnetic storage unit from an antiparallel state to a parallel state;

[0033] A self-terminating write circuit for writing a magnetic storage unit from an antiparallel state to a parallel state as described in any one of the above, configured to output a drive signal to the first write drive circuit;

[0034] a second write drive circuit electrically connected to the source line of the magnetic storage unit, the first write drive circuit being used to write the magnetic storage unit from a parallel state to an anti-parallel state;

[0035] The self-terminating write circuit for writing a magnetic storage unit from a parallel state to an anti-parallel state as described in any one of the above items is used to output a drive signal to the second write drive circuit.

[0036] The technical solution provided by the present invention determines whether the bit data is consistent with the write data during the writing process, and reduces the probability of judgment error through a timing adjustment module to terminate invalid write operations, reduce power consumption, and reduce the number of operations on the bit, so as to increase the life of the magnetic storage unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A schematic diagram of a self-termination write circuit according to an embodiment of the present invention;

[0038] Figure 2 A schematic diagram of a port of a comparator of a self-termination write circuit according to another embodiment of the present invention;

[0039] Figure 3 A schematic diagram of a timing sequence of a comparator voltage change in a self-termination write circuit according to another embodiment of the present invention;

[0040] Figure 4 A schematic diagram of voltage changes in the antiparallel state and the parallel state of a self-termination writing circuit according to another embodiment of the present invention;

[0041] Figure 5 A schematic diagram of a reading window of a reference voltage and a bit line voltage of a self-termination write circuit according to another embodiment of the present invention;

[0042] Figure 6 A schematic diagram of a self-termination write circuit according to another embodiment of the present invention;

[0043] Figure 7 FIG. 1 is a schematic diagram of the timing sequence of various signal voltages of a self-termination writing circuit according to another embodiment of the present invention. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0045] The embodiment of the present invention provides a self-terminating write circuit for writing a magnetic storage unit from an antiparallel state to a parallel state, such as Figure 1 As shown, the circuit comprises:

[0046] A delay unit, used to output a signal input from the first end from the second end after a predetermined delay;

[0047] A first AND gate, wherein a first input terminal of the first AND gate is electrically connected to a second terminal of the delay unit; and a second input terminal of the first AND gate is electrically connected to a first terminal of the delay unit;

[0048] a second AND gate, wherein a first input terminal of the second AND gate is electrically connected to an output terminal of the first AND gate;

[0049] A comparator, wherein an enable terminal of the comparator is electrically connected to an output terminal of the second AND gate, a first input terminal of the comparator is electrically connected to a bit line of the magnetic storage unit, and a second input terminal of the comparator is electrically connected to a reference voltage source corresponding to the magnetic storage unit;

[0050] A pull-up MOS transistor, wherein the gate of the pull-up MOS transistor is electrically connected to the first input terminal of the second AND gate, the first terminal of the pull-up MOS transistor is electrically connected to the pull-up voltage source, and the second terminal of the pull-up MOS transistor is electrically connected to the output terminal of the comparator;

[0051] A latch, wherein an output end of the latch is electrically connected to the second end of the pull-up MOS tube;

[0052] A third AND gate, wherein the first input terminal of the third AND gate is electrically connected to the output terminal of the latch, the second input terminal of the third AND gate is electrically connected to the first terminal of the delay unit, the first input terminal of the third AND gate is also electrically connected to the second input terminal of the second AND gate, and the output terminal of the third AND gate is used to output a drive signal to control a write drive circuit that writes the magnetic storage unit from an antiparallel state to a parallel state.

[0053] The writing process of the self-terminating writing circuit provided in this embodiment is analyzed as follows:

[0054] When a write operation is performed, the WRITE_AP2P_ENABLE signal is pulled high and COMPARE_EN is at a low level, so the pull-up circuit is turned on and the comparator output is pulled high. After passing through the logic circuit, the WRITE_AP2P_SET signal is high, and the circuit normally performs the write operation from the antiparallel state to the parallel state, that is, the AP2P write operation. After the predetermined time t1, the COMPARE_EN signal is pulled high. The predetermined time t1 is determined by the delay unit and the time can be adjusted. The consideration of delaying COMPARE_EN is to reduce the fluctuation in the voltage establishment process. The comparison voltage is not the actual stable voltage, resulting in the probability of comparison error. After COMPARE_EN is pulled high, the pull-up circuit is turned off. At this time, the output of the comparator is in a floating state, and the level is maintained by a latch without changing. At the same time, the comparator starts to compare the voltage conditions of the reference end and the bit line end. After a short comparison time t2, the comparator outputs its comparison result. If it has not been written or needs to be written, the comparator output is high. If it has been written or does not need to be written, the comparator output is low. If the output is low, the WRITE_AP2P_SET is pulled low through logic to turn off the write drive circuit and stop writing. If the output is high, the comparison continues until the comparison result changes or the write pulse ends.

[0055] like Figure 2-3 As shown, the voltage comparator is a four-port device, where Compare_en is an enable switch, and terminals A and B are comparison voltage input terminals. No current flows in during normal operation. Compare_out is the output terminal. When Compare_en is high, the voltages of A and B are compared. If the voltage of A is higher than that of B, the output Compare_out is 0. If the voltage of A is lower than that of B, the output Compare_out is 1. The comparison process continues when Compare_en is high until Compare_en is pulled low. When the voltage changes during the comparison process, Compare_out needs a time window T_SENSING to output. This time is related to the voltages of A and B and the voltage difference. The circuit can be adjusted according to the actual situation to make the time window T_SENSING smaller.

[0056] like Figure 4 As shown, since the MTJ resistance will flip after successful writing, its resistance value will jump after flipping. When the resistance jumps, the voltage of the bit line BL will also change due to the change in the resistance of the entire branch. For example, when the magnetic tunnel junction MTJ flips from the anti-parallel AP state to the parallel P state, the resistance suddenly decreases, and the voltage on the bit line will decrease due to the change in the voltage divider of the magnetic tunnel junction MTJ. At this time, if a reference voltage is used, and its voltage value is the middle value of the bit line voltage before and after the flip, it is possible to determine whether the writing is successful by judging the relationship between the voltage on BL and the reference.

[0057] As an optional embodiment, the difference between the voltage of the reference voltage source received by the second input terminal of the comparator and the first voltage output by the antiparallel magnetic storage unit is a first difference voltage; the difference between the voltage of the reference voltage source received by the second input terminal of the comparator and the second voltage output by the parallel magnetic storage unit is a second difference voltage; the first difference voltage is less than the second difference voltage.

[0058] In some embodiments, Figure 5 As shown in the figure, when the comparator is working, the voltage of the bit line BL will be compared with the reference, and the window size is the voltage difference between points AB. When the window is too small, comparison errors will occur, because the comparator is not an ideal device. Due to process fluctuations, etc., it will cause a certain range of inability to obtain correct comparison results. It is possible to regard the anti-parallel AP state as the parallel P state, that is, the unwritten state is regarded as written, or the parallel P state is regarded as the anti-parallel AP state, that is, the written state is regarded as unwritten. In fact, recognizing the P state as the AP state has little impact on the chip, and the impact is to continue the current write operation. The impact of the AP state thinking that the P state is relatively large, and the writing is stopped before the actual writing is completed. This leads to data errors. In order to increase the comparison window, the reference can be adjusted to be closer to point A, so that point B is less likely to be misidentified, and the resolution rate of the P state is improved to reduce the probability of write termination errors.

[0059] As an optional implementation manner, the preset delay of the delay unit is not greater than a write pulse width for writing the magnetic storage unit from an antiparallel state to a parallel state.

[0060] As an optional implementation manner, the preset delay of the delay unit is not less than the time difference from power-on to bit line voltage stabilization of the magnetic storage unit.

[0061] The embodiment of the present invention also provides a self-terminating write circuit for writing a magnetic storage unit from a parallel state to an anti-parallel state, such as Figure 6 As shown, the circuit comprises:

[0062] A delay unit, used to output a signal input from the first end from the second end after a predetermined delay;

[0063] A first AND gate, wherein a first input terminal of the first AND gate is electrically connected to a second terminal of the delay unit; and a second input terminal of the first AND gate is electrically connected to a first terminal of the delay unit;

[0064] a second AND gate, wherein a first input terminal of the second AND gate is electrically connected to an output terminal of the first AND gate;

[0065] A comparator, wherein an enable terminal of the comparator is electrically connected to an output terminal of the second AND gate, a first input terminal of the comparator is electrically connected to a source line of the magnetic storage unit, and a second input terminal of the comparator is electrically connected to a reference voltage source corresponding to the magnetic storage unit;

[0066] A pull-down MOS transistor, wherein a first end of the pull-down MOS transistor is electrically connected to a pull-down voltage source, and a second end of the pull-down MOS transistor is electrically connected to an output end of the comparator;

[0067] A first inverter, wherein an input end of the first inverter is electrically connected to the second end of the delay unit, and an output end of the first inverter is electrically connected to the gate of the pull-down MOS tube;

[0068] A latch, wherein an output end of the latch is electrically connected to the second end of the pull-down MOS tube;

[0069] a second inverter, wherein an input terminal of the second inverter is electrically connected to an output terminal of the latch;

[0070] A third AND gate, wherein the first input terminal of the third AND gate is electrically connected to the output terminal of the second inverter, the second input terminal of the third AND gate is electrically connected to the first terminal of the delay unit, the first input terminal of the third AND gate is also electrically connected to the second input terminal of the second AND gate, and the output terminal of the third AND gate is used to output a drive signal to control the write drive circuit of the magnetic storage unit from the parallel state to the anti-parallel state.

[0071] As follows, combined Figure 7 The timing diagram shown is used to analyze the writing process of the self-terminating writing circuit provided in this embodiment:

[0072] When performing P2AP writing, taking the case where writing is performed after a period of time as an example, the write pulse width is set to 30ns.

[0073] When the write operation starts at t=5ns, a WRITE_P2AP_ENALBE signal is input externally to start the write P2AP operation. At this time, the COMPARE_EN signal is low, COMPARE_OUT is pulled down, and the output is low. After passing through the second inverter, STOP_PA2P_WRITE_N is high. After logic, WRITE_P2AP_SET is high, and WRITE_DRIVER_P2AP starts working. At this time, the source line voltage rises, the word line is turned on, and the MTJ starts the write P2AP operation.

[0074] The delay module starts working at the same time, and the delay preset time is set to 3ns through the DELAY_TRIM signal. When t=8ns, after WRITE_DRIVER_P2AP is pulled high for 3ns, COMPARE_EN is pulled high, and the pull-down tube of COMPARE_OUT is closed. At this time, the latch maintains the level of COMPARE_OUT as low, which does not affect the back-end logic, and the write operation continues. At the same time, when the comparator starts working, it starts to compare the voltage of the source line SL with the reference voltage REF. After a 0.5ns time window, the result is low, indicating that the MTJ device is still not written at this time, and the write operation needs to continue. Since the result is still low, it does not affect the back-end logic, and the write operation continues, and the comparator continues to work to compare the voltage.

[0075] When the write operation reaches 15ns, that is, t=20ns, COMPARE_OUT becomes high. At this time, through the subsequent logic, STOP_PA2P_WRITE_N is pulled low, the write termination takes effect, and the comparator stops voltage comparison at the same time. The latch maintains COMPARE_OUT high until the write operation is completed. After the write is completed, WRITE_P2AP_ENABLE is pulled low, COMPARE_EN becomes low, the pull-down circuit is turned on, COMPARE_OUT is pulled low, STOP_PA2P_WRITE_N is high, and it returns to the initial state.

[0076] Compared with the traditional write termination structure, the present invention reduces the false shutdown operation that is easy to occur in the write termination structure through the adjustable preset time control comparison start time and biased reference, which can reduce the bit error rate of this architecture. The write termination structure can reduce the number and time of device writes, thereby improving the lifespan and reducing write power consumption.

[0077] As an optional embodiment, the difference between the voltage of the reference voltage source received by the second input terminal of the comparator and the first voltage output by the parallel magnetic storage unit is a first difference voltage; the difference between the voltage of the reference voltage source received by the second input terminal of the comparator and the second voltage output by the anti-parallel magnetic storage unit is a second difference voltage; and the first difference voltage is less than the second difference voltage.

[0078] In some embodiments, the reference voltage may not be at the middle value before and after the flip, but should be closer to the voltage before the flip, and may be raised with the write voltage adjustment, so as to increase the comparison window and improve the resolution of the AP state, thereby reducing the probability of write termination errors.

[0079] As an optional implementation manner, the preset delay of the delay unit is not greater than a write pulse width for writing the magnetic storage unit from an antiparallel state to a parallel state.

[0080] As an optional implementation manner, the preset delay of the delay unit is not less than the time difference from power-on to source line voltage stabilization of the magnetic storage unit.

[0081] An embodiment of the present invention further provides a magnetic storage device, comprising:

[0082] A magnetic storage unit, comprising a magnetic tunnel junction and a selection MOS tube, wherein a first end of the magnetic tunnel junction is electrically connected to a drain of the selection MOS tube, a second end of the magnetic tunnel junction is electrically connected to a bit line, a source of the selection MOS tube is electrically connected to a source line, and a gate of the selection MOS tube is electrically connected to a word line;

[0083] A first write drive circuit is electrically connected to the bit line of the magnetic storage unit, and the first write drive circuit is used to write the magnetic storage unit from an antiparallel state to a parallel state;

[0084] A self-terminating write circuit for writing a magnetic storage unit from an antiparallel state to a parallel state as described in any one of the above, configured to output a drive signal to the first write drive circuit;

[0085] a second write drive circuit electrically connected to the source line of the magnetic storage unit, the first write drive circuit being used to write the magnetic storage unit from a parallel state to an anti-parallel state;

[0086] The self-terminating write circuit for writing a magnetic storage unit from a parallel state to an anti-parallel state as described in any one of the above items is used to output a drive signal to the second write drive circuit.

[0087] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A self-terminating write circuit, characterized in that: For writing a magnetic memory cell from an antiparallel state to a parallel state, the circuit comprising: a delay unit, configured to output a signal input from the first end from the second end after a predetermined delay; a first AND gate, wherein a first input terminal of the first AND gate is electrically connected to the second terminal of the delay unit; and a second input terminal of the first AND gate is electrically connected to the first terminal of the delay unit; a second AND gate, wherein a first input terminal of the second AND gate is electrically connected to an output terminal of the first AND gate; a comparator, wherein an enable terminal of the comparator is electrically connected to the output terminal of the second AND gate, a first input terminal of the comparator is electrically connected to a bit line of the magnetic storage unit, and a second input terminal of the comparator is electrically connected to a reference voltage source corresponding to the magnetic storage unit; a pull-up MOS transistor, wherein a gate of the pull-up MOS transistor is electrically connected to the first input terminal of the second AND gate, a first terminal of the pull-up MOS transistor is electrically connected to a pull-up voltage source, and a second terminal of the pull-up MOS transistor is electrically connected to the output terminal of the comparator; a latch, wherein an output end of the latch is electrically connected to the second end of the pull-up MOS transistor; A third AND gate, wherein the first input end of the third AND gate is electrically connected to the output end of the latch, the second input end of the third AND gate is electrically connected to the first end of the delay unit, the first input end of the third AND gate is also electrically connected to the second input end of the second AND gate, and the output end of the third AND gate is used to output a drive signal to control the write drive circuit that writes the magnetic storage unit from an antiparallel state to a parallel state.

2. The self-termination write circuit according to claim 1, wherein: The difference between the voltage of the reference voltage source received by the second input terminal of the comparator and the first voltage output by the antiparallel magnetic storage unit is a first difference voltage; the difference between the voltage of the reference voltage source received by the second input terminal of the comparator and the second voltage output by the parallel magnetic storage unit is a second difference voltage; the first difference voltage is less than the second difference voltage.

3. The self-termination write circuit according to claim 1, wherein: The preset delay of the delay unit is no greater than a write pulse width for writing the magnetic storage unit from an antiparallel state to a parallel state.

4. The self-termination write circuit according to claim 3, wherein: The preset delay of the delay unit is not less than the time difference from power-up to bit line voltage stabilization of the magnetic storage unit.

5. A self-terminating write circuit, characterized in that: For writing a magnetic storage cell from a parallel state to an antiparallel state, the circuit comprising: a delay unit, configured to output a signal input from the first end from the second end after a predetermined delay; a first AND gate, wherein a first input terminal of the first AND gate is electrically connected to the second terminal of the delay unit; and a second input terminal of the first AND gate is electrically connected to the first terminal of the delay unit; a second AND gate, wherein a first input terminal of the second AND gate is electrically connected to an output terminal of the first AND gate; a comparator, wherein an enable terminal of the comparator is electrically connected to the output terminal of the second AND gate, a first input terminal of the comparator is electrically connected to the source line of the magnetic storage unit, and a second input terminal of the comparator is electrically connected to a reference voltage source corresponding to the magnetic storage unit; a pull-down MOS transistor, wherein a first end of the pull-down MOS transistor is electrically connected to a pull-down voltage source, and a second end of the pull-down MOS transistor is electrically connected to an output end of the comparator; a first inverter, wherein an input end of the first inverter is electrically connected to the second end of the delay unit, and an output end of the first inverter is electrically connected to the gate of the pull-down MOS transistor; a latch, wherein an output end of the latch is electrically connected to the second end of the pull-down MOS transistor; a second inverter, wherein an input terminal of the second inverter is electrically connected to an output terminal of the latch; A third AND gate, wherein the first input end of the third AND gate is electrically connected to the output end of the second inverter, the second input end of the third AND gate is electrically connected to the first end of the delay unit, the first input end of the third AND gate is also electrically connected to the second input end of the second AND gate, and the output end of the third AND gate is used to output a drive signal to control the write drive circuit to change the magnetic storage unit from a parallel state to an antiparallel state.

6. The self-termination write circuit according to claim 5, characterized in that: The difference between the voltage of the reference voltage source received by the second input terminal of the comparator and the first voltage output by the parallel magnetic storage unit is a first difference voltage; the difference between the voltage of the reference voltage source received by the second input terminal of the comparator and the second voltage output by the antiparallel magnetic storage unit is a second difference voltage; The first difference voltage is smaller than the second difference voltage.

7. The self-termination write circuit according to claim 5, characterized in that: The preset delay of the delay unit is no greater than a write pulse width for writing the magnetic storage unit from an antiparallel state to a parallel state.

8. The self-termination write circuit according to claim 7, wherein: The preset delay of the delay unit is not less than the time difference from power-on to source line voltage stabilization of the magnetic storage unit.

9. A magnetic storage device, characterized in that: include: A magnetic storage unit, comprising a magnetic tunnel junction and a selection MOS transistor, wherein a first end of the magnetic tunnel junction is electrically connected to a drain of the selection MOS transistor, a second end of the magnetic tunnel junction is electrically connected to a bit line, a source of the selection MOS transistor is electrically connected to a source line, and a gate of the selection MOS transistor is electrically connected to a word line; a first write driver circuit electrically connected to the bit line of the magnetic storage unit, the first write driver circuit being used to write the magnetic storage unit from an antiparallel state to a parallel state; The self-terminating write circuit according to any one of claims 1 to 4, configured to output a drive signal to the first write driver circuit; a second write driver circuit electrically connected to the source line of the magnetic storage unit, wherein the first write driver circuit is used to write the magnetic storage unit from a parallel state to an antiparallel state; The self-terminating write circuit according to any one of claims 5 to 8, configured to output a drive signal to the second write drive circuit.

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