Memory device

Abstract

The embodiment of the invention provides a memory device. The memory device includes a memory cell array including a plurality of memory cells and a plurality of redundant memory cells; the plurality of redundant memory cells are configured to repair a faulty memory cell among the plurality of memory cells; the fault address storage circuit is used for storing at least one first fault address corresponding to the first fault storage unit; a repair logic memory circuit including a plurality of first memory structures and a plurality of second memory structures; redundant addresses corresponding to a plurality of redundant storage units are stored in the plurality of first storage structures, and a first fault address is stored in the second storage structure; the repair logic storage circuit is configured to receive a first operation mode command, wherein the first operation mode command comprises at least one second fault address corresponding to a second fault storage unit; the second fault storage unit is different from the first fault storage unit; a second fail address is written to the second storage structure in response to the first mode of operation command.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of memory, and in particular to a memory device. Background Art

[0002] With the development of high-performance computing, big data analysis, and in-memory databases, the demand for memory capacity and bandwidth is increasing.

[0003] Driven by the continuous demand for memory capacity density and bandwidth performance, the manufacturing process of memory is constantly shrinking and the interface rate is constantly increasing. However, at the same time, with the process upgrade, the probability of memory errors and memory failure rate are gradually increasing, and memory reliability is facing huge risks. In order to repair the faults in the memory, a memory repair method called PostPackage Repair (PPR) is proposed, which uses the redundant addresses in the memory to replace the faulty addresses in the memory, thereby enabling the computer device to read and write data normally. Summary of the invention

[0004] In view of this, an embodiment of the present disclosure provides a storage device.

[0005] To achieve the above objectives, the technical solution of the present disclosure is implemented as follows:

[0006] An embodiment of the present disclosure provides a storage device, comprising: a storage cell array, comprising a plurality of storage cells and a plurality of redundant storage cells; the plurality of redundant storage cells are configured to repair a faulty storage cell among the plurality of storage cells; a fault address storage circuit, configured to store at least one first fault address corresponding to a first faulty storage cell; a repair logic storage circuit, comprising a plurality of first storage structures and a plurality of second storage structures, the first storage structures corresponding to the second storage structures one-to-one and internal storage data being mapped to each other; the plurality of first storage structures store redundant addresses corresponding to the plurality of redundant storage cells, and one of the redundant addresses corresponds to one of the first storage structures; the second storage structure stores the first fault address, and one of the first fault addresses corresponds to one of the second storage structures; the repair logic storage circuit is configured to: receive a first operation mode command, the first operation mode command including at least one second fault address corresponding to a second faulty storage cell; the second faulty storage cell is different from the first faulty storage cell; and in response to the first operation mode command, write the second fault address to the second storage structure.

[0007] In some embodiments, the first storage structure has a corresponding first storage address, and the second storage structure has a corresponding second storage address; the first operating mode command also includes a third storage address corresponding to the second fault address, and each of the third storage addresses is the same as one of the second storage addresses; the repair logic storage circuit is specifically configured to: in response to the first operating mode command, write the second fault address into the corresponding second storage structure according to the third storage address.

[0008] In some embodiments, at least one of the third storage addresses corresponds to a second storage structure storing the first fault address; and the repair logic storage circuit is configured to: in response to the first operating mode command, overwrite the first fault address stored in the second storage structure with the second fault address corresponding to at least one of the third storage addresses.

[0009] In some embodiments, at least one of the third storage addresses corresponds to a second storage structure that does not store the first fault address; and the repair logic storage circuit is configured to: in response to the first operation mode command, directly write the second fault address into the second storage structure.

[0010] In some embodiments, the repair logic storage circuit is configured to: in response to power-on of the storage device, obtain the first fault address from the fault address storage circuit; and write the first fault address to the second storage structure according to a first preset order; in response to power-on of the storage device, write the obtained redundant address to the first storage structure according to a second preset order.

[0011] In some embodiments, the repair logic storage circuit is further configured to: receive a second operating mode command, the second operating mode command including at least one fourth storage address; each of the fourth storage addresses is the same as one of the second storage addresses; and in response to the second operating mode command, read and output a fault address stored in the second storage structure corresponding to the fourth storage address.

[0012] In some embodiments, the repair logic storage circuit is further configured to: receive a third operating mode command, the third operating mode command including at least an access address of a storage unit to be accessed; and in response to the third operating mode command, match the access address with a fault address within the second storage structure; based on a successful match, output a first signal, the first signal being used to indicate access to a redundant address corresponding to the fault address that has successfully matched; and based on a failed match, output a second signal, the second signal being used to indicate access to the access address.

[0013] In some embodiments, the repair logic storage circuit includes a content addressable memory.

[0014] In some embodiments, the fail address storage circuit includes a fuse array or an anti-fuse array.

[0015] In some embodiments, the storage device further includes a mode register and an interface; the interface is configured to receive a bus command; the mode register couples the interface and the repair logic storage circuit, and is configured to generate a corresponding operation mode command according to the bus command.

[0016] In some embodiments, the interface is coupled to a memory controller, and the memory controller is configured to: obtain the fault degree of the first fault storage unit and the fault degree of the second fault storage unit in the memory device; compare the fault degree of the first fault storage unit with the fault degree of the second fault storage unit; determine a third storage address of the second fault address in a repair logic storage circuit based on the comparison result; and send the bus command containing the third storage address.

[0017] In some embodiments, the memory controller is further configured to: determine a third storage address of the second fault address in the repair logic storage circuit according to the comparison result and in combination with a usage rate of the redundant storage unit.

[0018] In some embodiments, the memory controller is further configured to: determine that the third storage address is the second storage address corresponding to the second storage structure that stores the first fault address based on the fact that the fault degree of the second fault storage unit is higher than the fault degree of the first fault storage unit, and the usage rate of the redundant storage unit is greater than a preset usage rate; determine that the third storage address is the second storage address corresponding to the second storage structure that does not store the first fault address based on the fact that the fault degree of the second fault storage unit is lower than or equal to the fault degree of the first fault storage unit, or the usage rate of the redundant storage unit is less than or equal to the preset usage rate.

[0019] In the disclosed embodiment, the repair logic storage circuit responds to the first operation mode command and writes the second fault address to the second storage structure. Here, since the first storage structure corresponds to the second storage structure one by one and the internal storage data are mapped to each other, when the second fault address is written to the second storage structure storing the first fault address, the mapping between the first fault address and the redundant address will be eliminated, and a new mapping will be formed between the second fault address and the redundant address; when the second fault address is written to the second storage structure not storing the first fault address, a mapping will be formed between the second fault address and the redundant address that does not correspond to the first fault address. In this way, the mapping relationship between the redundant address and the fault address is updated, the accuracy of the fault address is improved, the utilization rate of the redundant address is improved, and the service life of the product is extended. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A schematic diagram of the structure of the memory provided in the embodiment of the present disclosure;

[0021] Figure 2 A schematic diagram of a structural block diagram of a storage device provided in an embodiment of the present disclosure;

[0022] Figure 3 Schematic diagram of storage conditions of different storage locations in a repair logic storage circuit provided by an embodiment of the present disclosure Figure 1 ;

[0023] Figure 4 Schematic diagram of storage conditions of different storage locations in a repair logic storage circuit provided by an embodiment of the present disclosure Figure 2 ;

[0024] Figure 5 Schematic diagram of storage conditions of different storage locations in a repair logic storage circuit provided by an embodiment of the present disclosure Figure 3 ;

[0025] Figure 6 Schematic diagram of storage conditions of different storage locations in a repair logic storage circuit provided by an embodiment of the present disclosure Figure 4 ;

[0026] Figure 7 Schematic diagram of storage conditions of different storage locations in a repair logic storage circuit provided by an embodiment of the present disclosure Figure 5 ;

[0027] Figure 8 A schematic diagram of a structural block diagram of another storage device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0028] The following will be combined with the embodiments of the present disclosure and the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0029] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0030] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0031] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0032] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0033] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0034] In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below, but in addition to these detailed descriptions, the present disclosure may also have other implementations.

[0035] Figure 1 This is a schematic diagram of the structure of the memory provided by the embodiment of the present disclosure. Figure 1 As shown, the memory 100 may be a dual in-line memory module (DIMM). The DIMM may be loaded into the host through a memory slot provided by the host's motherboard, wherein a DIMM may be composed of one or more memory ranks 101, and a memory rank 101 may include a plurality of memory chips (memory particles, chips) 102. Exemplarily, a memory rank 101 includes eight memory chips 102. A memory chip 102 may include a plurality of memory banks, and a memory bank is an array composed of a plurality of storage cells, and the array includes a plurality of storage cell rows (rows), and a plurality of storage cell columns (columns).

[0036] The memory chip 102 in the memory 100 may be damaged when it leaves the factory. Specifically, the storage unit in the memory chip 102 may be damaged. The damaged storage unit cannot write or read data. Moreover, the storage unit may also be damaged during the subsequent use of the memory.

[0037] In some embodiments, the host supports checking the memory 100 and correcting the detected errors, that is, repairing the faults in the memory 100. For example, each time the memory 100 performs a read or write task, an error checking and correction (ECC) method is used to identify faults in the memory 100. Among them, the ECC method is used to identify errors when fewer bits in the memory 100 fail. Errors that can be corrected are called correctable errors (CE), which can also be called correctable faults. However, if the error correction algorithm is exceeded, for example, when there are a large range of multi-bit failures on the memory 100, the error correction will fail, resulting in an uncorrected error (UCE), which can also be called an uncorrectable fault. When UCE is generated, it will cause a serious failure of the computing device, such as a crash, resulting in the loss of data in the memory 100.

[0038] In order to avoid UCE, when the memory 100 fails, a redundant storage unit can be used to replace the failed storage unit, that is, when the host sends a command to the memory 100, the address information carried in the command is detected, and if the address in the command points to the failed storage unit, the redundant storage unit is accessed instead. Here, both the redundant storage unit and the failed storage unit can be located in the memory chip 102.

[0039] In the disclosed embodiment, PPR can be used to repair the memory 100 fault. The current DDR4 and DDR5 protocols use PPR to manage the fault address, and PPR can be subdivided into hardware repair (hard PPR, hPPR) and software repair (softPPR, sPPR). Both hPPR and sPPR send repair instructions and fault addresses to the memory chip 102 through the mode register (Mode Register). Among them, hPPR can permanently write the fault address through the fuse array (Electronic Fuse, EFUSE), so that in hPPR, the redundant address corresponding to the redundant storage unit that forms a mapping relationship with the fault address is not recyclable. The sPPR temporarily stores the fault address in a latch (Latch) or a trigger (DFF), so that in the sPPR, the redundant address corresponding to the redundant storage unit that forms a mapping relationship with the fault address is recyclable. Here, the fault address and the redundant address are both physical addresses associated with a specific word line, not logical addresses.

[0040] Here, PPR technology has some shortcomings, specifically: 1. hPPR cannot modify the fault address stored in EFUSE. It should be noted that the fault address here includes both the fault address written to EFUSE when the memory chip leaves the factory and the fault address written to EUFSE by the user during subsequent use. 2. When using hPPR, when all redundant addresses are mapped to the fault address. Since there is no unused redundant address, the subsequent sPPR will fail.

[0041] However, in the actual use of memory 100, there is indeed a need to modify the fault address permanently written in EFUSE. Exemplarily, when a certain address is judged as a fault address, the fault storage unit pointed to by the fault address cannot read and write data normally. However, the host can use the ECC method to identify the fault address and perform error correction on the fault address. At this time, the fault storage unit pointed to by the fault address can actually work normally. However, since the manufacturer has written the fault address in EFUSE when leaving the factory, the fault address cannot be modified, and subsequent users can no longer reuse the redundant address used to replace the fault address through the sppr technology. In addition, in the subsequent use of memory 100, it may happen that the fault degree of the fault storage unit 2 generated later is more serious than the fault degree of the fault storage unit 1 generated earlier. In the case of a limited number of redundant addresses, compared with the fault storage unit 1, the fault address of the fault storage unit 2 needs to be replaced by a redundant address, but the PPR technology involved in the aforementioned embodiment cannot solve this problem.

[0042] Based on this, an embodiment of the present disclosure provides a storage device.

[0043] An embodiment of the present disclosure provides a storage device, which includes: a storage cell array, including multiple storage cells and multiple redundant storage cells; the multiple redundant storage cells are configured to repair faulty storage cells among the multiple storage cells; a fault address storage circuit, configured to store at least one first fault address corresponding to a first faulty storage cell; a repair logic storage circuit, including multiple first storage structures and multiple second storage structures, the first storage structures correspond to the second storage structures one-to-one and the internal storage data are mapped to each other; the multiple first storage structures store redundant addresses corresponding to the multiple redundant storage cells, and one redundant address corresponds to one first storage structure; the second storage structure stores first fault addresses, and one first fault address corresponds to one second storage structure; the repair logic storage circuit is configured to: receive a first operation mode command, the first operation mode command includes at least one second fault address corresponding to a second faulty storage cell; the second faulty storage cell is different from the first faulty storage cell; and in response to the first operation mode command, write the second fault address to the second storage structure.

[0044] In some embodiments, the memory device may include a memory chip such as Figure 1 1. In some specific embodiments, the memory device may include a random access memory (DRAM), but is not limited thereto. Exemplarily, the memory device may be a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate synchronous dynamic random access memory (LPDDR SDRAM), a graphic double data rate synchronous dynamic random access memory (GDDR SDRAM), etc.

[0045] In the embodiment of the present disclosure, the storage device may also be a storage system including a storage chip, such as Figure 1 The memory 100 shown in FIG. 1 is a dual in-line memory module. In the embodiment of the present disclosure, the memory device may be coupled to a host, receive a bus command sent from the host, and perform corresponding operations in response to the bus command.

[0046] In some embodiments, the storage device may be included in various electronic devices. The electronic device may include a host. Here, the electronic device may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein.

[0047] Figure 2 A schematic diagram of a structural block diagram of a storage device provided by an embodiment of the present disclosure. Figure 2As shown, the memory device 200 includes a memory cell array 201, a fault address storage circuit 202, and a repair logic storage circuit 203. The memory cell array 201 may include a plurality of memory cells 204 at the intersections of a plurality of word lines and a plurality of bit lines. The memory cell array 201 may also include a plurality of redundant memory cells 205 at the intersections of a plurality of redundant word lines and a plurality of redundant bit lines. When a fault occurs in the memory cell 204, that is, there is a faulty memory cell ( Figure 2 When the redundant address corresponding to the redundant storage unit 205 in the storage unit array 201 replaces the faulty address of the faulty storage unit, the faulty storage unit can be repaired.

[0048] It should be noted that the storage cell 204 and the redundant storage cell 205 included in the storage cell array 201 can be structures or units with storage functions and similar structural features obtained according to the same process. The difference between the storage cell 204 and the redundant storage cell 205 is that they are formed at different positions in the storage device 200 and have different initial functional positioning. Specifically, the storage cell 204 is used to store user data, and the redundant storage cell 205 is used to repair the faulty storage cell 204, that is, to replace the faulty storage cell 204 to perform normal data reading or writing.

[0049] The fault address storage circuit 202 is coupled to the storage cell array 201, and the fault address storage circuit 202 is configured to store at least one first fault address corresponding to the first fault storage cell in the storage cell array 201. The first fault storage cell may include one or more fault storage cells, each of which corresponds to a first fault address. In other words, the fault address storage circuit 202 is configured to store a first fault address corresponding to at least one fault storage cell in the first fault storage cell of the one or more fault storage cells. Here, the first fault storage cell may be a fault storage cell identified by the manufacturer when the storage device 200 leaves the factory, or may also be a fault storage cell identified by the memory controller during subsequent use. In one example, the memory controller is coupled to the storage device 200, and the memory controller and the storage device 200 together constitute a storage system.

[0050] In the embodiment of the present disclosure, the fault address storage circuit 202 includes a non-volatile storage device, which may be a one-time programmable memory. In some embodiments, the fault address storage circuit 202 includes a fuse array or an anti-fuse array.

[0051] Here, both the fuse array and the antifuse array are programmable fuse arrays containing fuses. When the fuses in the fuse array and the antifuse array are blown, the resistance value of the fuse will change. At this time, the circuit inside the fuse array and the antifuse array can convert the resistance value of the fuse into a corresponding logic value. In other words, according to the different resistance values ​​of the fuses, the fuse array and the antifuse array will generate different levels, which can be identified and output by an external reading circuit, thereby realizing the programming function.

[0052] In one example, after the storage device 200 leaves the factory, a post-packaging repair technology can be used to repair the fault in the storage device 200, that is, to repair the first faulty storage unit in the storage device 200. Specifically, a hardware repair method can be used to blow the fuse in the fuse array to perform repair by permanently encoding the first faulty address corresponding to the first faulty storage unit into the fuse array. In this way, the first faulty address of the first faulty storage unit stored in the faulty address storage circuit 202 cannot be modified.

[0053] In some embodiments, the first storage structure has a corresponding first storage address and the second storage structure has a corresponding second storage address.

[0054] like Figure 2 As shown, the repair logic storage circuit 203 is coupled to the fault address storage circuit 202, and the repair logic storage circuit 203 includes a first storage structure 206 and a second storage structure 207. The first storage structure 206 has a corresponding first storage address, and the second storage structure 207 has a corresponding second storage address. In other words, the first storage address is the address of the first storage structure 206, and the second storage address is the address of the second storage structure 207.

[0055] It should be noted that the storage structure here can be understood in reference to the storage unit 204 in the aforementioned storage unit array 201, and the storage structure here and the aforementioned storage unit 204 can be the smallest storage modules in different memories respectively. The number of first storage structures 206 can be designed according to the number of redundant addresses, and the number of first storage structures 206 can include multiple. Exemplarily, the number of first storage structures 206 can be greater than or equal to the number of redundant addresses. In some embodiments, the number of second storage structures 207 can be equal to the number of first storage structures 206, so that a one-to-one correspondence between the first storage structure 206 and the second storage structure 207 can be ensured.

[0056] In some embodiments, the repair logic storage circuit is configured to: in response to power-on of the memory device, obtain a first fail address from the fail address storage circuit; and write the first fail address into the second storage structure according to a first preset sequence.

[0057] like Figure 2 As shown, the repair logic storage circuit 203 can obtain the first fault address of the first fault storage unit from the fault address storage circuit 202 in response to the power-on of the memory device 200. Furthermore, the repair logic storage circuit 203 can write the obtained first fault address into the second storage structure according to the first preset order.

[0058] In some embodiments, the first preset order may be a specific arrangement order determined according to a preset mapping algorithm. Specifically, the first preset order may include the writing order of each first fault address and the position of the second storage structure corresponding to the first fault address in the repair logic storage circuit 203. Since the first storage structure corresponds to the second storage structure one by one and the internal storage data are mapped to each other, after the first fault address is written into the second storage structure according to the specific arrangement order, a mapping relationship may be formed between the first fault address and the redundant address corresponding to its storage position.

[0059] In some other embodiments, writing the first fault addresses into the second storage structure 207 according to the first preset order includes: writing the first fault addresses into the second storage structure 207 sequentially.

[0060] In some embodiments, the repair logic storage circuit is configured to: in response to powering on the memory device, write the acquired redundant addresses into the first storage structure in a second preset order.

[0061] In the embodiment of the present disclosure, the repair logic storage circuit 203 can obtain the redundant addresses of all redundant storage units 205 from the initial storage position of the redundant address in response to the power-on of the storage device 200, and write the obtained redundant addresses to the first storage structure according to the second preset order. In some embodiments, the initial storage position of the redundant address can be located inside the repair logic storage circuit 203, for example, the initial storage position can be located in a non-volatile storage structure inside the repair logic storage circuit 203, and the non-volatile storage structure can be a read-only memory (ROM), and the ROM can still retain data when the memory is powered off, but the non-volatile storage structure here is not limited to this. In some other embodiments, the initial storage position of the redundant address can be located outside the repair logic storage circuit 203, for example, the initial storage position can be located in a non-volatile storage structure outside the repair logic storage circuit 203.

[0062] In some embodiments of the present disclosure, the second preset order may be a specific arrangement order determined according to a preset mapping algorithm. For details, reference may be made to the description of the first preset order, which will not be repeated here.

[0063] In some other embodiments of the present disclosure, writing the obtained redundant addresses into the first storage structure 206 according to the second preset order may include: writing the obtained redundant addresses into the first storage structure 206 sequentially.

[0064] In the embodiment of the present disclosure, the relationship between the storage position of the redundant address in the first storage structure 206 and the storage position of the fault address in the second storage structure 207 determines the mapping relationship between the redundant address and the fault address. In other words, the repair logic storage circuit 203 includes multiple first storage structures 206 and multiple second storage structures 207, and the positions of the multiple first storage structures 206 correspond to the positions of the multiple second storage structures 207 one by one. The first storage address is the address of the first storage structure 206, and the redundant address of a redundant storage unit is stored in one first storage structure 206. The second storage address is the address of the second storage structure 207, and the fault address of a fault storage unit is stored in one second storage structure 207. Since the positions of the multiple first storage structures 206 correspond to the positions of the multiple second storage structures 207 one by one, a mapping relationship between the redundant address and the fault address can be formed.

[0065] In some embodiments, the number of redundant addresses is greater than the number of first faulty addresses, that is, there is still some space in the redundant storage units corresponding to the redundant addresses that can be used to repair faulty storage units other than the first faulty storage units.

[0066] Figure 3 Schematic diagram of storage conditions of different storage locations in a repair logic storage circuit provided by an embodiment of the present disclosure Figure 1 For example, Figure 3 As shown, the repair logic storage circuit 203 includes a plurality of first storage structures 206 and a plurality of second storage structures 207. The repair logic storage circuit 203 may sequentially write the acquired multiple redundant addresses into the sequentially arranged first storage structure 206-1, the first storage structure 206-2, the first storage structure 206-3, the first storage structure 206-4, the first storage structure 206-5, and the first storage structure 206-6... The repair logic storage circuit 203 may also acquire the first fault addresses of the plurality of first fault storage units from the fault address storage circuit 202, and sequentially write the plurality of first fault addresses into the sequentially arranged second storage structure 207-1, the second storage structure 207-2, and the second storage structure 207-3...

[0067] It can be understood that the first fault address stored in the second storage structure 207-1 is mapped to the redundant address in the first storage structure 206-1, the first fault address stored in the second storage structure 207-2 is mapped to the redundant address in the first storage structure 206-2, the first fault address stored in the second storage structure 207-3 is mapped to the redundant address in the first storage structure 206-3, and other mapping relationships can be deduced by analogy.

[0068] In some implementations, the number of redundant addresses is equal to the number of first fault addresses. That is, the redundant storage units corresponding to the redundant addresses have all been used to repair the faults of the first fault storage units corresponding to the first fault addresses, and there are no redundant redundant storage units that can be used to repair faulty storage units other than the first faulty storage units.

[0069] Figure 4 Schematic diagram of storage conditions of different storage locations in a repair logic storage circuit provided by an embodiment of the present disclosure Figure 2 .like Figure 4 As shown, in other embodiments, the repair logic storage circuit 203 can obtain multiple first fault addresses corresponding to the first fault storage unit from the fault address storage circuit 202, and the number of first fault addresses obtained from the fault address storage circuit 202 can be equal to the number of second storage structures 207 in the repair logic storage circuit 203. At this time, all redundant addresses are mapped to the first fault addresses.

[0070] In the embodiment of the present disclosure, the repair logic storage circuit 203 may include a volatile memory.

[0071] In the embodiment of the present disclosure, the repair logic storage circuit 203 may be configured to receive a first operation mode command. The first operation mode command includes at least one second fault address corresponding to the second fault storage unit. Here, the second fault storage unit is different from the first fault storage unit, and the second fault storage unit may be a storage unit that fails in the subsequent use of the storage device, and the failed storage unit and its corresponding second fault address may be obtained by a corresponding test method.

[0072] In some embodiments, the second fault storage unit may include one or more fault storage units, each of which corresponds to a second fault address. In other words, the first operation mode command may include one or more second fault addresses.

[0073] In some embodiments, the first operating mode command also includes a third storage address corresponding to the second fault address, and each third storage address is the same as a second storage address; the repair logic storage circuit is specifically configured to: in response to the first operating mode command, write the second fault address into the corresponding second storage structure according to the third storage address.

[0074] Figure 5 Schematic diagram of storage conditions of different storage locations in a repair logic storage circuit provided by an embodiment of the present disclosure Figure 3 In the disclosed embodiment, the first operation mode command further includes a third storage address, which is a storage address corresponding to the second fault address. Each third storage address is the same as a second storage address. In other words, the third storage address belongs to the second storage address, that is, each third storage address is equivalent to a second storage address among the plurality of second storage addresses. Figure 3 and Figure 5 , the repair logic storage circuit 203 writes the second fault address into the second storage structure 207 according to the third storage address in response to the first operation mode command.

[0075] In some embodiments, at least one third storage address corresponds to a second storage structure storing a first fault address; and the repair logic storage circuit is configured to: in response to a first operation mode command, overwrite the first fault address stored in the second storage structure with a second fault address corresponding to the at least one third storage address.

[0076] The following description will be made by taking the case where the first operation mode command includes two second fault addresses as an example.

[0077] Combination Figure 3 and Figure 5 As shown, the third storage address corresponding to the first second fault address received by the repair logic storage circuit 203 corresponds to the second storage structure 207-2 storing the first fault address. In this way, the repair logic storage circuit 203 stores the first second fault address in the second storage structure 207-2. At this time, a mapping is formed between the second fault address stored in the second storage structure 207-2 and the redundant address stored in the first storage structure 206-2. In other words, the first fault address originally stored in the second storage structure 207-2 is overwritten by a second fault address newly received by the repair logic storage circuit 203, so that the mapping between the first fault address and the redundant address stored in the first storage structure 206-2 is eliminated. In other words, the first fault address originally stored in the second storage structure 207-2 is modified to a non-faulty address, and the storage unit corresponding to the non-faulty address is a non-faulty storage unit, and the non-faulty storage unit can be used normally.

[0078] The third storage address corresponding to the second second fault address received by the repair logic storage circuit 203 corresponds to the second storage structure 207-3 storing the first fault address. In this way, the repair logic storage circuit 203 stores the second second fault address in the second storage structure 207-3. At this time, a mapping is formed between the second fault address stored in the second storage structure 207-3 and the redundant address stored in the first storage structure 206-3. In other words, the first fault address originally stored in the second storage structure 207-3 is overwritten by another second fault address newly received by the repair logic storage circuit 203. In this way, the mapping between the first fault address and the redundant address stored in the first storage structure 206-3 is eliminated. In other words, the first fault address originally stored in the second storage structure 207-3 is modified to a non-faulty address, and the storage unit corresponding to the non-faulty address is a non-faulty storage unit, and the non-faulty storage unit can be used normally. Based on this, the second fault addresses corresponding to all the third storage addresses overwrite the first fault address stored in the second storage structure. In other words, the mapping relationship between part of the first failed addresses and the redundant addresses is replaced by the mapping relationship between the second failed addresses and the redundant addresses.

[0079] Figure 6 Schematic diagram of storage conditions of different storage locations in a repair logic storage circuit provided by an embodiment of the present disclosure Figure 4 . Combined Figure 3 and Figure 6 In response to the first operation mode command, the repair logic storage circuit 203 writes the second fault address into the second storage structure 207 according to the third storage address. Hereinafter, the first operation mode command including N (eg, N is greater than 2) second fault addresses is used as an example for description.

[0080] Combination Figure 3 and Figure 6 As shown, the third storage address corresponding to the first second fault address received by the repair logic storage circuit 203 corresponds to the second storage structure 207-2 storing the first fault address. In this way, the repair logic storage circuit 203 stores the first second fault address in the second storage structure 207-2. At this time, a mapping is formed between the second fault address stored in the second storage structure 207-2 and the redundant address stored in the first storage structure 206-2. In other words, the first fault address originally stored in the second storage structure 207-2 is overwritten by a second fault address newly received by the repair logic storage circuit 203, so that the mapping between the first fault address and the redundant address stored in the first storage structure 206-2 is eliminated.

[0081] The third storage address corresponding to the second second fault address received by the repair logic storage circuit 203 corresponds to the second storage structure 207-3 storing the first fault address. In this way, the repair logic storage circuit 203 stores the second second fault address in the second storage structure 207-3, and at this time, a mapping is formed between the second fault address stored in the second storage structure 207-3 and the redundant address stored in the first storage structure 206-3. In other words, the first fault address originally stored in the second storage structure 207-3 is overwritten by another second fault address newly received by the repair logic storage circuit 203, and in this way, the mapping between the first fault address and the redundant address stored in the first storage structure 206-3 is eliminated.

[0082] The third storage addresses corresponding to the third to Nth (exemplarily, N is equal to 4) second fault addresses received by the repair logic storage circuit 203 correspond to the second storage structures 207-4 to 207-N+1 that do not store the first fault addresses. The repair logic storage circuit 203 stores the received third to Nth second fault addresses in the second storage structures 207-4 to 207-N+1 in sequence. At this time, the second fault addresses stored in the second storage structures 207-4 to 207-N+1 are respectively mapped to the redundant addresses stored in the first storage structures 206-4 to 206-5.

[0083] Understandably, Figure 6 In the embodiment, some of the third storage addresses among the plurality of third storage addresses correspond to the second storage structure storing the first fault address, and some of the third storage addresses among the plurality of third storage addresses correspond to the second storage structure not storing the first fault address. Based on this, the second fault addresses corresponding to some of the third storage addresses cover some of the first fault addresses stored in the second storage structure. In other words, the mapping relationship between some of the second fault addresses and the redundant addresses replaces the mapping relationship between some of the first fault addresses and the redundant addresses, and a newly added mapping is formed between some of the second fault addresses and the redundant addresses.

[0084] In some embodiments, at least one third storage address corresponds to a second storage structure that does not store the first fail address; and the repair logic storage circuit is configured to directly write the second fail address into the second storage structure in response to the first operation mode command.

[0085] Figure 7 Schematic diagram of storage conditions of different storage locations in a repair logic storage circuit provided by an embodiment of the present disclosure Figure 5 . Combined Figure 3 and Figure 7In response to the first operation mode command, the repair logic storage circuit 203 writes the second fault address into the second storage structure 207 according to the third storage address. The following is an example in which the first operation mode command includes two second fault addresses.

[0086] Combination Figure 3 and Figure 7 , the third storage addresses corresponding to the two second fault addresses received by the repair logic storage circuit 203 correspond to the second storage structure 207-5 and the second storage structure 207-6 that do not store the first fault address. The repair logic storage circuit 203 stores the two second fault addresses in the second storage structure 207-5 and the second storage structure 207-6 respectively. At this time, a mapping is formed between the second fault address stored in the second storage structure 207-5 and the redundant address stored in the first storage structure 206-5, and a mapping is formed between the second fault address stored in the second storage structure 207-6 and the redundant address stored in the first storage structure 206-6. It can be understood that Figure 7 In the embodiment, all third storage addresses correspond to the second storage structure that does not store the first fault address. Based on this, a newly added mapping is formed between the second fault address and the redundant address.

[0087] It is understandable that in the embodiment of the present disclosure, the first operation mode command may further include a write flag and an enable signal, wherein the write flag is used to instruct the repair logic storage circuit 203 to write the second fault address to the second storage structure 207, and the enable signal is used to instruct the repair logic storage circuit 203 to start.

[0088] In the disclosed embodiment, the repair logic storage circuit 203 can write the second fault address to the second storage structure 207 in response to the first operation mode command, thereby solving the problem that the first fault address cannot be modified due to the permanent writing of the first fault address by the fuse array. The mapping relationship between the redundant address and the fault address is updated, and the utilization rate of the redundant storage unit 205 is improved.

[0089] It should be noted that the repair logic storage circuit 203 may be a volatile memory, and its data will be lost when the power is turned off. Therefore, after the mapping relationship between the redundant address and the fault address is updated, in order to prevent data loss, all current fault addresses can be saved to the fault address storage circuit 202 according to a preset rule before power is turned off, and when the storage device is powered on next time, all previously saved fault addresses are obtained from the fault address storage circuit 202.

[0090] In some embodiments, the repair logic storage circuit is further configured to: receive a second operating mode command, the second operating mode command including at least one fourth storage address; each fourth storage address is the same as a second storage address; and in response to the second operating mode command, read and output a fault address stored in the second storage structure corresponding to the fourth storage address.

[0091] In the disclosed embodiment, the repair logic storage circuit 203 may receive a second operation mode command. The second operation mode command includes one or more fourth storage addresses. Here, the fourth storage address may be an address of a storage structure currently used to store a fault address, and the fourth storage address belongs to the second storage address, that is, each fourth storage address is equivalent to one second storage address in the plurality of second storage addresses.

[0092] The repair logic storage circuit 203 may read and output the fault address stored in the second storage structure corresponding to the fourth storage address in response to the second operation mode command. Exemplarily, the repair logic storage circuit 203 may read and output the first fault address stored in the second storage structure 207 in response to the second operation mode command. Alternatively, the repair logic storage circuit 203 may read and output the second fault address stored in the second storage structure 207 in response to the second operation mode command.

[0093] It is understandable that, in the embodiment of the present disclosure, the second operation mode command may further include a read flag and an enable signal, wherein the read flag is used to instruct the repair logic storage circuit 203 to read and output the fault address stored in the second storage structure 207 corresponding to the fourth storage address, and the enable signal is used to instruct the repair logic storage circuit 203 to start.

[0094] It should be noted that, in the embodiment of the present disclosure, the fault address storage circuit 202 (e.g., fuse array) does not have a user-oriented interface, while the repair logic storage circuit 203 has an external interface oriented to the user. Therefore, using the repair logic storage circuit 203 to obtain the fault address in the fault address storage circuit 202 can enable the user to read the fault address stored in the fault address storage circuit 202.

[0095] It can be understood that in the embodiments of the present disclosure, the fault addresses corresponding to all faulty storage units can be simply and conveniently obtained when needed in the above manner.

[0096] In some embodiments, the repair logic storage circuit is further configured to: receive a third operating mode command, the third operating mode command including at least an access address of a storage unit to be accessed; and in response to the third operating mode command, match the access address with a fault address within the second storage structure; based on a successful match, output a first signal, the first signal being used to indicate that a redundant address corresponding to the fault address that has been successfully matched has been accessed; based on a failed match, output a second signal, the second signal being used to indicate that the access address has been accessed.

[0097] In the embodiment of the present disclosure, the repair logic storage circuit 203 receives a third operation mode command. The third operation mode command includes an access address of a storage unit to be accessed. Here, access includes reading and writing. The repair logic storage circuit 203 may match the received access address with the fault address stored in the second storage structure 207 in response to the third operation mode command. When the access address successfully matches the fault address, the repair logic storage circuit 203 outputs a first signal. In other words, when the second storage structure 207 of the repair logic storage circuit 203 stores a fault address that is the same as the access address, the repair logic storage circuit 203 outputs a first signal.

[0098] For example, Figure 7 As shown, when the access address successfully matches the first fault address stored in the second storage structure 207 or the second fault address stored in the second storage structure 207, the repair logic storage circuit 203 outputs a first signal. At this time, the first signal is used to indicate access to the redundant address mapped by the first fault address or the second fault address that successfully matches. Specifically, in the case of a successful match, the first signal can be used to indicate writing data into the redundant storage unit 205 pointed to by the redundant address mapped by the first fault address or the second fault address that successfully matches, or the first signal can be used to indicate reading data from the redundant storage unit 205 pointed to by the redundant address mapped by the first fault address or the second fault address that successfully matches.

[0099] In the case where the access address fails to match the fault address, the repair logic storage circuit 203 outputs a second signal. In other words, when the second storage structure 207 of the repair logic storage circuit 203 does not store the same fault address as the access address, the repair logic storage circuit 203 outputs a second signal. The second signal is used to indicate accessing the access address. Here, in the case of a match failure, the access address is the address corresponding to the storage unit 204. At this time, the second signal can be used to indicate writing data to the storage unit 204, or the second signal can be used to indicate reading data from the storage unit 204.

[0100] It is understandable that in the embodiment of the present disclosure, the third operation mode command may further include a match flag and an enable signal, wherein the match flag is used to instruct the repair logic storage circuit 203 to match the access address with the stored fault address, and the enable signal is used to instruct the repair logic storage circuit 203 to start.

[0101] In the disclosed embodiment, there is no limitation on the order and number of times of sending the first operation mode command, the second operation mode command and the third operation mode command to the repair logic storage circuit 203. The user can adaptively adjust the order and number of times of sending the above three operation mode commands according to the needs.

[0102] From the above embodiments, it can be seen that the repair logic storage circuit 203 needs to have both storage and matching functions. In some embodiments, the repair logic storage circuit 203 includes a content-addressable memory (CAM).

[0103] Content-addressable memory is a memory that has both storage and comparison functions. Content-addressable memory contains an embedded comparison logic in each storage unit. The data written into the content-addressable memory will be compared with the data stored inside it, and different information will be output based on the comparison result.

[0104] In the embodiment of the present disclosure, the repair logic storage circuit 203 is not limited to the content-addressable memory. Any memory or circuit that can realize the function of "searching for the corresponding redundant address according to the input access address and accessing the redundant address" falls within the protection scope of the embodiment of the present disclosure.

[0105] Figure 8 A schematic diagram of a structural block diagram of another storage device provided in an embodiment of the present disclosure. Figure 8 As shown, in the embodiment of the present disclosure, the memory device 800 includes a memory cell array 201, a fault address storage circuit 202, and a repair logic storage circuit 203. In some embodiments, the memory device 800 further includes a mode register 801 and an interface 802; the interface 802 is configured to receive a bus command; the mode register 801 is coupled to the interface 802 and the repair logic storage circuit 203, and is configured to: generate a corresponding operation mode command according to the bus command.

[0106] Here, the description of the storage cell array 201, the fault address storage circuit 202 and the repair logic storage circuit 203 can be referred to. Figure 2, which will not be described in detail here. Interface 802 can be an I / O port. Mode register 801 is coupled to interface 802, and mode register 801 is coupled to repair logic storage circuit 203. Interface 802 is used to receive bus commands from bus 803 and transmit them to mode register 801, and interface 802 is also used to output data in mode register 801 through bus 803. Mode register 801 can output corresponding first operation mode command, second operation mode command or third operation mode command according to the received bus command. In other words, the bus command sent by bus 803 can be parsed by mode register 801 into first operation mode command, second operation mode command or third operation mode command. And the first operation mode command, the second operation mode command and the third operation mode command can be sent to repair logic storage circuit 203.

[0107] In some embodiments, the interface 802 is coupled to a memory controller 804 .

[0108] In the embodiment of the present disclosure, the bus command may be output by the memory controller 804 and transmitted to the interface 802 via the bus 803. In some embodiments, the memory controller 804 may be integrated into an external device coupled to the memory device 800. In other embodiments, the memory controller 804 may be integrated into a memory system, which is used to control the memory chip.

[0109] In the embodiment of the present disclosure, bus 803 may include at least one, specifically, the bus may include a clock bus for transmitting a clock signal CK, a command / address bus for transmitting commands and / or addresses CA, and a data bus for transmitting data DQ.

[0110] In some embodiments, the memory controller is configured to: obtain the failure degree of a first faulty storage unit and the failure degree of a second faulty storage unit in the memory device; compare the failure degree of the first faulty storage unit with the failure degree of the second faulty storage unit; determine a third storage address of the second faulty address in the repair logic storage circuit based on the comparison result; and send a bus command containing the third storage address.

[0111] In the embodiment of the present disclosure, the third storage address can be determined by comparing the fault degree of the first fault storage unit with the fault degree of the second fault storage unit. Figure 7 As shown, when the failure degree of the first failed storage unit is higher than the failure degree of the second failed storage unit, the memory controller determines that the third storage address corresponds to the second storage structure 207 that does not store the first failed address. Figure 5As shown, when the failure degree of the first failed storage unit is lower than the failure degree of the second failed storage unit, the memory controller determines that the third storage address corresponds to the second storage structure storing the first failed address.

[0112] refer to Figure 8 After determining the third storage address, the memory controller 804 may send a bus command including the third storage address to the interface 802 via the bus 803 .

[0113] In some embodiments, the memory controller is further configured to: determine a third storage address of the second fault address in the repair logic storage circuit according to the comparison result and in combination with the usage rate of the redundant storage unit.

[0114] In the disclosed embodiment, the third storage address of the second fault address in the repair logic storage circuit can be determined based on the comparison result of the fault degree of the first fault storage unit and the fault degree of the second fault storage unit and combined with the usage rate of the redundant storage unit.

[0115] In some embodiments, the memory controller is further configured to: determine that the third storage address is the second storage address corresponding to the second storage structure storing the first fault address based on the fact that the fault degree of the second fault storage unit is higher than the fault degree of the first fault storage unit, and the usage rate of the redundant storage unit is higher than a preset usage rate; determine that the third storage address is the second storage address corresponding to the second storage structure not storing the first fault address based on the fact that the fault degree of the second fault storage unit is lower than or equal to the fault degree of the first fault storage unit, or the usage rate of the redundant storage unit is less than or equal to the preset usage rate.

[0116] In the embodiment of the present disclosure, the preset usage rate may be close to or equal to 100%. The preset usage rate may also be adjusted according to actual conditions. Specifically, when the failure degree of the first fault storage unit is lower than the failure degree of the second fault storage unit, and the usage rate of the redundant storage unit is greater than or equal to the preset usage rate, the third storage address is determined to be the second storage address corresponding to the second storage structure storing the first fault address. Here, reference may be made to Figure 4 ,like Figure 4 As shown, the utilization rate of the redundant storage unit is equal to 100%. At this time, if the failure degree of the first fault storage unit is lower than the failure degree of the second fault storage unit, the second fault address corresponding to the third storage address covers the first fault address stored in the second storage structure. In other words, the mapping relationship between at least part of the first fault address and the redundant address corresponding to its storage position is eliminated, and the mapping relationship between the second fault address and the redundant address is established.

[0117] When the failure degree of the first faulty storage unit is lower than the failure degree of the second faulty storage unit, and the usage rate of the redundant storage unit is lower than the preset usage rate, the third storage address is determined to be the second storage address corresponding to the second storage structure that does not store the first faulty address. Figure 7 As shown, when the usage rate of the redundant storage unit is less than the preset usage rate and the failure degree of the first fault storage unit is lower than the failure degree of the second fault storage unit, the third storage address is determined to be the second storage address corresponding to the second storage structure that does not store the first fault address, and a new mapping is formed between the second fault address and the redundant address.

[0118] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0119] The above description is only a preferred embodiment of the present disclosure, and does not limit the patent scope of the present disclosure. All equivalent structural changes made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. A storage device, characterized in that: include: A storage cell array, comprising a plurality of storage cells and a plurality of redundant storage cells; The plurality of redundant storage cells are configured to repair a failed storage cell among the plurality of storage cells; a fault address storage circuit configured to store at least one first fault address corresponding to the first fault storage unit; A repair logic storage circuit includes a plurality of first storage structures and a plurality of second storage structures, wherein the first storage structures correspond to the second storage structures one by one and internal storage data are mapped to each other; the plurality of first storage structures store redundant addresses corresponding to the plurality of redundant storage units, and one of the redundant addresses corresponds to one of the first storage structures; The second storage structure stores the first fault address, and one first fault address corresponds to one second storage structure; The repair logic storage circuit is configured as follows: receiving a first operation mode command, wherein the first operation mode command includes at least one second fault address corresponding to a second fault storage unit; the second fault storage unit is different from the first fault storage unit; and In response to the first operating mode command, the second fail address is written to the second storage structure.

2. The memory device according to claim 1, wherein: The first storage structure has a corresponding first storage address, and the second storage structure has a corresponding second storage address; the first operation mode command also includes a third storage address corresponding to the second fault address, and each of the third storage addresses is the same as one of the second storage addresses; The repair logic storage circuit is specifically configured as follows: In response to the first operation mode command, the second fail address is written into the corresponding second storage structure according to the third storage address.

3. The memory device according to claim 2, wherein: At least one of the third storage addresses corresponds to the second storage structure storing the first fault address; The repair logic storage circuit is configured as follows: In response to the first operation mode command, the first fail address stored in the second storage structure is overwritten with the second fail address corresponding to at least one of the third storage addresses.

4. The memory device according to claim 2, wherein: At least one of the third storage addresses corresponds to a second storage structure that does not store the first fault address; The repair logic storage circuit is configured as follows: In response to the first operating mode command, the second fail address is directly written into the second storage structure.

5. The memory device according to claim 1, wherein: The repair logic storage circuit is configured as: In response to powering on the memory device, obtaining the first fault address from the fault address storage circuit; and writing the first fault address into the second storage structure according to a first preset sequence; In response to the memory device being powered on, the acquired redundant addresses are written into the first storage structure according to a second preset sequence.

6. The memory device according to claim 1, wherein: The repair logic storage circuit is further configured as: receiving a second operation mode command, wherein the second operation mode command includes at least one fourth storage address; each of the fourth storage addresses is the same as one of the second storage addresses; In response to the second operation mode command, a fail address stored in the second storage structure corresponding to the fourth storage address is read and output.

7. The memory device according to claim 1, wherein: The repair logic storage circuit is further configured as: receiving a third operation mode command, the third operation mode command including at least an access address of a storage unit to be accessed; and In response to the third operation mode command, the access address is matched with the fault address in the second storage structure; based on a successful match, a first signal is output, and the first signal is used to indicate access to the redundant address corresponding to the fault address that has successfully matched; based on a failed match, a second signal is output, and the second signal is used to indicate access to the access address.

8. The memory device according to any one of claims 1 to 7, characterized in that: The repair logic storage circuit includes a content addressable memory.

9. The memory device according to any one of claims 1 to 7, characterized in that: The fail address storage circuit includes a fuse array or an anti-fuse array.

10. The memory device according to any one of claims 1 to 7, characterized in that: The memory device also includes a mode register and an interface; The interface is configured to receive a bus command; The mode register is coupled to the interface and the repair logic storage circuit, and is configured to generate a corresponding operation mode command according to the bus command.

11. The memory device according to claim 10, wherein: The interface is coupled to a memory controller, and the memory controller is configured to: Acquire the failure degree of the first failure storage unit and the failure degree of the second failure storage unit in the storage device; comparing the degree of failure of the first failure storage unit with the degree of failure of the second failure storage unit; Determine, according to the comparison result, a third storage address of the second fault address in the repair logic storage circuit; The bus command including the third storage address is sent.

12. The memory device according to claim 11, wherein: The memory controller is further configured to: According to the comparison result and in combination with the usage rate of the redundant storage unit, a third storage address of the second fault address in the repair logic storage circuit is determined.

13. The memory device according to claim 12, wherein: The memory controller is further configured to: According to the fault degree of the second fault storage unit being higher than the fault degree of the first fault storage unit, and the usage rate of the redundant storage unit being higher than a preset usage rate, determining that the third storage address is the second storage address corresponding to the second storage structure storing the first fault address; According to the fact that the fault degree of the second fault storage unit is lower than or equal to the fault degree of the first fault storage unit, or the utilization rate of the redundant storage unit is lower than or equal to the preset utilization rate, the third storage address is determined to be the second storage address corresponding to the second storage structure that does not store the first fault address.

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