Memory operation method, memory and memory system

Abstract

The invention provides a memory operation method, a memory and a memory system, and relates to the technical field of memories. The method includes applying a bias voltage to a bottom selection line of a second memory block including a memory block adjacent to a first memory block in a first time period to turn on a bottom selection tube of the second memory block, and then performing a first erase operation in a second time period after the first time period, comprising the following steps: providing an erasing working voltage to a source line of a first storage block, and setting a bottom selection line of a second storage block to be in a floating state, so that the voltage division influence of parasitic capacitance of a common source array wall is weakened when a word line of the second storage block is coupled and increased along with channel voltage; therefore, the voltage closer to the voltage before boosting can be recovered in the discharge stage, the voltage difference between the word line and the channel of the second memory block after multiple erasing cycles is reduced, and the loss of the reading window margin or the voltage distribution interval sum of the memory in the erasing process is reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of memory technology, and in particular to a memory operation method, a memory, and a storage system. Background Art

[0002] Flash memory is a low-cost, high-density, non-volatile solid-state storage medium that can be electrically erased and reprogrammed. Flash memory includes NOR flash memory and NAND flash memory. Various operations can be performed by flash memory, such as reading, programming (writing), and erasing to change the threshold voltage of each memory cell to a desired level. For NAND flash memory, an erase operation can be performed at the block level, a program operation can be performed at the page level, and a read operation can be performed at the page level.

[0003] The above information disclosed in this Background section is only for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not constitute the prior art that is already known to one of ordinary skill in the art. Summary of the invention

[0004] The purpose of the present disclosure is to provide a memory operation method, a memory and a storage system.

[0005] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by the practice of the present disclosure.

[0006] According to one aspect of the present disclosure, a memory operation method is provided, wherein the memory comprises a plurality of memory blocks, wherein the memory blocks comprise bottom selection tubes, wherein the bottom selection tubes are coupled to bottom selection lines, wherein the plurality of memory blocks comprise a first memory block and a second memory block, wherein the method comprises: applying a bias voltage to the bottom selection line of the second memory block in a first time period to turn on the bottom selection tube of the second memory block; performing a first erasing operation in a second time period, wherein the second time period is after the first time period, wherein performing the first erasing operation comprises: providing an erasing operating voltage to a source line of the first memory block; and setting the bottom selection line of the second memory block to a floating state.

[0007] According to an embodiment of the present disclosure, performing the first erasing operation further includes: applying an erasing control voltage to a word line of the first storage block, the erasing operating voltage being greater than the erasing control voltage.

[0008] According to an embodiment of the present disclosure, the method further includes: applying a first voltage to the source line in a third time period, the third time period is after the second time period, and the first voltage is less than the erase operating voltage.

[0009] According to one embodiment of the present disclosure, setting the bottom selection line of the second storage block to a floating state includes: setting the bottom selection line of the second storage block to a floating state so that the voltage of the bottom selection line of the second storage block rises from the bias voltage to a second voltage along with the source line, and the second voltage is not greater than the sum of the erase operating voltage and the bias voltage.

[0010] According to one embodiment of the present disclosure, the method also includes: maintaining the bottom selection line of the second storage block in a floating state during a third time period so that the voltage of the bottom selection line of the second storage block drops from the second voltage to the bias voltage to continue to keep the bottom selection tube of the second storage block turned on, and the third time period is after the second time period.

[0011] According to an embodiment of the present disclosure, the sum of the erase operating voltage and the bias voltage is less than a preset voltage threshold.

[0012] According to an embodiment of the present disclosure, the first erase operation is performed, and the method further includes: setting the word line of the second storage block to a floating state; the method further includes: maintaining the word line of the second storage block in a floating state during a third time period, and the third time period is after the second time period.

[0013] According to an embodiment of the present disclosure, the second storage block includes a third storage block, and the third storage block is adjacent to the first storage block.

[0014] According to one embodiment of the present disclosure, the method also includes: applying the bias voltage to the bottom selection line of the second storage block in a fourth time period, and the fourth time period is after the third time period; performing a second erase operation in a fifth time period, and the fifth time period is after the fourth time period, wherein performing the second erase operation includes: providing the erase operating voltage to the source line of the first storage block; and setting the bottom selection line of the second storage block to a floating state.

[0015] According to an embodiment of the present disclosure, the bias voltage ranges from 1V to 7V.

[0016] According to an embodiment of the present disclosure, the memory includes a plurality of planes, the plurality of planes include a first plane, the first plane is a plane selected from the plurality of planes, and the plurality of storage blocks are on the first plane.

[0017] According to another aspect of the present disclosure, a memory is provided, comprising: a memory cell array, the memory cell array comprising a plurality of memory blocks, the memory blocks comprising a bottom selection tube, the bottom selection tube being coupled to a bottom selection line, the plurality of memory blocks comprising a first memory block and a second memory block; a peripheral circuit, the peripheral circuit being coupled to the memory cell array, and being used for: applying a bias voltage to the bottom selection line of the second memory block in a first time period to turn on the bottom selection tube of the second memory block; performing a first erasing operation in a second time period, the second time period being after the first time period, wherein performing the first erasing operation comprises: providing an erasing operating voltage to a source line of the first memory block; and setting the bottom selection line of the second memory block to a floating state.

[0018] According to one embodiment of the present disclosure, the peripheral circuit includes a control circuit, a voltage generator, a bottom selection line driver and a source line driver, wherein: the voltage generator is used to generate the bias voltage; the control circuit is used to control the bottom selection line driver to apply the bias voltage to the bottom selection line of the second storage block within the first time period to turn on the bottom selection tube of the second storage block; the voltage generator is also used to generate the erase working voltage; the control circuit is also used to control the source line driver to apply the erase working voltage to the source line of the first storage block within the second time period; the control circuit is also used to control the bottom selection line driver to set the bottom selection line of the second storage block to a floating state within the second time period.

[0019] According to one embodiment of the present disclosure, the voltage generator is also used to generate an erase control voltage, and the erase operating voltage is greater than the erase control voltage; the peripheral circuit also includes a word line driver; the control circuit is also used to control the word line driver to apply the erase control voltage to the word line of the first storage block within the second time period.

[0020] According to one embodiment of the present disclosure, the voltage generator is also used to generate a first voltage, which is less than the erase operating voltage; the control circuit is also used to control the source line driver to apply the first voltage to the source line of the first storage block within a third time period, and the third time period is after the second time period.

[0021] According to one embodiment of the present disclosure, the control circuit is also used to control the bottom selection line driver to set the bottom selection line of the second storage block to a floating state during the second time period, so that the voltage of the bottom selection line of the second storage block rises from the bias voltage to a second voltage along with the source line, and the second voltage is not greater than the sum of the erase operating voltage and the bias voltage.

[0022] According to one embodiment of the present disclosure, the control circuit is also used to control the bottom selection line driver to keep the bottom selection line of the second storage block in a floating state within a third time period, so that the voltage of the bottom selection line of the second storage block drops from the second voltage to the bias voltage to continue to keep the bottom selection tube of the second storage block turned on, and the third time period is after the second time period.

[0023] According to an embodiment of the present disclosure, the sum of the erase operating voltage and the bias voltage is less than a preset voltage threshold.

[0024] According to one embodiment of the present disclosure, the control circuit is also used to control the word line driver to set the word line of the second storage block to a floating state during the second time period; the control circuit is also used to control the word line driver to keep the word line of the second storage block in a floating state during a third time period, and the third time period is after the second time period.

[0025] According to an embodiment of the present disclosure, the second storage block includes a third storage block, and the third storage block is adjacent to the first storage block.

[0026] According to one embodiment of the present disclosure, the peripheral circuit is also used to: apply the bias voltage to the bottom selection line of the second storage block in a fourth time period, and the fourth time period is after the third time period; perform a second erase operation in a fifth time period, and the fifth time period is after the fourth time period, wherein performing the second erase operation includes: providing the erase operating voltage to the source line of the first storage block; setting the bottom selection line of the second storage block to a floating state.

[0027] According to an embodiment of the present disclosure, the bias voltage ranges from 1V to 7V.

[0028] According to an embodiment of the present disclosure, the memory cell array includes a plurality of planes, the plurality of planes include a first plane, the first plane is a plane selected from the plurality of planes, and the plurality of memory blocks are on the first plane.

[0029] According to another aspect of the present disclosure, a storage system is provided, comprising a memory and a controller coupled to the memory, wherein: the memory comprises a storage cell array and a peripheral circuit, the storage cell array comprises a plurality of storage blocks, the storage block comprises a bottom selection tube, the bottom selection tube is coupled to a bottom selection line, the plurality of storage blocks comprises a first storage block and a second storage block, and the peripheral circuit is coupled to the storage cell array; the controller is used to control the peripheral circuit to execute any one of the above methods.

[0030] It is to be understood that the foregoing general description and the following detailed description are exemplary only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other objects, features and advantages of the present disclosure will become more apparent by describing in detail example embodiments thereof with reference to the attached drawings.

[0032] Figure 1 A schematic diagram of the structure of a non-volatile memory to which the present disclosure can be applied is shown.

[0033] Figure 2 A schematic diagram of a NAND FLASH memory cell array to which the present disclosure can be applied is shown.

[0034] Figure 3 A schematic diagram of a memory cell array including a plurality of memory blocks to which the present disclosure may be applied is shown.

[0035] Figure 4 is based on Figure 3 FIG. 1 is a diagram showing a first erase pulse waveform in the related art.

[0036] Figure 5 is based on Figure 4 and Figure 3 FIG. 1 is a second erase pulse waveform diagram in the related art.

[0037] Figure 6 The figure is a flow chart showing a memory operation method according to an exemplary embodiment.

[0038] Figure 7 Shows Figure 6 FIG. 5 is a schematic diagram of the processing process of step S604 in one embodiment.

[0039] Figure 8 according to Figure 6 FIG. 1 is a schematic diagram showing a process of applying voltage to a selected memory block during the erasing phase.

[0040] Fig. 9 according to Figure 6 FIG. 1 is a schematic diagram showing a process of applying voltage to unselected memory blocks during the erasing phase.

[0041] Fig.10 according to Figure 6 The figure shows a schematic diagram of the operation process for the word lines of unselected memory blocks in the erasing stage.

[0042] Fig.11 is based on Figure 6 A flowchart of another memory data processing method is shown.

[0043] Fig.12is based on Figures 6 to 11 An erase pulse waveform is shown.

[0044] Fig.13 is based on Figures 6 to 11 A structural block diagram of a memory is shown.

[0045] Fig.14 is based on Figures 6 to 11 A schematic structural diagram of a memory system is shown. DETAILED DESCRIPTION

[0046] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the disclosure will be more comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The accompanying drawings are only schematic illustrations of the disclosure and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and thus their repeated description will be omitted.

[0047] In addition, the described features, structures or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced while omitting one or more of the specific details, or other methods, devices, steps, etc. may be adopted. In other cases, well-known structures, methods, devices, implementations or operations are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0048] In addition, the terms "first", "second", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. The symbol " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0049] In this disclosure, unless otherwise clearly specified and limited, terms such as "connection" should be understood in a broad sense, for example, it can be an electrical connection or can communicate with each other; it can be directly connected or indirectly connected through an intermediate medium. For ordinary technicians in this field, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0050] Some memories can perform erase operations at the block level, that is, erase all memory cells in a selected memory block at the same time. A plane of the memory can include multiple memory blocks, and adjacent memory blocks share an array common source (ACS) wall. The ACS wall usually plays a role in maintaining chip stress. The ACS wall can be processed with high resistance and low doping. For example, polysilicon (PolySi) can be doped with a low concentration to form a nearly insulating ACS wall. The WLs of adjacent memory blocks are coupled to the same ACS wall, so the WLs of two adjacent memory blocks and the high-resistance, low-doping ACS wall can be equivalent to a capacitor, that is, a parasitic capacitor. The WLs of two adjacent memory blocks are equivalent to two plates, and the ACS wall is equivalent to the dielectric material between the two plates. The parasitic capacitor will couple the WL voltages of the adjacent memory blocks on both sides.

[0051] For example, in the process of erasing a target memory block selected from multiple memory blocks on a plane, a low voltage is applied to the WL of the target memory block, and the WL of the memory block adjacent to the target memory block is floated, and its voltage can be coupled with the channel boosting potential. However, in the case where there is a parasitic capacitance of a high-resistance, low-doped ACS wall between the adjacent memory block and the target memory block, the low voltage applied to the WL of the target memory block will be divided by the parasitic capacitance of the ACS wall, affecting the boosting speed of the WL of the adjacent memory block, thereby causing the WL of the adjacent memory block to be inconsistent with the channel boosting, which will form a voltage difference after multiple erase cycles, weakly erase the adjacent memory blocks, causing the threshold voltage of the storage unit of the adjacent memory block to shift, so that the read window margin or the voltage distribution interval sum (ESUM) of the memory is reduced.

[0052] Therefore, the present disclosure provides a memory operation method, by applying a bias voltage to the bottom selection line of a second storage block adjacent to the first storage block in a first time period to turn on the bottom selection tube of the second storage block, and then performing a first erase operation in a second time period after the first time period, including providing an erase operating voltage to the source line of the first storage block and setting the bottom selection line of the second storage block to a floating state. In the discharge phase after the second time period, the bottom selection line of the second storage block can float to the bias voltage, that is, it is still in the on state, then the gate induced drain leakage (GIDL) potential generated in the channel due to the voltage division effect of the ACS wall parasitic capacitance in the boost phase can continue to discharge to the initial potential (for example, it can be Vss), and the WL of the second storage block can weaken the voltage division effect of the ACSwall parasitic capacitance when it rises with the channel voltage coupling, and can be restored to a voltage closer to the voltage before the boost in the discharge phase, so that there will be no voltage accumulation in the next erase cycle, thereby reducing the voltage difference between the WL of the second storage block and the channel after multiple erase cycles, and reducing the read window margin or the total loss of the voltage distribution interval of the memory during the erase process.

[0053] Figure 1 FIG. 2 shows a schematic diagram of a non-volatile memory to which the present disclosure can be applied. Figure 1 As shown, the memory 10 may include a memory cell array 102 and a peripheral circuit 104 coupled to the memory cell array 102. The memory cell array 102 may be a NAND flash memory cell array, for example, Figure 2 1 shows a schematic diagram of a NAND flash memory cell array. The peripheral circuit 104 may include any suitable analog, digital, and mixed signal circuits to implement the operation of the memory cell array 102 by applying a voltage signal and / or a current signal to each target memory cell 10222 via a bit line (BL), WL, BSG line, TSG line, etc. and sensing a voltage signal and / or a current signal from each target memory cell 10222 (see FIG. 1 ). Figure 2 ). The peripheral circuit 104 may include various types of peripheral circuits formed using Metal-Oxide-Semiconductor (MOS) technology. For example, Fig.13 An exemplary peripheral circuit is shown.

[0054] Figure 2 FIG. 1 shows a schematic diagram of a memory cell array of a NAND FLASH to which the present disclosure can be applied. Figure 2As shown, in the memory cell array 102, the memory cells 10222 in the memory block 1020 are provided in the form of an array of NAND memory strings 1022, each of which extends vertically above a substrate (not shown). In some embodiments, each NAND memory string 1022 includes a plurality of memory cells 10222 coupled in series and stacked vertically. Each memory cell 10222 can hold a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped in the region of the memory cell 10222. Each memory cell 10222 can be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0055] In some embodiments, each memory cell 10222 may be a single-level cell (SLC) having two possible memory states and thus may store one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range.

[0056] In some embodiments, each memory cell 10222 may be a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC may store two bits per cell, three bits per cell (also known as a triple-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC may be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC may be programmed to take one of three possible programming levels from an erased state by writing one of three possible nominal storage values ​​to the cell. A fourth nominal storage value may be used for an erased state.

[0057] like Figure 2As shown, each NAND memory string 1022 may include a bottom select transistor 10224 with a bottom select gate (BSG) at its source terminal and a top select transistor 10226 with a top select gate (TSG) at its drain terminal. BSG and TSG may be configured to activate the selected NAND memory string 1022 (column of the array) during read and program operations. In some embodiments, the sources of the NAND memory strings 1022 in the same memory block 1020 may be coupled via the same source line (SL), for example, a common source line. The SLs of adjacent memory blocks may be coupled together, and in some embodiments, adjacent memory blocks BLK N and BLK N+1 may be coupled together.

[0058] In some embodiments, the TSG of each NAND memory string 1022 is coupled to a corresponding BL, and data can be read from or written to the BL via an output bus (not shown). In some embodiments, each NAND memory string 1022 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of a transistor having the BSG) or a deselect voltage (e.g., 0V) to the corresponding BSG via one or more BSG lines.

[0059] like Figure 2 As shown, the NAND memory string 1022 can be organized into a plurality of memory blocks 1020, each of which can have a common source line SL. In some embodiments, each memory block 1020 is a basic data unit for an erase operation, that is, all memory cells 10222 on the same memory block 1020 are erased at the same time. In one memory block 1020, the WL selects which row of memory cells 10222 is affected by read and program operations. In some embodiments, each WL is coupled to a page 1026 of memory cells 10222, which is a basic data unit for a program operation.

[0060] Figure 3 A schematic diagram of a memory cell array including multiple memory blocks to which the present disclosure can be applied is shown. The memory cell array may include multiple planes, each plane may include multiple memory blocks, Figure 3 An example plane is shown, which is referred to as the first plane below. When performing operations such as erasing on a memory cell array, one plane or multiple planes may be selected for the operation. In the embodiment disclosed herein, the first plane is taken as an example to be a plane selected from multiple planes.

[0061] like Figure 3As shown, the first plane includes a plurality of storage blocks BLK (Block) N, BLK N+1...BLK N+X (N, X are positive integers, X is greater than N), and storage blocks with adjacent numbers such as BLK N, BLK N+1 are adjacent storage blocks. The structure of each storage block can refer to Figure 2 In the memory block 1020, the WL of the adjacent memory block is coupled to the ACS wall 1023. In some embodiments, the ACS wall 1023 may be high-resistance and low-doped, thus forming a parasitic capacitor with the WL of BLK N and the WL of BLK N+1 as two plates (10232, 10236) and the ACS wall 1023 itself as the dielectric material 10234 between the plates 10232 and 10236.

[0062] In some embodiments, a high voltage N well (HVNW) 1024 may be formed in the substrate (not shown), and the source terminal of the NAND memory string 1022 may be in contact with the HVNW 1024. For example, the SL may be coupled to the HVNW 1024 so that during an erase operation, an erase operation voltage (Verase) (e.g., a high positive voltage, which may be 20V or higher) is applied to the SL through a peripheral circuit and applied to the HVNW 1024 (i.e., the source of the NAND memory string 1022). Figure 3 , taking BLK N as a selected memory block (which may be referred to as a first memory block) as an example, in order to erase the memory cell 10222 in the selected memory block BLK N, the source line SL coupled to BLK N and the unselected memory blocks BLK N+1...BLK N+X in the same plane as BLK N may be biased with Verase. It should be understood that in some examples, the erase operation may be performed at a half-block level, at a quarter-block level, or at a level having any suitable number of blocks or any suitable fraction of a block.

[0063] Figure 4 is based on Figure 3 The first erase pulse waveform diagram in the related art is shown. Figure 4In some embodiments, before the first erase pulse is applied at time t0, the BSG lines in BLK N+1...BLK N+X are connected to the common ground voltage (Vss), and the bottom selection tubes 10224 with BSG of each NAND memory string 1022 are turned off. The first erase pulse is applied at time t0, and Verase is applied to HVNW through SL, so that the source voltage of each NAND memory string 1022 in BLK N, BLK N+1...BLK N+X rises from the initial voltage (e.g., the power supply voltage (Vss)) to Verase at time t1. At time t0, an erase control voltage (e.g., Vss) is applied to the WL of the selected storage block BLK N, so that the WL of BLK N drops from the initial voltage (e.g., the system voltage (Vdd)) to the erase control voltage. At time t0, the bottom selection tube 10224 with BSG of each NAND memory string 1022 of the selected storage block BLK N receives a voltage from the BSG line to generate a GIDL current to allow holes to flow through the semiconductor channel of each NAND memory string 1022 of the corresponding selected storage block BLK N, so that the threshold voltage of each storage cell 10222 of the selected storage block BLK N shifts toward a more negative direction, that is, shifts to an erased state.

[0064] For the unselected storage blocks BLK N+1…BLK N+X, at time t0, the BSG lines of these storage blocks float, so that the voltage on the BSG lines of BLK N+1…BLK N+X rises with HVNW and rises to Verase at time t1. At the same time t0, the WL of BLK N+1…BLK N+X floats. During the BSG line boosting process between t0 and t1, the bottom selection tubes 10224 of BLK N+1…BLK N+X are turned on, so that the channel potential of BLK N+1…BLK N+X rises with HVNW, and the WL voltage of BLK N+1…BLK N+X rises accordingly. Since the WL of BLK N+1 is affected by the parasitic capacitance voltage divider between it and the WL of BLK N, the voltage rise rate of the WL of BLK N+1 is slower than the voltage rise rate of the WL of BLK N+X. Refer to Figure 4At time t1, the initial voltage on the WL of BLK N+X (for example, the system voltage (Vdd)) is coupled with the channel boost potential of BLK N+X to Verase+Vdd (if there is a coupling coefficient, it can be less than Verase+Vdd), while the voltage of the WL of BLK N+1 coupled to rise is less than Verase+Vdd. The lower voltage of the WL of BLK N+1 generates a gate induced drain leakage (GIDL) potential, which causes the channel potential of BLK N+1 to rise, and then couples with the WL of BLK N+1, resulting in the voltage of the WL of BLK N+1 rising to close to Verase+Vdd at time t2 after time t1. At time t3, the erase discharge begins. Due to the characteristics of the PN junction, the GIDL potential of the channel of BLK N+1 causes the channel of BLK N+1 to discharge to Vgidl instead of being completely discharged to the initial potential Vss like the channel of BLK N+X. Starting from time t3, the WLs of BLK N+1...BLK N+X float, and the WL of BLK N+1 cannot fall back to the system voltage Vdd due to the capacitive coupling effect like the WL of BLK N+X, but is reduced to Vdd+Vgidl due to its GIDL potential.

[0065] Figure 5 is based on Figure 4 and Figure 3 The second erase pulse waveform diagram in the related art is shown in FIG. The second erase pulse can be Figure 4 The next erase pulse is the first erase pulse shown. Figure 5 As shown, the second erase pulse is applied at time t0', the voltage applied to SL, the erase control voltage applied to WL of the selected memory block BLK N, and the floating of the BSG line and WL line of the unselected memory blocks BLK N+1...BLK N+X are all the same as the first erase pulse.

[0066] Reference Figure 5, for the unselected memory blocks BLK N+1...BLK N+X, at t0', the channel starting potential of BLK N+X is the same as that at t0, which is still Vss, while the channel starting potential of BLK N+1 is higher than that at t0, which is Vgidl; at t0', the WL initial voltage of BLK N+X is the same as that at t0, which is still Vdd, while the WL initial voltage of BLK N+1 is higher than that at t0, which is Vdd+Vgidl. The WL of BLK N+X is almost unaffected, and can still rise to Verase+Vdd at t1' with the channel boosting potential coupling. Since the initial potential of the channel of BLK N+1 becomes higher, it no longer generates the same GIDL potential as the WL of BLK N+1 at time t1', so that between time t1' and time t2', the part of the WL of BLK N+1 that rises due to coupling disappears or at least decreases, resulting in the voltage of the WL of BLK N+1 rising to a value lower than Verase+Vdd at time t2', for example, Verase+Vdd-Vgidl. At time t3', the erase discharge starts, the channel of BLK N+1 will discharge to Vgidl' which is higher than Vgidl, and the WL of BLKN+1 will also decrease to Vdd+Vgidl' which is higher than Vdd+Vgidl.

[0067] By analogy, after multiple erase pulse cycles, a voltage difference will accumulate between the WL and the channel of BLK N+1, which is equivalent to weakly erasing BLK N+1, causing additional memory read window margin or voltage distribution ESUM loss during the erase process.

[0068] Figure 6 FIG. 1 is a flow chart of a memory operation method according to an exemplary embodiment. Figure 6 The method shown can be applied, for example, to Figure 3 The memory cell array shown is used to solve Figure 4 and Figure 5 The neighboring memory blocks of the selected memory block shown cause additional technical problems of loss of read window margin or voltage distribution ESUM of the memory.

[0069] refer to Figure 6 , the method 60 provided in the embodiment of the present disclosure may include the following steps.

[0070] In step S602, a bias voltage is applied to the bottom selection line of the second storage block in a first time period to turn on the bottom selection transistor of the second storage block.

[0071] In some embodiments, the first time period may be a time period before the erase pulse, for example, Figure 4 The time period before time t0 can also be Figure 5The time period before time t0'.

[0072] In some embodiments, the second memory block may be all unselected memory blocks (eg Figure 3 BLK N+1...BLK N+X), or only the third storage block adjacent to the selected storage block (eg Figure 3 BLK N+1 in the plane), or all storage blocks in a plane including the selected storage block (for example, BLK N, BLK N+1, ..., BLK N+X). Figure 2 , the bottom selection tubes 10224 of each NAND memory string 1022 on the second storage block can be turned on by applying a bias voltage on the BSG line.

[0073] In some embodiments, when selecting the bias voltage, under the premise of determining that it is greater than the threshold voltage of the bottom selection tube of the second storage block, it can be considered that the sum of the erase working voltage and the bias voltage is less than the preset voltage threshold. The bias voltage can range from 1V to 7V, for example, it can be 1V, 2V, 2.5V, 5V, 6V, 7V, etc.

[0074] In step S604, a first erasing operation is performed in a second time period, where the second time period is after the first time period.

[0075] In some embodiments, an erase pulse may be applied starting at the second time period, for example Figure 4 The time t0 may be the beginning of the second time period, and performing the first erasing operation may be applying the first erasing pulse. Figure 5 The time t0' may also be the beginning of the second time period, and performing the first erasing operation may be applying the second erasing pulse.

[0076] In some embodiments, performing the first erase operation may include steps S6042 and S6044.

[0077] In step S6042, an erase operation voltage is provided to a source line of the first memory block.

[0078] In some embodiments, the erase operation voltage may be a high positive voltage, which may be 20V or higher, and may be represented as the above-mentioned Verase.

[0079] In some embodiments, the first memory block may be a selected memory block (eg, Figure 3 In this case, the second storage block may be all unselected storage blocks (e.g. Figure 3 BLK N+1...BLK N+X), or only the memory blocks adjacent to the selected memory block (e.g. Figure 3BLK N+1 in the first storage block). Executing the first erasing operation may also include applying an erasing control voltage (eg, Vss) to the word line of the first storage block to erase the first storage block. For a specific implementation, refer to Figure 7 . Reference Figure 3 By applying Verase to HVNW 1024, an erase operating voltage can be provided to the source line of the first memory block, and an erase operating voltage can also be provided to the source line of the second memory block.

[0080] In step S6044, the bottom selection line of the second memory block is set to a floating state.

[0081] In various implementations of the second storage block described above, setting the bottom selection line of the second storage block to a floating state includes setting the adjacent storage block (eg Figure 3 The bottom selection line of BLK N+1 in the above description (denoted by BLK N+1 in the following description) is set to a floating state, so that the voltage on the BSG line of BLK N+1 can rise from the bias voltage along with the voltage on the source line. Since the bottom selection tube of BLK N+1 is turned on in the first time period before the first erase operation is performed in step S602, the bottom selection tube of BLK N+1 can be continuously turned on in the second time period. In the third time period, the bottom selection line of BLK N+1 is still set to floating and can float to the bias voltage, that is, the bottom selection tube of BLK N+1 can be in the on state in the discharge stage, and the Vgidl generated in the channel due to the voltage division of the parasitic capacitance in the boost stage can continue to discharge to the initial potential Vss, so that in the discharge stage, the WL of BLK N+1 can be restored to a voltage closer to the voltage before the boost, and the next erase cycle can reduce or even no voltage accumulation, thereby reducing the voltage difference between the WL and the channel of the second storage block after multiple erase cycles, and reducing the read window margin or voltage distribution ESUM loss of the memory during the erase process.

[0082] Figure 7 Shows Figure 6 FIG. 5 is a schematic diagram of the processing process of step S604 in one embodiment. Figure 7 and Figure 6 The connection is that Figure 7 The embodiment of performing the first erasing operation when the first storage block is the selected storage block is shown. The above step S604 may include the following steps S702 to S706.

[0083] Step S702, providing an erase operation voltage to a source line of a first storage block.

[0084] Reference Figure 3By applying Verase to HVNW 1024, an erase operating voltage can be provided to the source line of the first memory block, and an erase operating voltage can also be provided to the source line of the second memory block.

[0085] Step S704: applying an erase control voltage to the word line of the first storage block, wherein the erase operation voltage is greater than the erase control voltage.

[0086] In some embodiments, the erase control voltage is a low voltage lower than the erase operation voltage. At the same stage (i.e., the second time period), a voltage is provided to the bottom selection line of the first storage block to the bottom selection tube to generate a GIDL current to generate holes flowing through the channel of the first storage block, so that the threshold voltage of each storage cell of the first storage block is shifted toward a more negative direction, i.e., shifted to an erased state.

[0087] Step S706, setting the bottom selection line of the second storage block to a floating state.

[0088] In some embodiments, the specific implementation of step S706 may refer to step S6044.

[0089] Figure 8 according to Figure 6 FIG. 1 is a schematic diagram showing a process of applying voltage to a selected memory block during the erasing phase. Figure 8 and Figure 6 The difference is that Figure 8 The voltage application operation in the erase discharge phase is also shown, that is, after step S6042 (step S802 ), step S804 may be further included.

[0090] Step S802: providing an erase operation voltage to a source line of the first storage block within a second time period.

[0091] In some embodiments, the specific implementation of step S802 may refer to step S6042.

[0092] Step S804, applying a first voltage to the source line in a third time period, the third time period being after the second time period, and the first voltage being less than the erase operation voltage.

[0093] by Figure 3 For example, in various implementations of the first storage block described in step S6042, applying the first voltage to the source line of the first storage block can apply the first voltage to the source lines of all storage blocks including BLK N, BLK N+1...BLK N+X.

[0094] In some embodiments, Fig.12 is based on Figures 6 to 11An erase pulse waveform diagram is shown, taking the first erase pulse (i.e., performing the first erase operation) at time t0" as an example, by applying an erase operation voltage (Verase) to HVNW, applying an erase operation voltage to the source line, and rising to the erase operation voltage at time t1". Fig.12 The first time period may be the time period before t0", the second time period may be the time period between t0" and t2", and the third time period may be the time period after t2", i.e., the erase discharge stage. The first voltage is a low voltage, for example, Vss. Starting at t2", the first voltage may be applied to HVNW to make it drop from the erase operating voltage to the first voltage, so that the source line voltage drops back to the first voltage, the first erase operation ends, and the next erase pulse is waited for.

[0095] Fig. 9 according to Figure 6 FIG. 1 is a schematic diagram showing a process of applying voltage to unselected memory blocks during the erasing phase. Fig. 9 yes Figure 6 An implementation manner in which the second memory block is an unselected memory block. Fig. 9 It is shown that step S6044 may further include step S902, and after step S6044, step S904 may be further included.

[0096] Step S902, setting the bottom selection line of the second storage block to a floating state within the second time period, so that the voltage of the bottom selection line of the second storage block rises from the bias voltage to the second voltage along with the source line, the second voltage is not greater than the sum of the erase operating voltage and the bias voltage, the sum of the erase operating voltage and the bias voltage is less than a preset voltage threshold, and the bias voltage ranges from 1V to 7V.

[0097] In some embodiments, at the beginning of the second time period, the voltage on the bottom selection line of the second storage block is the bias voltage. After the bottom selection line of the second storage block is floated, the voltage rises to the sum of the erase operation voltage and the bias voltage along with the coupling of the source line (for example, through HVNW). If there is a coupling coefficient, it can be less than the sum of the erase operation voltage and the bias voltage. When designing the bias voltage, it can be considered to make the sum of the erase operation voltage and the bias voltage less than the preset voltage threshold to avoid the breakdown of the bottom selection tube of the second storage block in the second time period.

[0098] Step S904, keeping the bottom selection line of the second storage block in a floating state during a third time period, so that the voltage of the bottom selection line of the second storage block drops from the second voltage to the bias voltage, so as to continue to keep the bottom selection tube of the second storage block turned on.

[0099] In some embodiments, reference Fig.12, after the third time period, i.e., time t2", the bottom selection line of the second storage block can be kept in a floating state, so that the voltage of the bottom selection line of the second storage block drops from the second voltage to the bias voltage, so as to continue to keep the bottom selection tube of the second storage block turned on, waiting for the next erase pulse to start. When the next erase pulse starts, the bottom selection tube of the second storage block is still turned on, thereby reducing the voltage difference between the WL and the channel of the second storage block in multiple erase cycles, and reducing the read window margin or voltage distribution ESUM loss of the memory during the erase process.

[0100] Fig.10 according to Figure 6 The figure shows a schematic diagram of the operation process for the word lines of unselected memory blocks in the erasing stage. Fig.10 yes Figure 6 An implementation manner in which the second memory block is an unselected memory block. Fig.10 It is shown that step S604 may further include steps S1002 and S1004.

[0101] Step S1002, setting the word line of the second storage block to a floating state within a second time period.

[0102] The second memory block is any unselected memory block (eg Figure 3 BLK N+1...BLK N+X in the example, hereinafter referred to as BLK N+X) Fig.12 Since the bottom selection tube of BLK N+X is already turned on at t0”, the voltage on the BSG line is Vbias. During the BSG line voltage boost process between t0” and t1” in the second time period, the bottom selection tube of BLK N+X is continuously turned on. Fig.12 At time t1”, the initial voltage on the WL of BLK N+X (for example, the system voltage (Vdd)) is coupled with the channel boost potential of BLK N+X and rises to Verase+Vdd (if a coupling coefficient exists, it may be less than Verase+Vdd), and the voltage coupled to the WL of BLK N+1 may also reach Verase+Vdd.

[0103] Step S1004: keeping the word line of the second storage block in a floating state during a third time period.

[0104] Still taking the implementation method in which the second storage block is any unselected storage block BLK N+X as an example, referring to Fig.12, erase discharge starts at time t2”, keeping WL of BLK N+X in floating state. Starting from time t2”, since the bottom selection line of BLK N+X floats to the bias voltage, the bottom selection tube of BLK N+X is still in the on state, so no matter whether X is 1 or not, the channel of BLK N+X can continue to discharge to the initial potential Vss, so that WL of BLK N+1 can also fall back to the system voltage Vdd like WL of BLK N+X (X is not 1). Therefore, when the next erase pulse comes, the initial potential of the channel of BLK N+1 does not change and is still Vss, and the initial voltage of WL of BLK N+1 does not change and is still Vdd, that is, the waveform of the next erase pulse can still be obtained by Fig.12 As shown in the figure, the voltage difference between the WL and the channel of the second storage block in multiple erase cycles is eliminated, and the read window margin or voltage distribution ESUM loss of the memory during the erase process is reduced. In practical applications, the loss of 100mV can be reduced.

[0105] Fig.11 is based on Figure 6 A flowchart of another memory data processing method is shown. Fig.11 and Figure 6 The connection is that Fig.11 The second erase operation shown is the next erase operation after the first erase operation in the plurality of erase cycles.

[0106] refer to Fig.11 , the method 110 provided in the embodiment of the present disclosure may include the following steps.

[0107] In step S1102 , a bias voltage is applied to the bottom selection line of the second memory block in a fourth time period, the fourth time period being after the third time period.

[0108] In step S1104, a second erasing operation is performed in a fifth time period, the fifth time period being after the fourth time period.

[0109] In step S11042, an erase operation voltage is provided to a source line of the first memory block.

[0110] In step S11044, the bottom selection line of the second memory block is set to a floating state.

[0111] In some embodiments, the fourth time period corresponds to the first time period, the fifth time period corresponds to the second time period, and the specific implementation of steps S1102 to S11044 can refer to the specific implementation of steps S602 to S6044.

[0112] Fig.13 is based on Figures 6 to 11 A structural block diagram of a memory is shown. Fig.13The memory cell array 1302 is shown as Figure 1 The example of the memory cell array 102 in FIG. 1 , that is, the peripheral circuit 104 may include a page buffer / sense amplifier 1304, a column decoder / BL driver 1306, a source line driver 1307, a row decoder / WL driver / BSG driver 1308, a voltage generator 1310, a control circuit 1312, a register 1314, an input / output circuit 1316, etc. It should be understood that in some examples, it may also include Fig.13 Additional peripheral circuits not shown.

[0113] The page buffer / sense amplifier 1304 may be configured to read data from the memory cell array 1302 and program (write) data to the memory cell array 1302 according to a control signal from the control circuit 1312. Figure 2 , the page buffer / sense amplifier 1304 can store a page of programming data (write data) to be programmed into a page 1026 of the memory cell array 102. In another example, the page buffer / sense amplifier 1304 can perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 10222 coupled to the selected memory block 1020. In yet another example, the page buffer / sense amplifier 1304 can also sense a low-power signal from the BL representing a data bit stored in the memory cell 10222, and amplify a small voltage swing to a recognizable logic level in a read operation. The column decoder / B driver 1306 can be configured to be controlled by the control circuit 1312, and select one or more NAND memory strings 1022 by applying a bit line voltage generated from the voltage generator 1310.

[0114] The source line driver 1307 may be configured to be controlled by the control circuit 1312 and provide a source voltage, such as an erase operation voltage, a first voltage, etc., to one or more NAND memory strings 1022 by applying a source voltage generated from the voltage generator 1310 .

[0115] The row decoder / WL driver / BSG driver 1308 may be configured to be controlled by the control circuit 1312, drive the WL using the WL voltage generated from the voltage generator 1310, and may also select / deselect and drive the BSG line. The voltage generator 1310 may be configured to be controlled by the control circuit 1312 and generate a WL voltage to be supplied to the memory cell array 1302, such as an erase control voltage, etc., and may also be configured to be controlled by the control circuit 1312 and generate a BSG line voltage to be supplied to the memory cell array 1302, such as a bias voltage, etc.

[0116] As part of the peripheral circuit, the control circuit 1312 can be coupled to the other peripheral circuits described above and configured to control the operation of the other peripheral circuits. The register 1314 can be coupled to the control circuit 1312 and include a status register, a command register, and an address register, etc. for storing status information, command operation codes (e.g., OP codes, command operation codes) and command addresses for controlling the operation of each peripheral circuit. The input / output circuit 1316 can be coupled to the control circuit 1312 and used as a control buffer to buffer and relay control commands received from a host (not shown) to the control circuit 1312 and status information received from the control circuit 1312 to the host. The input / output circuit 1316 can also be coupled to the column decoder / BL driver 1306 via a data bus (not shown) and used as a data input / output interface and a data buffer to buffer and relay data from the memory cell array 1302.

[0117] Fig.14 is based on Figures 6 to 11 A schematic diagram of the structure of a storage system is shown. Figure 3 A block diagram of an exemplary storage system 140 with a memory device according to some aspects of the present disclosure is shown. The storage system 140 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or a memory system in any other suitable electronic device having a memory device, connected to a host (not shown) in the electronic device. The host can be a processor (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host can be configured to send data to or receive data from the system 140.

[0118] The storage system 140 may include any memory device disclosed in the embodiments of the present disclosure, such as a NAND flash memory device (e.g., a three-dimensional (3D) NAND flash memory device) that can reduce the read window margin or voltage distribution ESUM loss of the memory during an erase operation as described in the embodiments of the present disclosure.

[0119] like Fig.14As shown, the storage system 140 may include a storage cell array 1402, a peripheral circuit 1404, and a controller 1406, the storage cell array 1402 and the peripheral circuit 1404 constituting a memory device. The controller 1406 is coupled to the peripheral circuit 1404 and the host, and is configured to control the peripheral circuit 1404 to operate the storage cell array 1402. The controller 1406 can manage the data stored in the storage cell array 1402 and communicate with the host. In some embodiments, the controller 1406 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the controller 1406 is designed to operate in a solid state drive (SSD) or an embedded Multi-Media-Card (eMMC) in a high duty cycle environment, and the SSD or eMMC is used as a data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc. and enterprise storage arrays. The controller 1406 can be configured to control the operation of the peripheral circuit 1404 on the storage cell array 1402, such as read, erase and program operations. The controller 1406 can also be configured to manage various functions related to the data stored or to be stored in the storage cell array 1402, including but not limited to bad block management, garbage collection, logical to physical address conversion, wear leveling, etc. In some embodiments, the controller 1406 is also configured to process the error correction code (Error Correction Code, ECC) of the data read from the storage cell array 1402 or written to the storage cell array 1402. The controller 1406 can also perform any other suitable function, for example, formatting the memory device. The controller 1406 can communicate with an external device (e.g., a host) according to a specific communication protocol.For example, the controller 1406 can communicate with an external device through at least one of various interface protocols, such as the Universal Serial Bus (USB) protocol, the Multi Media Card (MMC) protocol, the Peripheral Component Interconnection (PCI) protocol, the PCI-E protocol, the Advanced Technology Attachment (ATA) protocol, the Serial ATA protocol, the Parallel ATA protocol, the Small Computer Small Interface (SCSI) protocol, the Enhanced Small Disk Interface (ESDI) protocol, the Integrated Drive Electronic (IDE) protocol, the Firewire protocol, etc.

[0120] The controller 1406 and one or more memory devices including the memory cell array 1402 and the peripheral circuit 1404 can be integrated into various types of storage devices, for example, included in the same package (e.g., Universal Flash Storage (UFS) package or eMMC package). That is, the system 140 can be implemented and packaged into different types of terminal electronic products.

[0121] The exemplary embodiments of the present disclosure are specifically shown and described above. It should be understood that the present disclosure is not limited to the detailed structures, configurations or implementations described herein; on the contrary, the present disclosure is intended to cover various modifications and equivalent configurations included in the spirit and scope of the appended claims.

Claims

1. A memory operation method, characterized in that: The memory includes a plurality of memory blocks, the memory blocks include a bottom selection tube, the bottom selection tube is coupled to a bottom selection line, the plurality of memory blocks include a first memory block and a second memory block, and the method includes: Applying a bias voltage to the bottom selection line of the second storage block in a first time period to turn on the bottom selection tube of the second storage block; Performing a first erasing operation in a second time period, the second time period being after the first time period, wherein performing the first erasing operation includes: Providing an erase operation voltage to a source line of the first storage block; The bottom selection line of the second memory block is set to a floating state.

2. The method according to claim 1, characterized in that Executing the first erasing operation further includes: An erase control voltage is applied to the word line of the first storage block, and the erase operation voltage is greater than the erase control voltage.

3. The method according to claim 2, characterized in that Also includes: A first voltage is applied to the source line in a third time period, the third time period is after the second time period, and the first voltage is less than the erase operation voltage.

4. The method according to claim 1, characterized in that: Setting the bottom selection line of the second storage block to a floating state comprises: The bottom selection line of the second storage block is set to a floating state so that the voltage of the bottom selection line of the second storage block rises from the bias voltage to a second voltage along with the source line, and the second voltage is not greater than the sum of the erase working voltage and the bias voltage.

5. The method according to claim 4, characterized in that Also includes: The bottom selection line of the second storage block is kept in a floating state during a third time period so that the voltage of the bottom selection line of the second storage block drops from the second voltage to the bias voltage to continue to keep the bottom selection tube of the second storage block turned on. The third time period is after the second time period.

6. The method according to claim 1, characterized in that The sum of the erase operation voltage and the bias voltage is less than a preset voltage threshold.

7. The method according to claim 1, characterized in that Executing the first erasing operation further includes: Setting the word line of the second storage block to a floating state; The method further comprises: The word line of the second storage block is kept in a floating state during a third time period, and the third time period is after the second time period.

8. The method according to any one of claims 1 to 7, characterized in that The second storage block includes a third storage block, and the third storage block is adjacent to the first storage block.

9. The method according to any one of claims 3, 5 and 7, characterized in that Also includes: applying the bias voltage to the bottom selection line of the second storage block in a fourth time period, the fourth time period being after the third time period; Performing a second erasing operation in a fifth time period, the fifth time period being after the fourth time period, wherein performing the second erasing operation includes: Providing the erase operation voltage to the source line of the first storage block; The bottom selection line of the second memory block is set to a floating state.

10. The method according to claim 1, characterized in that The bias voltage ranges from 1V to 7V.

11. The method according to claim 1, characterized in that The memory includes a plurality of planes, the plurality of planes including a first plane, the first plane being a plane selected from the plurality of planes, and the plurality of storage blocks being on the first plane.

12. A memory, characterized in that: include: A memory cell array, the memory cell array comprising a plurality of memory blocks, the memory blocks comprising a bottom selection tube, the bottom selection tube being coupled to a bottom selection line, the plurality of memory blocks comprising a first memory block and a second memory block; A peripheral circuit, coupled to the memory cell array, configured to: Applying a bias voltage to the bottom selection line of the second storage block in a first time period to turn on the bottom selection tube of the second storage block; Performing a first erasing operation in a second time period, the second time period being after the first time period, wherein performing the first erasing operation includes: Providing an erase operation voltage to a source line of the first storage block; The bottom selection line of the second memory block is set to a floating state.

13. The memory according to claim 12, characterized in that: The peripheral circuit includes a control circuit, a voltage generator, a bottom selection line driver and a source line driver, wherein: The voltage generator is used to generate the bias voltage; The control circuit is used to control the bottom selection line driver to apply the bias voltage to the bottom selection line of the second storage block in the first time period, so as to turn on the bottom selection tube of the second storage block; The voltage generator is further used to generate the erase operation voltage; The control circuit is further used to control the source line driver to apply the erase operation voltage to the source line of the first storage block during the second time period; The control circuit is further configured to control the bottom selection line driver to set the bottom selection line of the second storage block to a floating state within the second time period.

14. The memory according to claim 13, characterized in that: The voltage generator is further used to generate an erase control voltage, and the erase operation voltage is greater than the erase control voltage; The peripheral circuit also includes a word line driver; The control circuit is further used to control the word line driver to apply the erase control voltage to the word line of the first storage block during the second time period.

15. The memory according to claim 14, characterized in that: The voltage generator is further used to generate a first voltage, wherein the first voltage is lower than the erase operation voltage; The control circuit is further configured to control the source line driver to apply the first voltage to the source line of the first storage block in a third time period, wherein the third time period is after the second time period.

16. The memory according to claim 13, characterized in that: The control circuit is also used to control the bottom selection line driver to set the bottom selection line of the second storage block to a floating state during the second time period, so that the voltage of the bottom selection line of the second storage block rises from the bias voltage to a second voltage along with the source line, and the second voltage is not greater than the sum of the erase operating voltage and the bias voltage.

17. The memory according to claim 16, characterized in that: The control circuit is also used to control the bottom selection line driver to keep the bottom selection line of the second storage block in a floating state during a third time period, so that the voltage of the bottom selection line of the second storage block drops from the second voltage to the bias voltage to continue to keep the bottom selection tube of the second storage block turned on, and the third time period is after the second time period.

18. The memory according to claim 12, characterized in that: The sum of the erase operation voltage and the bias voltage is less than a preset voltage threshold.

19. The memory according to claim 13, characterized in that: The control circuit is further used to control the word line driver to set the word line of the second storage block to a floating state during the second time period; The control circuit is further used to control the word line driver to keep the word line of the second storage block in a floating state within a third time period, and the third time period is after the second time period.

20. The memory according to any one of claims 12 to 19, characterized in that: The second storage block includes a third storage block, and the third storage block is adjacent to the first storage block.

21. The memory according to any one of claims 15, 17 and 19, characterized in that: The peripheral circuit is also used for: applying the bias voltage to the bottom selection line of the second storage block in a fourth time period, the fourth time period being after the third time period; Performing a second erasing operation in a fifth time period, the fifth time period being after the fourth time period, wherein performing the second erasing operation includes: Providing the erase operation voltage to the source line of the first storage block; The bottom selection line of the second memory block is set to a floating state.

22. The memory according to claim 12, characterized in that: The bias voltage ranges from 1V to 7V.

23. The memory according to claim 12, characterized in that: The memory cell array includes a plurality of planes, the plurality of planes including a first plane, the first plane being a plane selected from the plurality of planes, and the plurality of memory blocks being on the first plane.

24. A storage system, characterized in that: The invention comprises a memory and a controller coupled to the memory, wherein: The memory comprises a memory cell array and a peripheral circuit, wherein the memory cell array comprises a plurality of memory blocks, the memory block comprises a bottom selection tube, the bottom selection tube is coupled to a bottom selection line, the plurality of memory blocks comprises a first memory block and a second memory block, and the peripheral circuit is coupled to the memory cell array; The controller is used to control the peripheral circuit to execute the memory operation method according to any one of claims 1 to 11.

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