Signal time delay circuit and time sequence parameter testing method and system

Abstract

The invention provides a signal time delay circuit, a time sequence parameter testing method and a time sequence parameter testing system, and relates to the technical field of mobile communication. The signal time delay circuit comprises a plurality of delay circuits, the input ends of all the delay circuits are connected with the same original signal end, the output end of each delay circuit is connected with a unit to be tested, and each delay circuit is used for delaying a homologous original signal input through the original signal end according to a control signal to generate a corresponding delay signal. The starting points of the delay signals output by the plurality of delay circuits are aligned, the processing of the test time is simplified, the delay signals output by the delay circuits are flexibly configured according to the test requirements when the chip is tested, the to-be-tested unit in the chip is directly tested, and the test efficiency is improved. And the test accuracy of the time sequence parameters of each module in the chip is improved.

Description

Technical Field

[0001] The present application relates to the field of mobile communication technology, and in particular to a signal delay circuit, a timing parameter testing method and a timing parameter testing system. Background Art

[0002] In the field of chip testing, automatic test equipment (ATE) is usually used to test the timing parameters in the chip. However, the ATE testing method usually has problems such as high testing cost, strong professional and technical requirements for testers, and large external interference. In addition, the test stimulus of ATE can only enter the chip through the external interface of the chip. When testing the internal interface of the chip, a certain delay will be generated, which reduces the test accuracy; it is impossible to directly and accurately measure the timing parameters between the various modules inside the chip. Summary of the invention

[0003] The present application provides a signal delay circuit, a timing parameter testing method and a timing parameter testing system.

[0004] An embodiment of the present application provides a signal delay circuit, including: multiple delay circuits, the input ends of all delay circuits are connected to the same original signal end, the output end of each delay circuit is respectively connected to a unit to be tested, and each delay circuit is used to delay the original signal of the same source input through the original signal end according to a control signal to generate a corresponding delayed signal.

[0005] An embodiment of the present application provides a timing parameter testing method, the method comprising: based on any signal delay circuit in the embodiment of the present application, obtaining at least two delay signals with different delay levels, wherein at least two delay signals with different delay levels originate from the same original signal; inputting at least two delay signals of different levels into a unit to be tested, and testing the timing parameters of the unit to be tested.

[0006] An embodiment of the present application provides a timing parameter testing system, the system comprising: a control unit, a unit to be tested, and any one of the signal delay circuits in the embodiments of the present application; the signal delay circuit is used to delay the original signal of the same source input through the original signal end according to the control signal input by the control unit to generate a corresponding delayed signal; the unit to be tested is used to receive multiple delayed signals input by multiple delay circuits in the signal delay circuit, apply the multiple delayed signals to different test ports in the unit to be tested respectively, generate an output signal, and output the output signal to the control unit.

[0007] According to the signal delay circuit of the embodiment of the present application, by connecting the input ends of multiple delay circuits to the same original signal end, the output end of each delay circuit is used to connect the unit to be tested, so that the starting points of the delay signals output by the multiple delay circuits can be aligned, thereby simplifying the processing of the test time; and each delay circuit is used to delay the original signal of the same source input through the original signal end according to the control signal to generate a corresponding delayed signal. When testing the chip, the delay signal output by the delay circuit can be flexibly configured according to the test requirements, and the unit to be tested inside the chip can be directly tested, thereby improving the test accuracy of the timing parameters of each module inside the chip.

[0008] According to the timing parameter testing method and timing parameter testing system of the embodiments of the present application, at least two delay signals with different delay levels are obtained based on any one of the signal delay circuits in the embodiments of the present application, and at least two delay signals with different delay levels are derived from the same original signal, so that the starting points of the delay signals output by multiple delay circuits can be aligned, simplifying the processing of the test time; at least two delay signals of different levels are input into the unit to be tested, and the timing parameters of the unit to be tested are tested, so that at least two delay signals of different levels act on different test ports in the unit to be tested, respectively, wherein different levels of delay signals can be delayed for test signals of different test ports, thereby changing the phases of test signals corresponding to different test ports in the unit to be tested, so that the unit to be tested can obtain test signals with different phases, which not only improves the test flexibility of the unit to be tested, but also can improve the test accuracy of the unit to be tested.

[0009] With regard to the above embodiments and other aspects of the present application and their implementation, further description is provided in the accompanying drawings, detailed description and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A structural diagram of a signal delay circuit provided in an embodiment of the present application is shown.

[0011] Figure 2 A flow chart of a timing parameter testing method provided in an embodiment of the present application is shown.

[0012] Figure 3 A block diagram of a timing parameter testing system provided in an embodiment of the present application is shown.

[0013] Figure 4 A block diagram of a timing parameter testing system provided in an embodiment of the present application is shown.

[0014] Figure 5 A timing diagram of a read operation on data in a unit under test provided by an embodiment of the present application is shown.

[0015] Figure 6 A timing diagram for testing the signal setup test time in the timing parameters of the unit under test provided by an embodiment of the present application is shown.

[0016] Figure 7 A flow chart showing a method for testing the signal establishment test time in the timing parameters of the unit under test provided by an embodiment of the present application.

[0017] Figure 8 A timing diagram for testing the signal holding test duration in the timing parameters of the unit under test provided by an embodiment of the present application is shown.

[0018] Fig. 9 A flow chart showing a method for testing the signal retention test duration in the timing parameters of a unit under test provided by an embodiment of the present application.

[0019] Fig.10 A flow chart showing a method for testing a data read delay duration in a timing parameter of a unit under test provided by an embodiment of the present application is shown. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical solution and advantages of the present application more clear, the embodiments of the present application will be described in detail with reference to the accompanying drawings. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other arbitrarily without conflict.

[0021] Static Random-Access Memory (SRAM) is a type of random access memory. SRAM is used to store data in many different technical fields (such as the automotive field, electronic technology field, etc.). For the performance test of SRAM, the timing parameters of SRAM are tested to determine the performance of SRAM.

[0022] However, in the commonly used ATE test process, expensive ATE test equipment is required, and the test environment also needs to match the ATE equipment, which increases the test cost. In addition, the test stimulus of ATE can only enter the chip through the external interface of the chip (for example, the input / output (I / O) interface between the chip and the test equipment, etc.), and when testing the internal interface of the chip, a certain delay will be generated, which reduces the test accuracy; it is impossible to directly and accurately measure the timing parameters between the various modules inside the chip.

[0023] The present application provides a signal delay circuit, a timing parameter testing method and a timing parameter testing system. By connecting the input ends of multiple delay circuits to the same original signal end, the output end of each delay circuit is used to connect the unit to be tested, so that the starting points of the delay signals output by the multiple delay circuits can be aligned, thereby improving the test accuracy of the internal modules of the chip and simplifying the processing of the test time; and each delay circuit is used to delay the original signal of the same source input through the original signal end according to the control signal to generate a corresponding delay signal. When testing the chip, the delay signal output by the delay circuit can be flexibly configured according to the test requirements, and the unit to be tested inside the chip can be directly tested, thereby improving the test accuracy of the timing parameters of each module inside the chip.

[0024] Figure 1 FIG. 1 shows a structural diagram of a signal delay circuit provided by an embodiment of the present application. Figure 1 As shown, the signal delay circuit includes but is not limited to the following circuits.

[0025] Multiple delay circuits (for example, a first delay circuit 121, a second delay circuit 122, ..., an nth delay circuit 12n, etc., where n is an integer greater than 1), the input ends of all the delay circuits are connected to the same original signal end 110, the output end of each delay circuit is respectively used to connect to the unit under test 130, and each delay circuit is used to delay the original signal of the same source input through the original signal end 110 according to the control signal to generate a corresponding delayed signal.

[0026] The original signal terminal 110 may be a port connected to an external signal source (e.g., a clock signal source, etc.), or a port connected to a control unit; correspondingly, the original signal may be a signal generated by an external signal source (e.g., a clock signal source, etc.), or a signal generated by a control unit, etc., and the present application does not limit this, as long as the original signal can act on the signal delay circuit. In one example, the original signal may be generated by the control unit and input into the signal delay circuit via the original signal terminal 110.

[0027] The original signal can be used as an input signal of each delay circuit, so that the starting points of the delay signals output by the multiple delay circuits can be aligned, thereby improving the test accuracy of the unit under test 130 .

[0028] In some exemplary embodiments, the signal delay circuit may further include: a control unit (not shown in the figure) for generating a control signal, wherein the control signal is used to control the delay level of each delay circuit.

[0029] The delay level may be determined based on the control requirements of each delay circuit. For example, the original signal inputted by the original signal terminal 110 is evenly divided into a plurality of equal parts based on the control signal, and the delay level is determined based on the number of modulated equal parts.

[0030] For example, divide the original signal into 10 equal parts. If the test requirement corresponding to the signal delay circuit requires 3 equal parts of the signal, the corresponding delay level is 3; if the test requirement corresponding to the signal delay circuit requires 5 equal parts of the signal, the corresponding delay level is 5, and so on. It will not be repeated here.

[0031] The control unit is used to accurately control the delay level of each delay circuit based on the control signal to meet the test requirements of the unit under test 130 .

[0032] The control unit also includes: a signal receiving end, which is used to connect to the output end of the unit to be tested; and the control unit is also used to analyze the signal received by the signal receiving end.

[0033] Among them, the control unit can adjust the phase information of the signal input into the unit under test 130 by adjusting the timing of each delay circuit in the control signal delay circuit, so as to determine whether the unit under test 130 can work normally, flexibly adapt to the test requirements of the unit under test 130, and improve the test accuracy of the unit under test 130.

[0034] In some exemplary embodiments, the control unit is also used to generate multiple different types of excitation signals, and each excitation signal corresponds to a delay circuit; the excitation signal includes at least one of the address signal, bit write enable signal, read / write enable signal and chip enable signal of the unit under test 130.

[0035] Among them, since each excitation signal corresponds to a delay circuit, the phase of the excitation signal corresponding to the delay circuit can be controlled by controlling the delay circuit, thereby changing the phase relationship of each excitation signal input into the unit under test 130 to meet the test requirements of the unit under test 130 in different test scenarios and improve test flexibility.

[0036] In some exemplary embodiments, each delay circuit includes a coarse adjustment unit (not shown in the figure) and / or a fine adjustment unit (not shown in the figure); the coarse adjustment unit is used to determine the delay range of the delay circuit based on the control signal; the fine adjustment unit is used to determine the delay accuracy within the delay range based on the control signal.

[0037] Each coarse adjustment unit and / or fine adjustment unit may be controlled individually, and each delay circuit may include at least one coarse adjustment unit and / or at least one fine adjustment unit.

[0038] In some embodiments, the delay range may be a preset range, and the fine-tuning unit may adjust the delay accuracy within the preset range based on the control signal to meet the testing requirements in different scenarios.

[0039] It should be noted that the adjustment of the delay level can be divided into two parts: using the coarse adjustment unit for large-scale adjustment and using the fine adjustment unit for small-scale adjustment, wherein the delay time of a large-scale of the coarse adjustment unit is equal to the delay time of k small-scales of the full scale, and the adjustment process is the process of the coarse adjustment unit and the fine adjustment unit acting in combination. Wherein, k is an integer greater than or equal to 1, for example, k is 16, etc.

[0040] For example, the coarse adjustment unit can adjust the delayed signal output by the delay circuit to two delay levels: the maximum value of the delayed signal (for example, the input original signal) and the minimum value of the delayed signal (for example, 0); and the fine adjustment unit can further subdivide the accuracy of the delay level of the delayed signal output by the delay circuit.

[0041] For example, the signal range between the maximum value of the delayed signal and the minimum value of the delayed signal is divided into n levels to obtain n delay levels, where n is an integer greater than or equal to 1. For example, when n is equal to 16, the clock length between 0 and the original signal input by the control unit can be divided into 16 equally divided 16 delay levels, so as to facilitate the adjustment of different delay levels of the original signal input by the control unit, so as to flexibly adapt to different test requirements in the test process.

[0042] In some exemplary embodiments, the signal delay circuit is used to test the signal setup test time or the signal hold test time in the timing parameters of the unit under test 130, and the plurality of delay circuits include a first delay circuit 121 and a second delay circuit 122;

[0043] The first delay circuit 121 is used to generate a first delay signal based on the original signal, and the first delay signal is used to delay the excitation signal generated by the control unit to generate a data latch test signal; the second delay circuit 122 is used to generate a second delay signal based on the original signal, and the second delay signal is used to delay the clock signal of the unit to be tested to generate a data read and write test signal;

[0044] The original signal is an original clock signal generated by the control unit, and the first delayed signal and the second delayed signal are clock delay signals of two different levels.

[0045] By inputting the data latch test signal into the test port corresponding to the excitation signal and inputting the data read-write test signal into the clock signal test port, it is possible to input different test signals into different test ports of the unit under test, so that the unit under test can work normally; and gradually adjust the rising edge of the data latch test signal and the rising edge of the data read-write test signal, so that the unit under test obtains the excitation signal and the clock signal with different phase relationships, thereby changing the output signal of the unit under test; further, by analyzing the output signal of the unit under test, it is possible to clarify whether the timing parameters of the unit under test meet the preset parameter setting requirements, and flexibly test the unit under test.

[0046] In some exemplary embodiments, when it is determined that the signal establishment test time or the signal holding test duration in the timing parameters of the unit under test 130 is completed, the third delay signal generated by the third delay circuit 123 is further used to test the data reading delay duration in the timing parameters of the unit under test.

[0047] Among them, the signal delay circuit is also used to test the data reading delay duration in the timing parameters of the unit to be tested. The multiple delay circuits also include: a third delay circuit 123, which is used to generate a third delay signal based on the original signal, and the third delay signal is used to delay the output signal of the unit to be tested.

[0048] By reading the data delay time, it is possible to clearly know the delay time required for the unit under test to read different output signals, thereby reducing the delay between the unit under test inside the chip and other modules in the chip, and improving the test accuracy of the timing parameters of the unit under test.

[0049] In some exemplary embodiments, the unit to be tested is a memory chip. For example, the unit to be tested may be a memory unit to be tested in an SRAM, or an internal module of a chip that needs to be tested for timing parameters.

[0050] By using at least two different levels of delay signals generated by a signal delay circuit, a memory cell to be tested in an SRAM or a chip internal module that requires timing parameter testing is directly tested. This can reduce the impact of interference signals outside the chip on the test results and reduce the test delay, thereby improving the test accuracy of the memory chip.

[0051] The signal delay circuit of the embodiment of the present application connects the input ends of multiple delay circuits to the same original signal end, and the output end of each delay circuit is used to connect the unit to be tested, so that the starting points of the delay signals output by the multiple delay circuits can be aligned, thereby simplifying the processing of the test time; and each delay circuit is used to delay the original signal of the same source input through the original signal end according to the control signal to generate a corresponding delayed signal. When testing the chip, the delay signal output by the delay circuit can be flexibly configured according to the test requirements, and the unit to be tested inside the chip can be directly tested, thereby improving the test accuracy of the timing parameters of each module inside the chip.

[0052] Figure 2 FIG. 1 is a flow chart of a timing parameter testing method provided by an embodiment of the present application. The timing parameter testing method can be applied to a control unit. Figure 2 As shown, the timing parameter testing method includes but is not limited to the following steps.

[0053] Step S201: Based on any one of the signal delay circuits in the embodiments of the present application, at least two delayed signals with different delay levels are obtained.

[0054] Wherein, at least two delayed signals with different delay levels originate from the same original signal.

[0055] Step S202: inputting at least two delay signals of different levels into the unit to be tested to test the timing parameters of the unit to be tested.

[0056] In this embodiment, by obtaining at least two delay signals with different delay levels based on any one of the signal delay circuits in the embodiments of the present application, and at least two delay signals with different delay levels originate from the same original signal, it is possible to align the starting points of the delay signals output by multiple delay circuits, thereby simplifying the processing of the test time; at least two delay signals of different levels are input into the unit to be tested, and the timing parameters of the unit to be tested are tested, so that the at least two delay signals of different levels can flexibly adapt to the test requirements of the unit to be tested, thereby improving the test accuracy of the timing parameters of the unit to be tested.

[0057] Among them, when the unit to be tested is SRAM, the timing parameters of the unit to be tested may include at least one of transmission delay time, setup time, data retention time, operating frequency, and addressing access time. The test indicators corresponding to the above-mentioned multiple different timing parameters can reflect the performance of the unit to be tested to determine whether the unit to be tested meets normal working requirements.

[0058] In some exemplary embodiments, the at least two delay signals of different levels include a first delay signal and a second delay signal; before inputting the at least two delay signals of different levels into the unit under test in step S202 and testing the timing parameters of the unit under test, the method further includes:

[0059] The first delayed signal is applied to the excitation signal to determine the data latch test signal; the second delayed signal is applied to the clock signal of the unit to be tested to determine the data read-write test signal.

[0060] The excitation signal includes at least one of an address signal of the unit under test, a bit write enable signal, a read / write enable signal and a chip enable signal.

[0061] For example, the first delayed signal is applied to the bit write enable signal to obtain a data latch test signal corresponding to the bit write enable signal; the first delayed signal is applied to the read / write enable signal to obtain a data latch test signal corresponding to the read / write enable signal; the first delayed signal is applied to the chip enable signal to obtain a data latch test signal corresponding to the chip enable signal; and so on.

[0062] Furthermore, the second delayed signal is applied to the clock signal of the unit under test to obtain a data read / write test signal. By applying the first delayed signal to different excitation signals respectively, the phase relationship between the data latch test signal and the data read / write test signal corresponding to different excitation signals can be changed, thereby facilitating the realization of different test requirements and flexibly testing the unit under test.

[0063] In some exemplary embodiments, the step S202 of inputting at least two delay signals of different levels into the unit under test to test the timing parameters of the unit under test may be implemented in the following manner:

[0064] The data latch test signal and the data read-write test signal are respectively input into different test ports in the unit under test; the rising edge of the data latch test signal and the rising edge of the data read-write test signal are respectively dynamically adjusted, and the adjusted data latch test signal and the adjusted data read-write test signal are applied to the unit under test to obtain the output signal of the unit under test; the output signal of the unit under test is analyzed to determine the test result of the timing parameter of the unit under test.

[0065] The different test ports in the unit under test may include a test port corresponding to an excitation signal, a clock signal test port, and the like.

[0066] By inputting the data latch test signal into the test port corresponding to the excitation signal and inputting the data read-write test signal into the clock signal test port, it is possible to input different test signals into different test ports of the unit under test, so that the unit under test can work normally; and gradually adjust the rising edge of the data latch test signal and the rising edge of the data read-write test signal, so that the unit under test obtains the excitation signal and the clock signal with different phase relationships, thereby changing the output signal of the unit under test; further, by analyzing the output signal of the unit under test, it is possible to clarify whether the timing parameters of the unit under test meet the preset parameter setting requirements, and flexibly test the unit under test.

[0067] In some exemplary embodiments, before dynamically adjusting the rising edge of the data latch test signal and the rising edge of the data read / write test signal, respectively, the method further includes: determining the address signal of the unit to be tested; and determining that the bit write enable signal, the read / write enable signal and the chip enable signal of the unit to be tested are all in a valid state.

[0068] The valid state is used to indicate that when each different signal is at a high level or a low level, it is determined that the signal is available.

[0069] For example, the chip enable signal is set to a low level, the bit write enable signal or the read / write enable signal is set to a high level, and the address signal of the unit under test is obtained, so as to effectively control and test the unit under test.

[0070] In some exemplary embodiments, when testing the signal setup test time in the timing parameters of the unit under test, dynamically adjusting the rising edge of the data latch test signal and the rising edge of the data read / write test signal respectively includes:

[0071] Adjust the delay level corresponding to the data latch test signal and the delay level corresponding to the data read and write test signal respectively, so that the rising edge of the data read and write test signal is earlier than the rising edge of the data latch test signal, and obtain the sampling time corresponding to the rising edge of the data read and write test signal; increase the delay level corresponding to the data latch test signal in sequence, so that the rising edge of the data latch test signal gradually approaches the rising edge of the data read and write test signal.

[0072] Among them, the data latch test signal and the data read-write test signal can be coarse-adjusted respectively first, so that the phase relationship between the data latch test signal and the data read-write test signal meets the requirement that the unit under test can work normally, for example, so that the rising edge of the data read-write test signal is earlier than the rising edge of the data latch test signal.

[0073] Furthermore, the data latch test signal and the data read-write test signal can be fine-tuned. For example, the delay level corresponding to the data latch test signal can be gradually increased to dynamically adjust the delay level corresponding to the data latch test signal in real time, so that the rising edge of the data latch test signal gradually approaches the rising edge of the data read-write test signal. In the process of fine-tuning the data latch test signal, the phase relationship between the data latch test signal and the data read-write test signal can be slightly changed, thereby changing the output signal of the unit under test. By analyzing the changes in the output signal, the corresponding changes in the timing parameters of the unit under test under the action of different data latch test signals and data read-write test signals can be clearly understood.

[0074] For example, when it is determined that the output signal of the unit under test has a signal flip, the adjustment of the delay level of the data latch test signal is stopped, and the moment before the output signal of the unit under test has a signal flip is obtained; based on the difference between the moment before the output signal of the unit under test has a signal flip and the sampling moment corresponding to the rising edge of the data read / write test signal, the signal setup test time corresponding to the unit under test is determined, so that the signal setup test time obtained by the test is more accurate.

[0075] In some exemplary embodiments, when testing the signal holding test duration in the timing parameters of the unit under test, dynamically adjusting the rising edge of the data latch test signal and the rising edge of the data read / write test signal respectively includes:

[0076] Adjust the delay level corresponding to the data latch test signal and the delay level corresponding to the data read / write test signal respectively, so that the rising edge of the data latch test signal is earlier than the rising edge of the data read / write test signal, and obtain the sampling time corresponding to the rising edge of the data read / write test signal; reduce the delay level corresponding to the data latch test signal in turn, so that the rising edge of the data latch test signal gradually approaches the rising edge of the data read / write test signal.

[0077] Among them, by coarsely adjusting the data latch test signal and the data read-write test signal respectively (for example, adjusting the delay level of each signal to maximum or minimum, etc.), so that the rising edge of the data latch test signal is earlier than the rising edge of the data read-write test signal, the data latch test signal and the data read-write test signal input into the unit to be tested can meet the test requirements of the signal holding test time in the timing parameters of the unit to be tested.

[0078] Furthermore, the delay level corresponding to the data latch test signal is lowered in sequence to adjust the delay level corresponding to the data latch test signal in real time and dynamically, so that the rising edge of the data latch test signal gradually approaches the rising edge of the data read-write test signal, thereby in the process of fine-tuning the data latch test signal, the phase relationship between the data latch test signal and the data read-write test signal can be slightly changed, so that the output signal of the unit under test is changed, and by analyzing the changes in the output signal, the corresponding changes in the timing parameters of the unit under test under the action of different data latch test signals and data read-write test signals can be clearly understood.

[0079] For example, analyzing the output signal of the unit under test to determine the test result of the timing parameters of the unit under test, including: when it is determined that the output signal of the unit under test undergoes a signal flip, stopping the adjustment of the delay level of the data latch test signal, and obtaining the moment before the output signal of the unit under test undergoes a signal flip; based on the moment before the output signal of the unit under test undergoes a signal flip and the sampling moment corresponding to the rising edge of the data read and write test signal, determining the signal setup test time corresponding to the unit under test or the signal hold test duration of the unit under test.

[0080] Among them, if the moment before the output signal of the unit under test flips is set as Ta, and the sampling moment corresponding to the rising edge of the data read and write test signal is Tb, then the signal holding test duration of the unit under test is Ta-Tb; the signal establishment test time corresponding to the unit under test is Tb-Ta.

[0081] In some exemplary embodiments, the at least two different levels of delay signals further include a third delay signal; the test signal further includes a data capture test signal, the data capture test signal is a signal determined by applying the third delay signal to the output signal of the unit under test;

[0082] In the case of testing the data read delay time in the timing parameters of the unit under test, the rising edge of the data latch test signal and the rising edge of the data read and write test signal are dynamically adjusted respectively, including: in the case of determining that the signal establishment test time of the unit under test and the signal holding test time of the unit under test are completed, respectively adjusting the delay level corresponding to the data capture test signal and the delay level corresponding to the data read and write test signal, so that the rising edge of the data capture test signal is earlier than the rising edge of the data read and write test signal, and obtaining the sampling time corresponding to the rising edge of the data read and write test signal; determining the data establishment time of a trigger (for example, a D type flip-flop (DFF trigger), which can simultaneously support the measurement of the signal establishment time, the signal holding time, and the signal read delay time, etc.) connected to the unit under test; and sequentially reducing the delay level corresponding to the data capture test signal, so that the rising edge of the data capture test signal gradually approaches the rising edge of the data read and write clock signal;

[0083] The output signal of the unit under test is analyzed to determine the test result of the timing parameter of the unit under test, including: when it is determined that the output signal of the unit under test undergoes a signal flip, stopping the adjustment of the delay level of the data capture test signal, and obtaining the moment before the output signal of the unit under test undergoes a signal flip; based on the moment before the output signal of the unit under test undergoes a signal flip, the sampling moment corresponding to the rising edge of the data read and write test signal, and the data establishment time of the trigger, determining the data read delay time of the unit under test.

[0084] Among them, the trigger connected to the unit under test is used to capture the output signal of the unit under test based on the data capture test signal to obtain the output signal of the unit under test at different sampling times, which is convenient for testing the data reading delay time of the unit under test.

[0085] For example, the data reading delay time of the unit under test is equal to the difference obtained by subtracting the sampling time corresponding to the rising edge of the data read and write test signal and the data establishment time of the trigger from the moment before the output signal of the unit under test flips. Through the data reading delay time, it is possible to clearly know the delay time required for the unit under test to read different output signals, reduce the delay between the unit under test inside the chip and other modules in the chip, and improve the test accuracy of the timing parameters of the unit under test.

[0086] Figure 3 FIG. 1 is a block diagram showing a timing parameter test system provided by an embodiment of the present application. Figure 3 As shown, the timing parameter testing system 300 includes but is not limited to the following units: a control unit 310, a unit to be tested 320, and any signal delay circuit 330 in the embodiments of the present application.

[0087] The signal delay circuit 330 includes multiple delay circuits, the input terminals of all the delay circuits are connected to the same original signal terminal (not shown in the figure), and the output terminal of the signal delay circuit 330 is connected to the input terminal of the unit under test 320.

[0088] The signal delay circuit 330 is used to delay the original signal of the same source input through the original signal terminal according to the control signal input by the control unit 310, and generate a corresponding delayed signal.

[0089] The unit under test 320 is used to receive multiple delayed signals input by multiple delay circuits in the signal delay circuit 330, apply the multiple delayed signals to different test ports in the unit under test 320 respectively, generate output signals, and output the output signals to the control unit 310.

[0090] In this embodiment, by obtaining at least two delay signals with different delay levels based on any one of the signal delay circuits in the embodiments of the present application, and at least two delay signals with different delay levels originate from the same original signal, it is possible to align the starting points of the delay signals output by multiple delay circuits, thereby simplifying the processing of the test time; at least two delay signals of different levels are input into the unit to be tested, and the timing parameters of the unit to be tested are tested, so that at least two delay signals of different levels act on different test ports in the unit to be tested, respectively, wherein different levels of delay signals can be delayed for test signals of different test ports, thereby changing the phases of test signals corresponding to different test ports in the unit to be tested, so that the unit to be tested can obtain test signals with different phases, which not only improves the test flexibility of the unit to be tested, but also can improve the test accuracy of the unit to be tested.

[0091] In some exemplary embodiments, the control unit 310 is used to execute any one of the timing parameter testing methods in the embodiments of the present application, test the timing parameters of the unit under test 320, and analyze the output signal input to the unit under test 320 to determine the test results of the timing parameters of the unit under test 320.

[0092] By delaying the original signal of the same source input through the original signal end of the control unit according to the control signal input by the control unit based on any one of the signal delay circuits in the embodiments of the present application, and generating a corresponding delay signal, it is possible to align the starting points of the delay signals output by multiple delay circuits, thereby simplifying the processing of the test time; using the control unit to execute any one of the timing parameter testing methods in the embodiments of the present application, multiple delay signals of different levels are input to the unit under test, and the timing parameters of the unit under test are tested. When the unit under test receives multiple delay signals input by the signal delay circuit, the unit under test can respectively apply the multiple delay signals to different test ports in the unit under test, so that Delay signals of different levels can perform delay processing on test signals of different test ports, thereby changing the phases of test signals corresponding to different test ports in the unit under test, so that the unit under test can obtain test signals of different phases, thereby generating output signals under the action of test signals of different phases, and outputting the output signals to the control unit, so that the control unit can analyze the output signals input to the unit under test, determine the test results of the timing parameters of the unit under test, so that multiple delay signals of different levels can flexibly adapt to the test requirements of the unit under test, and directly test the unit under test inside the chip, thereby improving the test accuracy of the timing parameters of each module inside the chip.

[0093] Figure 4 FIG. 1 is a block diagram showing a timing parameter test system provided by an embodiment of the present application. Figure 4 As shown, the timing parameter testing system 400 includes but is not limited to the following units: a control unit 410, a unit to be tested 420, a signal delay circuit 430, multiple latches (for example, a first latch 441, a second latch 442, a third latch 443 and a fourth latch 444, etc.), and a trigger 450, etc.

[0094] The control unit 410 may be implemented using a field programmable gate array (FPGA) chip. The unit under test 420 includes a plurality of signal ports, for example, Figure 4 The address signal port shown (ADDR[m:0], m is an integer greater than or equal to 1, for example, when m is equal to 9, the ADDR[9:0] port can be obtained), the DI[n:0] port (for example, when n is equal to 3, the DI[3:0] port can be obtained), the write enable signal port (WEB[n:0], n is an integer greater than or equal to 1, for example, when n is equal to 3, the WEB[3:0] port can be obtained), the chip enable signal (CEB) port, the read / write enable signal (GWEB) port, the clock signal (CLK) port, the DQ[3:0] port, etc. Among them, the OTHERS port represents other ports in the unit under test 420.

[0095] In some embodiments, the initial state parameters pre-set by the host computer (e.g., the control unit 410) can be used to configure the initial state of all ports in the unit under test 420. For example, during testing, only one set of preset register tables needs to be configured, and the initial state of all ports in the unit under test 420 (e.g., the initial state of the GWEB port, the address signal port, the bit write enable signal port, etc.) is configured based on the initial state parameters stored in the set of preset register tables, so that the unit under test 420 can perform normal data read and write operations.

[0096] In some embodiments, the unit to be tested 420 may be a memory unit to be tested in an SRAM, or an internal module of a chip that needs to be tested for timing parameters.

[0097] The signal delay circuit 430 includes a plurality of delay circuits (not shown in the figure), each of which includes a coarse adjustment unit and a fine adjustment unit. Figure 4 As shown, the first delay circuit (not shown in the figure) includes a first coarse adjustment unit 4311 and a first fine adjustment unit 4312; the second delay circuit (not shown in the figure) includes a second coarse adjustment unit 4321 and a second fine adjustment unit 4322; the third delay circuit (not shown in the figure) includes a third coarse adjustment unit 4331 and a third fine adjustment unit 4332; the fourth delay circuit (not shown in the figure) includes a fourth coarse adjustment unit 4341 and a fourth fine adjustment unit 4342.

[0098] The first delay circuit is used to input the first delay signal generated by it into the first latch 441, so as to act on the excitation signal output by the control unit 410 (for example, at least one of the address signal, the bit write enable signal, the read / write enable signal and the chip enable signal of the unit to be tested 420) to obtain a data latch test signal (for example, marked as a LATCH_CLK signal). It should be noted that each excitation signal corresponds to a delay circuit, wherein the first delay circuit may include a plurality of first fine adjustment units 4312. For example, if there are 30 first fine adjustment units 4312, each first fine adjustment unit 4312 is respectively combined with the first coarse adjustment unit 4311 to obtain 30 different delay circuits, so that corresponding signal delays can be performed for 30 different excitation signals.

[0099] The second delay circuit is used to input the first delay signal generated by it into the second latch 442, so as to act on the clock signal corresponding to a CLK port of the unit under test 420 to obtain a first data read / write test signal (eg, marked as LCLKA signal).

[0100] The third delay circuit is used to input the third delayed signal generated by it into the third latch 443, so as to act on the clock signal corresponding to another CLK port of the unit under test 420 to obtain a second data read and write test signal (for example, marked as LCLKB signal).

[0101] The fourth delay circuit is used to input the fourth delay signal it generates (for example, marked as a data capture test (CAPTURE_CLK) signal) into the fourth latch 444 to capture the output signal of the output port of the unit under test 420. By triggering the trigger 450, the output signal of the output port of the unit under test 420 is processed using the fourth delay signal to obtain the DOUT signal, that is, the output signal that needs to be analyzed by the control unit 410.

[0102] Since each delay circuit uses the original signal input from the same original signal terminal as the starting signal of the signal, it is possible to align the starting points of the delay signals generated by each delay circuit, and in the process of signal testing, it is possible to facilitate the calculation of the difference between the delay signals generated by each delay circuit. In addition, the original signal input from the original signal terminal of the control unit 410 can be delayed at different levels through each delay circuit, so that the phase relationship of the delay signals of different levels acting on multiple different signals (e.g., excitation signal, clock signal (LCLKA), etc.) input to the unit under test 420 can be adjusted to meet the test requirements of the unit under test 420.

[0103] In some embodiments, the original signal input to the original signal terminal can be a clock signal of different frequencies generated by the internal clock resources of the control unit 410, so that when the unit under test 420 is at different clock frequencies, different test modes can be flexibly configured, which is convenient for testing the unit under test 420, has test versatility and portability, and reduces chip testing costs.

[0104] The coarse adjustment unit is used to determine the delay range of the delay circuit based on the control signal input by the control unit 410; the fine adjustment unit is used to determine the delay accuracy within the delay range based on the control signal input by the control unit 410. For example, the coarse adjustment unit can adjust the delay signal output by the delay circuit to two delay levels of the maximum value of the delay signal and the minimum value of the delay signal; and the fine adjustment unit can further subdivide the accuracy of the delay level of the delay signal output by the delay circuit.

[0105] For example, the signal range between the minimum value of the delay signal (e.g., 0) and the maximum value of the delay signal (e.g., the original signal input by the control unit 410) can be divided into n levels to obtain n delay levels, where n is an integer greater than or equal to 1. For example, when n is equal to 16, the clock length between 0 and the original signal input by the control unit 410 can be divided into 16 equally divided 16 delay levels, so as to facilitate the adjustment of different delay levels of the original signal input by the control unit 410, so as to flexibly adapt to different test requirements in the test process.

[0106] The unit under test 420 includes at least one of a data read (Read) operation state, a data write (Write) operation state and a data hold (Standby) operation state. In the data hold operation state, the unit under test 420 needs to be powered normally. The operation sequence corresponding to the data read operation state is the read operation sequence, and the operation sequence corresponding to the data write operation state is the write operation sequence.

[0107] For example, before performing different timing parameters on the unit under test 420, it is also necessary to determine the address signal of the unit under test 420; determine that the bit write enable signal, read / write enable signal, and chip enable signal of the unit under test 420 are all in a valid state. For example, the CEB signal is set to a low level, the WEN / GWEB signal is set to a high level, and the address signal of the unit under test 420 is obtained, so as to effectively control and test the unit under test 420.

[0108] In some exemplary embodiments, Figure 5 A timing diagram of a read operation on data in a unit under test provided by an embodiment of the present application is shown.

[0109] like Figure 5 As shown, CK represents the clock signal; ADDR[m-1:0] represents the address signal; WEN / GWEB represents the bit write enable signal / read / write enable signal, which is valid when the WEN / GWEB signal is at a high level; CEB represents the chip enable signal, which is valid when the CEB is at a low level; DQ[w-1:0] represents the data output signal, and w is an integer greater than 1. Q-1 represents the data output signal at the previous moment, and Q represents the data output signal at the current moment. Trc represents the effective duration of a clock signal CK.

[0110] It should be noted that when the chip enable signal CEB is at a high level, it indicates that the data read and write channel of the unit under test 420 is closed. At this time, the unit under test 420 can maintain the original data storage state, but cannot perform read and write operations on the unit under test 420.

[0111] When the chip enable signal CEB is set to a low level and WEN / GWEB is set to a high level, an address signal is input to the unit under test 420 through the address signal ADDR[m-1:0]. At this time, the unit under test 420 enters a data read operation state.

[0112] By inputting different signals to the chip enable signal CEB, the address signal ADDR[m-1:0], and WEN / GWEB, the working state of the unit under test 420 can be controlled, and each signal is triggered or locked based on the rising edge of the clock signal CK. Further, the data output signal DQ[w-1:0] will output the data in the form of an output signal after a delay of a period of time.

[0113] Among them, before the rising edge of the clock signal CK arrives, Figure 5 The Tas, Tws and Tces shown represent the signal setup test time (Setup time). Tas represents the input duration of the address signal ADDR[m-1:0], Tws represents the duration that the WEN / GWEB signal is at a high level, and Tces represents the duration that the CEB is at a low level.

[0114] After the rising edge of the clock signal CK arrives, Figure 5 The Tah, Twh and Tceh shown in the figure represent the signal hold test time (Hold time). Tah represents the input time of the address signal ADDR[m-1:0] after the rising edge of the clock signal CK arrives, Tws represents the time when the WEN / GWEB signal is at a high level, and Tces represents the time when CEB is at a low level.

[0115] Tcq represents the delay time from the rising edge of the clock signal CK starting to act on the unit under test 420 to the unit under test 420 outputting valid data, and is used to characterize the minimum delay time for data reading when the unit under test 420 is in a normal working state. The end time of Tcq is the time when the data output signal DQ[w-1:0] is flipped (i.e., the output data signal Q-1 is changed to the output data signal Q).

[0116] In some exemplary embodiments, Figure 6 FIG. 1 is a timing diagram of testing the signal establishment test time in the timing parameters of the unit under test provided by an embodiment of the present application. Figure 6 As shown, LATCH_CLK indicates the Figure 4 The signal delay of the first coarse adjustment unit 4311 and the first fine adjustment unit 4312 is input to the data latch test signal of the unit under test 420 through the first latch 441.

[0117] LCLKA indicates the Figure 4 The signal delay of the second coarse adjustment unit 4321 and the second fine adjustment unit 4322 is input to the first data read / write test signal of the CLK port of the unit under test 420 through the second latch 442.

[0118] Q represents the output signal of the unit under test 420 through the DQ[3:0] port; CAPTURE_CLK represents the output signal of the unit under test 420 through the DQ[3:0] port; Figure 4 The fourth delayed signal (or, referred to as a data capture test signal) is obtained by delaying the signals of the fourth coarse adjustment unit 4341 and the fourth fine adjustment unit 4342.

[0119] By adjusting the delay level corresponding to the LATCH_CLK signal and the delay level corresponding to the LCLKA signal respectively, so that the rising edge of the LCLKA signal is earlier than the rising edge of the LATCH_CLK signal, a sampling time (for example, marked as T1) corresponding to the rising edge of the LCLKA signal is obtained; further, the delay level corresponding to the LATCH_CLK signal is sequentially increased so that the rising edge of the LATCH_CLK signal gradually approaches the rising edge of the LCLKA signal, and the adjusted LATCH_CLK signal and the adjusted LCLKA signal are applied to the unit under test 420 to obtain the output signal of the unit under test 420;

[0120] When it is determined that the output signal of the unit under test 420 undergoes a signal flip (for example, the DQ signal of the unit under test 420 jumps from output signal 1 to output signal 0, or from output signal 0 to output signal 1), stop adjusting the delay level of the LATCH_CLK signal, and obtain the previous moment (for example, marked as T2) when the output signal of the unit under test 420 undergoes a signal flip; at this time, it can be determined that the signal setup test time Tsetup corresponding to the unit under test 420 is T2-T1.

[0121] For example, Figure 7 The flowchart of the test method for the signal establishment test time in the timing parameters of the unit under test provided by the embodiment of the present application is shown. Figure 7 As shown, the test method includes but is not limited to the following steps.

[0122] Step S701, selecting the unit to be tested 420.

[0123] For example, the control unit 410 (or other host computers with control functions, etc.) sends instructions to select a storage unit to be tested in the SRAM as the unit to be tested 420 .

[0124] In step S702, the control unit 410 sends a first control signal to the first delay circuit in the signal delay circuit 430, and applies the first control signal to the first coarse adjustment unit 4311 and the first fine adjustment unit 4312 in the first delay circuit, so that the first delay circuit sets the delay signal it outputs to the minimum value of the delay signal.

[0125] For example, the minimum value of the delay signal is 0. The delay signal output by the first delay circuit can act on the excitation signal sent by the control unit 410 (for example, Figure 5 The ADDR[m-1:0] signal, WEN / GWEB signal, and CEB signal shown in the figure) are adjusted to the minimum signal value.

[0126] It should be noted that all excitation signals need to be triggered by the rising edge of the LATCH_CLK signal output by the first delay circuit, and the first latch 441 is used to trigger the LATCH_CLK signal. Figure 6 The captured LATCH_CLK clock signal in the first latch 441 is captured, and the captured signal is stored in the first latch 441 to wait for the second delay circuit in the signal delay circuit 430 to output the signal. Figure 6 The arrival of the rising edge of the LCLKA signal is shown.

[0127] In step S703, the control unit 410 sends a second control signal to the second delay circuit in the signal delay circuit 430, and applies the second control signal to the second coarse adjustment unit 4321 and the second fine adjustment unit 4322 in the second delay circuit, so that the second delay circuit sets the delay signal it outputs to the maximum value of the delay signal.

[0128] For example, the maximum value of the delayed signal output by the second delay circuit may be the original signal output by the original signal terminal of the control unit 410, so that the rising edge of the LCLKA signal is earlier than the rising edge of the LATCH_CLK signal. At this time, the sampling time corresponding to the rising edge of the LCLKA signal is obtained (for example, marked as T1).

[0129] In step S704, the control unit 410 sends a third control signal to the fourth delay circuit in the signal delay circuit 430, and the third control signal is applied to the fourth coarse adjustment unit 4341 and the fourth fine adjustment unit 4342 in the fourth delay circuit, so that the fourth delay circuit sets the delay signal output by the fourth delay circuit to the maximum value of the delay signal; at the same time, the signal output by the trigger 450 is set to the maximum value in the delay level.

[0130] For example, the maximum value of the delayed signal output by the fourth delay circuit can be the original signal output by the original signal terminal of the control unit 410. Figure 6The CAPTURE_CLK shown captures the signal output from the DQ[3:0] port of the unit under test 420, and performs data sampling when the rising edge of CAPTURE_CLK arrives to obtain the output signal DOUT.

[0131] In step S705, the control unit 410 sends a fourth control signal to fine-tune the delay level of each delay circuit in the signal delay circuit 430. Each time a delay level is adjusted, an output signal DOUT is obtained, and the output signal DOUT is compared with the external input signal corresponding to the unit under test 420.

[0132] It should be noted that the adjustment of the delay level can be divided into two parts: using the coarse adjustment unit for large-speed adjustment and using the fine adjustment unit for small-speed adjustment. Among them, the delay time of a large-speed gear of the coarse adjustment unit is equal to the delay time of 16 small-speed gears of the full scale. The adjustment process is the process of combined action of the coarse adjustment unit and the fine adjustment unit.

[0133] For example, the fourth control signal is applied to the first coarse adjustment unit 4311 in the signal delay circuit 430 to adjust the large gear in the first coarse adjustment unit 4311 first; then, the fourth control signal is applied to the first fine adjustment unit 4312 to gradually adjust the delay time of each small gear in the first fine adjustment unit 4312 according to the delay level; so that the delay level corresponding to the LATCH_CLK signal output by the first delay circuit is gradually improved, thereby achieving the effect of gradually bringing the rising edge of the LATCH_CLK signal closer to the rising edge of the LCLKA signal.

[0134] Step S706 , determining whether the output signal DOUT of the unit under test 420 has a signal inversion.

[0135] For example, the output signal DOUT of the unit under test 420 may be inverted when: the DQ signal of the unit under test 420 changes from output signal 1 to output signal 0, or changes from output signal 0 to output signal 1.

[0136] If it is determined that the output signal DOUT of the unit under test 420 is inverted, step S707 is executed; if it is determined that the output signal DOUT of the unit under test 420 is not inverted, the execution returns to step S705.

[0137] Step S707 , stop adjusting the delay level of the LATCH_CLK signal, and record the time before the output signal DOUT of the unit under test 420 is flipped.

[0138] The time before the output signal DOUT of the unit under test 420 is reversed may be recorded as T2.

[0139] Step S708 , determining the signal setup test time Tsetup corresponding to the unit under test 420 based on the difference between T2 and T1 .

[0140] In some exemplary embodiments, Figure 8 A timing diagram for testing a signal holding test duration in a timing parameter of a unit under test provided by an embodiment of the present application is shown. Figure 8 The individual signals shown in Figure 6 The meanings of the signals shown in are the same and will not be repeated here.

[0141] In the process of testing the signal holding test duration in the timing parameters of the unit under test 420, it is necessary to adjust the delay level corresponding to the LATCH_CLK signal and the delay level corresponding to the LCLKA signal respectively, so that the rising edge of the LATCH_CLK signal is earlier than the rising edge of the LCLKA signal, and obtain the sampling time (for example, marked as T3) corresponding to the rising edge of the LCLKA signal; sequentially reduce the delay level corresponding to the LATCH_CLK signal, so that the rising edge of the LATCH_CLK signal gradually approaches the rising edge of the LCLKA signal; apply the adjusted LATCH_CLK signal and the adjusted LCLKA signal to the unit under test 420, and obtain the output signal of the unit under test 420;

[0142] When it is determined that the output signal of the unit under test 420 undergoes a signal flip (for example, the DQ signal of the unit under test 420 changes from output signal 1 to output signal 0, or from output signal 0 to output signal 1), the adjustment of the delay level of the LATCH_CLK signal is stopped, and the moment when the output signal of the unit under test 420 undergoes a signal flip is the critical point of the signal holding time of the unit under test 420, and the moment before the output signal of the unit under test undergoes a signal flip (for example, marked as T4) is obtained; at this time, it can be determined that the signal holding test duration Thold of the unit under test 420 is T4-T3.

[0143] For example, Fig. 9 A flow chart showing a method for testing the duration of a signal hold test in a timing parameter of a unit under test provided by an embodiment of the present application is shown. Fig. 9 As shown, the test method includes but is not limited to the following steps.

[0144] Step S901 , selecting a unit to be tested 420 .

[0145] For example, the control unit 410 (or other host computers with control functions, etc.) sends instructions to select a storage unit to be tested in the SRAM as the unit to be tested 420 .

[0146] In step S902, the control unit 410 sends a first control signal to the first delay circuit in the signal delay circuit 430, and applies the first control signal to the first coarse adjustment unit 4311 and the first fine adjustment unit 4312 in the first delay circuit, so that the first delay circuit sets the delay signal it outputs to the maximum value of the delay signal.

[0147] For example, the first coarse adjustment unit 4311 and the first fine adjustment unit 4312 are controlled based on the first control signal so that the maximum value of the delayed signal output by the first delay circuit is the original signal output by the original signal terminal of the control unit 410 .

[0148] The delayed signal output by the first delay circuit can act on the excitation signal sent by the control unit 410 (for example, Figure 5 The CK signal, ADDR[m-1:0] signal, WEN / GWEB signal, and CEB signal shown in the figure are adjusted to the maximum value of each excitation signal.

[0149] It should be noted that all excitation signals need to be output through the first delay circuit. Figure 8 The rising edge of the LATCH_CLK signal shown in FIG. 1 is triggered, the LATCH_CLK clock signal is captured by the first latch 441, and the captured signal is stored in the first latch 441 to wait for the second delay circuit in the signal delay circuit 430 to output the signal. Figure 8 The arrival of the rising edge of the LCLKA signal is shown.

[0150] In step S903, the control unit 410 sends a second control signal to the second delay circuit in the signal delay circuit 430, and applies the second control signal to the second coarse adjustment unit 4321 and the second fine adjustment unit 4322 in the second delay circuit, so that the second delay circuit sets the delay signal it outputs to the minimum value of the delay signal.

[0151] For example, the minimum value of the delay signal output by the second delay circuit may be 0, so that the rising edge of the LATCH_CLK signal is earlier than the rising edge of the LCLKA signal. At this time, the sampling time corresponding to the rising edge of the LCLKA signal is obtained (for example, marked as T3).

[0152] In step S904, the control unit 410 sends a third control signal to the fourth delay circuit in the signal delay circuit 430, and the third control signal is applied to the fourth coarse adjustment unit 4341 and the fourth fine adjustment unit 4342 in the fourth delay circuit, so that the fourth delay circuit sets the delay signal output by the fourth delay circuit to the maximum value of the delay signal; at the same time, the signal output by the trigger 450 is set to the maximum value in the delay level.

[0153] For example, the maximum value of the delayed signal output by the fourth delay circuit can be the original signal output by the original signal terminal of the control unit 410. Figure 8 The CAPTURE_CLK shown captures the signal output from the DQ[3:0] port of the unit under test 420, and performs data sampling when the rising edge of CAPTURE_CLK arrives to obtain the output signal DOUT.

[0154] In step S905, the control unit 410 sends a fourth control signal to fine-tune the delay level of each delay circuit in the signal delay circuit 430. Each time a delay level is adjusted, an output signal DOUT is obtained, and the output signal DOUT is compared with the external input signal corresponding to the unit under test 420.

[0155] For example, the fourth control signal is applied to the first fine adjustment unit 4312 in the signal delay circuit 430 to gradually reduce the delay level corresponding to the LATCH_CLK signal output by the first delay circuit, thereby gradually bringing the rising edge of the LATCH_CLK signal closer to the rising edge of the LCLKA signal.

[0156] Step S906 , determining whether the output signal DOUT of the unit under test 420 has a signal inversion.

[0157] For example, the output signal DOUT of the unit under test 420 may be inverted when: the DQ signal of the unit under test 420 changes from output signal 1 to output signal 0, or changes from output signal 0 to output signal 1.

[0158] If it is determined that the output signal DOUT of the unit under test 420 is inverted, step S907 is executed; if it is determined that the output signal DOUT of the unit under test 420 is not inverted, the execution returns to step S905.

[0159] Step S907 , stop adjusting the delay level of the LATCH_CLK signal, and record the time before the output signal DOUT of the unit under test 420 is flipped.

[0160] The time before the output signal DOUT of the unit under test 420 is reversed may be recorded as T4.

[0161] Step S908 , determining the signal holding test time Thold of the unit under test 420 based on the values ​​of T4 and T3 .

[0162] In some exemplary embodiments, during the process of testing the data read delay duration in the timing parameters of the unit under test, it is necessary to respectively adjust the delay level corresponding to the CAPTURE_CLK signal and the delay level corresponding to the LCLKA signal when it is determined that the test of the signal setup test time of the unit under test 420 and the signal hold test time of the unit under test 420 are completed, so that the rising edge of the CAPTURE_CLK signal is earlier than the rising edge of the LCLKA signal, and obtain the sampling time corresponding to the rising edge of the LCLKA signal (for example, marked as T5); determine the data setup duration (for example, marked as T6) of the trigger 450 connected to the unit under test 420; sequentially reduce the delay level corresponding to the CAPTURE_CLK signal, so that the rising edge of the CAPTURE_CLK signal gradually approaches the rising edge of the LCLKA signal; apply the adjusted CAPTURE_CLK signal to the trigger 450, and apply the LCLKA signal to the unit under test 420, and obtain the output signal DOUT of the unit under test 420.

[0163] Further, when it is determined that the output signal DOUT of the unit under test 420 undergoes a signal flip, the adjustment of the delay level of the CAPTURE_CLK signal is stopped, and the moment before the output signal of the unit under test 420 undergoes a signal flip (for example, marked as T7) is obtained; at this time, the data reading delay duration Tcq of the unit under test 420 can be determined to be T7-T6-T5.

[0164] For example, Fig.10 A flow chart of a method for testing the data read delay duration in the timing parameters of the unit under test provided by an embodiment of the present application is shown, wherein the data read delay duration is the Tcq of the unit under test 420 of a single port.

[0165] like Fig.10 As shown, the test method includes but is not limited to the following steps.

[0166] Step S1001 , selecting a unit to be tested 420 .

[0167] In step S1002, the control unit 410 sends a first control signal to the first delay circuit in the signal delay circuit 430, and applies the first control signal to the first coarse adjustment unit 4311 and the first fine adjustment unit 4312 in the first delay circuit, so that the first delay circuit sets the delay signal it outputs to the minimum value of the delay signal.

[0168] For example, the minimum value of the delay signal is 0, wherein the delay signal output by the first delay circuit can act on the excitation signal sent by the control unit 410 (for example, Figure 5The ADDR[m-1:0] signal, WEN / GWEB signal, and CEB signal shown in the figure) are adjusted to the minimum signal value.

[0169] It should be noted that all excitation signals need to be triggered by the rising edge of the LATCH_CLK signal output by the first delay circuit, and the first latch 441 is used to trigger the LATCH_CLK signal. Figure 6 The captured LATCH_CLK clock signal in the first latch 441 is captured, and the captured signal is stored in the first latch 441 to wait for the second delay circuit in the signal delay circuit 430 to output the signal. Figure 6 The arrival of the rising edge of the LCLKA signal is shown.

[0170] In step S1003, the control unit 410 sends a second control signal to the second delay circuit in the signal delay circuit 430, and applies the second control signal to the second coarse adjustment unit 4321 and the second fine adjustment unit 4322 in the second delay circuit, so that the second delay circuit sets the delay signal it outputs to the maximum value of the delay signal.

[0171] like Figure 5 As shown, it is necessary to determine Figure 5 The Tas / Tah, Tws / Twh and Tces / Tceh signals in the test circuit can meet the test requirements of the signal setup test time of the unit under test 420 and the signal hold test time of the unit under test 420. Further, by triggering the rising edge of the clock CK, the address signal ADDR[m-1:0] of the unit under test 420 is obtained, thereby completing the addressing operation of the unit under test 420. In addition, the CEB signal is set to a low level and the WEN / GWEB signal is set to a high level, so as to effectively control and test the unit under test 420.

[0172] At this time, the sampling time corresponding to the rising edge of the LCLKA signal is obtained (for example, marked as T5).

[0173] In step S1004, the control unit 410 sends a third control signal to the fourth delay circuit in the signal delay circuit 430, and the third control signal is applied to the fourth coarse adjustment unit 4341 and the fourth fine adjustment unit 4342 in the fourth delay circuit, so that the fourth delay circuit sets the delay signal output by the fourth delay circuit to the maximum value of the delay signal; at the same time, the signal output by the trigger 450 is set to the maximum value in the delay level.

[0174] like Figure 5 As shown, DQ[w-1:0] of the unit under test 420 outputs data after a delay of a period of time Tcq.

[0175] Step S1005 , determining the data establishment time length of the trigger 450 connected to the unit under test 420 .

[0176] The data establishment duration may be marked as T6.

[0177] In step S1006, the control unit 410 sends a fourth control signal to fine-tune the delay level of each delay circuit in the signal delay circuit 430. Each time a delay level is adjusted, an output signal DOUT is obtained, and the output signal DOUT is compared with the external input signal corresponding to the unit under test 420.

[0178] For example, the fourth control signal is applied to the fourth fine adjustment unit 4342 in the signal delay circuit 430, so that the delay level corresponding to the CAPTURE_CLK signal output by the fourth delay circuit is gradually reduced (i.e., adjusted from large to small), thereby achieving the effect of gradually bringing the rising edge of the CAPTURE_CLK signal closer to the rising edge of the LCLKA signal.

[0179] Step S1007 , determining whether the output signal DOUT of the unit under test 420 has a signal inversion.

[0180] For example, the output signal DOUT of the unit under test 420 may be inverted when: the DQ signal of the unit under test 420 changes from output signal 1 to output signal 0, or changes from output signal 0 to output signal 1.

[0181] If it is determined that the output signal DOUT of the unit under test 420 is inverted, step S1008 is executed; if it is determined that the output signal DOUT of the unit under test 420 is not inverted, the execution returns to step S1006.

[0182] Step S1008 , stop adjusting the delay level of the CAPTURE_CLK signal, and record the time before the output signal DOUT of the unit under test 420 is flipped.

[0183] The time before the output signal DOUT of the unit under test 420 is reversed may be recorded as T7.

[0184] Step S1009 , determining the data read delay time Tcq=T7-T6-T5 of the unit under test 420 .

[0185] It should be noted that the above test process for the timing parameters of the unit under test 420 is only an example. The signal delay circuit in the present application and the timing test system including the signal delay circuit can also be used to test the test time of signals such as address signals, bit write enable signals, read and write enable signals, and chip enable signals. Corresponding settings and debugging can be performed according to actual needs, which will not be repeated here.

[0186] It should be clear that the present invention is not limited to the specific configurations and processes described in the above embodiments and shown in the figures. For the convenience and brevity of description, a detailed description of the known methods is omitted here, and the specific working processes of the systems, modules and units described above can refer to the corresponding processes in the aforementioned method embodiments, which will not be repeated here.

[0187] By way of exemplary and non-limiting examples, a detailed description of exemplary embodiments of the present application has been provided above. However, various modifications and adjustments to the above embodiments will be apparent to those skilled in the art when considered in conjunction with the accompanying drawings and claims, but will not depart from the scope of the present invention. Therefore, the proper scope of the present invention will be determined according to the claims.

Claims

1. A signal delay circuit, characterized in that: include: Multiple delay circuits, the input ends of all the delay circuits are connected to the same original signal end, the output ends of each of the delay circuits are respectively connected to the unit to be tested, and each of the delay circuits is used to delay the original signal of the same source input through the original signal end according to the control signal to generate a corresponding delayed signal.

2. The signal delay circuit according to claim 1, characterized in that: The signal delay circuit further includes: The control unit is used to generate the control signal, and the control signal is used to control the delay level of each of the delay circuits.

3. The signal delay circuit according to claim 2, characterized in that: The control unit also includes: A signal receiving end, used to connect to the output end of the unit under test; The control unit is also used to analyze the signal received by the signal receiving end.

4. The signal delay circuit according to claim 2, characterized in that: Each of the delay circuits includes a coarse adjustment unit and a fine adjustment unit; The coarse adjustment unit is used to determine the delay range of the delay circuit based on the control signal; The fine adjustment unit is used to determine the delay accuracy within the delay range based on the control signal.

5. The signal delay circuit according to claim 2, characterized in that: The signal delay circuit is used to test the signal establishment test time or the signal holding test duration in the timing parameters of the unit under test, and the multiple delay circuits include a first delay circuit and a second delay circuit; The first delay circuit is used to generate a first delay signal based on the original signal, and the first delay signal is used to delay the excitation signal generated by the control unit to generate a data latch test signal; The second delay circuit is used to generate a second delayed signal based on the original signal, and the second delayed signal is used to delay the clock signal of the unit under test to generate a data read and write test signal; The original signal is an original clock signal generated by a control unit, and the first delayed signal and the second delayed signal are clock delay signals of two different levels.

6. The signal delay circuit according to claim 2, characterized in that: The signal delay circuit is also used to test the data read delay time in the timing parameters of the unit under test. The multiple delay circuits also include: a third delay circuit, The third delay circuit is used to generate a third delayed signal based on the original signal, and the third delayed signal is used to delay the output signal of the unit under test.

7. The signal delay circuit according to any one of claims 1 to 6, characterized in that: The unit to be tested is a memory chip.

8. A timing parameter testing method, characterized in that: The method comprises: Based on the signal delay circuit according to any one of claims 1 to 7, obtaining at least two delayed signals with different delay levels, wherein the at least two delayed signals with different delay levels are derived from the same original signal; The at least two delay signals of different levels are input into the unit to be tested to test the timing parameters of the unit to be tested.

9. The method according to claim 8, characterized in that The at least two delayed signals of different levels include a first delayed signal and a second delayed signal; Before inputting the at least two delay signals of different levels into the unit to be tested and testing the timing parameters of the unit to be tested, the method further comprises: Applying the first delayed signal to the excitation signal to determine the data latch test signal, wherein the excitation signal includes at least one of the address signal of the unit to be tested, the bit write enable signal, the read / write enable signal, and the chip enable signal; The second delayed signal is applied to the clock signal of the unit under test to determine a data read / write test signal.

10. The method according to claim 9, characterized in that Inputting the at least two delay signals of different levels into the unit to be tested to test the timing parameters of the unit to be tested includes: Inputting the data latch test signal and the data read-write test signal into different test ports in the unit under test respectively; Dynamically adjusting the rising edge of the data latch test signal and the rising edge of the data read / write test signal respectively, and applying the adjusted data latch test signal and the adjusted data read / write test signal to the unit under test to obtain an output signal of the unit under test; The output signal of the unit under test is analyzed to determine the test result of the timing parameter of the unit under test.

11. The method according to claim 10, characterized in that In the case of testing the signal establishment test time in the timing parameters of the unit under test, dynamically adjusting the rising edge of the data latch test signal and the rising edge of the data read / write test signal respectively, including: Respectively adjusting the delay level corresponding to the data latch test signal and the delay level corresponding to the data read / write test signal so that the rising edge of the data read / write test signal is earlier than the rising edge of the data latch test signal, and obtaining the sampling time corresponding to the rising edge of the data read / write test signal; The delay level corresponding to the data latch test signal is sequentially increased so that the rising edge of the data latch test signal gradually approaches the rising edge of the data read-write test signal.

12. The method according to claim 10, characterized in that In the case of testing the signal holding test duration in the timing parameters of the unit under test, dynamically adjusting the rising edge of the data latch test signal and the rising edge of the data read / write test signal respectively, including: Respectively adjusting the delay level corresponding to the data latch test signal and the delay level corresponding to the data read / write test signal so that the rising edge of the data latch test signal is earlier than the rising edge of the data read / write test signal, and obtaining the sampling time corresponding to the rising edge of the data read / write test signal; The delay level corresponding to the data latch test signal is sequentially reduced so that the rising edge of the data latch test signal gradually approaches the rising edge of the data read-write test signal.

13. The method according to claim 11 or 12, characterized in that: The step of analyzing the output signal of the unit under test to determine the test result of the timing parameter of the unit under test includes: When it is determined that the output signal of the unit under test has a signal flip, stop adjusting the delay level of the data latch test signal, and obtain the moment before the output signal of the unit under test has a signal flip; Based on the moment before the output signal of the unit under test flips and the sampling moment corresponding to the rising edge of the data read and write test signal, the signal setup test time corresponding to the unit under test or the signal hold test duration of the unit under test is determined.

14. The method according to claim 10, characterized in that The at least two delay signals of different levels further include a third delay signal; the test signal further includes a data capture test signal, and the data capture test signal is a signal determined by applying the third delay signal to the output signal of the unit under test; In the case of testing the data read delay duration in the timing parameters of the unit under test, respectively dynamically adjusting the rising edge of the data latch test signal and the rising edge of the data read / write test signal, including: When it is determined that the signal establishment test time of the unit under test and the signal holding test time of the unit under test are completed, respectively adjusting the delay level corresponding to the data capture test signal and the delay level corresponding to the data read-write test signal, so that the rising edge of the data capture test signal is earlier than the rising edge of the data read-write test signal, and obtaining the sampling time corresponding to the rising edge of the data read-write test signal; Determine the data establishment time of the trigger connected to the unit under test; Sequentially reduce the delay level corresponding to the data capture test signal so that the rising edge of the data capture test signal gradually approaches the rising edge of the data read / write clock signal; The step of analyzing the output signal of the unit under test to determine the test result of the timing parameter of the unit under test includes: When it is determined that the output signal of the unit under test undergoes a signal flip, the adjustment of the delay level of the data capture test signal is stopped, and a moment before the output signal of the unit under test undergoes a signal flip is acquired; The data read delay duration of the unit under test is determined based on the moment before the output signal of the unit under test flips, the sampling moment corresponding to the rising edge of the data read and write test signal, and the data establishment duration of the trigger.

15. The method according to claim 10, characterized in that Before dynamically adjusting the rising edge of the data latch test signal and the rising edge of the data read / write test signal respectively, the method further includes: Determining the address signal of the unit under test; It is determined that the bit write enable signal, the read / write enable signal and the chip enable signal of the unit under test are all in a valid state.

16. A timing parameter testing system, characterized in that: The system comprises: a control unit, a unit to be tested, and a signal delay circuit as claimed in any one of claims 1 to 7; The signal delay circuit is used to delay the original signal of the same source input through the original signal terminal according to the control signal input by the control unit, and generate a corresponding delayed signal; The unit under test is used to receive multiple delayed signals input by multiple delay circuits in the signal delay circuit, apply the multiple delayed signals to different test ports in the unit under test respectively, generate output signals, and output the output signals to the control unit.

17. The system according to claim 16, characterized in that The control unit is used to execute the timing parameter testing method as described in any one of claims 8 to 15, test the timing parameters of the unit under test, and analyze the output signal input to the unit under test to determine the test results of the timing parameters of the unit under test.

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