Method and assembly for depositing material in a gap

Abstract

The present disclosure relates to a method of depositing a silicon-containing material in a gap. The method includes providing a substrate including a gap, where the gap includes an inner surface, and exposing the substrate to a first plasma having a high ion energy to modify a predetermined region of the inner surface of the gap. The method further includes exposing the substrate to a second plasma having a low ion energy to passivate the modified region of the interstitial surface, thereby forming a passivated modified region on the interstitial surface, and contacting the substrate with a vapor phase silicon precursor to chemisorb the silicon precursor on the unmodified region of the interstitial surface, thereby forming a vapor phase silicon precursor on the unmodified region of the interstitial surface. Thereby depositing a material comprising silicon on the unmodified region. The present disclosure also relates to a method of controlling chemisorption of a vapor phase silicon precursor on a substrate, and a semiconductor processing assembly for performing the method according to the present disclosure.

Description

Technical Field

[0001] The present disclosure generally relates to methods and assemblies for processing semiconductor substrates. More specifically, the present disclosure relates to methods and assemblies for selectively depositing silicon-containing materials on semiconductor substrates. Background Art

[0002] Silicon oxide is used for various purposes in semiconductor devices. The ever-decreasing device dimensions require ever-improving control over growth rate and topological selectivity to allow the fabrication of such devices. Cyclic deposition methods such as atomic layer deposition and cyclic chemical vapor deposition can provide solutions to many of the challenges facing industry. In particular, plasma-enhanced methods may be suitable because they allow the use of low temperatures and are therefore compatible with the low thermal budgets of complex devices.

[0003] While various plasma-enhanced methods have been developed in the art, the inventors have recognized a continuing need for a more versatile and tunable method of depositing silicon-containing materials on substrates.

[0004] Any discussion set forth in this section, including discussion of problems and solutions, has been included in the present disclosure merely to provide a context for the present disclosure. Such discussion should not be considered as an admission that any information was known or constituted prior art at the time of the invention. Summary of the invention

[0005] This summary may introduce some concepts in a simplified form, which are further described in detail below. This summary is not intended to necessarily identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. Various embodiments of the present disclosure are directed to methods of depositing a material containing silicon in a gap and methods of controlling chemical adsorption of a vapor phase silicon precursor on a substrate. Embodiments of the present disclosure also relate to methods of manufacturing semiconductor devices, semiconductor devices, and semiconductor processing assemblies.

[0006] In one aspect, a method for depositing a material comprising silicon in a gap is disclosed. The method includes providing a substrate, the substrate including a gap, wherein the gap includes an inner surface, and exposing the substrate to a first plasma having a high ion energy to modify a predetermined region of the inner surface of the gap. The method also includes exposing the substrate to a second plasma having a low ion energy to passivate the modified region of the gap surface, thereby forming a passivated modified region on the gap surface, and contacting the substrate with a gas-phase silicon precursor to chemically adsorb the silicon precursor on the unmodified region of the gap, thereby depositing the material comprising silicon on the unmodified region.

[0007] In some embodiments, a substrate is provided in a reaction chamber and the substrate is exposed to a first plasma and a second plasma in the reaction chamber.

[0008] In some embodiments, passivation of the modified region comprises forming a nitrogen-containing terminus.

[0009] In some embodiments, the first plasma is generated by a gas selected from N, He, Ne, Ar, Kr, and Xe. In some embodiments, the second plasma includes nitrogen. In some embodiments, the second plasma is generated by a gas including at least one of N2, NH3, and N2H4. In some embodiments, the second plasma is generated by a gas including at least one of He, Ne, Ar, Kr, and Xe.

[0010] In some embodiments, the ion energy of the first plasma is at least about 15 eV. In some embodiments, the ion energy of the second plasma is at most 5 eV.

[0011] In some embodiments, the gap inner surface comprises an oxide surface. In some embodiments, the substrate comprises a silicon nitride surface.

[0012] In some embodiments, the silicon precursor is a nitrogen-containing silane containing 1 to 4 silicon atoms. In some embodiments, the silicon precursor is a silane having the formula Si a (NR2) b X cIt represents, wherein a is 1, 2, 3 or 4, b+c=2a+2, b is at least 1, each R is independently selected from H, methyl, ethyl, isopropyl, tert-butyl and phenyl, and each X is independently selected from H, methyl, ethyl, isopropyl, tert-butyl, phenyl, F, Cl, Br and I. In some embodiments, the silicon precursor is selected from SiH3[N(CH3)2], SiH3[N(CH2CH3)2], SiH3[N(CH3)(CH2CH3)], SiH3[N(C(CH3)3)2], SiH3[N(CH(CH3)2)2], SiH2[N(CH3)2]2, SiH2[N(CH2CH3)2]2, SiH2[N(CH3)(CH2CH3)]2, SiH2[N(C(CH3)3)2]2, SiH2[N(CH(CH3)2)2]2, SiH2[N(CH3)(CH2CH3)]2, SiH2[N(C(CH3)3)2]2, SiH2[N(CH(CH3)2)2]2, SiH(CH3)[N(CH3)2]2, SiH(CH3)[N(CH2CH3)2]2, SiH(CH3)[N(CH3)(CH2CH3)]2,SiH(CH3)[N(C(CH3)3)2]2,SiH(CH3)[N(CH(CH3)2)2]2,Si(CH3)2[N(CH3)2]2,S i(CH3)2[N(CH2CH3)2]2,Si(CH3)2[N(CH3)(CH2CH3)]2,Si(CH3)2[N(C(CH3)3)2]2,Si(CH3)2[N(CH(CH3)2)2]2 ,SiH[N(CH3)2]3,SiH[N(CH2CH3)2]3,SiH[N(CH3)(CH2CH3)]3,SiH[N(C(CH3)3)2]3,SiH[N(CH(CH3)2)2]3,Si[ N(CH3)2]4,Si[N(CH2CH3)2]4,Si[N(C(CH3)3)2]4,Si[N(CH(CH3)2)2]4,SiCl[N(CH3)2]3,SiCl[N(CH2CH3)2]3, SiCl[N(CH3)(CH2CH3)]3, SiCl[N(C(CH3)3)2]3,SiCl[N(CH(CH3)2)2]3, Si[NH(CH3)]3-Si[NH(CH3)]3,Si[NH(CH2CH3)]3-Si[NH(CH2CH3)]3,SiH2(NH(CH(CH3)2)2-SiH2.

[0013] In some embodiments, the gap includes a bottom, and the predetermined region modified by the first high energy plasma is the bottom.

[0014] In some embodiments, chemical adsorption of the silicon precursor on the passivated modified region is reduced by at least 60% relative to the unmodified region.

[0015] In some embodiments, the silicon-containing material is conformally deposited on the unmodified region of the gap. In some embodiments, the silicon-containing material at least partially fills the gap. In some embodiments, the gap is filled from the bottom of the gap upward.

[0016] In another aspect, a method of controlling chemical adsorption of a vapor-phase silicon precursor on a substrate having a surface is disclosed. The method includes providing a substrate in a reaction chamber, exposing the substrate to a first plasma having high ion energy to partially modify the surface, exposing the substrate to a second plasma having low ion energy to passivate the partially modified surface to form a partially passivated surface, and contacting the substrate with a vapor-phase silicon precursor to chemically adsorb the silicon precursor on the partially passivated surface, thereby depositing a material including silicon on the substrate.

[0017] In some embodiments of the method of controlling chemisorption of a vapor-phase silicon precursor on a substrate, the substrate includes a gap including an inner surface, and the first plasma partially modifies the inner surface of the gap.

[0018] In another aspect, a semiconductor processing assembly is disclosed. The semiconductor processing assembly includes a reaction chamber configured and arranged to hold a substrate, a first plasma gas source configured and arranged to contain a gas for generating at least one of a first plasma and a second plasma, a precursor source configured and arranged to contain and evaporate a silicon precursor, and a plasma generation system for generating the first plasma and the second plasma. The semiconductor processing assembly also includes an injection system, an exhaust device, and a controller, wherein the injection system is constructed and arranged to provide the first plasma and the second plasma into the reaction chamber, and to provide a gas-phase silicon precursor into the reaction chamber in a gas phase, and the controller is configured and arranged to cause the system to perform a method according to the present disclosure.

[0019] In some embodiments, the processing assembly further includes a second plasma gas source configured and arranged to contain a gas for generating a second plasma of the first plasma and the second plasma.

[0020] In yet another aspect, a structure formed by a method according to the present disclosure is disclosed.

[0021] In another aspect, a semiconductor device manufactured by using a method according to the present disclosure is disclosed. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings, which are included to provide a further understanding of the disclosure and constitute a part of this specification, illustrate exemplary embodiments and together with the description help to explain the principles of the disclosure.

[0023] In the attached picture:

[0024] Figure 1is a block diagram of an exemplary embodiment of a method according to the present disclosure.

[0025] Figure 2 is a block diagram of an additional exemplary embodiment of a method according to the present disclosure.

[0026] FIG. 3A to FIG. 3D is a schematic diagram of an exemplary embodiment of a method according to the present disclosure.

[0027] Figure 4 is a schematic diagram of an embodiment of a semiconductor processing assembly according to the present disclosure.

[0028] It should be understood that the elements in the drawings are shown for simplicity and clarity and are not necessarily drawn to scale. The illustrations presented herein are not meant to be actual views of any particular material, structure, or device, but are merely idealized representations used to describe embodiments of the present disclosure. For example, the size of some elements in the drawings may be exaggerated relative to other elements to help improve understanding of the illustrated embodiments of the present disclosure. DETAILED DESCRIPTION

[0029] The present disclosure is further explained by the following exemplary embodiments depicted in the accompanying drawings. The illustrations given herein are not meant to be actual views of any particular material, structure, or assembly, but are merely schematic representations of embodiments of the present disclosure. It should be understood that the elements in the drawings are shown for simplicity and clarity and are not necessarily drawn to scale. For example, the sizes of some elements in the drawings may be exaggerated relative to other elements to help improve the understanding of the illustrated embodiments of the present disclosure. The structures, devices, and assemblies depicted in the drawings may include additional elements and details, which may be omitted for clarity.

[0030] For the sake of brevity, conventional manufacturing, connection, preparation, and other functional aspects of the methods and assemblies described herein may not be described in detail. In addition, the connecting lines shown in the various figures are intended to represent exemplary functional relationships and / or physical connections between the various elements. Many alternative or additional functional relationships or physical connections may exist in actual systems, and / or may not exist in some embodiments.

[0031] The descriptions of exemplary embodiments of methods, structures, devices, and semiconductor processing assemblies provided below are merely exemplary and are for illustrative purposes only. The following description is not intended to limit the scope of the present disclosure or the claims. In addition, the recitation of multiple embodiments having the features shown is not intended to exclude other embodiments having additional features or other embodiments incorporating different combinations of the features described. For example, various embodiments are set forth as exemplary embodiments and may be recited in dependent claims. Unless otherwise indicated, the exemplary embodiments or components thereof may be combined or may be applied separately from each other.

[0032] The headings provided herein, if any, are for convenience only and do not necessarily affect the scope or meaning of the claimed subject matter.

[0033] Substrate

[0034] In one aspect, a method for depositing a material containing silicon in a gap is disclosed. The method includes providing a substrate, the substrate including a gap, wherein the gap includes an inner surface. The gap in the present disclosure is in or on the substrate. The gap should be understood to describe a change in the topology of the substrate surface that causes some areas of the substrate surface to be lower than other areas. Therefore, the gap includes a topological structure in which a portion of the substrate surface is lower than the majority of the substrate surface. These include grooves, through holes, grooves, valleys, cracks, etc. In addition, the area between the protruding features of the substrate surface that protrude upward also forms a gap. Therefore, the space between adjacent fins is considered to be a gap. The gap may include a top and a bottom. The upper part of the gap is the area at the gap opening, and the bottom of the gap is the gap portion away from the gap opening. In some embodiments, the gap includes a bottom, and the predetermined area modified by the first high-energy plasma is the bottom. The area outside the gap is referred to as the top surface of the gap, such as the highest horizontal part of the fin, or the substrate area between the hole or through hole. The gap may also have an inner surface (i.e., a sidewall). The inner surface is a surface connecting the top and bottom of the gap. The inner surface may be substantially vertical, or it may include an inclined portion. Therefore, the size of the gap opening at the top of the gap may be different from the area of ​​the bottom of the gap.

[0035] like Figure 1 As shown, the deposition method 100 according to the present invention includes providing a substrate 102. The substrate can be provided in a reaction chamber 202, such as Figure 2Embodiments of method 200 in . The substrate may be any one or more underlying materials that can be used to form or on which a structure, device, circuit or layer can be formed. The substrate may include a bulk material, such as silicon (e.g., single crystal silicon), other IV group materials, such as germanium, or other semiconductor materials, such as II-VI or III-V semiconductor materials, and may include one or more layers covering or located below the bulk material. In addition, the substrate according to the present disclosure includes a gap (e.g., a groove), and optionally includes other features formed in or on at least a portion of the layer of the substrate, such as a protrusion, etc. For example, the substrate may include a bulk semiconductor material and an insulating or dielectric material layer covering at least a portion of the bulk semiconductor material. The substrate may include a nitride, such as TiN, an oxide, an insulating material, a dielectric material, a conductive material, a metal, such as tungsten, ruthenium, molybdenum, cobalt, aluminum or copper, or a metallic material, a crystalline material, an epitaxial material, a heteroepitaxial material and / or a single crystal material. In some embodiments currently disclosed, the substrate includes silicon. As described above, in addition to silicon, the substrate may include other materials. Other materials may form layers. Specifically, the substrate may include a partially manufactured semiconductor device.

[0036] In some embodiments, the substrate may be pre-treated or cleaned before or at the start of a process according to the present disclosure. In some embodiments, the substrate may be subjected to a plasma cleaning process before or at the start of a process. In some embodiments, the pre-treatment or cleaning process may be performed in the same reaction chamber as the current process. However, in some embodiments, the pre-treatment or cleaning process may be performed in a separate reaction chamber.

[0037] In some embodiments, the inner surface of the gap includes an oxide surface. In some embodiments, the oxide surface includes, consists essentially of, or is composed of silicon oxide. In some embodiments, the oxide surface includes, consists essentially of, or is composed of a low-k material. The low-k material can be, for example, a silicon-based material having a k value similar to or lower than silicon oxide. Examples of low-k materials include SiC, SiCN, SiOC, SiON, and SiOCN. In some embodiments, the substrate includes a silicon nitride surface. In some embodiments, the substrate surface includes regions with different chemical compositions. In some embodiments, the inner surface of the gap is chemically different from the region outside the gap. For example, in some embodiments, the inner surface of the gap is a silicon oxide surface, and the substrate surface outside the gap includes a hard mask material, such as a metal oxide-based material. For example, when the substrate includes a partially manufactured semiconductor device, the surface of the substrate can include a variety of materials.

[0038] Reaction Chamber

[0039] In some embodiments, a substrate is provided in a reaction chamber and the substrate is exposed to a first plasma and a second plasma in the reaction chamber.

[0040] Thus, the method of depositing a material comprising silicon in a gap according to the present invention may include providing a substrate in a reaction chamber. In other words, the substrate is in a space where deposition conditions can be controlled. The reaction chamber may be a single wafer reactor. Alternatively, the reaction chamber may be a batch reactor. Figure 4 As shown, reaction chamber 402 may form part of a semiconductor processing assembly 400 for manufacturing semiconductor devices. Semiconductor processing assembly 400 may include one or more multi-station processing chambers. The reaction chamber may be part of a cluster tool in which different processes are performed to form an integrated circuit. The various stages of the method may be performed in a single reaction chamber, or they may be performed in multiple reaction chambers, such as a reaction chamber of a cluster tool, or a deposition station of a multi-station processing chamber.

[0041] In some embodiments, the substrate is exposed to the first plasma and the second plasma and contacted with the silicon precursor in the same reaction chamber. In some embodiments, at least two of exposing the substrate to the first plasma, exposing the substrate to the second plasma, and contacting the substrate with the silicon precursor are performed in one reaction chamber. In some embodiments, the substrate is exposed to the first plasma and the second plasma and contacted with the silicon precursor in different processing stations of a multi-station chamber. In some embodiments, the substrate is exposed to the first plasma and the second plasma and contacted with the silicon precursor in the same cluster tool.

[0042] In some embodiments, the reaction chamber may be a flow-type reactor, such as a cross-flow reactor. In some embodiments, the reaction chamber may be a showerhead reactor. In some embodiments, the reaction chamber may be a hot wall reactor. In some embodiments, the reaction chamber may be a spatially separated reactor. In some embodiments, the reaction chamber may be a single wafer ALD reactor. In some embodiments, the reaction chamber may be a single wafer ALD reactor for large-scale manufacturing. In some embodiments, the reaction chamber may be a batch reactor for simultaneously manufacturing multiple substrates.

[0043] The reaction chamber may form part of a semiconductor processing assembly, such as an atomic layer deposition (ALD) assembly. The reaction chamber may form part of a chemical vapor deposition (CVD) assembly. The semiconductor processing assembly may be an ALD or CVD deposition assembly, but in certain process steps, molecular layer deposition (MLD) may also be used for certain parts of the deposition process flow. In addition, the semiconductor processing assembly may be configured and arranged for an etching process. In some embodiments, the method is performed in a single reaction chamber of a combination tool, but other, previous or subsequent manufacturing steps of the structure or device are performed in additional reaction chambers of the same combination tool. Optionally, a semiconductor processing assembly including a reaction chamber may be provided with a heater to activate the reaction by raising the temperature of one or more substrates and / or reactants and / or precursors.

[0044] The first plasma

[0045] In the method according to the invention, Figure 1 and Figure 2 As shown (blocks 104, 204 and 106, 206, respectively), the substrate is exposed to a first plasma and then to a second plasma. The first plasma has a higher ion energy than the second plasma. The first plasma can remove active groups from the substrate surface. For example, -OH groups can be removed. In some embodiments, the substrate surface includes silicon oxide, and the first plasma removes -OH ends and exposes the substrate to the first plasma with high ion energy to modify a predetermined area of ​​the inner surface of the gap. In addition to removing active groups, dangling bonds can also be formed on or in the substrate.

[0046] According to the present invention, the design of the processing unit such as the reaction chamber affects the specific parameters selected for the first plasma and the second plasma exposure. For example, the pressure, plasma power and gap size can be adjusted to obtain the appropriate plasma ion energy and the desired result. In addition, the duration of plasma exposure can vary. In some embodiments, the duration of plasma exposure is longer than about 1 second, longer than about 5 seconds, longer than about 10 seconds, longer than about 30 seconds or longer than about 40 seconds. In some embodiments, the duration of plasma exposure is shorter than about 60 seconds, shorter than about 45 seconds, shorter than about 30 seconds, shorter than about 20 seconds, shorter than about 10 seconds, shorter than about 5 seconds or shorter than about 1 second. In some embodiments, the first plasma or the second plasma exposure may have a duration of about 0.5 seconds to about 60 seconds, such as about 1 second to about 30 seconds, about 1 second to about 15 seconds, about 10 seconds to about 50 seconds or about 10 to about 20 seconds, such as about 0.5 seconds, 1 second, 3 seconds, 4 seconds, 8 seconds, 15 seconds, 30 seconds or 45 seconds.

[0047] In some embodiments, the ion energy of the first plasma is at least about 15 eV. In some embodiments, the ion energy of the first plasma is at least about 20 eV. In some embodiments, the ion energy of the first plasma is at least about 25 eV. In some embodiments, the ion energy of the first plasma is at least about 40 eV.

[0048] Among other things, the plasma ion energy may be affected by pressure. In some embodiments, during exposure to the first plasma, the substrate is maintained at a pressure of about 5Pa to about 1000Pa. In some embodiments, during exposure to the first plasma, the substrate is maintained at a pressure of less than 1000Pa. The appropriate pressure will depend on the reaction chamber configuration. In some embodiments, during exposure to the first plasma, the substrate is maintained at a pressure of about 5Pa to about 50Pa, or at a pressure of about 5Pa to about 30Pa, or at a pressure of about 5Pa to about 15Pa. However, in some other embodiments, during exposure to the first plasma, the substrate is maintained at a pressure of about 1000Pa to about 3000Pa, or at a pressure of about 1000Pa to about 6700Pa, or at a pressure of about 1000Pa to about 2000Pa. In some embodiments, the ion energy of the first plasma and the second plasma is adjusted by changing the pressure in the reaction chamber. In some embodiments, during exposure of the substrate to the first plasma, the pressure in the reaction chamber is lower than the pressure during exposure of the substrate to the second plasma. In some embodiments, during the second plasma exposure, the substrate is maintained at a pressure at least three times, at least four times, at least five times, or at least six times higher than during the first plasma exposure.

[0049] In some embodiments of the present disclosure, a single plasma pulse for generating reactive species may be divided into multiple constituent micropulses. For example, multiple micropulses may be used as a substitute for a single static steady-state plasma pulse, and such micropulses may include a duty cycle (RF power on time) between 10% and 90%, with a plasma frequency between 10 Hz and 100,000 Hz.

[0050] In some embodiments, the first plasma is generated by a gas selected from nitrogen (N2) and a rare gas. According to the present invention, a rare gas refers to helium (He), neon (Ne), argon (Ar), krypton (Kr) and xenon (Xe). In some embodiments, the first plasma is generated by a gas selected from N, He, Ne and Ar. In some embodiments, the gas used to generate the first plasma is essentially composed of nitrogen. In some embodiments, the gas used to generate the first plasma is essentially composed of nitrogen and a rare gas.

[0051] In some embodiments, the first plasma and the second plasma are generated by the same gas flow. In some embodiments, the first plasma and the second plasma are generated by gases with different components. The gas in the present disclosure may be a gas mixture. In the present disclosure, "gas" may include a material that is a gas at normal temperature and pressure (NTP), a evaporated solid and / or an evaporated liquid, and may be composed of a single gas or a gas mixture according to the context. A passivation material precursor may be provided to the reaction chamber in a gas phase. A hard mask precursor may be provided to the reaction chamber in a gas phase. The term "inert gas" may refer to a gas that does not participate in a chemical reaction and / or does not become part of a layer to a perceptible degree. Exemplary inert gases include He and Ar and any combination thereof. In some cases, molecular nitrogen and / or hydrogen may be an inert gas. Gases other than process gases, i.e., gases that are not introduced by a precursor injector system, other gas distribution devices, etc., may be used, for example, to seal a reaction space, and may include a sealing gas. Gases including inert gases may be used to generate plasma therefrom.

[0052] Second plasma

[0053] The method further includes exposing the substrate to a second plasma, Figure 1 and 2 As shown in blocks 106 and 206 of . The second plasma has a lower ion energy (low ion energy plasma) to passivate the modified region of the gap surface, thereby forming a passivated modified region on the gap surface.

[0054] In some embodiments, the first plasma is nitrogen (N) plasma and the second plasma is N plasma. In some embodiments, the first plasma is a mixture of N and Ar and the second plasma is a mixture of N and Ar. In some embodiments, the first plasma is a mixture of N and He and the second plasma is a mixture of N and He. In some embodiments, the first plasma is Ar plasma and the second plasma is N plasma, or a mixture of N and another gas. Nitrogen plasma refers to a plasma generated by nitrogen gas. Corresponding nomenclature is also used for other plasmas, such as argon plasma and helium plasma.

[0055] In some embodiments, during exposure to the second plasma, the substrate is maintained at a pressure of at least about 10 Pa, such as at a pressure of about 15 Pa. In some embodiments, during exposure to the second plasma, the substrate is maintained at a pressure of at least about 20 Pa, such as at a pressure of about 25 Pa or 30 Pa. In some embodiments, during exposure to the second plasma, the substrate is maintained at a pressure of at least about 100 Pa, such as about 120 Pa. In some embodiments, during exposure to the second plasma, the substrate is maintained at a pressure of at least about 150 Pa. However, in some other embodiments, during exposure to the second plasma, the substrate is maintained at a pressure of from about 2500 Pa to about 15000 Pa. In some embodiments, during exposure to the second plasma, the substrate is maintained at a pressure of more than 1000 Pa.

[0056] In some embodiments, the passivation of the modified region comprises forming a nitrogen-containing terminal. In some embodiments, the nitrogen-containing terminal is an -NH terminal. In some embodiments, the second plasma comprises nitrogen. In some embodiments, the second plasma is generated by a gas comprising at least one of N2, NH3, hydrazine (N2H4) and an alkylhydrazine derivative. In some embodiments, the second plasma is generated by a gas comprising nitrogen and at least one of He, Ne, Ar, Kr and Xe. In some embodiments, the gas used to generate the second plasma consists essentially of nitrogen. In some embodiments, the gas used to generate the second plasma consists essentially of nitrogen and a rare gas.

[0057] In some embodiments, the ion energy of the second plasma is at most 5 eV. In some embodiments, the ion energy of the second plasma is at most 8 eV. In some embodiments, the ion energy of the second plasma is at most 10 eV. In some embodiments, the ion energy of the second plasma is between 4 eV and 10 eV.

[0058] Plasma generation

[0059] The first plasma and the second plasma can be generated in various ways. At least one of the first plasma and the second plasma can be a direct plasma. At least one of the first plasma and the second plasma can be a remote plasma. The plasma can be generated by radio frequency (RF plasma), microwave (microwave plasma) or electric current (e.g., inductively coupled plasma).

[0060] When direct plasma is used, plasma is generated in the reaction chamber. In such embodiments, the method of the present disclosure can be performed in an apparatus comprising two electrodes, with the substrate located between the two electrodes. The electrodes can be positioned in parallel at a predetermined distance referred to as an electrode gap. In some embodiments, the electrode gap can be at least 5 mm to at most 30 mm, at least 5 mm to at most 10 mm, or at least 10 mm to at most 20 mm, or at least 20 mm to at most 30 mm.

[0061] In some embodiments, a plasma frequency of at least 40 kHz to at most 2.45 GHz may be used to generate the first plasma and / or the second plasma, or a plasma frequency of at least 40 kHz to at most 80 kHz may be used, or a plasma frequency of at least 80 kHz to at most 160 kHz may be used, or a plasma frequency of at least 160 kHz to at most 320 kHz may be used, or a plasma frequency of at least 320 kHz to at most 640 kHz may be used, or a plasma frequency of at least 640 kHz to at most 1280 kHz may be used, or a plasma frequency of at least 1280 kHz to at most 2500 kHz may be used, or a plasma frequency of at least 2.5 MHz to at least 5 MHz may be used, or a plasma frequency of at least 5 MHz to at most 60 MHz may be used, or Or a plasma frequency of at least 5 MHz to at most 10 MHz can be used, or a plasma frequency of at least 10 MHz to at most 20 MHz can be used, or a plasma frequency of at least 20 MHz to at most 30 MHz can be used, or a plasma frequency of at least 30 MHz to at most 40 MHz can be used, or a plasma frequency of at least 40 MHz to at most 50 MHz can be used, or a plasma frequency of at least 50 MHz to at most 100 MHz can be used, or a plasma frequency of at least 100 MHz to at most 200 MHz can be used, or a plasma frequency of at least 200 MHz to at most 500 MHz can be used, or a plasma frequency of at least 500 MHz to at most 1000 MHz can be used, or a plasma frequency of at least 1 GHz to at most 2.45 GHz can be used. In an exemplary embodiment, the plasma can be an RF plasma, and the RF power can be provided at a frequency of 13.56 MHz. In a further exemplary embodiment, the plasma can be an RF plasma, and the RF power can be provided at a frequency of 60 MHz.

[0062] In some embodiments, the plasma exposure can be divided into multiple constituent micropulses. For example, multiple micropulses can be used as a substitute for a single static steady-state plasma exposure, and such micropulses can include a duty cycle (RF power on time) between 10% and 90%, and a plasma frequency between 10 Hz and 100,000 Hz.

[0063] Silicon Precursor

[0064] After the substrate is exposed to the first plasma and the second plasma, the substrate is contacted with a gas phase silicon precursor, respectively. Figure 1 and 2 The contact between the substrate and the silicon precursor can be performed by providing the silicon precursor into the reaction chamber, such as Figure 2 As in the embodiments of the present invention. The silicon precursor will be chemically adsorbed on the unmodified area of ​​the gap for depositing a material comprising silicon on the unmodified area. Without limiting the present disclosure to any particular theory, chemical adsorption of the silicon precursor may be reduced due to exposure to the first plasma and the second plasma. In some embodiments, plasma exposure can reduce chemical adsorption of the silicon precursor to the passivation area. The degree of reduction in chemical adsorption can be adjusted by selecting the plasma exposure conditions. In some embodiments, plasma exposure can substantially completely inhibit chemical adsorption of the silicon precursor to the passivation area.

[0065] In some embodiments, the chemical adsorption of the silicon precursor on the passivation modified area is reduced by at least 60% relative to the unmodified area. For example, using He plasma as the first plasma and N plasma as the second plasma, the chemical adsorption of the silicon precursor can be reduced by about 87%. In another example, where N plasma is used as the first plasma and the second plasma, the chemical adsorption of the silicon precursor is reduced by about 71%.

[0066] In some embodiments, the silicon-containing material is conformally deposited on the unmodified region of the gap. In some embodiments, the silicon-containing material at least partially fills the gap. In some embodiments, the gap is filled from the bottom of the gap upward.

[0067] Figures 3A to 3D A gap is depicted in which a material comprising silicon is deposited. Figure 3A In the , empty gaps are indicated. Figure 3B In such an embodiment, the silicon-containing material is preferentially deposited at the bottom of the gap. In such an embodiment, the suppression of silicon precursor chemisorption is most prevalent closer to the gap opening relative to the gap bottom. Figure 3C In , the gap is filled substantially in a bottom-up manner as the deposition of silicon-containing material continues faster toward the bottom of the gap. Figure 3DIn such an embodiment, the silicon-containing material is substantially uniformly deposited on the gap wall. In such an embodiment, the plasma treatment substantially suppresses the chemical adsorption of the silicon precursor only at the bottom of the gap. Figure 3D The embodiments shown in the embodiments can be used to deposit thin layers on the sidewalls of a gap having a small critical dimension. For example, it is contemplated that the deposition rate decreases along the sidewalls of the gap, and deposition is substantially completely suppressed at the bottom of the gap. This can allow careful thickness control of the deposition on the sidewalls, which can be useful in some applications.

[0068] In some embodiments, the silicon precursor comprises silicon and nitrogen. In some embodiments, the silicon precursor comprises silicon and carbon. In some embodiments, the silicon precursor comprises silicon, carbon and nitrogen. In some embodiments, the silicon precursor comprises silicon, carbon and oxygen. In some embodiments, the silicon precursor comprises silicon and oxygen. In some embodiments, the silicon precursor comprises silicon, oxygen and nitrogen. In some embodiments, the silicon precursor comprises silicon, carbon, oxygen and nitrogen. In some embodiments, the silicon precursor consists of silicon, carbon and hydrogen. In some embodiments, the silicon precursor comprises a silicon-nitrogen bond. In some embodiments, the silicon precursor comprises only one silicon atom. In some embodiments, the silicon precursor comprises at most two silicon atoms. In some embodiments, the silicon precursor comprises at most three silicon atoms. In some embodiments, the silicon precursor comprises two silicon atoms. In some embodiments, the silicon precursor comprises three silicon atoms.

[0069] In some embodiments, the silicon precursor is a nitrogen-containing silane containing 1 to 4 silicon atoms. In some embodiments, the silicon precursor is an alkylaminosilane. In some embodiments, the silicon precursor is an alkylaminosilane with one silicon atom. In some embodiments, the silicon precursor is an alkylaminodisilane. In some embodiments, the silicon precursor is an alkylaminotrisilane. In some embodiments, the silicon precursor is an alkylaminotetrasilane. The alkylaminosilane according to the present invention may contain 1 to 4 alkylamino groups. For example, the alkyliminosilane may contain up to three alkylamino groups or up to three alkylamino groups. Examples of alkylaminosilanes according to the present invention include (NH2R)3SiH, (NH2R)2SiH2, (NH2R)SiH3, wherein each R is independently selected from linear and branched C1 to C5 alkyl groups. In some embodiments, at least one R is saturated. In some embodiments, all R are saturated. In some embodiments, at least one R is unsaturated. In some embodiments, all R are unsaturated.

[0070] In some embodiments, the silicon precursor is of the formula Si a (NR2) b X cIt represents, wherein a is 1, 2, 3 or 4, b+c=2a+2, b is at least 1, each R is independently selected from H, methyl, ethyl, isopropyl, tert-butyl and phenyl, and each X is independently selected from H, methyl, ethyl, isopropyl, tert-butyl, phenyl, F, Cl, Br and I. In some embodiments, the silicon precursor is selected from SiH3[N(CH3)2], SiH3[N(CH2CH3)2], SiH3[N(CH3)(CH2CH3)], SiH3[N(C(CH3)3)2], SiH3[N(CH(CH3)2)2], SiH2[N(CH3)2]2, SiH2[N(CH2CH3)2]2, SiH2[N(CH3)(CH2CH3)]2,SiH2[N(C(CH3)3)2]2, SiH2[N(CH(CH3)2)2]2, SiH2[N(CH3)(CH2CH3)]2,SiH2[N(C(CH3)3)2]2, SiH2[N(CH(CH3)2)2]2, SiH(CH3)[N(CH3)2]2,SiH(CH3)[N(CH2CH3)2]2, SiH(CH3)[N(CH3)(CH2CH3)]2,SiH(CH3)[N(C(CH3)3)2]2,SiH(CH3)[N(CH(CH3)2)2]2,Si(CH3)2[N(CH3)2]2,S i(CH3)2[N(CH2CH3)2]2,Si(CH3)2[N(CH3)(CH2CH3)]2,Si(CH3)2[N(C(CH3)3)2]2,Si(CH3)2[N(CH(CH3)2)2]2 ,SiH[N(CH3)2]3,SiH[N(CH2CH3)2]3,SiH[N(CH3)(CH2CH3)]3,SiH[N(C(CH3)3)2]3,SiH[N(CH(CH3)2)2]3,Si[ N(CH3)2]4,Si[N(CH2CH3)2]4,Si[N(C(CH3)3)2]4,Si[N(CH(CH3)2)2]4,SiCl[N(CH3)2]3,SiCl[N(CH2CH3)2]3, SiCl[N(CH3)(CH2CH3)]3, SiCl[N(C(CH3)3)2]3,SiCl[N(CH(CH3)2)2]3,Si[NH(CH3)]3-Si[NH(CH3)]3,Si[NH(CH2CH3)]3-Si[NH(CH2CH3)]3,SiH2(NH(CH(CH3)2)2-SiH2.

[0071] The alkylaminosilane according to the invention may contain 1 to 4 alkylamino groups. In embodiments in which the alkyliminosilane contains up to three alkylamino groups, the additional groups may be, for example, alkyl or alkoxy groups.

[0072] In another aspect, a method of controlling chemical adsorption of a vapor-phase silicon precursor on a substrate having a surface is disclosed. The method includes providing a substrate in a reaction chamber, exposing the substrate to a first plasma having high ion energy to partially modify the surface, exposing the substrate to a second plasma having low ion energy to passivate the partially modified surface to form a partially passivated surface, and contacting the substrate with a vapor-phase silicon precursor to chemically adsorb the silicon precursor on the partially passivated surface, thereby depositing a material including silicon on the substrate.

[0073] In some embodiments of the method of controlling chemisorption of a vapor-phase silicon precursor on a substrate, the substrate includes a gap including an inner surface, and the first plasma partially modifies the inner surface of the gap.

[0074] Deposited materials

[0075] The material deposited in the gap includes silicon. The material comprising silicon can be understood to include silicon and at least one other compound, such as oxygen, carbon or nitrogen. The deposited material can be silicon oxide. The deposited material can be a low-k material containing silicon. In some embodiments, the material comprising silicon includes an -OH terminal. In some embodiments, the material comprising silicon is silicon oxide. As used herein, silicon oxide refers to a material comprising silicon and oxygen. Silicon oxide can be represented by the formula SiO xRepresents, where x can be between 0 and 2 (e.g., SiO2). In some cases, silicon oxide may not include stoichiometric silicon oxide. In some cases, silicon oxide may include other elements, such as carbon, nitrogen, hydrogen, etc. In some embodiments, the material containing silicon is silicon nitride. Silicon nitride (SiN) may refer to a material including silicon and nitrogen. Silicon nitride is not necessarily a stoichiometric composition. The amount of silicon may be in the range of 5 to 50 atomic %, and the amount of nitrogen may be in the range of about 50 to about 95 atomic %. In some embodiments, in addition to Si and N, SiN includes one or more elements, such as H or C. In some embodiments, the material containing silicon is silicon carbide. Silicon carbide (SiC) may refer to a material including silicon and carbon. Silicon carbide is not necessarily a stoichiometric composition. The amount of silicon may be in the range of 5 to 50 atomic %, and the amount of carbon may be in the range of about 50 to about 95 atomic %. In some embodiments, in addition to Si and C, SiC includes one or more elements, such as H or N. In some embodiments, the material containing silicon is silicon oxide carbide. Silicon oxide carbide (SiOC) may refer to a material containing silicon, oxygen, and carbon. As used herein, unless otherwise specified, SiOC is not intended to limit, restrict or define bonding or chemical states, such as oxidation states of Si, O, C and / or any other elements in the material. In some embodiments, in addition to Si, O and C, SiOC also includes one or more elements, such as H or N. In some embodiments, SiOC includes Si-C bonds and / or Si-O bonds. In some embodiments, SiOC includes Si-C bonds and Si-O bonds, and does not include Si-N bonds. In some embodiments, in addition to Si-C and / or Si-O bonds, SiOC also includes Si-H bonds. In some embodiments, SiOC includes -OH termini. In some embodiments, SiOC does not include nitrogen. In some other embodiments, SiOC includes nitrogen in an amount of about 0% to about 40% by atoms (atomic %). As a specific example, SiOC can be or include a layer including SiOCN. In some embodiments, silicon oxycarbide can be composed of the chemical formula Si z O x C y , wherein z can be in the range of about 0 to about 2, x can be in the range of about 0 to about 2, and y can be in the range of about 0 to about 5. Silicon oxycarbon nitride (SiOCN) refers to a material comprising silicon, oxygen, nitrogen, and carbon. As used herein, unless otherwise specified, SiOCN is not intended to limit, restrict, or define bonding or chemical states, such as the oxidation state of Si, O, C, N, and / or any other element in the material. In some embodiments, SiOCN comprises an -OH terminus. In some embodiments, SiOCN can be made of the formula Si z O x C y N wA material represented by, wherein z may be in the range of about 0 to about 2, x may be in the range of about 0 to about 2, y may be in the range of about 0 to about 2, and w may be in the range of about 0 to about 2.

[0076] Although the silicon-containing material is deposited in the gap, it may also be deposited on the surface of the substrate, depending on the topology of the substrate. This may be desirable or undesirable, and if necessary, additional processing steps may be utilized to remove the silicon-containing material from areas outside the gap.

[0077] Cyclic Process

[0078] In some embodiments, the deposition process according to the present disclosure is a cyclic process. Generally, in a cyclic deposition process according to the present disclosure, such as atomic layer deposition (ALD) and molecular layer deposition (MLD), during each cycle, a precursor is introduced into a reaction chamber and chemically adsorbed onto a substrate surface (e.g., a substrate surface that may include previously deposited material from a previous deposition cycle or other material), such as at each cycle. Figure 1 and 2 In stages 108 and 208 of the present invention. In some embodiments, the precursor on the substrate surface is not easily reacted with additional precursors (i.e., the deposition of the precursor can be a partially or completely self-limiting reaction). Thereafter, another precursor or reactant can be introduced into the reaction chamber for converting the chemically adsorbed precursor into the desired material on the deposition surface. The second precursor or reactant is capable of further reacting with the chemically adsorbed precursor. During one or more cycles, for example, during each step of each cycle, a purge step can be utilized to remove any excess precursor from the reaction space (e.g., reaction chamber) and / or to remove any excess reactant and / or reaction byproducts from the reaction space (e.g., reaction chamber). Therefore, in some embodiments, the cyclic deposition process includes purging the reaction chamber after the precursor is provided to the reaction chamber. In some embodiments, the cyclic deposition process includes purging the reaction chamber after the first precursor is provided to the reaction chamber. In some embodiments, the cyclic deposition process includes purging the reaction chamber after the second precursor is provided to the reaction chamber. In some embodiments, the cyclic deposition process includes purging the reaction chamber after the first precursor is provided to the reaction chamber, and after the second precursor is provided to the reaction chamber. Without limiting the present disclosure to any particular theory, ALD and MLD may be similar processes in terms of self-limiting reactions and slower and more controllable layer growth rates compared to CVD. Typically, ALD is used to deposit inorganic materials, while in MLD, the precursors may be entirely organic molecules.

[0079] The process may include one or more cyclic stages. In certain embodiments, the process includes one or more non-cyclic (i.e., continuous) stages. In certain embodiments, the deposition process includes a continuous flow of at least one precursor. In such embodiments, the process includes a continuous flow of a first polymer precursor or a second polymer precursor. In certain embodiments, one or more precursors are provided continuously in a reaction chamber.

[0080] exist Figure 1 In an embodiment, the deposition process may include a cycle 110 in which, after contacting the substrate with the silicon precursor, exposure to the first plasma is repeated. Figure 1 The process may or may not include contacting the substrate with a second precursor between contacting the substrate with the silicon precursor and repeatedly exposing to the first plasma. In embodiments where the substrate is not contacted with a second precursor or reactant, the deposition process may be cyclic CVD, and the silicon-containing material is based on a silicon precursor. Embodiments where the method includes contacting the substrate with a second precursor or reactant may be a cyclic CVD process or an ALD process, depending on the precursors and conditions in the reaction space (e.g., reaction chamber).

[0081] Cycle 110 is optional, so in some embodiments, the process can be a non-cyclic process. For example, the process can be a CVD type process. The CVD type process is characterized by vapor deposition, which is not self-limiting. They generally involve gas phase reactions between two or more precursors and / or reactants. Precursors and reactants can be provided to the reaction space or substrate at the same time, or provided in partially or completely separated pulses. However, CVD can be performed with a single precursor or two or more precursors that do not react with each other. A single precursor such as a silicon precursor can be decomposed into reactive components deposited on the substrate surface. For example, decomposition can be performed by plasma or thermal methods. The substrate and / or reaction space can be heated to promote the reaction between gaseous precursors and / or reactants. In some embodiments, precursors and reactants are provided until a layer with a desired thickness is deposited. In some embodiments, a cyclic CVD process can use multiple cycles to deposit a film with a desired thickness. In the cyclic CVD process, precursors and / or reactants can be provided to the reaction chamber in the form of pulses that do not overlap or partially or completely overlap.

[0082] exist Figure 2 In an embodiment of the present invention, the process includes providing a silicon precursor 208 and a reactant 209 to a reaction chamber. In some embodiments, the silicon precursor and the reactant are provided to the reaction chamber alternately and sequentially. However, in some embodiments, the provision of the silicon precursor and the reactant to the reaction chamber may at least partially overlap. The provision of the silicon precursor and the reactant may be repeated, such as Figure 2 The number of repetitions 209b may be adjusted according to the amount of silicon-containing material to be deposited. Therefore, in some embodiments, the cyclic process according to the present disclosure may be an ALD process.

[0083] Also in Figure 2 In the embodiment of , the inhibition of the silicon precursor can be restarted, as shown in loop 210. Similar to Figure 1 The mode of deposition (i.e., gap fill or conformal, or something in between) and / or the rate of deposition may be affected by looping back to stage 204 (or by looping back to stage 210). Figure 1 The effect of the interval in loop 110 and looping back to stage 104).

[0084] In another aspect, a semiconductor processing assembly is disclosed, such as Figure 4 As shown. The semiconductor processing assembly includes a reaction chamber configured and arranged to hold a substrate, a first plasma gas source configured and arranged to contain a gas for generating at least one of a first plasma and a second plasma, a silicon precursor source configured and arranged to contain and evaporate a silicon precursor, and a plasma generation system for generating the first plasma and the second plasma. The semiconductor processing assembly also includes an injection system, an exhaust device, and a controller, the injection system is constructed and arranged to provide the first plasma and the second plasma into the reaction chamber, and to provide a gas-phase silicon precursor into the reaction chamber in a gas phase, and the controller is configured and arranged to cause the system to perform a method according to the present disclosure. The injection system can couple a source fluid to the reaction chamber.

[0085] On the other hand, Figure 4 As shown, a semiconductor processing assembly 400 for depositing a material containing silicon in a gap is disclosed. The semiconductor processing assembly 400 includes one or more reaction chambers 402, which are constructed and arranged to hold a substrate; an injection system 403, which is constructed and arranged to provide a first plasma and a second plasma into the reaction chamber 402, and to provide a gas-phase silicon precursor into the reaction chamber in a gas phase. The semiconductor processing assembly 400 also includes a first plasma gas source 404 constructed and arranged to contain a first plasma gas, a silicon precursor source 406 constructed and arranged to contain a silicon precursor, and an optional second plasma gas source 408 constructed and arranged to contain a second plasma gas. The semiconductor processing assembly also includes a plasma generation system 420 for generating the first plasma and the second plasma. As described above, the first plasma and the second plasma can be generated by the same plasma gas maintained in the first plasma gas source 404. However, in some embodiments, the second plasma is generated by the second plasma gas, which is maintained in the second plasma gas source 406.

[0086] Although plasma generation system 420 is depicted along lines 414-418. This configuration is typical of remote plasma generation. However, as described above, direct plasma can be used in processes according to the present disclosure. Therefore, it should be understood that plasma generation system 420 can alternatively be located inside reaction chamber 402, or otherwise integrated into reaction chamber 402. For example, the reaction chamber can include a substrate support and an upper electrode, and the substrate support includes a lower electrode. In some embodiments, a semiconductor processing assembly according to the present disclosure includes, consists essentially of, or consists of more than one plasma generation system. For example, the assembly can include remote plasma and direct plasma generation systems.

[0087] The silicon precursor may be provided to the reaction chamber 402 by a thermal process or a plasma process. In particular, some plasma enhanced CVD processes may involve generating a plasma while providing the silicon precursor to the reaction chamber. Figure 4 , a plasma generation system 420 is indicated as extending over line 416 .

[0088] The semiconductor processing assembly 400 is constructed and arranged to provide silicon precursors and optional reactants into a reaction chamber 402 via an injection system 403 for depositing a silicon-containing material in a substrate gap.

[0089] In some embodiments, the semiconductor processing assembly 400 further includes one or more additional precursor or reactant sources ( Figure 4 ), and the injection system 403 is constructed and arranged to provide one or more reactants in the gas phase into the reaction chamber. In addition, the semiconductor processing assembly can include any number of additional sources for various processes that can be part of a given process flow performed in the assembly.

[0090] The processing assembly 400 can be used to perform the methods described herein. In the illustrated example, the processing assembly 400 includes one or more reaction chambers 402, a precursor injector system 403, a first plasma gas source 404, a silicon precursor source 406, an optional second plasma gas source 408, an exhaust source 410, and a controller 412. The processing assembly 400 may include one or more additional gas sources (not shown), such as an inert gas source, a carrier gas source, and / or a purge gas source. The reaction chamber 402 may include any suitable reaction chamber, such as an ALD or CVD reaction chamber described herein.

[0091] Silicon precursor source 406 may include a container and a silicon precursor as described herein - alone or mixed with one or more carrier gases (e.g., inert gases). Although three sources 404-408 are shown, processing assembly 400 may include any suitable number of sources. Sources 404-408 may be coupled to reaction chamber 402 via pipelines 414-418, which may each include a flow controller, a valve, a heater, etc. In some embodiments, each of the silicon precursor in silicon precursor source 406, the optional reactant (not shown) in the reactant source, and / or another reactant in another reactant source may be independently heated or maintained at ambient temperature. In some embodiments, the source container is heated so that the precursor or reactant reaches a temperature suitable for evaporation.

[0092] Exhaust source 410 may include one or more vacuum pumps.

[0093] Controller 412 includes electronic circuits and software to selectively operate valves, manifolds, heaters, pumps, and other components included in process assembly 400. Such circuits and components are used to introduce precursors, reactants, and other gases from respective sources. Controller 412 can control the timing of gas pulse sequences, the temperature of substrate and / or reaction chamber 402, the pressure within reaction chamber 402, and various other operations to provide proper operation of process assembly 400. Controller 412 can include control software to electrically or pneumatically control valves to control the flow of precursors, reactants, and other gases into and out of reaction chamber 402. Controller 412 can include modules, such as software or hardware components, that perform specific tasks.

[0094] Other configurations of the processing assembly 400 are also possible, including precursor and reactant sources of different numbers and types. For example, the reaction chamber 402 may include more than one, such as two or four deposition stations. This multi-station configuration may have the advantage of, for example, allowing suppression in the same reaction chamber as the deposition material containing silicon. In addition, it should be understood that the arrangement of many valves, conduits, precursor sources, and reactant sources may be used to achieve the goal of selectively and in a coordinated manner supplying gas to the reaction chamber 402. In addition, as a schematic representation of the processing assembly 400, many components have been omitted for simplicity of description, and these components may include, for example, various valves, manifolds, purifiers, heaters, containers, vents, and / or bypasses.

[0095] During operation of the processing assembly 400, a substrate, such as a semiconductor wafer (not shown), is transferred from, for example, a substrate handling system to the reaction chamber 402. Once the substrate is transferred to the reaction chamber 402, one or more gases, such as precursors, reactants, carrier gases, and / or purge gases, are introduced into the reaction chamber 402 from a gas source.

[0096] In yet another aspect, a structure formed by a method according to the present disclosure is disclosed. In a further aspect, a semiconductor device fabricated by using a method according to the present disclosure is disclosed.

[0097] It should be understood that the configuration and / or method described herein are exemplary in nature, and these specific embodiments or examples should not be considered restrictive, because many variations are possible. The specific routine or method described herein can represent one or more of any number of processing strategies. Therefore, the various actions shown can be performed in the order shown, in other orders, or omitted in some cases.

[0098] The subject matter of the present disclosure includes all novel and nonobvious combinations and subcombinations of the various methods and components, and other features, functions, acts, and / or properties disclosed herein, and any and all equivalents thereof.

Claims

1. A method of depositing a material comprising silicon in a gap, the method comprising: providing a substrate comprising a gap, wherein the gap comprises an inner surface; exposing the substrate to a first plasma having a high ion energy to modify a predetermined region of the inner surface of the gap; exposing the substrate to a second plasma having a low ion energy to passivate the modified region of the gap surface, thereby forming a passivated modified region on the gap surface; as well as The substrate is contacted with a vapor phase silicon precursor to chemically adsorb the silicon precursor on the unmodified regions of the gaps, thereby depositing a silicon-containing material on the unmodified regions.

2. The method according to claim 1, wherein: A substrate is provided in a reaction chamber and is exposed to the first plasma and the second plasma in the reaction chamber.

3. The method according to claim 1 or 2, wherein: Passivation of the modified region includes forming a nitrogen-containing terminus.

4. A method according to any one of the preceding claims, wherein: The first plasma is generated from a gas selected from the group consisting of N, He, Ne, Ar, Kr and Xe.

5. A method according to any one of the preceding claims, wherein: The second plasma includes nitrogen.

6. The method according to claim 5, wherein: The second plasma is generated from a gas including at least one of N2, NH3, and N2H4.

7. A method according to any one of the preceding claims, wherein: The second plasma is generated from a gas including at least one of He, Ne, Ar, Kr, and Xe.

8. A method according to any one of the preceding claims, wherein: The first plasma has an ion energy of at least about 15 eV.

9. A method according to any one of the preceding claims, wherein: The ion energy of the second plasma is at most 5 eV.

10. A method according to any one of the preceding claims, wherein: The inner surface of the gap includes an oxide surface.

11. A method according to any one of the preceding claims, wherein: The substrate includes a silicon nitride surface.

12. A method according to any one of the preceding claims, wherein: The silicon precursor is a nitrogen-containing silane containing 1 to 4 silicon atoms.

13. The method according to claim 12, wherein: The silicon precursor is of the formula Si a (NR2) b X c It represents, wherein a is 1, 2, 3 or 4, b+c=2a+2, b is at least 1, each R is independently selected from H, methyl, ethyl, isopropyl, tert-butyl and phenyl, and each X is independently selected from H, methyl, ethyl, isopropyl, tert-butyl, phenyl, F, Cl, Br and I.

14. The method according to claim 13, wherein: The silicon precursor is selected from SiH3[N(CH3)2], SiH3[N(CH2CH3)2], SiH3[N(CH3)(CH2CH3)], SiH3[N(C(CH3)3)2], SiH3[N(CH(CH3)2)2], SiH2[N(CH3)2]2, SiH2[N(CH2CH3)2]2, SiH2[N(CH3)(CH2CH3)]2, SiH2[N(C(CH3)3)2]2, SiH2[N(CH(CH3)2) 2]2,SiH(CH3)[N(CH3)2]2,SiH(CH3)[N(CH2CH3)2]2,SiH(CH3)[N(CH3)(CH2CH3)]2,SiH(CH3)[N(C(CH3)3)2]2 ,SiH(CH3)[N(CH(CH3)2)2]2,Si(CH3)2[N(CH3)2]2,Si(CH3)2[N(CH2CH3)2]2,Si(CH3)2[N(CH3)(CH2CH3)]2,Si (CH3)2[N(C(CH3)3)2]2,Si(CH3)2[N(CH(CH3)2)2]2,SiH[N(CH3)2]3,SiH[N(CH2CH3)2]3,SiH[N(CH3)(CH2CH3 )]3,SiH[N(C(CH3)3)2]3,SiH[N(CH(CH3)2)2]3,Si[N(CH3)2]4,Si[N(CH2CH3)2]4,Si[N(C(CH3)3)2]4,Si[N(CH (CH3)2)2]4,SiCl[N(CH3)2]3,SiCl[N(CH2CH3)2]3,SiCl[N(CH3)(CH2CH3)]3,SiCl[N(C(CH3)3)2]3,SiCl[N(C H(CH3)2)2]3,Si[NH(CH3)]3-Si[NH(CH3)]3,Si[NH(CH2CH3)]3-Si[NH(CH2CH3)]3,SiH2(NH(CH(CH3)2)2-SiH2.

15. A method according to any one of the preceding claims, wherein: The gap includes a bottom, and the predetermined region modified by the first high-energy plasma is the bottom.

16. A method according to any one of the preceding claims, wherein: Chemical adsorption of the silicon precursor on the passivated modified region is reduced by at least 60% relative to the unmodified region.

17. A method according to any one of the preceding claims, wherein: The silicon-containing material is conformally deposited on the unmodified region of the gap.

18. The method according to any one of claims 1 to 16, wherein: The silicon-containing material at least partially fills the gap.

19. The method according to claim 18, wherein: The gap is filled from the bottom of the gap upward.

20. A method for controlling chemical adsorption of a vapor phase silicon precursor on a substrate having a surface, the method comprising: providing a substrate in a reaction chamber; exposing the substrate to a first plasma having high ion energy to partially modify the surface; exposing the substrate to a second plasma having a low ion energy to passivate the partially modified surface, thereby forming a partially passivated surface; The substrate is contacted with a vapor phase silicon precursor to chemically adsorb the silicon precursor onto the partially passivated surface, thereby depositing a silicon-containing material on the substrate.

21. The method according to claim 20, wherein: The substrate includes a gap including an inner surface, and the first plasma partially modifies the inner surface of the gap.

22. A semiconductor processing assembly, the assembly comprising: a reaction chamber configured and arranged to hold a substrate; a first plasma gas source configured and arranged to contain a gas for generating at least one of a first plasma and a second plasma; a silicon precursor source configured and arranged to contain and vaporize a silicon precursor; a plasma generating system for generating a first plasma and a second plasma; an injection system constructed and arranged to provide the first plasma and the second plasma into the reaction chamber and to provide a gas phase silicon precursor in a gas phase into the reaction chamber; Exhaust system; as well as A controller configured and arranged to cause the system to perform a method according to any one of the preceding claims.

23. The semiconductor processing assembly of claim 22, further comprising a second plasma gas source configured and arranged to contain a gas for generating a second plasma of the first plasma and the second plasma.

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