Systems and techniques for clock multiplication

Abstract

The invention relates to systems and techniques for clock multiplication. The clock adjustment circuit may receive as inputs two clock signals each having the same frequency and different phases and may generate a clock signal having a higher frequency than the two clock signal inputs. A duty cycle monitor may monitor and support correction of an offset of relative phases of the two input clocks to maintain a consistent duty cycle of the generated higher frequency clock signal. The clock adjustment circuit may reduce the length of a clock tree traversed by the higher frequency clock to, for example, reduce bias temperature instability degradation or other types of signal degradation.

Description

[0001] Cross Reference

[0002] This patent application claims priority to U.S. patent application No. 18 / 749,057, entitled “SYSTEMS AND TECHNIQUES FOR CLOCK DOUBLING,” filed by Funfrock et al. on June 20, 2024, and U.S. patent application No. 63 / 525,053, entitled “SYSTEMS AND TECHNIQUES FOR CLOCK DOUBLING,” filed by Funfrock et al. on July 5, 2023, each of which is assigned to its assignee and the entire contents of each of which are expressly incorporated herein by reference.

[0003] The technical field relates to one or more systems for memory, including systems and techniques for clock multiplication. Background Art

[0004] Memory devices are used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and others. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, typically represented by a logical 1 or a logical 0. In some examples, a single memory cell can support more than two states, either of which can be stored by the memory cell. To store information, a memory device can write (e.g., program, set, assign) a state to a memory cell. To access stored information, a memory device can read (e.g., sense, detect, retrieve, determine) a state from a memory cell. Summary of the invention

[0005] A method is described. The method may include: receiving a command to access one or more memory cells of a memory device; generating a first clock signal having a first frequency based at least in part on the command; generating a second clock signal having the first frequency based at least in part on the command, wherein a first phase of the first clock signal is different from a second phase of the second clock signal; generating a third clock signal based at least in part on the first clock signal and the second clock signal, the third clock signal having a second frequency higher than the first frequency; and accessing the one or more memory cells based at least in part on the third clock signal.

[0006] An apparatus is described. The apparatus may include: a first circuit configured to generate a first clock signal having a first frequency and a second clock signal having the first frequency, wherein a first phase of the first clock signal is different from a second phase of the second clock signal; a second circuit coupled to the first circuit, the second circuit configured to generate a third clock signal based at least in part on the first clock signal and the second clock signal, the third clock signal having a second frequency higher than the first frequency; and at least one controller coupled to the second circuit and configured to access a memory array of the apparatus using the third clock signal.

[0007] An apparatus is described. The apparatus may include: a memory device; and a controller coupled to the memory device, wherein the controller is configured to cause the apparatus to: receive a command to access one or more memory cells of the memory device; generate a first clock signal having a first frequency based at least in part on the command; generate a second clock signal having the first frequency based at least in part on the command, wherein a first phase of the first clock signal is different from a second phase of the second clock signal; generate a third clock signal based at least in part on the first clock signal and the second clock signal, the third clock signal having a second frequency higher than the first frequency; and access the one or more memory cells based at least in part on the third clock signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1

[00136] An example of a system supporting systems and techniques for clock multiplication according to examples disclosed herein is presented.

[0009] Figure 2A and 2B Examples of circuits and timing diagrams supporting systems and techniques for clock multiplication according to examples disclosed herein are shown.

[0010] Figure 3A , 3B and 3C show examples of circuits and timing diagrams supporting systems and techniques for clock multiplication according to examples disclosed herein.

[0011] Figure 4A and 4B Examples of circuits and timing diagrams supporting systems and techniques for clock multiplication according to examples disclosed herein are shown.

[0012] Figure 5 A block diagram of a memory system supporting systems and techniques for clock multiplication according to examples disclosed herein is shown.

[0013] Figure 6

[0013] Flowcharts illustrating one or more methods supporting systems and techniques for clock multiplication according to examples disclosed herein are shown. DETAILED DESCRIPTION

[0014] Clock signals coordinate the operation of many circuits, including the operation of memory systems. Faster clock signals (e.g., higher clock signal frequencies) can support faster processing and operation of memory systems relative to slower clock signals. However, faster clock signals are more susceptible to bias temperature instability (BTI) degradation, such as negative BTI (NBTI). Some systems (e.g., systems with relatively long clock trees) may also be more susceptible to BTI degradation. For example, BTI degradation may be a function of the length of the clock signal path. That is, the longer the clock tree, the more susceptible the clock signal is to BTI degradation, which may degrade one or more edges of the clock signal (e.g., the falling and / or rising edges of the clock). BTI degradation may result in an increase in the threshold voltage of the system, a decrease in drain current, and a decrease in transconductance.

[0015] Systems, techniques, and devices for generating high-frequency clock signals while mitigating (e.g., reducing) BTI degradation are described herein. A circuit that multiplies a clock signal (which may be referred to as a clock multiplier) may provide a faster clock signal (e.g., a higher signal frequency) with improved BTI degradation resistance than other high-frequency clocks and may be used in memory systems with relatively long clock trees. For example, a clock multiplier circuit may receive two clock signals with the same frequency (e.g., and opposite phases) as inputs and generate a clock signal with twice the frequency of the two clock signal inputs. By implementing a clock multiplier, a lower frequency input clock may traverse a larger portion of the clock tree (e.g., routed through a larger portion of the clock tree). For example, a clock multiplier may be located near the end of the clock tree, and a lower frequency input clock may traverse the clock tree before reaching the clock multiplier. Thus, the clock tree traversed by the higher frequency clock may be reduced, which may reduce BTI degradation and improve the duty cycle (e.g., resolution, accuracy) of the high frequency clock. Thus, implementing a clock multiplier may enable the use of a higher frequency clock with higher quality (eg, resolution, accuracy), which may reduce latency of the memory system and allow the memory system to support higher bandwidth.

[0016] In some examples, the relative phases of the two input clocks may shift (e.g., due to Monte Carlo effects and / or asymmetric layout of the paths of the two input clocks) and the mismatch may result in an uneven duty cycle (e.g., a duty cycle greater than 50%) of the multiplied clock signal. This mismatch may be monitored and corrected using a duty cycle monitor, such as by adjusting the delay of one of the input clocks into the clock multiplier circuit and other techniques described herein. Thus, a clock multiplier may be implemented while compensating for defects that would otherwise degrade the quality of the multiplied clock signal.

[0017] Features of the present disclosure are illustrated and described in the context of systems and architectures. Features of the present disclosure are further illustrated and described in the context of systems, circuits, timing diagrams, block diagrams, and flow charts.

[0018] Figure 1 An example of a system 100 supporting systems and techniques for clock multiplication according to examples disclosed herein is illustrated. The system 100 may include a portion of an electronic device, such as a computing device, a mobile computing device, a wireless communication device, a graphics processing device, a vehicle, a smartphone, a wearable device, an Internet-connected device, a vehicle controller, a system on a chip (SoC), or other fixed or portable electronic system, among other examples. The system 100 includes a host system 105, a memory system 110, and one or more channels 115 coupling the host system 105 with the memory system 110 (e.g., to support a communication coupling). The system 100 may include any number of one or more memory systems 110 coupled to the host system 105.

[0019] The host system 105 may include one or more components (e.g., circuitry, processing circuitry, processing components) that perform processes using memory, any one or more of which may be referred to as a processor 125 or included in a processor 125. The processor 125 may include at least one of one or more processing elements that may be co-located or distributed, including a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a controller, discrete gate or transistor logic, one or more discrete hardware components, or a combination thereof. The processor 125 may be an example of a central processing unit (CPU), a graphics processing unit (GPU), a general purpose GPU (GPGPU), or a SoC or components thereof, among other examples.

[0020] The host system 105 may also include at least one of one or more components (e.g., circuitry, logic, instructions) that implement the functionality of an external memory controller (e.g., a host system memory controller), which may be referred to as or included in the host system controller 120. For example, the host system controller 120 may issue commands or other signaling for operating the memory system 110, such as write commands, read commands, configuration signaling, or other operational signaling. In some examples, the host system controller 120 or associated functionality described herein may be implemented by or be part of the processor 125. For example, the host system controller 120 may be hardware, instructions (e.g., software, firmware), or some combination thereof implemented by the processor 125 or other components of the host system 105. In various examples, the host system 105 or the host system controller 120 may be referred to as a host.

[0021] The memory system 110 provides physical memory locations (e.g., addresses) that can be used or referenced by the system 100. The memory system 110 can include a memory system controller 140 and one or more memory devices 145 (e.g., memory packages, memory dies, memory chips) operable to store data. The memory system 110 can be configured for operation with different types of host systems 105, and can respond to commands from the host system 105 (e.g., from the host system controller 120). For example, the memory system 110 (e.g., the memory system controller 140) can receive a write command instructing the memory system 110 to store data received from the host system 105, or receive a read command instructing the memory system 110 to provide the host system 105 with data stored in the memory device 145, or receive a refresh command instructing the memory system 110 to refresh data stored in the memory device 145, as well as other types of commands and operations.

[0022] The memory system controller 140 may include at least one of one or more components (e.g., circuitry, logic, instructions) operable to control the operation of the memory system 110. The memory system controller 140 may include hardware or instructions that support the memory system 110 to perform various operations, and may be operable to receive, transmit, or respond to commands, data, or control information related to the operation of the memory system 110. The memory system controller 140 may be operable to communicate with one or more of the host system controller 120, one or more memory devices 145, or the processor 125. In some examples, the memory system controller 140 may cooperate with the host system controller 120, the local controller 150 of the memory device 145, or any combination thereof to control the operation of the memory system 110. Although examples of the memory system controller 140 are illustrated as separate components of the memory system 110, in some examples, aspects of the functionality of the memory system 110 may be implemented by at least one of the processor 125, the host system controller 120, the one or more local controllers 150, or any combination thereof.

[0023] Each memory device 145 may include a local controller 150 and one or more memory arrays 155. The memory array 155 may be a collection of memory cells (e.g., a two-dimensional array, a three-dimensional array), each of which is operable to store data (e.g., as one or more memory bits). Each memory array 155 may include memory cells of various architectures, such as random access memory (RAM) cells, dynamic RAM (DRAM) cells, synchronous dynamic RAM (SDRAM) cells, static RAM (SRAM) cells, ferroelectric RAM (FeRAM) cells, magnetic RAM (MRAM) cells, resistive RAM (RRAM) cells, phase change memory (PCM) cells, chalcogenide memory cells, NOR memory cells, and NAND memory cells, or any combination thereof.

[0024] The local controller 150 may include at least one of one or more components (e.g., circuitry, logic, instructions) operable to control the operation of the memory device 145. In some examples, the local controller 150 may be operable to communicate (e.g., receive or transmit data or commands or both) with the memory system controller 140. In some examples, the memory system 110 may not include the memory system controller 140, and the local controller 150 or the host system controller 120 may perform the functions of the memory system controller 140 described herein. In some examples, the local controller 150 or the memory system controller 140 or both may include a decoding component operable to access addresses of the memory array 155, a sensing component for sensing states of memory cells of the memory array 155, a writing component for writing states to memory cells of the memory array 155, or various other components operable to support the described operations of the memory system 110.

[0025] The host system 105 (e.g., host system controller 120) and the memory system 110 (e.g., memory system controller 140) may communicate information (e.g., data, commands, control information, configuration information) using one or more channels 115. Each channel 115 may be an example of a transmission medium that carries information, and each channel 115 may include one or more signal paths (e.g., transmission media, electrical conductors, conductive paths) between terminals (e.g., nodes, pins, contacts) associated with components of the system 100. Terminals may be examples of conductive input or output points of devices of the system 100, and terminals may operate as part of a channel 115. To support communication over channel 115, host system 105 (e.g., host system controller 120) and memory system 110 (e.g., memory system controller 140) may include a receiver (e.g., a latch) for receiving signals, a transmitter (e.g., a driver) for transmitting signals, a decoder for decoding or demodulating received signals or an encoder for encoding or modulating signals to be transmitted, and other components that support signaling over channel 115, which may be included in corresponding interface portions of the corresponding systems.

[0026] The channels 115 are dedicated to conveying one or more types of information, and the channels 115 may include unidirectional channels, bidirectional channels, or both. For example, the channels 115 may include one or more command and address channels, one or more clock signal channels, one or more data channels, and other channels or combinations thereof. In some examples, the channels 115 may be configured (e.g., operable) to provide power from one system to another (e.g., from the host system 105 to the memory system 110, according to a regulated voltage). In some examples, at least a subset of the channels 115 may be configured according to a protocol (e.g., a logic protocol, a communication protocol, an operating protocol, an industry standard), which may support configuration operations of the host system 105 and the memory system 110 and interactions between the host system 105 and the memory system 110.

[0027] The command / address channel (e.g., CA channel) is operable to communicate commands, including control information (e.g., address information) associated with the commands, between the host system 105 and the memory system 110. The commands carried by the command / address channel may include a write command having an address of data to be written to the memory system 110 or a read command having an address of data to be read from the memory system 110.

[0028] The clock signal channel may be operable to communicate one or more clock signals between the host system 105 and the memory system 110. The clock signal may oscillate between a high state and a low state, and may support coordination (e.g., in time) between the operations of the host system 105 and the memory system 110. In some examples, the clock signal may provide a timing reference for the operations of the memory system 110. The clock signal may be referred to as a control clock signal, a command clock signal, or a system clock signal. The system clock signal may be generated by a system clock, which may include one or more hardware components (e.g., oscillators, crystals, logic gates, transistors).

[0029] The data channels (e.g., DQ channels) may be operable to communicate information (e.g., data, control information) between the host system 105 and the memory system 110 (e.g., bidirectionally). For example, the data channels may communicate information written from the host system 105 to the memory system 110 or information read from the memory system 110 to the host system 105. In some examples, the channels 115 may include one or more error detection code (EDC) channels. The EDC channels may be operable to communicate error detection signals, such as checksum or parity bits, which may accompany information transmitted through the data channels.

[0030] A clock signal with a higher frequency may result in a faster (e.g., reduced latency) system 100. However, some components (e.g., capacitors, transistors) may be associated with higher manufacturing costs in order to operate at the high frequency of the faster clock signal. In addition, the higher frequency clock signal may be more sensitive to BTI degradation of the transistor, increase voltage threshold, reduce drain current, reduce transconductance, shorten the life of the transistor, or a combination thereof. BTI degradation may affect various transistors in different ways, resulting in high variability between transistors in the system 100. BTI degradation may also occur when the clock signal is turned off and in some cases, may be more harmful than when the clock signal is at a low frequency. In order to reduce the impact of BTI degradation (e.g., and manufacturing costs) while maintaining the benefits of a high frequency clock, the system clock signal may be adjusted for different parts of the system 100. A subset of the components of the system 100 may operate at a higher frequency to increase the speed of the system 100 as a whole (e.g., while not every component of the system 100 operates at a higher frequency). For example, a higher frequency clock may be restricted to areas of system 100 with high data traffic (e.g., channel 115 coupling host system 105 with memory system 110, circuitry for accessing memory cells in memory array 155), while other areas of system 100 may operate at a lower frequency clock.

[0031] The memory system 110 may include one or more circuits, such as clock multipliers, to adjust the frequency, phase, or other aspects of a clock signal (e.g., a branch of a system clock signal). Thus, different portions of the memory system 110 may operate at clock signals of different frequencies, phases, or both. Clock adjustment circuits, such as clock multiplier circuits (e.g., circuits that output a clock signal having a higher signal frequency from two or more input clock signals having a lower signal frequency) may improve BTI degradation resistance over other implementations of high frequency clocks. For example, a clock multiplier circuit of the memory system 110 may receive as input two (e.g., or more) clock signals having the same frequency (e.g., and opposite phases) and generate an output clock signal having a higher frequency (e.g., doubling the frequency) of the two input clock signals. In some examples, the input clock signal may be generated by the memory system 110, such as based on (e.g., in response to) an access command from the host system 105, and the input clock signal may traverse a portion of the clock tree of the memory system 110 (e.g., be routed through the portion) before reaching the clock multiplier circuit.

[0032] In some examples, the relative phases of the two input clocks may shift (e.g., due to Monte Carlo effects and / or layout asymmetry of the paths of the two input clocks), and the mismatch may result in uneven spacing between subsequent pulses of the output clock signal (e.g., this may result in a duty cycle of the output clock signal that is greater or less than 50%). For example, this mismatch may be monitored and corrected by adjusting the delay of one of the input clocks into the clock multiplier circuit.

[0033] In some cases, such as when the memory system 110 or a portion of the memory system 110 is in an idle mode, the clock multiplier circuit may be bypassed. In these cases, a portion of the memory system 110 that receives a multiplied clock signal when the memory system is not in the idle mode may instead receive one of the input clock signals (e.g., having a frequency lower than the frequency of the clock multiplier output clock signal). This bypassing may support the reduced power consumption of the memory system 110 that is expected in the idle mode by operating the portion of the memory system 110 with a lower frequency input clock signal when in the idle mode and may also avoid BTI degradation associated with a lack of a clock signal in circuits located after the clock multiplier.

[0034] The clock multiplier circuit allows the lower frequency clock to traverse a larger portion of the clock tree of the memory system 110. The portion of the clock tree traversed by the higher frequency clock can be reduced, which can reduce BTI degradation and improve the duty cycle (e.g., resolution, accuracy) of the high frequency clock. Therefore, incorporating a clock multiplier reduces latency of the memory system 110, allows the memory system 110 to support higher bandwidth, increases the drain current, transconductance, lifetime, and stability of threshold voltage of transistors in the memory system 110. In some examples, other systems (e.g., the host system 105) can implement the clock multiplier circuit to mitigate BTI degradation while supporting operation at a higher frequency clock signal.

[0035] In addition to being applied to the systems described herein, systems and techniques for clock multiplication while using a divided clock to prevent BIT may be generally implemented to improve the performance of various electronic devices and systems (including games). Some electronic device applications (including games and other high-performance applications) may be associated with relatively high processing requirements while also benefiting from relatively fast response times to improve the user experience. Thus, it may be desirable to increase processing speed, reduce response time, or otherwise improve electronic device performance. Implementation of the techniques described herein may improve the performance of electronic devices by supporting higher clock signal frequencies to increase processing speed and bandwidth and reduce latency and response time (e.g., improve user experience) while preventing (e.g., reducing, alleviating) BTI degradation and other benefits.

[0036] Figure 2A and 2BAn example of a circuit 200 (e.g., a clock multiplier) supporting systems and techniques for clock multiplication according to examples disclosed herein and an example of a timing diagram 201 are illustrated, respectively. Circuit 200 can be incorporated into system 100 (e.g., as part of memory system 110) and includes inputs 205-a and 205-b, output 210, delay elements 215-a and 215-b, and various logic gates, such as inverters 216-a and 216-b, AND gates 217-a and 217-b, and OR gate 218. Input 205-a can correspond to clock signal 220-a having a rising edge 230 (e.g., rising edges 230-a and 230-b). Input 205-b can correspond to clock signal 220-b having a rising edge 235 (e.g., rising edges 235-a and 235-b). Clock signal 220-a and clock signal 220-b can have the same frequency and the phases can be offset relative to each other. Output 210 may correspond to a clock signal 225 having a rising edge 240 (e.g., rising edges 240-a to 240-d) and a falling edge 242 (e.g., falling edges 242-a to 242-d). Clock signal 225 may have a variable pulse width that is individually trimmed with pulse width variability 245. Circuit 200 may be coupled with a controller (e.g., memory system controller 140, local controller 150) that is configured to, for example, access memory array 155 using (e.g., based on) clock signal 225 output by circuit 200. Clock signals 220 and 225 may be generated internally in a memory system 110 implementing circuit 200 and propagated along a clock tree of memory system 110 to various components (e.g., various components of memory system 110, memory device 145). In some examples, clock signals 220, 225 may be generated in response to a command (e.g., a read command, a command to access a memory cell). In some examples, clock signal 220 may be always on.

[0037] Due to the high frequency clock and the long clock tree path, the clock signal may suffer from BTI degradation. In order to reduce BTI degradation, the system may include a low frequency clock signal. However, the low frequency clock signal may result in slower operation, lower bandwidth, lower data rate and other adverse effects. The circuit 200 may allow the system 100 to support the use of a lower frequency clock signal 220 along a portion of the clock tree (e.g., a portion upstream of the circuit 200, such as closer to the channel 115) and the use of a higher frequency clock signal 225 (e.g., a clock having a frequency twice that of the lower frequency clock signal 220) along another portion of the clock tree (e.g., the end of the clock tree, a portion downstream of the circuit 200, such as closer to the memory array 155). The higher frequency clock signal 225 may be generated based on an external command (e.g., a read command, a command to access a memory cell). The clock signal 225 may be used to execute a command (e.g., access a memory cell). For example, access circuitry (e.g., one or more decoders, one or more sensing components, one or more controllers, one or more input / output (I / O) components) included in the memory system 110 and used to access the memory array 155 may operate according to the clock signal 225.

[0038] Input 205-a (e.g., clock signal 220-a) and input 205-b (e.g., clock signal 220-b) of circuit 200 can be combined to produce output 210 (e.g., clock signal 225). Clock signal 220 can be generated internally (e.g., on a DRAM chip). Clock signal 220-a (e.g., input 205-a) and clock signal 220-b (e.g., input 205-b) can have the same frequency. In some examples, both clock signal 220-a and clock signal 220-b can start in the same low mode (e.g., both clock signals 220 are low before the rising edge 230-a of clock signal 220-a). The rising edge 235 of clock signal 220-b can be delayed (e.g., offset) relative to the rising edge 230 of clock signal 220-a. For example, clock signal 220-b may be delayed 180 degrees relative to clock signal 220-a, so that rising edge 235 of clock signal 220-b corresponds (e.g., aligned, simultaneous, or nearly simultaneous) to falling edge 236 of clock signal 220-a. In some cases, the phases of clock signal 220 may be offset such that they are not 180 degrees relative to each other, which may be referred to as a phase mismatch of clock signal 220. In some examples, the duty cycle monitor circuit may support adjusting the phase to maintain a 180 degree relationship, as described herein, including reference Figures 3A to 3C .

[0039] An input 205 (e.g., clock signal 220) of circuit 200 may be used to generate an output 210 (e.g., clock signal 225). Input 205-a may be routed through delay component 215-a and inverter 216-a before being input into AND gate 217-a. Another input of AND gate 217-a may be unmodified input 205-a (e.g., undelayed and uninverted). Input 205-b of circuit 200 may enter delay component 215-b and inverter before being input into AND gate 217-b. Another input of AND gate 217-b may be unmodified input 205-b (e.g., undelayed and uninverted). Delay component 215 may be adjusted to modify the delay of corresponding input 205 into corresponding AND gate 217. The output of AND gate 217-a and the output of AND gate 217-b may be inputs to OR gate 218. The output of OR gate 218 may be output 210 and corresponds to clock signal 225.

[0040] The clock signal 225 may have different properties than the clock signal 220. The clock signal 225 may have twice the frequency of the input clock signal 220 (the clock signals 220-a and 220-b have the same frequency). The clock signal 225 may have a smaller pulse width (e.g., half the pulse width of the input clock signal 220) than the input clock signal 220 (the clock signals 220-a and 220-b have the same pulse width). The pulse width of the clock signal 225 may be based on the delay component 215-a and the delay component 215-b. For example, the clock signal 225 (e.g., the rising edge 240 and the falling edge 242) may be generated based on the respective rising edges 230 and 235 of the clock signals 220-a and 220-b and the delay of the clock signal 220 applied by the delay component 215. For example, if the unmodified input 205 is high and the modified input 205 (e.g., the input 205 routed through the delay component 215 and the inverter 216) is low (e.g., because the inverter 216 inverts the modified input 205), then the output of the AND gate 217 may be high. Thus, the output of the AND gate 217, and therefore the clock signal 225, may be high (e.g., turned on, asserted) for the duration that the modified input 205 is delayed by the delay component 215 and the unmodified input 205 is high. Thus, the rising edge of the unmodified input 205 may correspond to the rising edge 240 of the pulse of the clock signal 225, and the rising edge of the modified input 205 may correspond to the falling edge 242 of the pulse of the clock signal 225.

[0041] The duty cycle of the clock signal 225 (e.g., the percentage or ratio of time that the time signal 225 is high) can be adjusted by modifying (e.g., adding, fusing) the delay component 215 to modify the delay applied by the delay component 215 on the input 205. For example, adjusting the delay applied by the delay component 215 can adjust the duration between the rising edge of the unmodified input 205 and the rising edge of the modified input 205, where the duration between the rising edges corresponds to the pulse width of the clock signal 225. Thus, the pulse width of the clock signal 225 can be individually trimmed using the delay component 215. The delay component 215 can be controlled (e.g., adjusted by a test mode) so that the delay component 215 adjusts the pulse width of the clock signal 225 according to the pulse width variability 245. For example, after the clock signal 225 is initially generated, the pulse width of the clock signal 225 can be adjusted by adjusting the delay applied by the delay component 215. The adjustment of the clock signal 225 (e.g., as part of a test mode) can compensate for Monte Carlo effects or process variations in the duty cycle of the clock signal 225. In some examples, the pulse width of clock signal 225 may be half the pulse width of clock signal 220-a. In other examples, the pulse width of clock signal 225 may be less than half the pulse width of clock signal 220-a. In other examples, the pulse width of clock signal 225 may be greater than half the pulse width of clock signal 220-a.

[0042] The phase of clock signal 225 may be different from the phases of clock signal 220 - a and clock signal 220 - b. For example, the phase of clock signal 225 may be offset (eg, delayed) relative to clock signal 220 , such as due to clock signal 220 propagating through circuit 200 .

[0043] A controller coupled to circuit 200 may use clock signal 225 to execute commands (e.g., access a memory array). For example, the controller may use clock signal 225 to access one or more memory cells of a memory array according to a command. Clock signal 225 may be less sensitive to BTI degradation than other clock signals of similar frequency, for example, due to propagation along a smaller (e.g., shorter) portion of the clock tree. Thus, clock signal 225 may improve BTI resistance and robustness in systems implemented via longer clock paths.

[0044] Figure 3A , 3B3C show an example of a circuit 300 supporting systems and techniques for clock multiplication according to examples disclosed herein and examples of timing diagrams 301-a and 301-b, respectively. Circuit 300 may be incorporated into system 100 (e.g., as part of memory system 110) and frequency multiplication circuit 317 may be an example of circuit 200 (e.g., a circuit supporting outputting a higher frequency clock signal using two lower frequency clock signals as inputs). Circuit 300 may include inputs 305-a and 305-b, output 310, monitoring output 313, frequency multiplication circuit 317, delay components 320 (e.g., delay components 320-a and 320-b), monitoring circuit 322, or a combination thereof. Frequency multiplication circuit 317 may correspond to circuit 200 and include delay components 315 (e.g., delay components 315-a and 315-b, delay components 215), inverters, AND gates, and OR gates. The monitoring circuit 322 may include a clock component 325 , a multiplexer 330 , a duty cycle monitor 335 , and an inverter 316 .

[0045] The frequency multiplication circuit 317 may be coupled with the monitoring circuit 322 such that the output of the frequency multiplication circuit 317 is input to the monitoring circuit 322. The clock signals 340, 345, and 350 may be generated internally in the memory system 110 implementing the circuit 300 and propagated to various components (e.g., various components of the memory system 110, memory device 145) along the clock tree of the memory system 110. In some examples, the monitoring output 313 may relay an indication of whether the duty cycle of the clock signal or the output of the frequency multiplication circuit 317 meets a threshold to a pin (e.g., a pin of the memory system 110, e.g., to support adjustments during testing).

[0046] Timing diagrams 301-a and 301-b show examples of clock signals generated by circuit 300. In the example of timing diagram 301-a, input 305-a may correspond to clock signal 340-a having rising edge 342 (e.g., rising edges 342-a and 342-b), input 305-b may correspond to clock signal 340-b having rising edge 343 (e.g., rising edges 343-a and 343-b), and output 310 may correspond to clock signal 345 having rising edge 347 (e.g., rising edges 347-a to 347-d). Additionally, signal 312 generated by monitoring circuit 322 (e.g., output by clock component 325) may correspond to clock signal 350 having rising edge 352 (e.g., rising edge 352-a and 352-b) and falling edge 354 (e.g., falling edge 354-a and 354-b). In the example of timing diagram 301-b, input 305-a may correspond to clock signal 360-a having rising edge 362 (e.g., rising edges 362-a and 362-b), input 305-b may correspond to clock signal 360-b having rising edge 363 (e.g., rising edges 363-a and 363-b), output 310 may correspond to clock signal 365 having rising edge 367 (e.g., rising edges 367-a to 367-d), and signal 312 may correspond to clock signal 370 having rising edge 372 (e.g., rising edge 372-a and 372-b) and falling edge 374 (e.g., falling edge 374-a and 374-b). Clock signals 340-a, 340-b, 350, 360-a, 360-b, and 370 may each have the same frequency. Clock signals 345 and 365 may have the same frequency, which is higher (eg, twice) than the frequency of clock signal 340 (eg, clock signal 360).

[0047] The frequency multiplication circuit 317 can use the clock signal 340 to generate a clock signal 345, as shown in FIG. Figure 2A and 2B301 -a. Clock signal 340-a and clock signal 340-b may have the same frequency, but the phases may be offset relative to each other. In some examples, a 180 degree relative phase shift may distribute the pulses of clock signal 345 more evenly than other relative phase shifts. However, in some cases, the relative phase shift of clock signal 340 may be different from 180 degrees, for example due to the Monte Carlo effect and the asymmetric layout of the clock paths of clock signals 340-a and 340-b. In the example of timing diagram 301 -a, clock signal 340-b has a phase shift of more than 180 degrees relative to clock signal 340-a, so that rising edge 363 occurs after the falling edge of clock signal 340-a, and this non-180 degree relative phase shift may be referred to as a phase-to-phase mismatch. This mismatch may result in unevenly spaced pulses of clock signal 345 (e.g., rising edge 347-b may be closer to rising edge 347-c than rising edge 347-a).

[0048] The monitoring circuit 322 may identify and support correcting the phase mismatch of the clock signal 340-a and the clock signal 340-b. The monitoring circuit 322 may receive the clock signal 345 as an input and output one or more of the feedback signal 337 and the monitoring output 313. In order to support outputting the feedback signal 337 and the monitoring output 313, the clock signal 345 may be input into the clock component 325. The clock component 325 may adjust the clock signal 345 to a signal 312 (corresponding to the clock signal 350) having a lower frequency than the clock signal 345 (e.g., half the frequency of the clock signal 345). For example, the clock component 325 and the inverter 316 that feeds back the output of the clock component 325 to the input of the clock component 325 may operate as a clock divider to generate the clock signal 350 from the clock signal 345. The clock signal 350 may be generated based on the rising edge 347 of the clock signal 345. For example, two consecutive rising edges 347 may generate rising edge 352 and falling edge 354 of clock signal 350 (e.g., rising edge 347-a may correspond to rising edge 352-a, rising edge 347-b may correspond to falling edge 354-a, etc.). Clock signal 350 (e.g., signal 312) may be input to multiplexer 330. Clock signal 345 (e.g., output 310) may also be directly input to multiplexer 330.

[0049] Monitoring circuit 322 may identify and support correction of phase-to-phase mismatches according to various techniques, such as based on whether multiplexer 330 outputs clock signal 350 or clock signal 345. In some examples, multiplexer 330 outputs clock signal 350 (e.g., based on a selection signal input into multiplexer 330) to duty cycle monitor 335. Duty cycle monitor 335 may monitor the duty cycle of clock signal 350. Mismatches (e.g., relative phase shifts other than 180 degrees, misalignment between rising edge 342 of clock signal 340-a and falling edge of clock signal 340-b) may cause clock signal 345 to be non-periodic (e.g., having unevenly spaced pulses). If there is a mismatch between clock signals 340-a and 340-b, duty cycle monitor 335 may measure whether the duty cycle of clock signal 350 is above or below 50%. For example, if clock signal 340-b is delayed by more than 180 degrees relative to clock signal 340-a (as depicted), duty cycle monitor 335 may determine that the duty cycle of clock signal 350 is more than 50%. (For example, vice versa, if clock signal 340-b is delayed by less than 180 degrees relative to clock signal 340-a.) In other words, if the duty cycle of clock signal 350 is not 50%, duty cycle monitor 335 may determine that there is a mismatch between the phase of clock signal 340-a and the phase of clock signal 340-b.

[0050] In some examples, the multiplexer outputs the clock signal 345 (e.g., based on the selection signal input into the multiplexer 330) to the duty cycle monitor 335. The duty cycle monitor 335 may monitor the duty cycle of the clock signal 345 and receive an indication of the frequency of the clock signal 340, such as provided by the tester. Using the frequency of the clock signal 340 and the duty cycle of the clock signal 345, the duty cycle monitor 335 may determine (e.g., calculate) a pulse width (e.g., an absolute pulse width, such as high time in picoseconds) of the clock signal 345. If the duty cycle monitor 335 determines that the pulse width of the clock signal 345 fails to meet a threshold pulse width (e.g., the pulse width is not equal to the threshold pulse width, the pulse width is not within a pulse width range), then the duty cycle monitor 335 may determine that there is a mismatch between the phase of the clock signal 340-a and the phase of the clock signal 340-b.

[0051] If the duty cycle monitor 335 determines that there is a mismatch between the phase of the clock signal 340-a and the phase of the clock signal 340-b, the duty cycle monitor 335 may attempt to correct it. For example, the duty cycle monitor 335 may transmit a feedback signal 337 (e.g., directly) to one or more of the delay components 315, one or more of the delay components 320, or both to adjust the corresponding delays of the components. For example, the feedback signal 337 may indicate a corresponding adjustment to the corresponding delay of the corresponding delay component. Additionally or alternatively, the duty cycle monitor 335 may transmit the feedback signal 337 to a device 338 (e.g., a device, a state machine, a logic block that implements a safe adjustment mode or a training algorithm) to adjust the delay of the delay component 320. For example, the feedback signal 337 may indicate whether there is a mismatch between the phases, such as whether the duty cycle of the clock signal meets a threshold (e.g., is not 50%) or whether the pulse width of the clock signal 345 fails to meet a threshold pulse width. Based on the feedback signal 337 indicating the phase-to-phase mismatch, the device 338 can determine and perform one or more adjustments to the delay component. Additionally or alternatively, the duty cycle monitor 335 can output a monitoring output 313 indicating whether there is a phase-to-phase mismatch, such as to a tester, which can be used to determine and perform one or more adjustments to the delay component.

[0052] Clock signal 345, and therefore clock signal 350, may be adjusted based on adjusting one or more of the delays of the delay components. For example, adjusting the respective delays of one or more of the delay components 320 may adjust the phase of clock signal 340-a relative to clock signal 340-b. Adjusting the respective delays of one or more of the delay components 315 may adjust the pulse width of clock signal 345. Duty cycle monitor 335 may determine whether adjusted clock signal 340 is mismatched if the relative phase shift meets a threshold (e.g., if the duty cycle of adjusted clock signal 350 is greater than or less than 50%, then the phase shift is less than 179 degrees or greater than 181 degrees) or, for example, if the pulse width still fails to meet the threshold pulse width. In some examples, adjusting the pulse width of clock signal 345 may not adjust the relative phase of clock signal 340, but may adjust clock signal 345 so that clock signal 345 meets one or more operational constraints of clock signal 345. If the adjusted clock signal still mismatches after adjustment, the duty cycle monitor 335 can support additional adjustments to one or more delays of the delay component. The duty cycle monitor 335 can repeat this process (e.g., using a guess-and-check approach to adjusting the delays) until the phase-to-phase mismatch is corrected, such as until the phase shift between the two inputs 305-a and 305-b no longer meets a threshold (e.g., a phase shift of 180 degrees produces a duty cycle of the clock signal 370 of 49 to 51%) or, for example, until the pulse width meets a threshold pulse width.

[0053] Timing diagram 301-b shows an example of a corrected timing diagram (e.g., timing diagram 301-b after correcting for phase-to-phase mismatch). In the example of timing diagram 301-b, clock signal 360-a may correspond to clock signal 340-a, and clock signal 360-b may correspond to clock signal 340-b after delay component 320-b is adjusted to, for example, reduce the delay of clock signal 340-b. Clock signal 365 may correspond to adjusted clock signal 345 and may have a pulse interval (e.g., absolute pulse width) that is more ideal (e.g., uniform, symmetrical) than the pulse interval of clock signal 345. Clock signal 370 may correspond to clock signal 350 and may have a duty cycle that is closer to (e.g., equal to) 50% than the duty cycle of clock signal 350.

[0054] Clock signal 370 may be less sensitive to BTI degradation than other clock signals of similar frequency while maintaining a 50% duty cycle and evenly spaced pulses. Thus, clock signal 370 may be implemented in systems with improved BTI resistance and robustness via longer clock paths.

[0055] Figure 4A and 4B An example of a circuit 400 supporting systems and techniques for clock multiplication according to examples disclosed herein and an example of a timing diagram 401 are shown. Circuit 400 may include input 405, output 410, bypass signal 415, bypass select signal 418, multiplexer 420, signal 425, output 430, AND gates 435 (e.g., AND gates 435-a and 435-b), delay elements 437 (e.g., delay elements 437-a and 437-b), and multiplying circuit 417, which may be an example of circuit 200 or multiplying circuit 317. Input 405-a may correspond to clock signal 440-a having a rising edge 455 (e.g., rising edges 455-a and 455-b), input 405-b may correspond to clock signal 440-b having a rising edge 460 (e.g., rising edges 460-a and 460-b), output 430 may correspond to clock signal 445 having a rising edge 470 (e.g., rising edges 470-a to 470-d), and signal 425 may correspond to clock signal 450 having a rising edge 480 (e.g., rising edges 480-a and 480-b).

[0056] Circuit 400 may implement aspects of circuit 200 or circuit 300. For example, frequency multiplication circuit 417 may use inputs 405-a and 405-b (clock signals 440-a and 440-b, each having the same frequency and a relative 180 degree phase shift, which may be corrected to 180 degrees, e.g., by using monitoring circuit 322) to generate output 430 (clock signal 445 having a frequency higher (e.g., twice) than the frequency of clock signal 440). In some examples, multiplexer 420 may select output 430 such that output 410 corresponds to clock signal 445. In other examples, multiplexer 420 may select signal 425 such that output 410 corresponds to clock signal 450. Multiplexer 420 may select output 430 or signal 425 based on bypass select signal 418.

[0057] In some cases, if a clock signal is not present, BTI degradation in the circuit may increase. A high frequency clock signal may be more sensitive to BTI degradation because it operates at a lower pulse width, which may result in having a tighter timing budget. Because BTI degradation may be relatively more detrimental when a clock signal is not present than when a clock signal is present, it may be beneficial to implement a relatively low frequency clock signal into the circuit to mitigate the degradation effects. For example, when the circuit is in a low power or idle mode, a lower frequency clock may be used because a lower frequency clock may be associated with lower power consumption than a higher frequency clock.

[0058] In some examples, circuit 400 (e.g., a memory system implementing circuit 400) may enter an idle mode (e.g., due to a command, lack of or reduction in executing access commands). In response to entering the idle mode, circuit 400 may switch the output of multiplexer 420 from output clock signal 445 (e.g., selecting output 430) to output clock signal 450 (e.g., selecting signal 425). Signal 425 may be forward input 405-a of multiplexer 420. Thus, signal 425 may correspond to clock signal 440-a with a relatively small phase shift relative to clock signal 440-a, for example, due to clock signal 440-a propagating to multiplexer 420. A memory system implementing circuit 400 (e.g., a controller of the memory system) may drive bypass select signal 418 so that multiplexer 420 may select signal 425 so that output 410 corresponds to clock signal 450. If the memory system exits idle mode, the memory system may drive bypass select signal 418 to cause multiplexer to select output 430 such that output 410 corresponds to clock signal 445. Thus, clock signal 445 (e.g., a high frequency clock) may be used when the memory system is not in idle mode, and clock signal 450 (e.g., a low frequency clock) may be used when the memory system is in idle mode. In some examples, input 405-b may be forwarded instead of input 405-a such that output 410 corresponds to delayed clock signal 440-b. Using a lower frequency clock (as opposed to a high frequency clock or no clock at all) may mitigate the effects of BTI degradation while maintaining the reduced power consumption expected in idle mode.

[0059] Maintaining the high or low state of frequency multiplication circuit 417 may cause degradation of clock signal 440. If frequency multiplication circuit 417 is maintained in a high state (e.g., when circuit 400 is in idle mode), rising edges 455 and 460 of clock signal 440 may be degraded because they are again routed through frequency multiplication circuit 417 (e.g., after exiting idle mode). If frequency multiplication circuit 417 is maintained in a low state, falling edges of clock signal 440 may be degraded (e.g., and rising edges 455 and 460 may be maintained) because they are again routed through frequency multiplication circuit 417. Because clock signal 445 is generated based on rising edges 455 and 460 of clock signal 440, maintaining rising edges 455 and 460 (e.g., reducing degradation of rising edges 455 and 460) may be more beneficial than maintaining falling edges. To prevent (e.g., reduce, mitigate) rising edge degradation and pulse width degradation when the output of the frequency multiplier circuit 417 is bypassed (e.g., when the multiplexer 420 selects the signal 425), the circuit 400 can use the AND gate 435 and the bypass signal 415 to maintain the frequency multiplier circuit 417 in a low state. For example, based on entering the idle mode, the memory system can switch the bypass signal 415 to a low state. The AND gate 435 can receive the bypass signal 415 and its corresponding input 405 as inputs. Based on the bypass signal 415 being in a low state, the AND gate 435 can output a low signal to maintain the frequency multiplier circuit 417 in a low state when the circuit 400 is in the idle mode. If the memory system is not in the idle mode, the bypass signal 415 can be switched to a high state and the AND gate 435 can output its corresponding input 405 (e.g., the corresponding clock signal 440).

[0060] In response to exiting the idle mode (e.g., due to a determination, due to a command, to enter a non-idle state), the circuit 400 may switch the output 410 of the multiplexer from the output clock signal 450 to the output clock signal 445, for example, based on the state of the switch bypass select signal 418. By using the clock signal 450 during the idle mode operation, a lower frequency clock (rather than the higher frequency clock signal 445 or no clock at all), BTI degradation, and power consumption associated with the idle mode operation are reduced.

[0061] Figure 5 A block diagram 500 is shown of a memory system 520 that supports systems and techniques for clock multiplication according to examples disclosed herein. The memory system 520 may be a reference Figures 1 to 4B5. The memory system 520 or its various components may be examples of means for performing various aspects of the systems and techniques for clock multiplication, as described herein. For example, the memory system 520 may include a command component 525, a first clock component 530, a second clock component 535, a third clock component 540, an access component 545, a fourth clock component 550, a monitoring component 555, an adjustment component 560, a pulse width component 565, an idle component 570, a switch component 575, or any combination thereof. Components of each of these components or subcomponents thereof (e.g., one or more processors, one or more memories) may communicate with each other directly or indirectly (e.g., via one or more buses).

[0062] The command component 525 may be configured as or otherwise support means for receiving a command to access one or more memory cells of a memory device. The first clock component 530 may be configured as or otherwise support means for generating a first clock signal having a first frequency based at least in part on the command. The second clock component 535 may be configured as or otherwise support means for generating a second clock signal having a first frequency based at least in part on the command, wherein a first phase of the first clock signal is different from a second phase of the second clock signal. The third clock component 540 may be configured as or otherwise support means for generating a third clock signal based at least in part on the first clock signal and the second clock signal, the third clock signal having a second frequency higher than the first frequency. The access component 545 may be configured as or otherwise support means for accessing one or more memory cells based at least in part on the third clock signal.

[0063] In some examples, the fourth clock component 550 may be configured or otherwise support means for generating a fourth clock signal based at least in part on the third clock signal, the fourth clock signal having a third frequency that is lower than the second frequency. In some examples, the monitoring component 555 may be configured or otherwise support means for monitoring a duty cycle of the fourth clock signal. In some examples, the adjustment component 560 may be configured or otherwise support means for adjusting a first delay of the first clock signal or a second delay of the second clock signal based at least in part on the duty cycle satisfying a threshold duty cycle, wherein the duration between respective pulses of the third clock signal is adjusted based at least in part on adjusting the first delay or the second delay.

[0064] In some examples, monitoring component 555 can be configured or otherwise support means for monitoring a duty cycle of the fourth clock signal after adjusting the first delay or the second delay. In some examples, adjustment component 560 can be configured or otherwise support means for adjusting the first delay or the second delay based at least in part on the duty cycle satisfying a threshold duty cycle after adjusting the first delay or the second delay.

[0065] In some examples, the duty cycle satisfying the threshold duty cycle includes the duty cycle being greater than a 50% duty cycle.

[0066] In some examples, the second phase is shifted 180 degrees relative to the first phase based at least in part on the adjustment.

[0067] In some examples, monitoring component 555 may be configured or otherwise support means for monitoring a duty cycle of the third clock signal. In some examples, pulse width component 565 may be configured or otherwise support means for determining a pulse width of the third clock signal based at least in part on the first frequency and the duty cycle of the third clock signal. In some examples, adjustment component 560 may be configured or otherwise support means for adjusting a first delay of the first clock signal or a second delay of the second clock signal based at least in part on the pulse width satisfying a threshold pulse width, wherein the pulse width of the third clock signal is adjusted based at least in part on adjusting the first delay or the second delay.

[0068] In some examples, the second frequency is twice the first frequency.

[0069] In some examples, the first clock signal has a first pulse width, the second clock signal has a first pulse width, and the third clock signal has a second pulse width that is smaller than the first pulse width.

[0070] In some examples, adjustment component 560 can be configured or otherwise support means for adjusting the second pulse width after generating the third clock signal.

[0071] In some examples, the third clock signal has a third phase different from the first phase and the second phase.

[0072] In some examples, the second phase is shifted 180 degrees relative to the first phase.

[0073] In some examples, idle component 570 can be configured as or otherwise support means for determining that the memory device is in an idle state after accessing one or more memory cells. In some examples, switch component 575 can be configured as or otherwise support means for switching the output of the multiplexer from the third clock signal to the first clock signal based at least in part on the memory device being in an idle state.

[0074] In some examples, the described functionality of the memory system 520 or its various components may be supported by or may refer to at least a portion of at least one processor, where such at least one processor may include one or more processing elements (e.g., a controller, a microprocessor, a microcontroller, a digital signal processor, a state machine, discrete gate logic, discrete transistor logic, discrete hardware components, or any combination of one or more of such elements). In some examples, the described functionality of the memory system 520 or its various components may be implemented at least in part by instructions (e.g., stored in a memory, a non-transitory computer-readable medium) that are executable by such at least one processor.

[0075] Figure 6 A flowchart illustrating a method 600 for supporting systems and techniques for clock multiplication according to examples disclosed herein is shown. The operations of the method 600 may be implemented by the memory system or components thereof described herein. For example, the operations of the method 600 may be implemented by reference to Figures 1 to 5 The memory system described herein performs. In some examples, the memory system may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the memory system may use dedicated hardware to perform aspects of the described functions.

[0076] At 605, the method may include receiving a command to access one or more memory cells of a memory device. In some examples, aspects of operation 605 may be described with reference to Figure 5 The command component 525 described here executes.

[0077] At 610, the method may include generating a first clock signal having a first frequency based at least in part on the command. In some examples, aspects of operation 610 may be referred to as Figure 5 The first clock component 530 is described to perform.

[0078] At 615, the method may include generating a second clock signal having a first frequency based at least in part on the command, wherein a first phase of the first clock signal is different from a second phase of the second clock signal. In some examples, aspects of operation 615 may be referred to as Figure 5 The second clock component 535 described performs.

[0079] At 620, the method may include generating a third clock signal based at least in part on the first clock signal and the second clock signal, the third clock signal having a second frequency that is higher than the first frequency. In some examples, aspects of operation 620 may be referred to as Figure 5 The third clock component 540 is described to perform.

[0080] At 625, the method may include accessing one or more memory cells based at least in part on the third clock signal. In some examples, aspects of operation 625 may be referred to as Figure 5 The access component 545 described above performs the above.

[0081] In some examples, an apparatus described herein may perform one or several methods, such as method 600. An apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure, or any combination thereof:

[0082] Aspect 1: A method, apparatus, or non-transitory computer-readable medium comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: receiving a command to access one or more memory cells of a memory device; generating a first clock signal having a first frequency based at least in part on the command; generating a second clock signal having the first frequency based at least in part on the command, wherein a first phase of the first clock signal is different from a second phase of the second clock signal; generating a third clock signal based at least in part on the first clock signal and the second clock signal, the third clock signal having a second frequency higher than the first frequency; and accessing the one or more memory cells based at least in part on the third clock signal.

[0083] Aspect 2: The method, apparatus, or non-transitory computer-readable medium according to Aspect 1, further comprising the following operations, features, circuit systems, logic, components, or instructions, or any combination thereof: generating a fourth clock signal based at least in part on the third clock signal, the fourth clock signal having a third frequency lower than the second frequency; monitoring the duty cycle of the fourth clock signal; and adjusting the first delay of the first clock signal or the second delay of the second clock signal based at least in part on the duty cycle satisfying a threshold duty cycle, wherein the duration between corresponding pulses of the third clock signal is adjusted at least in part based on adjusting the first delay or the second delay.

[0084] Aspect 3: The method, apparatus, or non-transitory computer-readable medium according to Aspect 2, further comprising the following operations, features, circuit systems, logic, components, or instructions, or any combination thereof: monitoring the duty cycle of the fourth clock signal after adjusting the first delay or the second delay; and adjusting the first delay or the second delay based at least in part on the duty cycle satisfying the threshold duty cycle after adjusting the first delay or the second delay.

[0085] Aspect 4: The method, apparatus, or non-transitory computer-readable medium of any of Aspects 2-3, wherein the duty cycle satisfies the threshold duty cycle includes the duty cycle being greater than a 50% duty cycle.

[0086] Aspect 5: The method, apparatus, or non-transitory computer-readable medium of any of aspects 2 to 4, wherein the second phase is shifted 180 degrees relative to the first phase based at least in part on the adjustment.

[0087] Aspect 6: The method, apparatus, or non-transitory computer-readable medium according to Aspect 1, further comprising the following operations, features, circuit systems, logic, components, or instructions, or any combination thereof: monitoring the duty cycle of the third clock signal; determining the pulse width of the third clock signal based at least in part on the first frequency and the duty cycle of the third clock signal; and adjusting the first delay of the first clock signal or the second delay of the second clock signal based at least in part on the pulse width satisfying a threshold pulse width, wherein the pulse width of the third clock signal is adjusted at least in part based on adjusting the first delay or the second delay.

[0088] Aspect 7: The method, apparatus, or non-transitory computer-readable medium of any one of aspects 1 to 6, wherein the second frequency is twice the first frequency.

[0089] Aspect 8: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 7, wherein the first clock signal has a first pulse width, the second clock signal has the first pulse width, and the third clock signal has a second pulse width smaller than the first pulse width.

[0090] Aspect 9: The method, apparatus, or non-transitory computer-readable medium of aspect 8, further comprising operations, features, circuit systems, logic, means, or instructions, or any combination thereof, for: adjusting the second pulse width after generating the third clock signal.

[0091] Aspect 10: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 to 9, wherein the third clock signal has a third phase different from the first phase and the second phase.

[0092] Aspect 11: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 to 10, wherein the second phase is shifted 180 degrees relative to the first phase.

[0093] Aspect 12: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 11, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: determining that the memory device is in an idle state after accessing the one or more memory cells; and switching the output of the multiplexer from the third clock signal to the first clock signal based at least in part on the memory device being in the idle state.

[0094] It should be noted that the aspects described herein describe possible implementations, and that operations and steps may be rearranged or otherwise modified and other implementations are possible. Furthermore, portions from two or more of the methods may be combined.

[0095] An apparatus is described. The following provides an overview of aspects of the apparatus described herein:

[0096] Aspect 13: A device comprising: a first circuit configured to generate a first clock signal having a first frequency and a second clock signal having the first frequency, wherein a first phase of the first clock signal is different from a second phase of the second clock signal; a second circuit coupled to the first circuit, the second circuit configured to generate a third clock signal based at least in part on the first clock signal and the second clock signal, the third clock signal having a second frequency higher than the first frequency; and at least one controller coupled to the second circuit and configured to use the third clock signal to access a memory array of the device.

[0097] Aspect 14: An apparatus according to Aspect 13, wherein the apparatus further comprises: a third circuit configured to: generate a fourth clock signal based at least in part on the third clock signal and having a third frequency lower than the second frequency; and output a signal indicating a duty cycle of the fourth clock signal.

[0098] Aspect 15: An apparatus according to Aspect 14, wherein the third circuit is configured to: output the signal to a delay component associated with the first clock signal or the second clock signal or both, wherein the delay component is configured to adjust a first delay of the first clock signal or a second delay of the second clock signal based at least in part on the signal indicating that the duty cycle satisfies a threshold duty cycle.

[0099] Aspect 16: An apparatus according to any one of Aspects 14 to 15, wherein the first circuit includes a first delay component configured to delay the first clock signal for a first duration and a second delay component configured to delay the second clock signal for a second duration, and the first duration, the second duration, or both are adjusted at least in part based on the signal indicating that the duty cycle satisfies a threshold duty cycle.

[0100] Aspect 17: The apparatus according to any one of aspects 13 to 16, wherein the second frequency is twice the first frequency.

[0101] Aspect 18: An apparatus according to any one of Aspects 13 to 17, wherein the second circuit includes a first delay component configured to delay the first clock signal and a second delay component configured to delay the second clock signal, wherein the pulse width of the third clock signal is at least partially based on the delay of the first clock signal and the delay of the second clock signal.

[0102] Aspect 19: An apparatus according to Aspect 18, wherein the apparatus further comprises: a third circuit coupled to the second circuit and configured to: determine the pulse width of the third clock signal based at least in part on the first frequency and the duty cycle of the third clock signal; and output a signal to the first delay component, the second delay component, or both for adjusting the delay of the first clock signal, the delay of the second clock signal, or both, wherein the pulse width of the third clock signal is adjusted at least in part based on outputting the signal.

[0103] Aspect 20: An apparatus according to any one of aspects 13 to 19, wherein the second circuit includes: a multiplexer configured to receive the first clock signal and the third clock signal as inputs and output the first clock signal or the third clock signal based at least in part on a state of the apparatus.

[0104] Aspect 21: The apparatus of aspect 20, wherein the multiplexer is configured to: output the first clock signal when the apparatus is in an idle state; and output the third clock signal when the apparatus is in a non-idle state.

[0105] Aspect 22: An apparatus according to any one of Aspects 13 to 21, wherein the second circuit further comprises: a first logic gate configured to receive the first clock signal and the bypass signal as inputs and output the first clock signal or the first signal to a first delay component of the second circuit based at least in part on the bypass signal, the bypass signal being based at least in part on a state of the apparatus; and a second logic gate configured to receive the second clock signal and the bypass signal as inputs and output the second clock signal or the second signal to a second delay component of the second circuit based at least in part on the bypass signal, wherein the third clock signal is generated at least in part on the bypass signal.

[0106] Aspect 23: The apparatus according to any one of aspects 13 to 22, wherein the first clock signal has a first pulse width, the second clock signal has the first pulse width, and the third clock signal has a second pulse width smaller than the first pulse width.

[0107] Aspect 24: The apparatus of aspect 23, wherein the second circuit is configured to: adjust the second pulse width after generating the third clock signal.

[0108] Aspect 25: The apparatus of any one of aspects 13 to 24, wherein the third clock signal has a third phase different from the first phase and the second phase.

[0109] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, or signaling symbols that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, a signal may represent a bus of signals, where the bus may have various bit widths.

[0110] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports the flow of signals between the components. Components may be considered to be in electronic communication (e.g., conductive contact, connection, coupling) with each other if there is any electrical path (e.g., conductive path) between the components that can support the flow of signals (e.g., charge, current, voltage) between the components at any time. The conductive path between components that are in electronic communication (e.g., conductive contact, connection, coupling) with each other may be an open circuit or a closed circuit based on the operation of the device including the connected components. The conductive path between the connected components may be a direct conductive path between the components or may be an indirect conductive path including an intermediate component (e.g., a switch, transistor, or other component). In some examples, the flow of signals between the connected components may be interrupted for a period of time, for example, using one or more intermediate components (e.g., a switch or transistor).

[0111] The switch components (e.g., transistors) discussed herein may be field effect transistors (FETs) and may include a source (e.g., a source terminal), a drain (e.g., a drain terminal), a channel between the source and the drain, and a gate (e.g., a gate terminal). The conductivity of the channel may be controlled (e.g., modulated) by applying a voltage to the gate, which may cause the channel to become conductive in some examples. The switch component may be an example of an n-type FET or a p-type FET.

[0112] The description set forth herein describes example configurations in conjunction with the accompanying drawings and does not represent all examples that may be implemented or within the scope of the claims. The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some examples, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0113] In the accompanying drawings, similar components or features may have the same reference label. Similar components may be distinguished by following the reference label with one or more dashes and an additional label that distinguishes the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components with the same first reference label, regardless of the additional reference label.

[0114] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted by a computer-readable medium as one or more instructions (e.g., code). Due to the nature of software, the functions described herein may be implemented using software executed by a processor, hardware, firmware, hardwiring, or a combination of any of these. Features implementing the functions may be physically located at various locations, including distributed such that portions of the functions are implemented at different physical locations.

[0115] The illustrative blocks and modules described herein may be implemented or executed with a processor designed to perform the functions described herein, such as a DSP, ASIC, FPGA, discrete gate logic, discrete transistor logic, discrete hardware components, other programmable logic devices, or any combination thereof. A processor may be an example of a microprocessor, a controller, a microcontroller, a state machine, or other type of processor. A processor may also be implemented as at least one of one or more computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0116] As used herein (including in the claims), "or" used in a list of items (e.g., a list of items preceded by a phrase such as "at least one of" or "one or more of") indicates an inclusive list, so that (for example) a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). In addition, as used herein, the phrase "based on" should not be interpreted as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0117] Computer-readable media include both non-transitory computer storage media and communication media, including any media that facilitates the transfer of a computer program from one location to another. Non-transitory storage media may be any available media or combination of multiple media that can be accessed by a computer. For example, but not limited to, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disk storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media or combination of media that can be used to carry or store desired program code components in the form of instructions or data structures and can be accessed by a computer or processor.

[0118] The description and drawings are provided to enable one of ordinary skill in the art to make or use the present disclosure. One of ordinary skill in the art will appreciate various modifications to the present disclosure, and the techniques disclosed herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but should be given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method comprising: receiving a command to access one or more memory cells of a memory device; generating a first clock signal having a first frequency based at least in part on the command; generating a second clock signal having the first frequency based at least in part on the command, wherein a first phase of the first clock signal is different from a second phase of the second clock signal; generating a third clock signal based at least in part on the first clock signal and the second clock signal, the third clock signal having a second frequency higher than the first frequency; and The one or more memory cells are accessed based at least in part on the third clock signal.

2. The method according to claim 1, further comprising: generating a fourth clock signal based at least in part on the third clock signal, the fourth clock signal having a third frequency that is lower than the second frequency; monitoring a duty cycle of the fourth clock signal; and A first delay of the first clock signal or a second delay of the second clock signal is adjusted based at least in part on the duty cycle satisfying a threshold duty cycle, wherein a duration between corresponding pulses of the third clock signal is adjusted based at least in part on adjusting the first delay or the second delay.

3. The method according to claim 2, further comprising: After adjusting the first delay or the second delay, monitoring the duty cycle of the fourth clock signal; and The first delay or the second delay is adjusted based at least in part on the duty cycle satisfying the threshold duty cycle after adjusting the first delay or the second delay. The method of claim 2 , wherein the duty cycle satisfying the threshold duty cycle comprises the duty cycle being greater than a 50% duty cycle. The method of claim 2 , wherein the second phase is shifted 180 degrees relative to the first phase based at least in part on the adjustment.

6. The method according to claim 1, further comprising: monitoring a duty cycle of the third clock signal; determining a pulse width of the third clock signal based at least in part on the first frequency and the duty cycle of the third clock signal; and A first delay of the first clock signal or a second delay of the second clock signal is adjusted based at least in part on the pulse width satisfying a threshold pulse width, wherein the pulse width of the third clock signal is adjusted based at least in part on adjusting the first delay or the second delay. The method of claim 1 , wherein the second frequency is twice the first frequency.

8. The method of claim 1, wherein the first clock signal has a first pulse width, the second clock signal has the first pulse width, and the third clock signal has a second pulse width smaller than the first pulse width.

9. The method according to claim 8, further comprising: After generating the third clock signal, adjusting the second pulse width.

10. The method of claim 1, wherein the third clock signal has a third phase different from the first phase and the second phase. The method of claim 1 , wherein the second phase is shifted 180 degrees relative to the first phase.

12. The method according to claim 1, further comprising: After accessing the one or more memory cells, determining that the memory device is in an idle state; and An output of a multiplexer is switched from the third clock signal to the first clock signal based at least in part on the memory device being in the idle state.

13. An apparatus comprising: a first circuit configured to generate a first clock signal having a first frequency and a second clock signal having the first frequency, wherein a first phase of the first clock signal is different from a second phase of the second clock signal; a second circuit coupled to the first circuit, the second circuit configured to generate a third clock signal based at least in part on the first clock signal and the second clock signal, the third clock signal having a second frequency higher than the first frequency; and At least one controller is coupled to the second circuit and configured to access a memory array of the device using the third clock signal.

14. The apparatus of claim 13, wherein the apparatus further comprises: A third circuit is configured to: generating a fourth clock signal based at least in part on the third clock signal and having a third frequency lower than the second frequency; and A signal indicating a duty cycle of the fourth clock signal is output.

15. The apparatus of claim 14, wherein the third circuit is configured to: The signal is output to a delay component associated with the first clock signal or the second clock signal, or both, wherein the delay component is configured to adjust a first delay of the first clock signal or a second delay of the second clock signal based at least in part on the signal indicating that the duty cycle satisfies a threshold duty cycle.

16. An apparatus according to claim 14, wherein the first circuit includes a first delay component configured to delay the first clock signal for a first duration and a second delay component configured to delay the second clock signal for a second duration, wherein the first duration, the second duration, or both are adjusted at least in part based on the signal indicating that the duty cycle satisfies a threshold duty cycle.

17. The apparatus of claim 13, wherein the second frequency is twice the first frequency.

18. The apparatus of claim 13, wherein the second circuit comprises a first delay component configured to delay the first clock signal and a second delay component configured to delay the second clock signal, wherein a pulse width of the third clock signal is based at least in part on the delay of the first clock signal and the delay of the second clock signal.

19. The apparatus of claim 18, wherein the apparatus further comprises: A third circuit is coupled to the second circuit and is configured to: determining the pulse width of the third clock signal based at least in part on the first frequency and a duty cycle of the third clock signal; and A signal for adjusting the delay of the first clock signal, the delay of the second clock signal, or both is output to the first delay component, the second delay component, or both, wherein the pulse width of the third clock signal is adjusted at least in part based on outputting the signal.

20. The apparatus of claim 13, wherein the second circuit comprises: A multiplexer is configured to receive the first clock signal and the third clock signal as inputs and to output either the first clock signal or the third clock signal based at least in part on a state of the apparatus.

21. The apparatus of claim 20, wherein the multiplexer is configured to: When the device is in an idle state, outputting the first clock signal; and When the device is in a non-idle state, the third clock signal is output.

22. The apparatus of claim 13, wherein the second circuit further comprises: a first logic gate configured to receive as inputs the first clock signal and a bypass signal and to output the first clock signal or a first signal to a first delay component of the second circuit based at least in part on the bypass signal, the bypass signal being based at least in part on a state of the device; and A second logic gate is configured to receive the second clock signal and the bypass signal as inputs and output the second clock signal or a second signal to a second delay component of the second circuit based at least in part on the bypass signal, wherein the third clock signal is generated based at least in part on the bypass signal.

23. The apparatus of claim 13, wherein the first clock signal has a first pulse width, the second clock signal has the first pulse width, and the third clock signal has a second pulse width that is smaller than the first pulse width.

24. The apparatus of claim 23, wherein the second circuit is configured to: After generating the third clock signal, adjusting the second pulse width.

25. The apparatus of claim 13, wherein the third clock signal has a third phase different from the first phase and the second phase.

26. An apparatus comprising: Memory device; and a controller coupled to the memory device, wherein the controller is configured to cause the apparatus to: receiving a command to access one or more memory cells of the memory device; generating a first clock signal having a first frequency based at least in part on the command; generating a second clock signal having the first frequency based at least in part on the command, wherein a first phase of the first clock signal is different from a second phase of the second clock signal; generating a third clock signal based at least in part on the first clock signal and the second clock signal, the third clock signal having a second frequency higher than the first frequency; and The one or more memory cells are accessed based at least in part on the third clock signal.

27. The apparatus of claim 26, wherein the controller is further configured to cause the apparatus to: generating a fourth clock signal based at least in part on the third clock signal, the fourth clock signal having a third frequency that is lower than the second frequency; monitoring a duty cycle of the fourth clock signal; and A first delay of the first clock signal or a second delay of the second clock signal is adjusted based at least in part on the duty cycle satisfying a threshold duty cycle, wherein a duration between corresponding pulses of the third clock signal is adjusted based at least in part on adjusting the first delay or the second delay.

28. The apparatus of claim 27, wherein the controller is further configured to cause the apparatus to: After adjusting the first delay or the second delay, monitoring the duty cycle of the fourth clock signal; and The first delay or the second delay is adjusted based at least in part on the duty cycle satisfying the threshold duty cycle after adjusting the first delay or the second delay.

29. The apparatus of claim 27, wherein the duty cycle satisfying the threshold duty cycle comprises the duty cycle being greater than a 50% duty cycle.

30. The apparatus of claim 27, wherein the second phase is shifted 180 degrees relative to the first phase based at least in part on the adjustment.

31. The apparatus of claim 26, wherein the controller is further configured to cause the apparatus to: monitoring a duty cycle of the third clock signal; determining a pulse width of the third clock signal based at least in part on the first frequency and the duty cycle of the third clock signal; and A first delay of the first clock signal or a second delay of the second clock signal is adjusted based at least in part on the pulse width satisfying a threshold pulse width, wherein the pulse width of the third clock signal is adjusted based at least in part on adjusting the first delay or the second delay.

32. The apparatus of claim 26, wherein the second frequency is twice the first frequency.

33. The apparatus of claim 26, wherein the first clock signal has a first pulse width, the second clock signal has the first pulse width, and the third clock signal has a second pulse width that is smaller than the first pulse width.

34. The apparatus of claim 33, wherein the controller is further configured to cause the apparatus to adjust the second pulse width after generating the third clock signal.

35. The apparatus of claim 26, wherein the third clock signal has a third phase different from the first phase and the second phase.

36. The apparatus of claim 26, wherein the second phase is shifted 180 degrees relative to the first phase.

37. The apparatus of claim 26, wherein the controller is further configured to cause the apparatus to: After accessing the one or more memory cells, determining that the memory device is in an idle state; and An output of a multiplexer is switched from the third clock signal to the first clock signal based at least in part on the memory device being in the idle state.

Images