Inter-symbol interference compensation for analog-to-digital converters

Abstract

An apparatus may include a delta-sigma analog-to-digital converter (ADC) configured to convert an analog input signal to a digital signal, the digital signal being a digital approximation of the analog input signal. A bitstream modifier is configured to receive the digital signal, output a first signal based on the digital signal at a first output, and output a first difference signal comprising a first difference between a first value of the digital signal and a second value of the digital signal at a second output. The second value is immediately prior to the first value in the digital signal. An error correction system is configured to receive the first signal, receive the first difference signal, determine a correction value using the first signal and the first difference signal, and modify the digital signal by applying the correction value to generate a corrected digital signal.

Description

Technical Field

[0001] Errors in analog-to-digital converters (ADCs) are compensated using an error correction system that may implement a machine learning engine. The error correction system is configured to compensate for inter-symbol interference that may occur in various ADCs, such as a delta-sigma ADC. Background Art

[0002] In electronics, an analog-to-digital converter ("ADC") is a system that converts an analog signal, such as sound picked up by a microphone or light entering a digital camera, into a digital signal. An ADC can also provide isolated measurements when implemented as an electronic device that converts an input analog voltage or current into a digital number representing the voltage or current magnitude.

[0003] More specifically, an ADC converts a continuous-time and continuous-amplitude analog signal into an output digital signal of discrete-time and discrete-amplitude. The conversion involves quantization of the input, so a small amount of error or noise is necessarily introduced into the process. In addition, rather than performing conversions continuously, the ADC performs conversions periodically, sampling the input signal at a certain sampling rate, which limits the permissible bandwidth of the input signal.

[0004] When using a non-return-to-zero coding scheme, a continuous-time sigma-delta (ΣΔ) modulator can suffer from signal degradation due to inter-symbol interference. This can result in falling and rising edge errors, as well as positive and negative glitch errors in the sigma-delta modulator that outputs a series of identical symbols. Summary of the invention

[0005] In some aspects, the technology described herein relates to a system comprising: a delta-sigma analog-to-digital converter (ADC) configured to convert an analog input signal into a digital signal, wherein the digital signal is a digital approximation of the analog input signal; a bitstream modifier configured to: receive the digital signal from the delta-sigma ADC; output a first signal at a first output terminal, wherein the first signal is based on the digital signal; and output a first difference signal at a second output terminal, wherein the first difference signal comprises a first difference between a first value of the digital signal and a second value of the digital signal, wherein the second value immediately precedes the first value in the digital signal; and an error correction system configured to: receive the first signal from the first output terminal of the bitstream modifier; receive the first difference signal from the second output terminal of the bitstream modifier; determine a correction value using the first signal and the first difference signal; and modify the digital signal by applying the correction value to generate a corrected digital signal.

[0006] According to one or more embodiments, the bitstream modifier is configured to:

[0007] determining a second difference between the first value of the digital signal and the second value of the digital signal,

[0008] determining a first squared difference of the second difference, and

[0009] The first squared difference value is output at a third output terminal of the bitstream modifier.

[0010] According to one or more embodiments, the error correction system is configured to receive the first squared difference value from the third output terminal of the bitstream modifier and to determine the correction value using the first squared difference signal.

[0011] According to one or more embodiments, the bitstream modifier is configured to:

[0012] determining a third difference between the second value of the digital signal and a third value of the digital signal, wherein the third value immediately precedes the second value in the digital signal,

[0013] determining a second squared difference of the third difference, and

[0014] The second square difference value of the third difference value is outputted at a fourth output terminal as a second square difference signal.

[0015] According to one or more embodiments, the error correction system is configured to receive the second squared difference value from the fourth output terminal of the bitstream modifier and to determine the correction value using the second squared difference signal from the fourth output terminal.

[0016] According to one or more embodiments, the error correction system is configured to receive a parameter value from a sensor, wherein the output of the delta-sigma ADC varies depending on the value of the parameter, and the parameter includes at least one of semiconductor manufacturing related process variations, voltage, and temperature.

[0017] According to one or more embodiments, the error correction system includes a neural network that has been configured through a training phase to compensate for variations in the output of the sigma-delta ADC using the parameters.

[0018] In some aspects, the technology described herein relates to a system comprising: a delta-sigma analog-to-digital converter (ADC) configured to convert an analog input signal into a digital signal, wherein the digital signal is a digital approximation of the analog input signal; a bitstream modifier comprising: an input terminal configured to receive the digital signal from the delta-sigma ADC; a first signal path connected between the input terminal of the bitstream modifier and a first output terminal of the bitstream modifier to output a first signal at the first output terminal; a first filter between the input terminal of the bitstream modifier and the first output terminal of the bitstream modifier; a second signal path connected between the input terminal of the bitstream modifier and a second output terminal of the bitstream modifier, wherein the second signal path comprises a filter configured to determine a first value of the digital signal and a first circuit for determining a first difference between a first value of the digital signal and a second value of the digital signal, wherein the second value immediately precedes the first value in the digital signal, and outputs the first difference as a first difference signal at the second output terminal; and a second filter, which is between the first circuit of the second signal path and the second output terminal of the bit stream modifier; and an error correction system, which includes: a first input terminal, which is connected to the first output terminal of the bit stream modifier; a second input terminal, which is connected to the second output terminal of the bit stream modifier; and a neural network, which is configured to: determine a correction value using the first signal from the first output terminal and the first difference signal from the second output terminal, and modify the digital signal by applying the correction value to generate a corrected digital signal, thereby compensating for inter-symbol interference in the digital signal.

[0019] According to one or more embodiments, the first filter is configured to attenuate signals having frequencies outside a first bandwidth, and the second filter is configured to attenuate signals having frequencies outside a second bandwidth, and wherein the first bandwidth is equal to the second bandwidth.

[0020] According to one or more embodiments, the bitstream modifier comprises a third signal path connected between the input terminal of the bitstream modifier and a third output terminal of the bitstream modifier, wherein the third signal path comprises:

[0021] a second circuit configured to determine a second difference between the first value of the digital signal and the second value of the digital signal,

[0022] a third circuit configured to determine a first squared value of the second difference value, wherein the bitstream modifier is configured to output the first squared value of the second difference value as a first squared difference signal at the third output terminal, and

[0023] A third filter is connected between the third circuit and the third output of the bit stream modifier, the third filter being configured to attenuate signals having frequencies outside a third bandwidth.

[0024] According to one or more embodiments, the error correction system comprises a third input connected to the third output of the bitstream modifier, and the neural network is configured to determine the correction value using the first squared difference signal from the third output.

[0025] According to one or more embodiments, the bitstream modifier comprises a fourth signal path connected between the input terminal of the bitstream modifier and a fourth output terminal of the bitstream modifier, wherein the fourth signal path comprises:

[0026] a fourth circuit configured to determine a third difference between the second value of the digital signal and a third value of the digital signal, wherein the third value immediately precedes the second value in the digital signal,

[0027] a fifth circuit configured to determine a second squared value of the third difference value, wherein the bitstream modifier is configured to output the second squared value of the third difference value as a second squared difference signal at the fourth output terminal, and

[0028] A fourth filter is connected between the fifth circuit and the fourth output of the bit stream modifier, the fourth filter being configured to attenuate signals having frequencies outside a fourth bandwidth.

[0029] According to one or more embodiments, the error correction system comprises a fourth input connected to the fourth output of the bit stream modifier, and the neural network is configured to determine the correction value using the second squared difference signal from the fourth output.

[0030] According to one or more embodiments, the system further includes a sensor configured to provide a parameter to the error correction system, wherein the output of the sigma-delta ADC varies depending on a value of the parameter.

[0031] According to one or more embodiments, the neural network has been configured through a training phase to compensate for variations in the output of the sigma-delta ADC using the parameters.

[0032] According to one or more embodiments, the parameter includes at least one of semiconductor manufacturing related process variation, voltage and temperature.

[0033] In some aspects, the technology described herein relates to a method comprising: receiving a digital signal from a delta-sigma analog-to-digital converter (ADC); generating a first difference signal comprising a first difference between a first value of the digital signal and a second value of the digital signal, wherein the second value immediately precedes the first value in the digital signal; determining a correction value using the first signal and the first difference signal; and modifying the digital signal by applying the correction value to generate a corrected digital signal, thereby compensating for inter-symbol interference in the digital signal.

[0034] According to one or more embodiments, the method further comprises:

[0035] determining a second difference between the first value of the digital signal and the second value of the digital signal;

[0036] determining a first squared difference of the second difference; and

[0037] The correction value is determined using the first squared difference signal.

[0038] According to one or more embodiments, the method further comprises:

[0039] determining a third difference between the second value of the digital signal and a third value of the digital signal, wherein the third value immediately precedes the second value in the digital signal;

[0040] determining a second square value of the third difference; and

[0041] The correction value is determined using the second squared difference signal.

[0042] According to one or more embodiments, the method further comprises:

[0043] determining a parameter value using a sensor, wherein the parameter comprises at least one of semiconductor manufacturing related process variations, voltage, and temperature; and

[0044] The correction value is determined using the parameter value. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] A more complete understanding of the subject matter may be obtained by referring to the detailed description and claims when considered in conjunction with the following drawings, in which like reference numerals refer to similar elements throughout the various figures.

[0046] Figure 1 is a block diagram depicting components of an example sigma-delta modulator 100 .

[0047] Figure 2Depicted is the inter-symbol interference (ie, "falling edge" error) of the output signal of the delta-sigma modulator as it transitions from a first symbol having a value of '1' to a second symbol having a value of '-1'.

[0048] Figure 3 Depicted is the inter-symbol interference (ie, "rising edge" error) of the output signal of the sigma-delta modulator as it transitions from a first symbol having a value of '-1' to a second symbol having a value of '1'.

[0049] Figure 4 Depicts intersymbol interference (ie, "positive glitch" error) of an output signal of a delta-sigma modulator, where the output includes a first symbol and consecutive second symbols each having a value of '1'.

[0050] Figure 5 Depicts intersymbol interference (ie, "negative-going glitch" error) of an output signal of a delta-sigma modulator, where the output includes a first symbol and consecutive second symbols each having a value of '-1'.

[0051] Figure 6 is a graph depicting an example analog input signal and corresponding output bit stream that may be generated by an example sigma-delta modulator.

[0052] Figure 7 It is based on the description Figure 6 A graph of the falling edge error signal generated by the analog input signal is shown.

[0053] Figure 8 It is based on the description Figure 6 A graph of the rising edge error signal generated by the analog input signal is shown.

[0054] Fig. 9 It is based on the description Figure 6 A graph of the positive-going glitch error signal generated by the analog input signal is shown.

[0055] Fig.10 It is based on the description Figure 6 A graph of the negative-going glitch error signal generated by the analog input signal is shown.

[0056] Fig.11 is a graph depicting a conventional representation of the frequency domain noise characteristics of an output signal of a delta-sigma modulator.

[0057] Fig.12 is a graph that takes into account the nonlinearity introduced by intersymbol interference Fig.11 A graph of the frequency domain noise characteristics of the output signal of the sigma-delta modulator.

[0058] Fig.13A system including an error correction system configured to correct or minimize errors generated by a sigma-delta modulator due to ISI is described.

[0059] Fig.14 is a diagram depicting the functional components of a bitstream modifier.

[0060] Fig.15 is a graph depicting the frequency spectrum of a signal output by a bitstream modifier.

[0061] Fig.16 A system including an error correction system configured to correct or minimize errors generated by a sigma-delta modulator due to ISI is described.

[0062] Fig.17 is a flow chart of an example method for compensating for inter-symbol interference in a delta-sigma ADC. DETAILED DESCRIPTION

[0063] The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter of the present application and the uses of such embodiments. As used herein, the words "exemplary" and "exemplary" mean "serving as an example, instance, or illustration". Any embodiment or embodiment described herein as exemplary or exemplary is not necessarily to be construed as being preferred or advantageous over other embodiments. In addition, it is not intended to be bound by any express or implied theory presented in the aforementioned technical field, background technology, or the following detailed description.

[0064] Like all circuits, analog-to-digital converters (ADCs) can suffer from signal degradation due to circuit nonlinearities. A sigma-delta modulator is an ADC configured to generate a digital output bit stream (which may include individual bits) in the form of a sequence of symbols, where the average magnitude of the output symbols is equal to or comparable to the magnitude of the analog input signal to the sigma-delta modulator.

[0065] Figure 1 is a block diagram depicting components of an example sigma-delta modulator 100. The sigma-delta modulator 100 includes an input 102 configured to receive an analog input signal. The input signal passes through a summing node 104 to a loop filter 106, which may include a discrete or continuous time analog filter. The output of the loop filter 106 is supplied to a quantizer 108, which is configured to convert the output of the integration stage into an amplitude and time discrete (i.e., digital) value or sign that is output as a digital signal at an output 110.

[0066] The digital signal output by the delta-sigma modulator 100 at the output 110 is also passed back through a digital-to-analog converter 112, which is configured to convert the output digital signal back into a corresponding analog signal. Ideally, the analog signal generated by the digital-to-analog converter 112 accurately matches the input signal originally received at the input 102. The analog output of the digital-to-analog converter 112 is supplied to the negative input of the summing node 104.

[0067] In this configuration, the digital-to-analog converter 112 provides a feedback loop such that the analog signal output by the digital-to-analog converter 112 is subtracted from the analog input signal received at the input 102. The result of this subtraction is supplied to the loop filter 106. In this manner, the sigma-delta modulator 100 is configured to generate a digital output bit stream whose average power level matches the power level of the analog input signal to the modulator.

[0068] Inter-symbol interference (ISI) in the output of a continuous-time delta-sigma modulator may degrade the integrity of the modulator's output signal. Specifically, when the modulator's output includes a series of symbols including digital values, the value of a particular symbol in the output signal may affect the symbol immediately following it. Therefore, there is a certain dependency between consecutive output symbols.

[0069] Figure 2-5 is a graph illustrating inter-symbol interference that may occur in a digital output signal of a sigma-delta modulator. Figure 2 Depicts intersymbol interference 200 (i.e., a "falling edge" error) in the output signal of a delta-sigma modulator as it transitions from a first symbol 202 having a value of '1' to a second symbol 204 having a value of '-1'. Specifically, the intersymbol interference is represented as the shaded area 206 because it takes some time for the actual value of the second symbol 204 to fully transition to the value -1. This delay can cause inaccuracies or errors in the output of the delta-sigma modulator that may need to be corrected.

[0070] Figure 3 Depicted is intersymbol interference 210 (i.e., a "rising edge" error) of the output signal of the delta-sigma modulator as it transitions from a first symbol 212 having a value of '-1' to a second symbol 214 having a value of '1'. Specifically, the intersymbol interference is represented as the shaded area 216 because it takes some time for the actual value of the second symbol 214 to fully transition to the value of 1. This delay can cause inaccuracies or errors in the output of the delta-sigma modulator that may need to be corrected.

[0071] Figure 4Depicted is intersymbol interference 220 (i.e., a "positive glitch" error) of an output signal of a delta-sigma modulator, where the output includes a first symbol 222 and a consecutive second symbol 224, each having a value of '1'. Specifically, the intersymbol interference is represented as a shaded area 226, which is generated due to the interference generated by the two sequential identical values. This can cause the output of the delta-sigma modulator to be inaccurate or erroneous, which may require correction.

[0072] Figure 5 Depicts intersymbol interference 230 (i.e., a "negative-going glitch" error) of an output signal of a delta-sigma modulator, where the output includes a first symbol 232 and a consecutive second symbol 234, each having a value of '-1'. Specifically, the intersymbol interference is represented as a shaded area 236, which is generated due to the interference generated by the two sequential identical values. This can cause the output of the delta-sigma modulator to be inaccurate or erroneous, which may require correction.

[0073] During operation, the signal modulation inside the ADC of the delta-sigma modulator creates output signal pulses based on the analog input signal received by the modulator. When the amplitude of the analog input signal is zero or almost zero, the output signal of the delta-sigma modulator will include a series of alternating symbols with an average value of zero or almost zero. In the alternating bit stream, when the amplitude of the input is close to zero, the falling edge and rising edge errors (e.g., Figure 2 and 3 On the other hand, the output of a sigma-delta modulator tends to be a continuous stream of '1's or '-1's when the analog input signal is at its maximum value (whether positive or negative), and is therefore most sensitive to positive and negative glitches, resulting in even-order distortion.

[0074] These different types of distortion are Figure 7-10 Shown in. Figure 6 is a graph depicting an example analog input signal 302 (which, in this example, approximates a sine wave) and a corresponding output bit stream 304 that may be generated by an example sigma-delta modulator. Figure 6 In , the horizontal axis represents time (ie, number of samples), and the vertical axis represents magnitude, which in this example can range from a maximum unitless value of '1' to a minimum value of '-1'.

[0075] like Figure 6 , the analog input signal 302 has regions 306 where the value of the analog input signal transitions between values ​​close to a maximum value of 1 and a minimum value of −1, and thus has an average value of zero to near zero. Those regions 306 represent time periods during which the output bit stream 304 switches at its highest frequency. Therefore, regions 306 of the output bit stream 304 are most likely to suffer from falling edge and rising edge errors or noise, which are respectively Figure 2 and3 Depicted in.

[0076] The analog input signal 302 has regions 308 where the value of the analog input signal is at or near its maximum value of 1. Thus, those regions 306 represent time periods during which the value of the output bit stream 304 is most likely to be subject to positive glitches, which are Figure 4 Depicted in.

[0077] The analog input signal 302 has regions 310 where the value of the analog input signal is at or near its minimum value of -1. Thus, those regions 310 represent time periods during which the value of the output bit stream 304 is most likely to be subject to negative-going glitches, which occur at Figure 5 Depicted in.

[0078] Figure 7 It is based on the description Figure 6 FIG. 3 is a graph of a falling edge error signal generated by a simulated input signal 302. Figure 7 In the figure, the horizontal axis represents time, and Figure 6 The horizontal axis is aligned with the value of , and the vertical axis represents the magnitude, which can range from a maximum unitless value of '1' to a minimum value of '-1'. Figure 7 In the example, the falling edge error signal consists of a signal represented by curve 320. When the value of the analog input signal 302 is specified as sin(x), the falling edge error signal depicted by curve 320 generally has the form cos(x) 2 This falling edge error signal can be derived by examining the density of a particular type of error (in this case, falling edge errors) in different time regions 306, 308, and 310. In this example, the error signal has a sinusoidal form, but for other input signals, the falling edge error signal may have a different shape.

[0079] Figure 8 It is based on the description Figure 6 FIG. 3 is a graph of a rising edge error signal generated by a simulated input signal 302. Figure 8 In the figure, the horizontal axis represents time, and Figure 6 The horizontal axis is aligned with the value of , and the vertical axis represents the magnitude, which can range from a maximum unitless value of '1' to a minimum value of '-1'. Figure 8 In the embodiment of the present invention, the rising edge error signal is composed of the signal represented by curve 330. When the value of the analog input signal 302 is specified as sin(x), the rising edge error signal depicted by curve 330 generally has the form -cos(x) 2 This rising edge error signal can be derived by examining the density of a particular type of error (in this case, rising edge errors) in different time regions 306, 308, and 310. In this example, the error signal has a sinusoidal form, but for other input signals, the rising edge error signal may have a different shape.

[0080] Fig. 9 It is based on the description Figure 6 FIG. 3 is a graph of a positive-going glitch error signal generated by a simulated input signal 302. Fig. 9 In the figure, the horizontal axis represents time, and Figure 6 The horizontal axis is aligned with the value of , and the vertical axis represents the magnitude, which can range from a maximum unitless value of '1' to a minimum value of '-1'. Fig. 9 , the positive-going glitch error signal consists of a signal represented by curve 340 , which is the sum of curves 342 and 344 .

[0081] When the value of analog input signal 302 is specified as sin(x), the positive-going glitch error signal depicted by curve 340 (which is the sum of curves 342 and 344) generally has the form -0.5sin(x)+0.5cos(x) 2 -0.5.

[0082] Fig.10 It is based on the description Figure 6 FIG. 3 is a graph of a negative-going glitch error signal generated by a simulated input signal 302. Fig.10 In the figure, the horizontal axis represents time, and Figure 6 The horizontal axis is aligned with the value of , and the vertical axis represents the magnitude, which can range from a maximum unitless value of '1' to a minimum value of '-1'. Fig.10 , the negative-going glitch error signal is composed of signals represented by curves 350, 352, and 354. When the value of the analog input signal 302 is specified as sin(x), the negative-going glitch error signal depicted by curve 350 (which is the sum of curves 352 and 354) generally has the form -0.5sin(x)-0.5cos(x) 2 +0.5.

[0083] In a sigma-delta modulator, nonlinearities in the feedback loop DAC of the sigma-delta modulator can produce intermodulation (IM) products, which can have the effect of reducing the signal-to-noise ratio (SNR) of the sigma-delta modulator due to the specific noise shaping characteristics of the sigma-delta modulator. Specifically, a sigma-delta modulator is typically configured to shape the quantization noise (N_quant) of the device so that most of the quantization noise is moved to the higher frequencies of the spectrum of the modulator's output signal (enabling those noise signals to be filtered via a suitably configured low-pass filter). The nonlinearities introduced by ISI (i.e., falling edge, rising edge, positive glitch, and negative glitch noise or error signals) can produce intermodulation products between these high-frequency quantization noise components, which can cause the high-frequency noise to be folded back into the frequency band of interest (N_foldback), thereby reducing the SNR of the sigma-delta modulator. This phenomenon is particularly evident in the sigma-delta modulator. Fig.11 and 12Shown.

[0084] Fig.11 It is a graph that depicts the traditional representation of the frequency domain noise characteristics of the output signal of a delta-sigma modulator. The horizontal axis represents the frequency (logarithmic scale), while the vertical axis represents the signal magnitude at the corresponding frequency. Fig.11 As shown, as conventionally understood, most of the noise in the output signal (represented by arrow 402) is in the higher frequencies of the output spectrum of the output signal. Therefore, the noise represented by arrow 402 is separated (in the frequency domain) from the output signal of the modulator (represented by arrow 404), enabling the use of a low pass filter to remove high frequency noise components from the output signal of the delta-sigma modulator. This capability produces a relatively low noise floor at the frequencies of interest (see the shape of the noise floor 403).

[0085] Fig.12 is a graph that takes into account the nonlinearity introduced by ISI. Fig.11 A diagram of the frequency domain noise characteristics of the output signal of the delta-sigma modulator. Fig.12 In the graph, the horizontal axis represents frequency (logarithmic scale), while the vertical axis represents the signal size at the corresponding frequency. Fig.12 As shown, the nonlinearity causes harmonic components (arrow 410) to appear in the output signal of the modulator at frequencies near the frequency of the signal component (arrow 404). In addition, the nonlinearity causes new ISI frequency components located at the difference between each combination of frequency components (intermodulation products), which in the case of N_quant can cause the noise to fold back into the signal band of interest, thereby increasing the in-band noise floor shown as N_foldback 412, which reduces the ability to filter noise from the output signal of the modulator.

[0086] The present disclosure provides a method for correcting nonlinearities caused by ISI in a delta-sigma modulator by modifying the modulator's output bitstream, wherein the modification has a spectral content similar to the distortion originally introduced by ISI. These modified bitstreams serve as inputs to an error correction system that will modify or scale each bitstream input to correct these nonlinearities. The modified bitstream signal can not only compensate for the harmonic components of the distortion, but also compensate for the quantization noise (Q noise) folding effect in the modulator's output.

[0087] In the present disclosure, the error correction system can be implemented as a numerical optimizer or a neural network, wherein the applied error correction scheme can be learned by the error correction system. When the error correction system is implemented using machine learning, the error correction scheme can be implemented in any suitable configuration or using any suitable technology (e.g., artificial neural network, deep neural network, convolutional neural network, recursive neural network, autoencoder, reinforcement learning, etc.), fuzzy logic, artificial intelligence ("AI"), deep learning algorithm, deep structured learning hierarchical learning algorithm, support vector machine ("SVM") (e.g., linear SVM, nonlinear SVM, SVM regression, etc.), decision tree learning (e.g., classification and regression tree ("CART"), ensemble method (e.g., ensemble learning, random forest, sampling with replacement and sampling without replacement (Bagging and Pasting), patches and subspaces (Patches and Subspaces), boosting (Boosting), stacking (Stacking), etc.), dimensionality reduction (e.g., projection, manifold learning (Manifold Learning), principal component analysis, etc.) and / or deep machine learning algorithm.Non-limiting examples of publicly available machine learning algorithms, software, and libraries that may be utilized within embodiments of the present disclosure include Python, OpenCV, Inception, Theano, Torch, PyTorch, Pylearn2, Numpy, Blocks, TensorFlow, MXNet, Caffe, Lasagne, Keras, Chainer, Matlab Deep Learning, CNTK, MatConvNet (a MATLAB toolbox for implementing convolutional neural networks for computer vision applications), DeepLearnToolbox (a Matlab toolbox for deep learning (from Rasmus BergPalm)), BigDL, Cuda-Convnet (a fast C++ / CUDA implementation of convolutional (or more generally, feed-forward) neural networks), Deep Belief Networks (Deep Belief Networks), RNNLM, RNNLIB-RNNLIB, matrbm, deeplearning4j, Eblearn.lsh, deepmat, MShadow, Matplotlib, SciPy, CXXNET, Nengo-Nengo, Eblearn, cudamat, Gnumpy, 3-way factored RBM and mcRBM, mPoT, ConvNet, Elektronn, OpenNN, NeuralDesigner, Theano Generalized Hebbian Learning, Apache Singa, Lightnet, and SimpleDNN.

[0088] Various embodiments disclosed herein are described with respect to the use of artificial neural networks (also referred to herein simply as "neural networks") However, one of ordinary skill in the art will be able to implement any suitable machine learning system or other logic network or optimization system to perform error correction in a modulator in accordance with embodiments of the present disclosure.

[0089] Neural networks are typically based on a collection of connected units or nodes called artificial neurons, which loosely model neurons in biological brains. Each connection, like a synapse in a biological brain, can transmit signals to other neurons. The artificial neuron that receives the signal then processes it and can send signals to the neurons connected to it. In a neural network implementation, the "signal" at the connection is a real number, and the output of each neuron is calculated by a nonlinear function of the sum of its inputs (e.g., S-shaped activation). Connections are called edges. Neurons and edges typically have weights that are adjusted as the training of the neural network proceeds. The weight increases or decreases the signal strength at the connection. Neurons can have a threshold so that a signal is sent only when the aggregate signal exceeds the threshold. Typically, neurons are aggregated into layers. Different layers can perform different transformations on their inputs. The signal travels from the first layer (input layer) to the last layer (output layer), possibly after traversing these layers multiple times. The neural network architecture can be configured as a feedforward network with one or more hidden layers and a back-propagation learning algorithm. The implementation of a neural network can involve three stages: a training or learning stage; a verification stage; and an inference or generation stage. In the training phase, the neural network essentially learns by comparing its actual output to known correct outputs (or at least outputs that are closer to the desired output) to find errors. The model is then modified accordingly. In the validation phase, the trained neural network is tested against data (the "validation set"), which may be different from the data used in the training phase. In the inference or production phase, the trained and validated neural network is now configured and able to provide outputs corresponding to any input.

[0090] When the error correction system is implemented as a neural network, the neural network can be implemented in any type of hardware and / or software (as will be disclosed elsewhere herein), such as within a set of appropriate digital circuit systems suitable for implementing a neural network or other type of machine learning system. The neural networks shown in the figures do not limit the scope of the embodiments of the present disclosure. In each figure, "(A)" indicates that the signal is an analog signal, and "(D)" indicates that the signal is a digital signal.

[0091] Fig.13 Depicted is a system 500 including an error correction system 502 configured to correct or minimize errors generated by a delta-sigma modulator 504 due to ISI. The system 500 includes an input 506 configured to receive an analog input signal. The system 500 is configured to convert the analog input signal into an output digital bit stream at an output 508. The magnitude of the values ​​in the output digital data stream is equal to the corresponding magnitude of the analog input signal.

[0092] In system 500, sigma delta modulator 504 is configured to continuously measure or sample the magnitude of an analog input signal at input 506 and convert the analog value into a corresponding digital output bit stream that is output at output 510 of sigma delta modulator 504. If sigma delta modulator 504 is an ideal device, then the magnitude of the output digital value 'x' will be equal to the analog input signal x. a or x analog However, in practice, as described above, the output of the delta-sigma modulator 504 includes a certain ISI, so that the size of the digital output bit stream is not exactly equal to the sampled size of the analog input signal.

[0093] Thus, system 500 includes an error correction system 502 that corrects the output of a delta-sigma modulator 504 to handle ISI. In the depicted embodiment, the error correction system 502 includes an optimizer 512 that is configured to apply a number of weights (i.e., via multiplication) and a number of bias values ​​(e.g., via addition or subtraction) to values ​​received via a number of input lines 514a-514c. Within the error correction system 502, input lines 514a, 514b, and 514c (although other embodiments of the error correction system 502 may include more or fewer bit lines) are configured to receive signals from a bitstream modifier 516 that includes various modified versions of the bitstream output of the delta-sigma modulator 504. The bitstream modifier 516 is described in more detail below.

[0094] By applying appropriate weights and biases to the signals received on the various input lines 514a - 514c , the error correction system 502 generates several correction signals that are summed together at summing block 522 .

[0095] Next, the summed corrected signal output by block 522 is combined with a delayed (via delay element 525) and filtered (via filter 524) version of the original output signal of the sigma delta modulator 504 at summing node 526 to generate a corrected output signal at output 508, wherein ISI has been removed from the corrected output signal. Delay element 525 is configured to delay the signal received from the sigma delta modulator 504 by an amount equal to the delay inherent in the bitstream modifier 516 and the error correction system 502. Filter 524 may include a low pass or band pass filter configured to remove or attenuate signals having frequencies outside of a frequency band of interest or bandwidth of the sigma delta modulator 504 from the signal supplied to delay element 525.

[0096] In order to enable the error correction system 502 to compensate for the ISI inherent in the output of the delta-sigma modulator 504, the bitstream modifier 516 is configured to process the output signal of 504 to generate a plurality of different output signals, wherein the spectral components of each output signal of the bitstream modifier 516 are consistent with the spectral components of the ISI to be removed, for example, Figure 7-10 Those depicted in and described above.

[0097] To further illustrate, Fig.14 is a diagram depicting the functional components of the bitstream modifier 516. Specifically, the bitstream modifier 516 includes an input terminal 602 configured to receive an input signal including a delta-sigma modulator (e.g., Fig.13 The output signal of the delta-sigma modulator 504 is then divided into a plurality of signal paths 604a-604d received at the input terminal 602. Each signal path 604a-604d modifies the received input signal to generate an output signal at a plurality of corresponding output terminals 606a-606d.

[0098] The signal path 604a is configured to generate a filtered version of the distorted output signal of the sigma delta modulator received at the input 602. Thus, the signal path 604a includes a filter 608 (which may include a low pass or band pass filter) configured to remove or attenuate signals having frequencies outside the frequency band of interest or bandwidth of the sigma delta modulator from the signal output at the output 606a. Thus, the signal output at the output 606a is equivalent to the signal that would be fed into the decimator of the sigma delta modulator if no correction was applied.

[0099] Signal path 604b is configured to generate an output signal at output 606b that is equivalent to the difference between the input signal bit stream received at input 602 and the bit stream with a delay of 1 sample, which is equivalent to a discrete (first order) difference. Therefore, in the example where the input signal is a (distorted) sine wave, the difference bit stream output at output 606b will be approximately a cos(x) function. Specifically, signal path 604b includes a calculation circuit 610 configured to determine the difference between the current bit stream value of the input signal and the immediately preceding value of the bit stream. Then, the difference is supplied to filter 612 (which may include a low pass or band pass filter), which is configured to remove or attenuate the signal whose frequency is outside the frequency band of interest or bandwidth of the delta-sigma modulator from the signal output at output 606a. Then, the filtered difference signal is output at output 606b.

[0100] Signal path 604c is configured to determine a square version of the difference bit stream and output the square version at output 606c. Thus, the output signal generated at output 606c will be cos(x)2 form. Specifically, signal path 604c includes a logic function circuit 614 configured to determine the difference between the current bit stream value of the input signal and the immediately preceding value of the bit stream. The difference is then supplied to a square function 616, which is configured to output the squared value of the difference. The squared value is then passed to a filter 618 (which may include a low pass or band pass filter), which is configured to remove or attenuate signals with frequencies outside the frequency band of interest or bandwidth of the delta-sigma modulator from the signal output at output 606a. The filtered squared difference signal is then output at output 606c.

[0101] Signal path 604d is configured to determine a squared version of another delayed version of the difference bit stream (e.g., the bit stream output at output 606b) and output the delayed squared version at output 606d. Thus, the output signal generated at output 606d will be cos(x) 2 , but delayed by one sample. Specifically, signal path 604d includes a logic function circuit 620 configured to determine the difference between a version of the bit stream value of the input signal delayed by 1 sample and the immediately preceding value of the bit stream. Then, the difference is supplied to a square function 622, which is configured to output the squared value of the delayed difference. Then, the squared value output by the square function 622 is passed to a filter 624 (which may include a low-pass or band-pass filter), which is configured to remove or attenuate signals with frequencies outside the frequency band of interest or bandwidth of the delta-sigma modulator from the signal output at the output terminal 606a. Then, the filtered square difference signal is output at the output terminal 606d.

[0102] In this configuration, the signals output at the output terminals 606a-606d of the bitstream modifier 516 include the signals corresponding to the Figure 7-10 The same spectral components as those present in the ISI signal described above are depicted in FIG. Figure 7-10 , when the input signal has the form of a sin(x) signal, the ISI noise signal has the form of a cos(x) 2 (e.g., present in the falling edge error signal), -cos(x) 2 (e.g., present in rising edge error signals) and sin(x), cos(x) present in positive and negative glitch errors 2 As mentioned above about Fig.14 As depicted, those components are all present in the output of bitstream modifier 516 .

[0103] For the squared output signals of the bitstream modifier 516 (i.e., generated by signal paths 604c and 604d), the squaring functions 616, 622 are positioned before their respective filters 618, 624 so that all signal squaring occurs prior to filtering. Thus, in signal paths 604c and 604d, any shaped quantization noise will also produce intermodulation products when squared, thereby simulating the quantization noise folding caused by ISI, which negatively affects the output signal of the delta-sigma modulator. Thus, if the modified bitstream generated at the outputs 606a-606d of the bitstream modulator 516 is to be compared with the expected distortion caused by ISI, such as Figure 7-10 As shown in , the output signal of the bitstream modifier 516 then has a spectral content similar to the distortion components of the expected ISI.

[0104] In general, signal paths 604c and 604d are substantially the same signal, but shifted by one sample (i.e., signal path 604d is delayed by one sample relative to signal path 604c). This offset enables the ratio between the signal and the second order component to be varied while not affecting the quantization noise compensation. The following describes the values ​​of these two offset signals when used for the ISI noise component.

[0105] Fig.15 is a graph depicting the frequency spectra of the signals output by the bitstream modifier 516 at the output terminals 606c and 606d. The horizontal axis represents the frequency on a logarithmic scale, while the vertical axis represents the magnitude of the respective signals at the corresponding frequencies. Because the two bitstreams are delayed versions of each other, the spectra are identical (hence, Fig.15 If an error correction system (e.g. Fig.13 If the error correction system 502 of FIG. 51 uses only one of the square bit streams (e.g., generated by signal path 604c or signal path 604d of bit stream modifier 516) to perform ISI correction, the resulting correction will cause the ratio of the signal component to the second-order component to be locked, i.e. (constant)(in Fig.15 604c to generate the delayed signal of signal path 604d), a phase shift will occur. The phase shift that occurs depends on the frequency components that are present; when the square bit stream is shifted by one sample, the frequency component f sig will have a phase shift φ sig , and the second-order component f 2nd will have a phase shift φ 2nd If the delayed signal (eg, the signal of signal path 604d) and the non-delayed signal (eg, the signal of signal path 604c) are different, then signals with different ratios of signal to second-order components are generated. The new signal is expressed as follows:

[0106]

[0107] Equation (1) has different signal to second order ratios, but remains non-adjustable. However, if we take into account the weights generated by the error correction system (e.g., Fig.13 The weights generated by the error correction system 502 are then the delayed and non-delayed modified bit streams can be scaled separately. In this case, equation (1) becomes:

[0108]

[0109] Basically, in equation (2), the different phase shifts that occur between the signal and the second order component can be amplified or reduced using the weights of the optimizer / neural network and the delayed squared signal generated by the bitstream modifier 516.

[0110] Thus, using all of the signals generated by the bitstream modifier 516, the error correction system can determine weights and biases configured to compensate for various combinations of falling / rising edge and positive / negative going glitch errors.

[0111] Back to Fig.13 , the optimizer 512 of the error correction system 502 can be trained using a training signal that represents a known "ideal" digital signal conversion of an analog input signal. Fig.13 In the configuration shown, an "ideal" digital signal (ie, a signal representing the bit stream output of an ideal sigma-delta modulator based on the analog input signal received at input 506) may be used.

[0112] The ideal digital signal received at input 527 is supplied to a first input of summing node 528. The corrected output signal at output 508 is supplied at a negative input of summing node 528. Thus, the difference between the ideal digital signal and the corrected digital signal represents an error and is supplied to cost function 530 which is used to modify optimizer 512 such that the output generated by error correction system 502 minimizes the magnitude of the error signal (i.e., the difference between the corrected output signal at output 508 and the ideal signal received at input 527).

[0113] According to certain embodiments of the present disclosure, one or more process, voltage, temperature (PVT) sensors 520 may optionally be incorporated into the system 500 to provide PVT parameters to the error correction system 502, such that the error correction system 502 may also modify the output of the sigma-delta modulator 504 to correct for PVT dependency, where the output of the sigma-delta modulator 504 varies as a function of the PVT value. Thus, when the error correction system 502 is optimized, the error correction system 502 will account for the effects of PVT on the error generated by the sigma-delta modulator 504.

[0114] According to various embodiments of the present disclosure, any type of process, voltage, or temperature related information may be added as PVT input to the error correction system 502, such as various technology parameters (e.g., electron mobility, transistor parameters (e.g., Vt, fT, β, doping), resistor parameters (e.g., nominal resistor value, voltage dependency) or capacitor parameters (e.g., nominal capacitor value, voltage dependency), voltage parameters (e.g., supply voltage, reference voltage, bias conditions on the device), and temperature parameters (e.g., device or system operating temperature). As long as there is a way to measure the process related parameters, the output of this measurement may be provided as PVT input to the error correction system 502.

[0115] refer to Fig.13 , the PVT sensor 520 is configured to generate output signals s1, s2, and s3 at a number of output terminals 518a, 518b, 518c, respectively, which can each include PVT parameter values. In various embodiments of the system 500, the PVT sensor 520 can be configured to measure any number (e.g., one or more) of PVT parameters and supply the parameters as input to the error correction system 502. The parameter values ​​(in this case, s1, s2, and s3) are supplied to the optimizer 512 of the error correction system 502, which is configured to use the parameter values ​​as input to one or more functions (e.g., f(x), g(x), and k(x)), which are configured to determine weight / offset values ​​for various signal paths that are supplied to block 522.

[0116] In various embodiments, Fig.13 The error correction system 502 may be implemented using machine learning, such as a neural network. For example, Fig.16 Depicted is a system 800 including an error correction system 802 configured to correct or minimize errors generated by a delta-sigma modulator 804 due to ISI. The system 800 includes an input 806 configured to receive an analog input signal. The system 800 is configured to convert the analog input signal into an output digital bit stream at an output 808. The magnitude of the values ​​in the output digital data stream is equivalent to the corresponding magnitude of the analog input signal.

[0117] In system 800, sigma delta modulator 804 is configured to continuously measure or sample the magnitude of an analog input signal at input 806 and convert the analog value into a corresponding digital output bit stream that is output at output 810 of sigma delta modulator 804. If sigma delta modulator 804 is an ideal device, then the magnitude of the output digital value 'x' will be equal to the analog input signal x. a or x analog However, in practice, as described above, the output of the delta-sigma modulator 804 includes a certain ISI, so that the size of the digital output bit stream is not exactly equal to the sampled size of the analog input signal.

[0118] Thus, system 800 includes an error correction system 802 that corrects the output of a delta-sigma modulator 804 to handle ISI. In the depicted embodiment, error correction system 802 includes a neural network 812 configured to apply modifications to various signals received from a bitstream modifier 816, including various modified versions of the bitstream output of the delta-sigma modulator 804. The bitstream modifier 816 applies modifications to the bitstream output of the delta-sigma modulator 804. Fig.14 824 and the error correction system 802. The signals generated by the neural network 812 are summed together at a summing node 826, where the summed corrected signal is combined with a delayed (via a delay element 825) and filtered (via a filter 824) version of the original output signal of the delta-sigma modulator 804 at the summing node 826 to generate a corrected output signal at the output 808, where ISI has been removed from the corrected output signal. The delay element 825 is configured to delay the signal received from the delta-sigma modulator 804 by an amount that is equal to the delay inherent in the bitstream modulator 816 and the error correction system 802. The filter 824 may include a low pass or band pass filter configured to remove or attenuate signals having frequencies outside the frequency band of interest or bandwidth of the delta-sigma modulator 804 from the signal supplied to the delay element 825.

[0119] The neural network 812 of the error correction system 802 can be trained using a training signal that represents a known "ideal" digital signal conversion of an analog input signal. Fig.16 In the configuration shown, an “ideal” digital signal (ie, a signal representing the bit stream output of an ideal sigma-delta modulator based on the analog input signal received at input 806 ) is provided.

[0120] The ideal digital signal received at input 827 is supplied to a first input of summing node 828. The corrected output signal at output 808 is supplied at a negative input of summing node 828. Thus, the difference between the ideal digital signal and the corrected digital signal represents an error and is supplied to cost function 830 which is used to modify neural network 812 such that the output generated by error correction system 802 minimizes the magnitude of the error signal (i.e., the difference between the corrected output signal at output 808 and the ideal signal received at input 827).

[0121] According to certain embodiments of the present disclosure, one or more process, voltage, temperature (PVT) sensors 820 may optionally be incorporated into the system 800 to provide PVT parameters to the error correction system 802, so that the error correction system 802 may also modify the output of the sigma-delta modulator 804 to correct for the PVT dependency. Thus, when the error correction system 802 is optimized, the error correction system 802 will account for the effects of PVT on the error generated by the sigma-delta modulator 804.

[0122] According to various embodiments of the present disclosure, any type of process, voltage or temperature related information may be added as PVT input to the error correction system 802, such as various technology parameters (e.g., electron mobility, transistor parameters (e.g., Vt, fT, β, doping), resistor parameters (e.g., nominal resistor value, voltage dependency) or capacitor parameters (e.g., nominal capacitor value, voltage dependency), voltage parameters (e.g., supply voltage, reference voltage, bias conditions on the device), and temperature parameters (e.g., device or system operating temperature). As long as there is a way to measure the process related parameters, the output of this measurement may be provided to the error correction system 802 as a PVT input.

[0123] Fig.17 is a flow chart of an example method for compensating for inter-symbol interference in a delta-sigma ADC. For example, method 900 may be performed by Fig.13 System 500 or Fig.16 The system 800 of the present invention is implemented. At step 910, a digital signal is received from a delta-sigma analog-to-digital converter (ADC). At step 920, a first difference signal is generated, wherein the first difference signal includes a first difference between a first value of the digital signal and a second value of the digital signal. The second value immediately precedes the first value in the digital signal. At step 930, a correction value is determined using the first signal and the first difference signal. At step 940, the digital signal is modified by applying the correction value to generate a corrected digital signal, thereby compensating for inter-symbol interference in the digital signal.

[0124] As described herein, various embodiments of the present disclosure implement error correction systems configured to compensate for ADC errors in ADC devices, such as Nyquist and delta-sigma ADC devices. Such error correction systems may include neural networks implemented in hardware and / or software, such as implemented in one or more data processing systems. However, the functionality described herein is not limited to implementation into any particular hardware / software platform.

[0125] Those skilled in the art will appreciate that aspects of the present disclosure may be embodied as systems, processes, methods, and / or program products. Thus, aspects of the present disclosure (e.g., a machine learning system) may take the form of an all-hardware embodiment, an all-software embodiment (including firmware, resident software, microcode, etc.), or an embodiment combining software and hardware aspects, which may generally be referred to herein as a "circuit," "circuitry," "module," or "system." Additionally, aspects of the present disclosure may take the form of a program product embodied in one or more computer-readable storage media having computer-readable program code embodied thereon. (However, any combination of one or more computer-readable media may be utilized. The computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium.)

[0126] A computer-readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, biological, atomic, or semiconductor system, device, controller, or apparatus, or any suitable combination of the above, wherein the computer-readable storage medium is not a transient signal itself. More specific examples of computer-readable storage media (a non-exhaustive list) may include the following: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory ("RAM"), a read-only memory ("ROM"), an erasable programmable read-only memory ("EPROM" or flash memory), an optical fiber, a portable compact disc read-only memory ("CD-ROM"), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the context of this article, a computer-readable storage medium may be any tangible medium in which a program for use by or in conjunction with an instruction execution system, device, controller, or apparatus may be contained or stored. The program code embodied on a computer-readable signal medium may be transmitted using any appropriate medium, including but not limited to wireless, wires, fiber optic cables, RF, etc., or any suitable combination of the above.

[0127] A computer readable signal medium may include a propagated data signal in which a computer readable program code is embodied, for example, in baseband or as part of a carrier wave. Such propagated signals may take any of a variety of forms, including but not limited to electromagnetic, optical, or any suitable combination thereof. A computer readable signal medium may be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in conjunction with an instruction execution system, device, controller, or apparatus.

[0128] The block diagrams in the figures illustrate the architecture, functions and operations of possible implementation schemes of circuit systems, systems, methods, processes and program products according to various embodiments of the present disclosure. In this regard, certain blocks in the block diagram (e.g., error correction systems 502, 802 and / or neural networks 812) may represent modules, segments or portions of code, including one or more executable program instructions for implementing a specified logic function. It should also be noted that in some embodiments, the functions shown in the boxes may not appear in the order shown in the figures. For example, in fact, two boxes shown in succession may be executed substantially in parallel, or the boxes may sometimes be executed in reverse order, depending on the functions involved.

[0129] The module implemented in software for being executed by various types of processors may, for example, include one or more physical or logical blocks of computer instructions, which may, for example, be organized as objects, processes or functions. However, the executable program of the identified module does not need to be physically located together, but may include different instructions stored in different locations, which include the module and realize the purpose of the module when logically connected together. In fact, the module of executable code may be a single instruction or multiple instructions, and may even be distributed on several different code segments, between different programs and between several memory devices. Similarly, operational data (e.g., the knowledge base of adaptive weights and / or biases described herein) may be identified in the module and shown herein, and may be embodied and organized in any suitable type of data structure in any suitable form. Operational data may be collected as a single data set, or may be distributed in different locations, including on different storage devices. Data may provide electronic signals on a system or network.

[0130] These program instructions may be provided to a general purpose computer, one or more processors and / or controllers of a special purpose computer or other programmable data processing devices (e.g., a controller) to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices create a circuit system or method for implementing the functions / actions specified in one or more blocks of the block diagram.

[0131] It should also be noted that each block of the block diagram and the combination of blocks in the block diagram can be implemented by a dedicated hardware-based system (e.g., which may include one or more graphics processing units) or a combination of dedicated hardware and computer instructions that performs the specified functions or actions. For example, a module can be implemented as a hardware circuit, including a custom VLSI circuit or gate array, an off-the-shelf semiconductor (e.g., a logic chip, a transistor, a controller, or other discrete components). A module can also be implemented in a programmable hardware device, such as a field programmable gate array, a programmable array logic, a programmable logic device, a dedicated IC, a microcontroller, a system on a chip, a general-purpose processor, a microprocessor, etc.

[0132] Computer program code, i.e., instructions, for performing operations of various aspects of the present disclosure may be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, Smalltalk, Python, C++, conventional procedural programming languages ​​such as the "C" programming language or similar programming languages, or any of the machine learning software disclosed herein.

[0133] These program instructions may also be stored in a computer-readable storage medium, which may direct a computer system, other programmable data processing device, controller or other apparatus to function in a specific manner so that the instructions stored in the computer-readable medium produce an article of manufacture, which includes instructions for implementing the functions / actions specified in one or more blocks of the block diagram.

[0134] The program instructions may also be loaded onto a computer, other programmable data processing device, controller or other apparatus to cause a series of operating steps to be executed on the computer, other programmable device or other apparatus to produce a computer-implemented process, so that the instructions executed on the computer, other programmable device or other apparatus provide a process for implementing the functions / actions specified in one or more blocks of the block diagram.

[0135] The preceding detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and uses of such embodiments.

[0136] As used herein, the word "exemplary" means "serving as an example, instance, or illustration." Any implementation described herein as exemplary is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background or detailed description.

[0137] The connecting lines shown in each figure contained herein are intended to represent exemplary functional relationships and / or physical couplings between the various elements. It should be noted that many alternative or additional functional relationships or physical connections may exist in the embodiments of this theme. In addition, some terms may also be used only for reference purposes in this article, and are therefore not intended to be restrictive, and the terms "first", "second" and other such numerical terms referring to structures do not mean order or sequence, unless the context clearly indicates.

[0138] As used herein, a "node" refers to any internal or external reference point, connection point, junction, signal line, conductive element, etc. at which a given signal, logic level, voltage, data pattern, current or quantity exists. In addition, two or more nodes may be implemented by one physical element (and two or more signals may be multiplexed, modulated, or otherwise distinguished, even if received or output at a common node).

[0139] The above description refers to elements or nodes or features that are "connected" or "coupled" together. As used herein, unless otherwise expressly stated, "connection" refers to an element being directly connected (or directly communicating) with another element, and not necessarily being mechanically connected. Similarly, unless otherwise expressly stated, "coupling" refers to an element being directly or indirectly connected (or directly or indirectly communicating, electrically or otherwise) with another element, and not necessarily being mechanically connected. Therefore, although the schematic diagram shown in the figure depicts an exemplary arrangement of elements, additional intermediate elements, devices, features or components may be present in the embodiments of the depicted subject matter.

[0140] Although at least one exemplary embodiment has been presented in the foregoing detailed description, it should be understood that there are a large number of variations. It should also be understood that one or more exemplary embodiments described herein are not intended to limit the scope, applicability or configuration of the claimed subject matter in any way. On the contrary, the foregoing detailed description will provide a convenient roadmap for implementing the one or more embodiments described to those skilled in the art. It should be understood that various changes may be made to the functions and arrangements of the elements without departing from the scope defined by the claims, and the claims include equivalents and foreseeable equivalents known at the time of filing this patent application.

Claims

1. A system, characterized in that: include: a sigma-delta analog-to-digital converter ADC configured to convert an analog input signal into a digital signal, wherein the digital signal is a digital approximation of the analog input signal; A bitstream modifier configured to: receiving the digital signal from the sigma-delta ADC, outputting a first signal at a first output terminal, wherein the first signal is based on the digital signal, and outputting a first difference signal at a second output terminal, wherein the first difference signal comprises a first difference between a first value of the digital signal and a second value of the digital signal, wherein the second value immediately precedes the first value in the digital signal; and An error correction system configured to: receiving the first signal from the first output of the bitstream modifier, receiving the first difference signal from the second output terminal of the bit stream modifier, determining a correction value using the first signal and the first difference signal, and The digital signal is modified by applying the correction value to generate a corrected digital signal.

2. The system according to claim 1, characterized in that The bitstream modifier is configured to: determining a second difference between the first value of the digital signal and the second value of the digital signal, determining a first squared difference of the second difference, and The first squared difference value is output at a third output terminal of the bitstream modifier.

3. The system according to claim 2, characterized in that The error correction system is configured to receive the first squared difference value from the third output of the bitstream modifier and to determine the correction value using the first squared difference signal.

4. The system according to claim 3, characterized in that The bitstream modifier is configured to: determining a third difference between the second value of the digital signal and a third value of the digital signal, wherein the third value immediately precedes the second value in the digital signal, determining a second squared difference of the third difference, and The second square difference value of the third difference value is outputted at a fourth output terminal as a second square difference signal.

5. A system, characterized in that: include: a sigma-delta analog-to-digital converter ADC configured to convert an analog input signal into a digital signal, wherein the digital signal is a digital approximation of the analog input signal; A bitstream modifier comprising: an input terminal configured to receive the digital signal from the sigma-delta ADC, a first signal path connected between the input terminal of the bit stream modifier and a first output terminal of the bit stream modifier to output a first signal at the first output terminal, a first filter between the input of the bit stream modifier and the first output of the bit stream modifier, a second signal path connected between the input of the bitstream modifier and a second output of the bitstream modifier, wherein the second signal path comprises a first circuit configured to determine a first difference between a first value of the digital signal and a second value of the digital signal, wherein the second value immediately precedes the first value in the digital signal, and output the first difference as a first difference signal at the second output, and a second filter between the first circuit of the second signal path and the second output of the bit stream modifier; and An error correction system comprising: a first input terminal connected to said first output terminal of said bit stream modifier, a second input terminal connected to said second output terminal of said bit stream modifier, and A neural network configured as: determining a correction value using the first signal from the first output terminal and the first difference signal from the second output terminal, and Intersymbol interference in the digital signal is compensated by applying the correction value to modify the digital signal to generate a corrected digital signal.

6. The system according to claim 5, characterized in that The bitstream modifier comprises a third signal path connected between the input terminal of the bitstream modifier and a third output terminal of the bitstream modifier, wherein the third signal path comprises: a second circuit configured to determine a second difference between the first value of the digital signal and the second value of the digital signal, a third circuit configured to determine a first squared value of the second difference value, wherein the bitstream modifier is configured to output the first squared value of the second difference value as a first squared difference signal at the third output terminal, and A third filter is connected between the third circuit and the third output of the bit stream modifier, the third filter being configured to attenuate signals having frequencies outside a third bandwidth.

7. The system according to claim 6, characterized in that The bitstream modifier comprises a fourth signal path connected between the input terminal of the bitstream modifier and a fourth output terminal of the bitstream modifier, wherein the fourth signal path comprises: a fourth circuit configured to determine a third difference between the second value of the digital signal and a third value of the digital signal, wherein the third value immediately precedes the second value in the digital signal, a fifth circuit configured to determine a second squared value of the third difference value, wherein the bitstream modifier is configured to output the second squared value of the third difference value as a second squared difference signal at the fourth output terminal, and A fourth filter is connected between the fifth circuit and the fourth output of the bit stream modifier, the fourth filter being configured to attenuate signals having frequencies outside a fourth bandwidth.

8. A method, characterized in that include: receiving a digital signal from a delta-sigma analog-to-digital converter ADC; generating a first difference signal comprising a first difference between a first value of the digital signal and a second value of the digital signal, wherein the second value immediately precedes the first value in the digital signal; determining a correction value using the first signal and the first difference signal; as well as Intersymbol interference in the digital signal is compensated by applying the correction value to modify the digital signal to generate a corrected digital signal.

9. The method according to claim 8, characterized in that Also includes: determining a second difference between the first value of the digital signal and the second value of the digital signal; determining a first squared difference of the second difference; as well as The correction value is determined using the first squared difference signal.

10. The method according to claim 8, characterized in that Also includes: determining a third difference between the second value of the digital signal and a third value of the digital signal, wherein the third value immediately precedes the second value in the digital signal; determining a second square value of the third difference; and The correction value is determined using the second squared difference signal.

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