LDPC decoder, decoding method and electronic equipment

Abstract

The invention provides an LDPC (Low Density Parity Check) decoder, a decoding method and electronic equipment, and the method comprises the steps: obtaining a channel message and an index value of a code word, and carrying out the cyclic shift of the channel message based on the index value; generating first feedback information, wherein the first feedback information is feedback information from the variable node to the check node; according to the first feedback information, second feedback information is generated, and the second feedback information is feedback information which is from the check node to the variable node and is compressed; third feedback information is generated, the third feedback information is the updated channel message, and a decoding result is generated according to the third feedback information; and performing parity check on the decoding result to output a parity check result, and if the parity check result is low level, outputting the decoding result. According to the method, the change of multiple code rates and code lengths can be adapted by using different decoding configurations, the decoding process is simplified, different applications can be compatible, and the problem of low flexibility of an LDPC (Low Density Parity Check) decoder is solved.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to an LDPC decoder, a decoding method and an electronic device. Background Art

[0002] 5G NR (New Radio) is one of the standards for mobile communication networks. Wi-Fi can provide high-density wireless connection support within the local area network. Both 5G NR and Wi-Fi are designed to provide electronic devices with higher data transmission rates. In addition, 5G NR requires channel coding and error correction technologies to complete data transmission and error correction in a short time to support ultra-reliable low-latency communication (URLLC) scenarios, high-speed data transmission (eMBB) and massive machine type communication (mMTC).

[0003] Channel coding is used to protect the integrity of data in the presence of noise and interference. In 5G NR, two main channel coding schemes are used. Among them, LDPC (Low-Density Parity-Check) achieves efficient error correction capability through a sparse check matrix and obtains performance close to the Shannon limit at a low signal-to-noise ratio (SNR). The LDPC decoder is optimized for a single communication standard and can achieve higher performance in a single application scenario.

[0004] However, LDPC decoders only support specific data block sizes and code rates. When the scenario changes, that is, the code length, code rate, etc. change, they cannot be used in the new scenario. In addition, some LDPC decoders can support some code rates of 5G NR, but are not compatible with LDPC decoding in WIFI mode and support decoding of multi-rate LDPC codes. Therefore, LDPC decoders cannot adapt to application scenarios such as 5G NR and Wi-Fi, resulting in low flexibility of LDPC decoders. Summary of the invention

[0005] The present application provides an LDPC decoder, a decoding method and an electronic device to solve the problem of low flexibility of the LDPC decoder.

[0006] In a first aspect, the present application provides an LDPC decoder, comprising:

[0007] A first storage unit, used for receiving and buffering input channel messages;

[0008] A first shift unit, configured to receive an index value and cyclically shift the channel message based on the index value;

[0009] A processing unit, the processing unit comprising a variable node processing module and a check node processing module, the variable node processing module is used to generate first feedback information according to the output of the first shift unit, the first feedback information is feedback information from the variable node to the check node;

[0010] The check node processing module is used to generate second feedback information according to the first feedback information, where the second feedback information is feedback information from the check node to the variable node and is compressed feedback information;

[0011] A channel message updating module, configured to generate third feedback information, wherein the third feedback information is an updated channel message;

[0012] A parity check unit is used to generate a decoding result according to the third feedback information, and perform a parity check on the decoding result to output the parity check result, and output the decoding result if the parity check result is a low level.

[0013] In some feasible embodiments, it also includes:

[0014] a multiplexer, connected to the variable node processing module, and configured to receive the first feedback information;

[0015] If the multiplexer receives the first feedback information, output the first feedback information to the first storage unit;

[0016] If the multiplexer does not receive the first feedback information, the channel message is output to the first storage unit.

[0017] In some feasible embodiments, it also includes:

[0018] A second storage unit, configured to store the second feedback information;

[0019] A first decompression unit, configured to decompress the second feedback information and input the decompressed second feedback information to the variable node processing module;

[0020] The variable node processing module is further configured to output variable node information according to the decompressed second feedback information, wherein the variable node information has a different bit width from the first feedback information.

[0021] In some feasible embodiments, it also includes:

[0022] a second decompression unit, configured to decompress the second feedback information, and input the decompressed second feedback information into the channel message update module, so as to generate a decoding result through the channel message update module;

[0023] The second shift unit is configured to shift the updated channel message and transmit the shifted channel message to the multiplexer.

[0024] In some feasible embodiments, the check node processing module is further used to obtain a first value, a second value, and a first value index according to the first feedback information, the first value is the smallest first feedback information in the variable node, the second value is the smallest first feedback information except the first value, the bit width of the first value index is the maximum row weight bit width, and the row weight is the number of valid elements of a row in the check matrix;

[0025] and determining a sign bit according to the first feedback information, wherein the bit width of the sign bit is a maximum row weight value;

[0026] The check node processing module is further configured to perform an XOR operation on the first feedback information and the sign bit to output second feedback information.

[0027] In a second aspect, the present application provides a decoding method, comprising:

[0028] Acquire a channel message and an index value of a variable node, and cyclically shift the channel message based on the index value;

[0029] Generate first feedback information, where the first feedback information is feedback information from the variable node to the check node;

[0030] Generate second feedback information according to the first feedback information, where the second feedback information is compressed feedback information from the check node to the variable node;

[0031] generating third feedback information, where the third feedback information is an updated channel message;

[0032] Generate a decoding result according to the third feedback information;

[0033] Performing a parity check on the decoding result to output a parity check result;

[0034] If the parity check result is a low level, the decoding result is output.

[0035] In some feasible embodiments, before obtaining the channel message and index value of the variable node, the method includes:

[0036] Get the reset signal;

[0037] In response to the reset signal being pulled low, performing a reset operation, and after the reset is completed, pulling the reset signal high to generate configuration information, the configuration information including a boost factor and a control word;

[0038] After the decoding information is generated based on the configuration information, the reset signal is pulled low and the first storage unit is cleared.

[0039] In some feasible embodiments, the obtaining of the channel message and index value of the variable node includes:

[0040] When the first storage unit receives and buffers the input channel message, it pulls up the input information valid signal and transmits the channel message to the first shift unit.

[0041] In some feasible embodiments, the method further includes:

[0042] When the channel message update module generates a decoding result, the enable signal is pulled high;

[0043] When the parity check result output by the parity check unit is at a low level, the output information valid signal is pulled high.

[0044] In a third aspect, the present application provides an electronic device, including:

[0045] Memory, used to store programs;

[0046] A processor is used to execute the program, wherein the program is specifically used to implement the decoding method described in any one of the second aspects.

[0047] It can be seen from the above technical solutions that the present application provides an LDPC decoder, a decoding method and an electronic device, wherein the method obtains the channel message and index value of the variable node, and cyclically shifts the channel message based on the index value; regenerates the first feedback information, the first feedback information is the feedback information from the variable node to the check node; generates the second feedback information according to the first feedback information, the second feedback information is the feedback information from the check node to the variable node and compressed; generates the third feedback information, the third feedback information is the updated channel message, and generates the decoding result according to the third feedback information; performs a parity check on the decoding result to output the parity check result, and outputs the decoding result if the parity check result is a low level. The method can adapt to the changes of multiple code rates and code lengths by obtaining the channel message and index value of the variable node, simplifies the decoding process, and is compatible with different applications to solve the problem of low flexibility of the LDPC decoder. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the technical solution of the present application, the drawings required for use in the embodiments are briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0049] Figure 1A schematic diagram of the structure of an LDPC decoder provided in an embodiment of the present application;

[0050] Figure 2 A schematic diagram of the hardware output of the LDPC decoder provided in an embodiment of the present application;

[0051] Figure 3 A schematic diagram of a WIFI check matrix provided in an embodiment of the present application;

[0052] Figure 4 A schematic diagram of a first compressed c2v message provided in an embodiment of the present application;

[0053] Figure 5 A schematic diagram of a second compressed c2v message provided in an embodiment of the present application;

[0054] Figure 6 A schematic diagram of a process for outputting decoding results provided in an embodiment of the present application;

[0055] Figure 7 A schematic diagram of index flow provided in an embodiment of the present application;

[0056] Figure 8 A flowchart of a decoding method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0057] The following embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following embodiments do not represent all implementations consistent with the present application. They are only examples of systems and methods consistent with some aspects of the present application as detailed in the claims.

[0058] An LDPC decoder is a device or algorithm used to decode LDPC codes, and is used to recover the original transmitted data from the received noisy signal as accurately as possible. In a single application scenario, the LDPC decoder is specifically optimized for a specific data block size (Lift Size, Zc) and code rate, so it can achieve higher performance. These decoders use a fixed hardware architecture and algorithm and are debugged to maximize performance advantages. However, they can only operate under specific conditions. Once the scenario changes, for example, the code length, code rate, etc. change, the original decoder cannot adapt to the new requirements.

[0059] Because the hardware architecture and algorithms of LDPC decoders are customized for specific application scenarios, they cannot flexibly adjust themselves to adapt to new code rates and data block sizes. For example, if a decoder is designed to process data blocks of a specific length, then when the data block length changes, the performance of the decoder may degrade or even fail to work properly. Similarly, if a decoder is designed for a specific code rate, then when the code rate changes, the decoder will not be able to effectively process new data.

[0060] In addition, since different communication standards have different requirements, for example, 5G NR and Wi-Fi are different in data block size, code rate, etc., a separate decoder must be designed for each standard. This not only increases costs, but also makes the manufacturing process more complicated.

[0061] Some LDPC decoders can support some code rates of 5G NR, but due to the large differences between 5G NR and Wi-Fi in terms of data block size, code rate, etc., these decoders often find it difficult to take both into account. To support multi-rate LDPC code decoding, decoders need to have higher flexibility and configurability, which requires more complex hardware and software design. Therefore, although some decoders can support some code rates of 5G NR, they may not be fully compatible with LDPC decoding in Wi-Fi mode, nor can they support all possible code rate combinations. In summary, the reason why LDPC decoders perform well in a single application scenario is that they are optimized for specific conditions, but this also leads to their low flexibility.

[0062] To solve the problem of low flexibility of LDPC, see Figure 1 , Figure 2 Some embodiments of the present application provide an LDPC decoder, including: a first storage unit, a first shift unit, a processing unit, a channel message update module, and a parity check unit. The decoder can simultaneously support different code lengths and code rates in 5G NR and WIFI scenarios.

[0063] The first storage unit may be one or more memory areas, such as RAM, ROM or other types of storage media, for receiving and buffering input channel messages (ch_llr). In the LDPC decoding process, the channel message is represented in the form of a log likelihood ratio (LLR), which is the logarithmic ratio of the probability that the channel message receiving bit is 0 or 1. The LLR value is input into the first storage unit as the channel message for subsequent iterative decoding processes.

[0064] The first shift unit is a barrel shifter, which is used to receive the index value and cyclically shift the channel message based on the index value. At the input of the LDPC decoder, these code blocks are processed as input data. The code blocks (i.e., the received coded data blocks) are first converted into channel messages (LLR values), which are stored in the first storage unit as the starting point of the decoding process and then shifted by the barrel shifter. The code blocks are LDPC-encoded data blocks received from the channel. These data blocks are encoded before transmission to increase redundancy so that errors can be detected and corrected at the receiving end.

[0065] Shifting the channel message through the barrel shifter can make the decoding process more efficient and flexible, allowing the decoder to properly rearrange and preprocess the received data according to the structure and characteristics of the LDPC code, thereby improving the decoding performance.

[0066] The processing unit includes a variable node processing module and a check node processing module.

[0067] The variable node processing module is used to generate first feedback information (v2c) according to the output of the first shift unit, and the first feedback information is feedback information from the variable node to the check node. The variable node represents the coding bit or information bit. During the decoding process, each variable node collects information from its adjacent check node and updates its own state based on this information. The variable node processing module implements the update algorithm of the variable node, and the update algorithm is, for example, a variant of the sum-product algorithm (SPA) or the minimum sum algorithm (MSA).

[0068] The update formula of the first feedback information v2c is as follows:

[0069] v2c=app-c2v old ;

[0070] In the first iteration, app (A Posteriori Probability) is initialized to ch_llr (channel llr), c2v old Initialized to 0. Output v2c message (9 bits) and variable node (variablenode) message (10 bits), wherein the v2c message is transmitted to the check node processing module, and the variable node message is transmitted to the first storage unit for storage.

[0071] The check node processing module is used to generate second feedback information (c2v) according to the first feedback information, where the second feedback information is feedback information from the check node to the variable node and compressed feedback information. For example, the check node processing module processes calculations related to the check node, receives messages from the variable node, and generates new messages based on these messages and sends them to the variable node.

[0072] In some embodiments, the check node processing module obtains the first value min1, the second value min2 and the first value index min1_idx according to the first feedback information, the first value is the smallest first feedback information in the variable node, and the second value is the smallest first feedback information except the first value; and determines the sign bit sign_reg according to the input first feedback information, and the bit width of the sign bit is the maximum row weight value; the check node processing module is also used to perform an XOR operation on the first feedback information and the sign bit to output the second feedback information.

[0073] The bit width of the first value index is the maximum row weight bit width, which is 5 bits. The first value index is the valid codeword index of each layer, ranging from 0–row_degree–1. sign_reg is the sign bit of the valid codeword of each layer, and its bit width is row_degree. Considering compatibility, the maximum row_degree is Z=27 and R=5 / 6 in the WIFI protocol tableF-1, and its value is 22. Figure 3 As shown, therefore, the bit width of min1_idx is 5 bits, and the bit width of sign_reg is 22 bits, that is, the maximum row weight value is 22 bits.

[0074] The update of the second feedback information is based on a simplified form of the Min-Sum algorithm. The Min-Sum algorithm is an LDPC decoding algorithm that performs decoding by comparing and selecting the minimum value. The Min-Sum algorithm can improve the friendliness of the decoding hardware and reduce the computational complexity. The update formula of the second feedback information is as follows:

[0075]

[0076] Among them, V c is the set of all variable nodes connected to the current check node c, V is the specific variable node currently being considered, and V c \v is from the set V c The set obtained by removing the element V from the , that is, the set of all variable nodes connected to the current check node c except V, v2c v′ is the message from variable node v′ to check node c (i.e. v2c).

[0077] That is to say, the check node updates its own state according to the message received from the variable node, and sends the updated state back to the corresponding variable node. This is an iterative process. In each iteration, the check node recalculates its own state according to the latest message received until it reaches a stable state or reaches the maximum number of iterations. In this embodiment, the maximum number of iterations is 63.

[0078] See also Figure 4 , Figure 5 After secondary compression, Xor is XORed with each bit in sign_reg, and the c2v message (43 bits) is output while meeting compatibility.

[0079] Since the c2v message has been compressed in the check node processing module, in order to store and decompress the c2v message, in some embodiments, the decoder further includes a second storage unit and a first decompression unit. The second storage unit stores the second feedback information, wherein the second storage unit, like the first storage unit, can be one or more memory areas; the first decompression unit is used to decompress the second feedback information and input the decompressed second feedback information to the variable node processing module. The first decompression unit may include a dedicated hardware logic, such as a logic block or a software algorithm in an FPGA, for executing a decompression algorithm. The first decompression unit restores the compressed c2v message to a c2v message with a bit width of 9 bits.

[0080] The variable node processing module is further used to output the variable node information according to the decompressed second feedback information, and then perform the update operation of the variable node according to the variable node information, for example, calculating a new LLR value, updating the state of the node, etc. The bit width of the variable node information is different from that of the first feedback information, the bit width of the first feedback information is 9 bits, and the bit width of the variable node message is 10 bits.

[0081] Exemplarily, during the decoding process, the check node processing module generates and compresses the second feedback information and stores it in the second storage unit. When the variable node needs to be updated, the first decompression unit reads the compressed second feedback information from the second storage unit and decompresses it. The decompressed second feedback information is input to the variable node processing module, which performs an update operation based on this information and other possible inputs, such as the first feedback information. The variable node processing module outputs the updated variable node information, and the variable node information is used for subsequent decoding iterations or final decoding decisions.

[0082] Through the second storage unit and the first decompression unit, the decoder can process the compressed feedback information, reducing the storage and transmission costs. At the same time, the variable node processing module can process information of different widths, which can enhance the adaptability of the decoder.

[0083] The channel message updating module is used to generate the third feedback information, which is the updated channel message. The third feedback information is the result of the accumulation of the first feedback information and the second feedback information. The third feedback information is generated by referring to the following formula:

[0084] app new =v2c+c2v new ;

[0085] Among them, v2c is the first feedback information, c2v new It is the second feedback information.

[0086] join Figure 6 The parity check unit is used to generate a decoding result according to the third feedback information, and perform a parity check on the decoding result (S301) to output the parity check result. The parity check unit may include a check logic for verifying the correctness of the decoding result. If the parity check result is a low level, the decoding result is output (S302) and the iteration is stopped. If the parity check result is a high level, the decoding is continued (S302). If the decoding reaches the maximum number of iterations and still does not meet the check condition, the decoding is stopped and the current decoding result is output.

[0087] In some embodiments, it also includes: a multiplexer, the multiplexer is connected to the variable node processing module, and is used to receive first feedback information; if the multiplexer receives the first feedback information, the first feedback information is output to the first storage unit; if the multiplexer does not receive the first feedback information, the channel message is output to the first storage unit.

[0088] A multiplexer is a digital circuit that allows one signal to be selected from multiple input signals and transmitted to a single output line. It is controlled by a select signal, which determines which input signal is selected. The multiplexer contains multiple input ports, one or more select ports, and an output port. In this embodiment, multiple input signals from different sources (e.g., variable node processing modules or other inputs) are received and one of the outputs is selected based on a control signal.

[0089] Exemplarily, if the variable node processing module generates first feedback information according to the shifted channel message, the multiplexer receives the first feedback information, and the multiplexer receives the first feedback information and outputs the first feedback information to the first storage unit. If the multiplexer does not receive the first feedback information, the channel message is output to the first storage unit.

[0090] In some embodiments, the decoder further includes a second decompression unit and a second shift unit, the second decompression unit being used to decompress the second feedback information and input the decompressed second feedback information into a channel message update module so as to generate third feedback information through the channel message update module, wherein the third feedback information is an updated channel message; the second shift unit being used to shift the updated channel message and transmit the shifted channel message to the multiplexer.

[0091] Among them, similar to the first decompression unit, the second decompression unit may include special hardware logic, for example, a logic block or a software algorithm in an FPGA, for executing a decompression algorithm. The second decompression unit is a unit for processing compressed data, receiving the compressed second feedback information, and restoring it to its original format through a decompression algorithm. That is, after the check node processing module generates the compressed second feedback information, it is sent to the second storage unit and the second decompression unit respectively.

[0092] After the channel message update module generates the third feedback information, it is sent to the second shift unit. The second shift unit is similar to the first shift unit and can be a barrel shifter. The second shift unit shifts the decoding result, and the shifted third feedback information is transmitted to the multiplexer. It can be understood that the multiplexer can also output the third feedback information as required and input it to the first storage unit.

[0093] See also Figure 7 , the first shift unit obtains the index value, the index value idx is an integer used to indicate the position of the code block in the entire code frame. For example, if idx = 0, it means that the codeword is the first code block of the entire code frame. It should be noted that idx starts counting from 0, idx>0. This index value is provided by a controller outside the decoder to control the behavior of the decoder.

[0094] In some embodiments, the control information required for decoding may also be generated by a decoding state machine.

[0095] The LDPC decoder proposes a highly flexible hardware architecture with high flexibility, which can adapt to different usage scenarios without redesigning the hardware. When in use, you only need to configure the scene control word, lift_size and the maximum number of iterations to switch to different scenarios. At the same time, under the existing framework, you only need to redesign the configuration information memory and the mapping relationship between the control word and the memory within the hardware to support new usage scenarios without redesigning other parts of the decoder.

[0096] See also Figure 8 , the present application provides a decoding method, comprising:

[0097] S100: Acquire a channel message and an index value of a variable node, and cyclically shift the channel message based on the index value.

[0098] In some embodiments, before obtaining a channel message, a reset (rst_n) signal is first obtained; then, in response to the reset signal being pulled low, a reset operation is performed, and after the reset is completed, the reset signal is pulled high to generate configuration information, the configuration information includes a lifting factor (lift_size) and a control word (mode), wherein lift_size determines the size and structure of the check matrix, and mode includes other configuration information, such as the selection of check matrix information, etc.; after generating decoding information based on the configuration information, the reset signal is pulled low and the first storage unit is cleared.

[0099] Among them, the control word is a 6-bit binary number, which is used to specify the scenario and basic check matrix (BaseGraph, BG) configuration used. The upper two bits (the highest bit and the second highest bit) are used to define the selected scenario, and the lower four bits (the remaining four bits) are used to define which specific background configuration. The upper two bits: 00 represents 5G NR BaseGraph 1 (5G new radio check matrix 1); 01 represents 5G NR BaseGraph 2; 10 represents WiFi check matrix. The lower four bits: The bits are used to further distinguish the specific background configuration in each scenario. For example, in the 5G NR scenario, there can be multiple different check matrix configurations, such as base 2, base 3, etc. Similarly, there can be different configurations in the WiFi scenario.

[0100] This mode control word allows the decoder to select the appropriate configuration according to different application scenarios and requirements. For example, when the Mode value is 000000, it means that the first configuration in 5G NR BaseGraph 1 is selected; when the Mode value is 000001, it means that the second configuration in 5G NR BaseGraph 1 is selected. Mode provides sufficient flexibility so that the decoder can switch to different working modes and configurations as needed to adapt to different wireless environments and technical requirements.

[0101] Exemplarily, before obtaining the channel message, a control word containing scene information, a boost factor and other configuration information are sent to the decoder. The decoder configures the decoding information accordingly and initializes the first storage unit or resets the internal state of the decoder to prepare for a new iterative decoding process.

[0102] When the decoding is initialized, 5 initial addresses are obtained, COL_IDX_MEMORY (column index memory), SHIFTER_NUBER_MEMORY (shift factor memory), ROW_DEGREE_MEMORY (row weight memory), H_SHIFTER_MEMORY (check matrix shift factor memory), H_MATRIX_MEMORY (check matrix valid element memory). During the decoding process, the information required for decoding is read in sequence starting from the initial address, and the initial address is returned after one iteration.

[0103] The column index memory (COL_IDX_MEMORY) is used to store the index information of each column in the check matrix (H matrix). These indexes are used to indicate which variable nodes are connected to a specific check node. During the decoding process, based on these index information, the decoder can determine which variable nodes need to participate in the calculation of the current check node.

[0104] The shift factor memory (SHIFTER_NUMBER_MEMORY) is used to store the shift factors associated with each check node. These shift factors are used to indicate how many bits need to be cyclically shifted when passing a message. During the iterative decoding process, based on these numbers, the decoder can correctly cyclically shift the message to adapt to the structure of the check matrix.

[0105] The row weight memory (ROW_DEGREE_MEMORY) is used to store the number of valid blocks for each row in the check matrix. The number of valid blocks indicates how many variable nodes are connected to the row. During the decoding process, based on this row weight information, the decoder can know how many messages each check node needs to process.

[0106] The check matrix shift factor memory (H_SHIFTER_MEMORY) is used to store the shifter information related to the check matrix. This information usually includes the number of shifts required for each row or column. During the iterative decoding process, based on this shift information, the decoder can correctly adjust the cyclic shift in the message passing.

[0107] The check matrix valid element memory (H_MATRIX_MEMORY) is used to store the complete valid elements of the check matrix (H matrix). The check matrix defines the connection relationship between the variable nodes and the check nodes. During the decoding process, according to the check matrix, the decoder can determine which variable nodes are connected to which check nodes, so as to perform correct message transmission and update.

[0108] Decoding configuration Memory (ROM), when decoding is initialized, five initial addresses are obtained from ROM, these addresses point to the starting positions of the above five memories. During the decoding process, the required information is read in sequence from these initial addresses. After one iteration is completed, it returns to the initial address and starts the next iteration again.

[0109] Then obtain the channel message. Before the first storage unit receives and caches the input channel message, pull up the configuration enable (initial_en) signal. initial_en is a control signal used to indicate whether the configuration information is valid. After the configuration information is input, pull down the initial_en signal. After the configuration information is input, the decoder is ready to receive the data to be decoded.

[0110] Input the data to be decoded, pull the input_valid signal high, input_valid is a control signal used to indicate whether the data to be decoded is valid, characterizes the data to be input to be decoded, input ch_llr, ch_llr is the maximum likelihood probability of the channel to be decoded, input a code block in each cycle, and each code block contains 384 maximum likelihood probabilities. When lift_size is less than 384, the high bits are filled with 0, that is, if lift_size is less than 384, the lifting factor is not enough to cover 384 bits, and the high bits are filled with 0 to meet the requirements of the check matrix.

[0111] S200: Generate first feedback information.

[0112] The first feedback information is feedback information from the variable node to the check node. It can be understood that the process of generating the first feedback information can refer to the process of generating the first feedback information by the variable node processing module in the LDPC decoder in the above embodiment, which will not be described in detail here.

[0113] S300: Generate second feedback information according to the first feedback information.

[0114] The second feedback information is compressed feedback information from the check node to the variable node. It can be understood that the process of generating the second feedback information can refer to the process of generating the second feedback information by the check node processing module in the LDPC decoder in the above embodiment, which will not be described in detail here.

[0115] S400: Generate third feedback information.

[0116] The third feedback information is the result of accumulating the first feedback information and the second feedback information. It can be understood that the process of generating the third feedback information can refer to the process of generating the third feedback information by the channel message update module in the LDPC decoder in the above embodiment, which will not be described in detail here.

[0117] S500: Generate a decoding result according to the third feedback information, and perform a parity check on the decoding result to output a parity check result.

[0118] S600: If the parity check result is a low level, output the decoding result.

[0119] Output the parity check result (parity_code_check). If parity_code_check is at a low level, it means that the decoding meets the check condition and the iteration is stopped. Otherwise, the decoding continues.

[0120] In some embodiments, an enable signal (output_en) is externally pulled high; when the output_en signal is pulled high and decoding is completed, the output_valid signal is pulled high, and the output_valid signal indicates whether the output data is valid. At the same time, the decoded data is output, and 128 bits are output per cycle, that is, a part of the decoding result is output each time.

[0121] It can be understood that, for the decoding process, reference may be made to the process of the LDPC decoder in the above embodiment, which will not be described in detail here.

[0122] The present application also provides an electronic device, comprising:

[0123] Memory, used to store programs;

[0124] The processor is used to execute the program, and the program is specifically used to implement the decoding method.

[0125] The electronic device may be a server or terminal device that other electronic devices can log in and access. The electronic device may include at least one memory and at least one processor. The processor may execute multiple computer instructions stored in the memory to implement the steps of the information processing method proposed in the above-mentioned embodiment of the present application. The implementation process can refer to the description of the corresponding method embodiment above, and this embodiment will not be described in detail here.

[0126] In the embodiment of the present application, the memory may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device or other volatile solid-state storage device. The processor may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, etc. The present application does not limit the structure and model of the above-mentioned memory and processor, and can be flexibly adjusted according to actual needs.

[0127] It can be seen from the above technical solutions that the present application provides an LDPC decoder, a decoding method and an electronic device, wherein the method obtains a channel message and an index value of a variable node, and cyclically shifts the channel message based on the index value; regenerates the first feedback information, the first feedback information is the feedback information from the variable node to the check node; generates the second feedback information according to the first feedback information, the second feedback information is the feedback information from the check node to the variable node and compressed; generates the third feedback information, the third feedback information is the result of the accumulation of the first feedback information and the second feedback information; performs a parity check on the decoding result to output the parity check result, and outputs the decoding result if the parity check result is a low level. The method can adapt to changes in multiple code rates and code lengths by using different decoding configurations, simplifies the decoding process, and is compatible with different applications to solve the problem of low flexibility of the LDPC decoder.

[0128] Similar parts between the embodiments provided in this application can be referenced to each other. The specific implementation methods provided above are only a few examples under the general concept of this application and do not constitute a limitation on the protection scope of this application. For those skilled in the art, any other implementation methods expanded based on the scheme of this application without creative work belong to the protection scope of this application.

Claims

1. An LDPC decoder, characterized in that: include: A first storage unit, used for receiving and buffering input channel messages; A first shift unit, configured to receive an index value and cyclically shift the channel message based on the index value; A processing unit, the processing unit comprising a variable node processing module and a check node processing module, the variable node processing module is used to generate first feedback information according to the output of the first shift unit, the first feedback information is feedback information from the variable node to the check node; The check node processing module is used to generate second feedback information according to the first feedback information, where the second feedback information is feedback information from the check node to the variable node and is compressed feedback information; A channel message updating module, configured to generate third feedback information, wherein the third feedback information is an updated channel message; A parity check unit is used to generate a decoding result according to the third feedback information, and perform a parity check on the decoding result to output the parity check result, and output the decoding result if the parity check result is a low level.

2. The LDPC decoder according to claim 1, characterized in that: Also includes: a multiplexer, connected to the variable node processing module, and configured to receive the first feedback information; If the multiplexer receives the first feedback information, output the first feedback information to the first storage unit; If the multiplexer does not receive the first feedback information, the channel message is output to the first storage unit.

3. The LDPC decoder according to claim 2, characterized in that: Also includes: A second storage unit, configured to store the second feedback information; A first decompression unit, configured to decompress the second feedback information and input the decompressed second feedback information to the variable node processing module; The variable node processing module is further configured to output variable node information according to the decompressed second feedback information, wherein the variable node information has a different bit width from the first feedback information.

4. The LDPC decoder according to claim 3, characterized in that: Also includes: a second decompression unit, configured to decompress the second feedback information, and input the decompressed second feedback information into the channel message update module, so as to generate a decoding result through the channel message update module; The second shift unit is configured to shift the updated channel message and transmit the shifted channel message to the multiplexer.

5. The LDPC decoder according to claim 1, characterized in that: The check node processing module is further used to obtain a first value, a second value and a first value index according to the first feedback information, the first value is the smallest first feedback information in the variable node, the second value is the smallest first feedback information except the first value, and the bit width of the first value index is the maximum row weight bit width, and the row weight is the number of valid elements of a row in the check matrix; and determining a sign bit according to the first feedback information, wherein the bit width of the sign bit is a maximum row weight value; The check node processing module is further configured to perform an XOR operation on the first feedback information and the sign bit to output second feedback information.

6. A decoding method, characterized in that: The LDPC decoder applied to any one of claims 1 to 5, comprising: Acquire a channel message and an index value of a variable node, and cyclically shift the channel message based on the index value; Generate first feedback information, where the first feedback information is feedback information from the variable node to the check node; Generate second feedback information according to the first feedback information, where the second feedback information is compressed feedback information from the check node to the variable node; generating third feedback information, where the third feedback information is an updated channel message; Generate a decoding result according to the third feedback information; Performing a parity check on the decoding result to output a parity check result; If the parity check result is a low level, the decoding result is output.

7. The decoding method according to claim 6, characterized in that: Before obtaining the channel message and index value of the variable node, the method includes: Get reset signal; In response to the reset signal being pulled low, performing a reset operation, and after the reset is completed, pulling the reset signal high to generate configuration information, the configuration information including a boost factor and a control word; After the decoding information is generated based on the configuration information, the reset signal is pulled low and the first storage unit is cleared.

8. The decoding method according to claim 7, characterized in that: The obtaining of the channel message and index value of the variable node includes: When the first storage unit receives the input information valid signal and buffers the input channel message, the channel message is transmitted to the first shift unit.

9. The decoding method according to claim 8, characterized in that: The method further comprises: When the channel message update module generates the third feedback information, the enable signal is pulled high; When the parity check result output by the parity check unit is at a low level, the output information valid signal is pulled high.

10. An electronic device, characterized in that: include: Memory, used to store programs; A processor is used to execute the program, wherein the program is specifically used to implement the decoding method according to any one of claims 6 to 9.

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