Current starvation type PUF circuit using SRAM

Abstract

The invention discloses a current hunger type PUF (Physical Unclonable Function) circuit utilizing an SRAM (Static Random Access Memory), which comprises a mode configuration circuit, a decoding circuit, a PUF array and a reading circuit, and is characterized in that the PUF array has a conventional SRAM storage mode and a PUF mode capable of generating entropy source voltage, the PUF array comprises m * n PUF units and n pre-charging modules, each PUF unit comprises a first PMOS (P-channel Metal Oxide Semiconductor) tube, a second PMOS tube, a third PMOS tube, a first NMOS (N-channel Metal Oxide Semiconductor) tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube and a sixth NMOS tube; the method has the advantages that a PUF array does not need to be additionally designed and added, only the first PMOS transistor, the first NMOS transistor and the fourth NMOS transistor need to be added in each SRAM unit of an original SRAM storage array of the Internet of Things equipment, the PUF array formed by the PUF units with the monostable characteristic is formed, the function of the original SRAM storage array is not affected, and the cost is reduced. Therefore, the method has relatively high reliability, and meanwhile, the overall hardware overhead is relatively low.

Description

Technical Field

[0001] The present invention relates to a PUF circuit, and in particular to a current-starved PUF circuit using SRAM. Background Art

[0002] Physical Unclonable Function (PUF) uses process deviations in silicon wafer manufacturing to generate keys for identity identification and device authentication, effectively improving the security of IoT devices. IoT devices have a number of SRAM cells distributed in an array to form an SRAM storage array, where each SRAM cell is composed of two cross-coupled inverters. After the SRAM storage array is powered on, each SRAM cell has a power-on state of low level 0 or high level 1, and the power-on state of each SRAM cell depends on its own process deviation.

[0003] The SRAM PUF circuit is a PUF circuit that is widely used in IoT devices. It uses the existing SRAM storage array in the IoT device as the PUF array. The SRAM cells in the SRAM storage array are used as PUF cells in the PUF array to generate an entropy source voltage for extracting the PUF response. This eliminates the need to design a special PUF array to generate the entropy source voltage, significantly reducing the hardware overhead of IoT devices and has been widely used in IoT devices.

[0004] However, since the PUF response of each bit of the SRAM PUF circuit is extracted by using the entropy source voltage generated by the bistable characteristics of the cross-coupled inverters of the SRAM unit during the power-on process, when the process deviation of the SRAM unit itself is small, the power-on result (i.e., the entropy source voltage) may be determined by environmental disturbances rather than process deviations, resulting in low reliability of the extracted PUF response. Therefore, the SRAM PUF circuit itself is not reliable, which will have an adverse impact on the security of identity recognition and device authentication of IoT devices.

[0005] In order to improve the security of identity recognition and device authentication of IoT devices, some researchers have proposed other types of PUF circuits. These PUF circuits do not use SRAM storage arrays as PUF arrays, but redesign PUF units and PUF arrays. Their PUF units have monostable characteristics. Even when the process deviation is small, the entropy source voltage used to extract the PUF response is determined by its process deviation. Therefore, these PUF circuits have high reliability. However, since the PUF array is generally large in scale, these PUF circuits will result in large hardware overhead when used in IoT devices compared to SRAM PUF circuits. Summary of the invention

[0006] The technical problem to be solved by the present invention is to provide a current-starved monostable PUF circuit using SRAM which has high reliability and low overall hardware overhead.

[0007] The technical solution adopted by the present invention to solve the above technical problems is: a current-starved PUF circuit using SRAM, including a mode configuration circuit, a decoding circuit, a PUF array and a readout circuit, wherein the PUF array has a conventional SRAM storage mode and a PUF mode capable of generating an entropy source voltage; the PUF array includes m*n PUF units and n pre-charging modules, wherein * is a multiplication symbol, and m=2 P , n = 2 K, P and K are both positive integers, m*n PUF units are distributed according to m rows and n columns, n pre-charging modules are distributed according to 1 row and n columns, each PUF unit has a left bit line port, a right bit line port, a first mode configuration port, a second mode configuration port, a third mode configuration port and a word line port; each pre-charging module has a left pre-charging port, a right pre-charging port and a pre-charging control port; the left bit line ports of the m PUF units located in the i-th column are connected to the left pre-charging port of the pre-charging module located in the i-th column, and the connecting line forms the i-th left bit line of the PUF array, denoted as BL[i-1], i=1,2,…,n, the right bit line ports of the m PUF units located in the i-th column are connected to the left pre-charging port of the pre-charging module located in the i-th column The right pre-charging port of the pre-charging module is connected, and the connection line forms the i-th right bit line of the PUF array, denoted as BLB[i-1], the first mode configuration ports of the m PUF units located in the i-th column are connected, and the connection line forms the i-th first mode configuration line of the PUF array, denoted as Vu[i-1], the second mode configuration ports of the m PUF units located in the i-th column are connected, and the connection line forms the i-th second mode configuration line of the PUF array, denoted as Vd[i-1], the third mode configuration ports of the m PUF units located in the i-th column are connected, and the connection line forms the i-th third mode configuration line of the PUF array, denoted as E[i-1], and the n PUF units located in the j-th row The word line port of the PUF array is connected, and its connection line forms the jth word line of the PUF array, denoted as WL[j-1], j=1, 2, ..., m; the precharge control ports of the n precharge modules are connected, and their connection ends are the precharge control ports of the PUF array; the mode configuration circuit has a mode selection port, n first mode signal output ports and n second mode signal output ports, the mode selection port of the mode configuration circuit is used to access the mode selection signal S, under the control of the mode selection signal S, the n first mode signal output ports and the n second mode signal output ports of the mode configuration circuit can respectively generate corresponding n-bit mode configuration signal outputs; when S is low level 0 and the n When the signals connected to the third mode configuration lines are all low level 0, the PUF array is configured as a conventional SRAM storage mode, and each PUF unit works in the conventional SRAM storage mode; when S is high level 1 and the signals connected to the n third mode configuration lines of the PUF array are all high level 1, the PUF array is configured as a PUF mode capable of generating an entropy source voltage, and each PUF unit works in a PUF mode capable of generating an entropy source voltage; the decoding circuit has an m-bit output terminal, and the decoding circuit is used to convert an external address signal input thereto into an m-bit row selection signal and output it through its m-bit output terminal in a one-to-one correspondence, and only one bit of the m-bit row selection signal is a high level 1, and the other bits are all low level 0;The readout circuit has a reference voltage input terminal, n left input ports, n right input ports, n left output ports and n right output ports; the n first mode signal output ports of the mode configuration circuit are connected one-to-one with the n first mode configuration lines of the PUF array, the n second mode signal output ports of the mode configuration circuit are connected one-to-one with the n second mode configuration lines of the PUF array, the n third mode configuration lines of the PUF array are used to access external n-bit mode configuration signals, the m-bit output terminal of the decoding circuit is connected one-to-one with the m word lines of the PUF array, the n left input ports of the readout circuit are connected one-to-one with the n left bit lines of the PUF array, the n right input ports of the readout circuit are connected one-to-one with the n right bit lines of the PUF array, and when a word line of the PUF array is connected to a high level 1, it is connected to the word line of the PUF array. A row of PUF units corresponding to a word line is selected, and the i-th PUF unit in the row outputs the voltage value of its left bit line port to the i-th left input port of the readout circuit through the i-th left bit line, and the i-th PUF unit in the row outputs the voltage value of its right bit line port to the i-th right input port of the readout circuit through the i-th right bit line, and the readout circuit compares the voltage value connected to its i-th left input port and the voltage value connected to its i-th right input port with the reference voltage connected to its reference voltage input terminal, respectively, and if the voltage value connected to its i-th left input port is greater than the reference voltage connected to its reference voltage input terminal, then the digital signal 0 is output at its i-th left output port, otherwise the digital signal 1 is output, and if the voltage value connected to its i-th right input port is greater than the reference voltage connected to its reference voltage input terminal, then the digital signal 1 is output at its i-th right output port, otherwise the digital signal 0 is output;Each of the PUF units includes a first PMOS tube, a second PMOS tube, a third PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube and a sixth NMOS tube. The gate of the first PMOS tube is the first mode configuration port of the PUF unit. The source of the first PMOS tube is connected to the power supply voltage VDD. The drain of the first PMOS tube, the source of the second PMOS tube and the source of the third PMOS tube are connected. The gate of the second PMOS tube, the gate of the second NMOS tube, the drain of the third PMOS tube, the drain of the third NMOS tube, the drain of the fourth NMOS tube and the drain of the sixth NMOS tube are connected. The drain of the second PMOS tube and the drain of the second NMOS tube are connected. The drain, the gate of the third PMOS tube, the gate of the third NMOS tube N3, the source of the fourth NMOS tube and the drain of the fifth NMOS tube are connected, the source of the first NMOS tube is grounded VSS, the drain of the first NMOS tube, the source of the second NMOS tube and the source of the third NMOS tube are connected, the gate of the first NMOS tube is the second mode configuration port of the PUF unit, the gate of the fourth NMOS tube is the third mode configuration port of the PUF unit, the gate of the fifth NMOS tube is connected to the gate of the sixth NMOS tube, and the connection end thereof is the word line port of the PUF unit, the source of the fifth NMOS tube is the left bit line port of the PUF unit, and the source of the sixth NMOS tube is the right bit line port of the PUF unit. ;

[0008] Each of the pre-charging modules includes a fourth PMOS tube, a fifth PMOS tube and a sixth PMOS tube, the gate of the fourth PMOS tube is connected to the gate of the fifth PMOS tube and the gate of the sixth PMOS tube, and the connection end thereof is the pre-charging control port of the pre-charging module, the source of the fourth PMOS tube and the source of the fifth PMOS tube are both connected to the half power supply voltage VDD / 2, the drain of the fourth PMOS tube is connected to the source of the sixth PMOS tube, and the connection end thereof is the left pre-charging port of the pre-charging module, and the drain of the fifth PMOS tube is connected to the drain of the sixth PMOS tube, and the connection end thereof is the right pre-charging port of the pre-charging module.

[0009] The mode configuration circuit includes a bias voltage source and n mode selectors, wherein the bias voltage source has a first bias voltage output port and a second bias voltage output port, each mode selector has a low level access port, a high level access port, a first bias voltage access port, a second bias voltage access port, a mode selection signal port, a first mode signal output port and a second mode signal output port, the low level access port of each mode selector is connected to a low level 0, and the high level access port is connected to a high level 1, the first bias voltage output port of the bias voltage source is connected to the first bias voltage access ports of the n mode selectors, the second bias voltage output port of the bias voltage source is connected to the second bias voltage access ports of the n mode selectors, the mode selection signal ports of the n mode selectors are connected, and the connection ends thereof are the mode selection ports of the mode configuration circuit, the first mode signal output ports of the n mode selectors serve as the n first mode signal output ports of the mode configuration circuit, and the second mode signal output ports of the n mode selectors serve as the n second mode signal output ports of the mode configuration circuit.

[0010] The bias voltage source includes a seventh PMOS tube, an eighth PMOS tube, a seventh NMOS tube and an eighth NMOS tube. The source of the seventh PMOS tube is connected to the power supply voltage VDD. The gate of the seventh PMOS tube, the drain of the seventh PMOS tube and the source of the eighth PMOS tube are connected, and the connection end thereof is the first bias voltage output port of the bias voltage source. The gate of the eighth PMOS tube, the drain of the eighth PMOS tube, the drain of the eighth NMOS tube N8 and the gate of the eighth NMOS tube are connected. The gate of the seventh NMOS tube, the drain of the seventh NMOS tube and the source of the eighth NMOS tube N8 are connected, and the connection end thereof is the second bias voltage output port of the bias voltage source. The source of the seventh NMOS tube is connected to the ground VSS.

[0011] Each of the mode selectors has two multiplexers, each of which has a first input port, a second input port, a selection end and an output end. When the selection end is connected to a high level, the first input end is connected to its output end, and when the selection end is connected to a low level, the second input end is connected to its output end. The two multiplexers are respectively called a first multiplexer and a second multiplexer. The first input port of the first multiplexer is a first bias voltage access port of the mode selector, the second input port of the first multiplexer is a low level access port of the mode selector, the first input port of the second multiplexer is a second bias voltage access port of the mode selector, and the second input port of the second multiplexer is a high level access port of the mode selector.

[0012] Compared with the prior art, the present invention has the advantages of constructing a current-starved PUF circuit using SRAM through a mode configuration circuit, a decoding circuit, a PUF array and a readout circuit, the PUF array has a conventional SRAM storage mode and a PUF mode capable of generating an entropy source voltage, the PUF array comprises m*n PUF units and n pre-charging modules, each PUF unit comprises a first PMOS tube, a second PMOS tube, a third PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube and a sixth NMOS tube; when the PUF array is configured as a PUF mode capable of generating an entropy source voltage, the n first mode output ports of the mode configuration circuit all output the same voltage signal, and the voltage signal is recorded as V b1 , n second mode output ports also output the same voltage signal, which is recorded as V b2 , where V b1 Greater than V b2 , V b1 is less than the threshold voltage of the first PMOS tube, V b2 is less than the threshold voltage of the first NMOS tube. At this time, the first mode configuration port of each PUF unit in the PUF array is connected to the voltage signal V b1 , the second mode configures the port to access the voltage signal V b2 , each PUF unit in the PUF array works in the PUF mode that can generate entropy source voltage. At this time, in each PUF unit, the gate of the first PMOS tube is connected to the voltage signal V b1 , the gate of the first NMOS tube is connected to the voltage signal V b2 , due to V b1 is less than the threshold voltage of the first PMOS tube, V b2 is less than the threshold voltage of the first NMOS tube, so the first PMOS tube and the first NMOS tube are not turned on and are in the deep subthreshold region. The current flowing through them is a weak subthreshold current. The subthreshold current flowing through the first PMOS tube is recorded as I P1 , the subthreshold current flowing through the first NMOS tube is recorded as I N1 , I P1 with I N1 Only nA difference, because the second PMOS tube and the third PMOS tube are in parallel, and the first PMOS tube is in series with them. According to Kirchhoff's current law, the current I flowing through the first PMOS tube is P1 Equal to the current I flowing through the second PMOS tube P2 The current I flowing through the third PMOS tube P3 The sum of the current I P1 Under the limitation of P2 with IP3 It is also a weak subthreshold current, which forces the second PMOS tube and the third PMOS tube to enter the deep subthreshold region. P1 ,I P2 ,I P3 The combined effect of the current generates a matching voltage V1 at the connection node of the drain of the first PMOS tube, the source of the second PMOS tube, and the source of the third PMOS tube. Similarly, the current I flowing through the first NMOS tube N1 Equal to the current I flowing through the second NMOS tube N2 and the current I flowing through the third NMOS tube N3 N3 The sum of the current I N1 Under the limitation of N2 with I N3 It is also a weak subthreshold current, which forces the second NMOS tube and the third NMOS tube to enter the deep subthreshold region. N1 ,I N2 ,I N3 The combined effect of the current generates a matching voltage V2 at the connection node of the drain of the first NMOS tube, the source of the second NMOS tube, and the source of the third NMOS tube, and the current I flowing through the second PMOS tube is P2 The current I flowing through the third PMOS tube P3 The sum is equal to the current I flowing through the second NMOS tube N2 N2 and the current I flowing through the fourth NMOS tube N4 The sum of the currents, combined with the matching voltages V1 and V2, generates an entropy source voltage V in PUF mode at the connection node of the drain of the second PMOS tube, the drain of the third PMOS tube, the drain of the second NMOS tube, and the drain of the third NMOS tube. M , V M It is related to the process parameters of the first PMOS tube, the second PMOS tube, the third PMOS tube, the first NMOS tube, the second NMOS tube and the third NMOS tube. Due to the inevitable introduction of process deviations in the actual chip manufacturing process, these process parameters will change randomly, especially the difference in threshold voltage is the most obvious. These offsets are amplified by the source barrier lowering effect, which leads to V M After each PUF unit in the PUF array generates an entropy source voltage, all pre-charging modules of the PUF array perform a pre-charging operation to refresh the charge of all left bit lines and right bit lines of the PUF array, so that the voltages of all left bit lines and right bit lines of the PUF array remain equal. Then all pre-charging modules stop performing the pre-charging operation, and the decoding circuit outputs an m-bit row selection signal to select one row of n PUF units in the PUF array. The entropy source voltage V generated by each selected PUF unit is MThe data is transmitted to a left bit line and a right bit line connected to the PUF unit through its fifth NMOS tube and the sixth NMOS tube. At this time, the i-th right bit line and the i-th left bit line of the PUF array are connected to the entropy source voltage generated by the PUF unit located in the i-th column of the selected row of n PUF units. Each left input port of the readout circuit is connected and each right input port is respectively connected to the corresponding entropy source voltage. The readout circuit digitizes the entropy source voltage currently connected to its n left input ports and n right input ports to obtain the PUF response output. After completing the current PUF response output, all the pre- The charging module performs the pre-charging operation again to refresh the charge of all the left bit lines and right bit lines of the PUF array, so that the voltage of all the left bit lines and right bit lines of the PUF array remains equal, and then all the pre-charging modules stop performing the pre-charging operation, and then the decoding circuit outputs the m-bit row selection signal again, and repeats the process until the required number of PUF responses are output; when the PUF array is configured as a conventional SRAM storage mode, the n first mode output ports of the mode configuration circuit all output a low level 0, and the n second mode output ports all output a high level 1. At this time, all the PUF units in the PUF array are The first mode configuration ports are all connected to the low level 0, and the second mode configuration ports of all PUF units in the PUF array are all connected to the high level 1. At this time, the first PMOS tube and the first NMOS tube are fully turned on, which is equivalent to a wire. Each PUF unit in the PUF array works in the conventional SRAM storage mode. The second PMOS tube, the third PMOS tube, the second NMOS tube and the third NMOS tube in the PUF unit form a pair of cross-coupled inverters with positive feedback function, where the connection point between the drain of the second PMOS tube and the drain of the second NMOS tube is the left data storage node, denoted as Q, where The connection point between the drain of the third PMOS tube and the drain of the third NMOS tube is the right data storage node, denoted as QB. The PUF unit is equivalent to a conventional SRAM unit. When performing a data write operation, the external write circuit transmits an n-bit data signal to the n left bit lines and n right bit lines of the PUF array. The decoding circuit outputs an m-bit row selection signal to select a row of n PUF units in the PUF array. Each selected PUF unit transmits data to the left storage node Q and the right storage node QB of the PUF unit working in the conventional SRAM storage mode through the fifth NMOS tube and the sixth NMOS tube.When performing the hold operation, the decoding circuit has no signal output, and the fifth NMOS tube and the sixth NMOS tube of all PUF units in the PUF array are turned off. Under the action of the positive feedback of the cross-coupled inverter, the data (i.e., voltage) of the left storage node Q and the right storage node QB are maintained. Before data reading, all pre-charging modules of the PUF array perform a pre-charging operation to refresh the charges of all left bit lines and right bit lines of the PUF array so that the voltages of all left bit lines and right bit lines of the PUF array remain equal. Subsequently, all pre-charging modules stop performing the pre-charging operation, and the decoding circuit outputs an m-bit row selection signal to select one row of n PUF units in the PUF array. In each selected PUF unit, the data of the left storage node Q and the data of the right storage node QB are transmitted to a left bit line and a right bit line connected to the PUF unit through the fifth NMOS tube and the sixth NMOS tube. At this time, the i-th left bit line and the i-th right bit line of the PUF array are connected to the data of the left storage node Q and the data of the right storage node QB of the PUF unit located in the i-th column of the selected row of n PUF units. Each left input port of the readout circuit is connected to corresponding data, and each right input port is connected to corresponding data. The readout circuit digitizes the data currently connected to its n left input ports and n right input ports as corresponding data output. After the data is output, all pre-charging modules of the PUF array perform pre-charging operation again, refresh the charge of all left bit lines and right bit lines in the PUF array, so that the voltage of all left bit lines and right bit lines of the PUF array remains equal, and then all pre-charging modules stop performing pre-charging operation, and then the decoding circuit outputs m-bit row selection signal again, and repeats until all data is read out; the current-starved PUF circuit using SRAM of the present invention does not need additional design to increase the PUF array, and only needs to add three transistors, namely, the first PMOS tube, the first NMOS tube and the fourth NMOS tube, to each SRAM unit of the original SRAM storage array of the Internet of Things device, so as to form a PUF array composed of PUF units with monostable characteristics, and does not affect the original SRAM storage array function, so that the present invention has high reliability and low overall hardware overhead. ; BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a module block diagram of a current-starved PUF circuit using SRAM of the present invention;

[0014] Figure 2 A structural block diagram of a PUF array of a current-starved PUF circuit using SRAM according to the present invention;

[0015] Figure 3 A circuit diagram of a PUF unit of a current-starved PUF circuit using SRAM according to the present invention;

[0016] Figure 4 An equivalent circuit diagram of a PUF unit of a current-starved PUF circuit using SRAM of the present invention working in a PUF mode;

[0017] Figure 5 An equivalent circuit diagram of a PUF unit of a current-starved PUF circuit using SRAM according to the present invention operating in a bistable data storage mode;

[0018] Figure 6 A circuit diagram of a pre-charging circuit of a current-starved PUF circuit using SRAM of the present invention;

[0019] Figure 7 A structural block diagram of a mode configuration circuit of a current-starved PUF circuit using SRAM of the present invention;

[0020] Figure 8 A circuit diagram of a bias voltage source of a current-starved PUF circuit using SRAM according to the present invention;

[0021] Fig. 9 A circuit diagram of a mode selection circuit of a current-starved PUF circuit using SRAM according to the present invention;

[0022] Fig.10 It is a distribution diagram of the inter-chip Hamming distance of the PUF response of the current-starved PUF circuit using SRAM of the present invention;

[0023] Fig.11 This is a graph showing the bit error rate of the current-starved PUF circuit using SRAM according to the present invention as a function of temperature and voltage. DETAILED DESCRIPTION

[0024] The present invention is further described in detail below with reference to the accompanying drawings.

[0025] Embodiment 1: Figure 1 As shown, Figure 1 As shown, a current-starved PUF circuit using SRAM includes a mode configuration circuit, a decoding circuit, a PUF array and a readout circuit, wherein the PUF array has a conventional SRAM storage mode and a PUF mode capable of generating an entropy source voltage; Figure 2 As shown, the PUF array includes m*n PUF units and n pre-charging modules, where * is a multiplication symbol and m=2 P , n = 2 K, P=5, K=3; m*n PUF units are distributed according to m rows and n columns, n pre-charging modules are distributed according to 1 row and n columns, each PUF unit has a left bit line port, a right bit line port, a first mode configuration port, a second mode configuration port, a third mode configuration port and a word line port; each pre-charging module has a left pre-charging port, a right pre-charging port and a pre-charging control port; the left bit line ports of the m PUF units located in the i-th column are connected to the left pre-charging port of the pre-charging module located in the i-th column, and the connection line forms the i-th left bit line of the PUF array, denoted as BL[i-1], i=1,2,…,n, the right bit line ports of the m PUF units located in the i-th column are connected to the right pre-charging port of the pre-charging module located in the i-th column The electrical ports are connected, and their connection lines form the i-th right bit line of the PUF array, denoted as BLB[i-1]; the first mode configuration ports of the m PUF units located in the i-th column are connected, and their connection lines form the i-th first mode configuration line of the PUF array, denoted as Vu[i-1]; the second mode configuration ports of the m PUF units located in the i-th column are connected, and their connection lines form the i-th second mode configuration line of the PUF array, denoted as Vd[i-1]; the third mode configuration ports of the m PUF units located in the i-th column are connected, and their connection lines form the i-th third mode configuration line of the PUF array, denoted as E[i-1]; the word line ports of the n PUF units located in the j-th row are connected, and their connection lines form the PUF array The j-th word line of the column is recorded as WL[j-1], j=1, 2, ..., m; the precharge control ports of n precharge modules are connected, and the connection end thereof is the precharge control port of the PUF array; the mode configuration circuit has a mode selection port, n first mode signal output ports and n second mode signal output ports, the mode selection port of the mode configuration circuit is used to access the mode selection signal S, under the control of the mode selection signal S, the n first mode signal output ports and the n second mode signal output ports of the mode configuration circuit can respectively generate corresponding n-bit mode configuration signal outputs; when S is low level 0 and the signals accessed by the n third mode configuration lines of the PUF array are all low level 0, the PUF array is configured as a conventional SR AM storage mode, at this time, each PUF unit works in the conventional SRAM storage mode; when S is high level 1 and the signals connected to the n third mode configuration lines of the PUF array are all high level 1, the PUF array is configured as a PUF mode that can generate an entropy source voltage, and at this time, each PUF unit works in a PUF mode that can generate an entropy source voltage; the decoding circuit has an m-bit output terminal, and the decoding circuit is used to convert the address signal input externally thereto into an m-bit row selection signal and output it through its m-bit output terminal in a one-to-one correspondence, and only one bit of the m-bit row selection signal is high level 1, and the other bits are low level 0; the readout circuit has a reference voltage input terminal, n left input ports, n right input ports, n left output ports and n right output ports;The n first mode signal output ports of the mode configuration circuit are connected to the n first mode configuration lines of the PUF array in a one-to-one correspondence, the n second mode signal output ports of the mode configuration circuit are connected to the n second mode configuration lines of the PUF array in a one-to-one correspondence, the n third mode configuration lines of the PUF array are used to access the external n-bit mode configuration signal, the m-bit output end of the decoding circuit is connected to the m word lines of the PUF array in a one-to-one correspondence, the n left input ports of the readout circuit are connected to the n left bit lines of the PUF array in a one-to-one correspondence, the n right input ports of the readout circuit are connected to the n right bit lines of the PUF array in a one-to-one correspondence, when a word line of the PUF array is connected to a high level 1, a row of PUF units corresponding to the word line is selected, and the i-th PUF unit of the row sets the voltage of its left bit line port to 1. The voltage value is output to the i-th left input port of the readout circuit through the i-th left bit line, and the i-th PUF unit in the row outputs the voltage value of its right bit line port to the i-th right input port of the readout circuit through the i-th right bit line. The readout circuit compares the voltage value connected to its i-th left input port and the voltage value connected to its i-th right input port with the reference voltage connected to its reference voltage input terminal, respectively. If the voltage value connected to its i-th left input port is greater than the reference voltage connected to its reference voltage input terminal, then the digital signal 0 is output at its i-th left output port, otherwise the digital signal 1 is output. If the voltage value connected to its i-th right input port is greater than the reference voltage connected to its reference voltage input terminal, then the digital signal 1 is output at its i-th right output port, otherwise the digital signal 0 is output; such as; Figure 3As shown, each PUF unit includes a first PMOS tube P1, a second PMOS tube P2, a third PMOS tube P3, a first NMOS tube N1, a second NMOS tube N2, a third NMOS tube N3, a fourth NMOS tube N4, a fifth NMOS tube N5 and a sixth NMOS tube N6. The gate of the first PMOS tube P1 is a first mode configuration port of the PUF unit, the source of the first PMOS tube P1 is connected to the power supply voltage VDD, the drain of the first PMOS tube P1, the source of the second PMOS tube P2 and the source of the third PMOS tube P3 are connected, the gate of the second PMOS tube P2, the gate of the second NMOS tube N2, the drain of the third PMOS tube P3, the drain of the third NMOS tube N3, the drain of the fourth NMOS tube N4 and the drain of the sixth NMOS tube N6 are connected, and the second PMOS tube P The drain of the first NMOS tube N2, the drain of the second NMOS tube N2, the gate of the third PMOS tube P3, the gate of the third NMOS tube N3, the source of the fourth NMOS tube N4 and the drain of the fifth NMOS tube N5 are connected, the source of the first NMOS tube N1 is grounded VSS, the drain of the first NMOS tube N1, the source of the second NMOS tube N2 and the source of the third NMOS tube N3 are connected, the gate of the first NMOS tube N1 is the second mode configuration port of the PUF unit, the gate of the fourth NMOS tube N4 is the third mode configuration port of the PUF unit, the gate of the fifth NMOS tube N5 and the gate of the sixth NMOS tube N6 are connected, and the connection end thereof is the word line port of the PUF unit, the source of the fifth NMOS tube N5 is the left bit line port of the PUF unit, and the source of the sixth NMOS tube N6 is the right bit line port of the PUF unit.

[0026] In this embodiment, a current-starved PUF circuit using SRAM is constructed by a mode configuration circuit, a decoding circuit, a PUF array, and a readout circuit. The PUF array has a conventional SRAM storage mode and a PUF mode capable of generating an entropy source voltage. The PUF array includes m*n PUF units and n pre-charging modules. Each PUF unit includes a first PMOS tube P1, a second PMOS tube P2, a third PMOS tube P3, a first NMOS tube N1, a second NMOS tube N2, a third NMOS tube N3, a fourth NMOS tube N4, a fifth NMOS tube N5, and a sixth NMOS tube N6. When the PUF array is configured as a PUF mode capable of generating an entropy source voltage, the n first mode output ports of the mode configuration circuit all output the same voltage signal, which is recorded as V b1 , n second mode output ports also output the same voltage signal, which is recorded as V b2 , where V b1 Greater than V b2 , V b1 is less than the threshold voltage of the first PMOS tube P1, V b2is less than the threshold voltage of the first NMOS tube N1, at this time, the first mode configuration port of each PUF unit in the PUF array is connected to the voltage signal V b1 , the second mode configures the port to access the voltage signal V b2 , each PUF unit in the PUF array works in the PUF mode that can generate entropy source voltage, and its equivalent circuit is as follows Figure 4 As shown, at this time, in each PUF unit, the gate of the first PMOS tube P1 is connected to the voltage signal V b1 , the gate of the first NMOS tube N1 is connected to the voltage signal V b2 , due to V b1 is less than the threshold voltage of the first PMOS tube P1, V b2 is less than the threshold voltage of the first NMOS tube N1, so the first PMOS tube P1 and the first NMOS tube N1 are not turned on and are in the deep subthreshold region. The current flowing through them is a weak subthreshold current. The subthreshold current flowing through the first PMOS tube P1 is recorded as I P1 , the subthreshold current flowing through the first NMOS tube N1 is recorded as I N1 , I P1 with I N1 Only nA difference, because the second PMOS tube P2 and the third PMOS tube P3 are in parallel, and the first PMOS tube P1 is in series with them, according to Kirchhoff's current law, the current I flowing through the first PMOS tube P1 P1 Equal to the current I flowing through the second PMOS tube P2 P2 The current I flowing through the third PMOS tube P3 P3 The sum of the current I P1 Under the limitation of P2 with I P3 It is also a weak subthreshold current, which forces the second PMOS tube P2 and the third PMOS tube P3 to also enter the deep subthreshold region. P1 ,I P2 ,I P3 The combined effect of the current generates a matching voltage V1 at the connection node of the drain of the first PMOS tube P1, the source of the second PMOS tube P2, and the source of the third PMOS tube P3; similarly, the current I flowing through the first NMOS tube N1 N1 Equal to the current I flowing through the second NMOS tube N2 The current I flowing through the third NMOS tube N3 The sum of the current I N1 Under the limitation of N2 with I N3 It is also a weak subthreshold current, which forces the second NMOS tube N2 and the third NMOS tube N3 to enter the deep subthreshold region. N1,I N2 ,I N3 The combined effect of the current generates a matching voltage V2 at the connection node of the drain of the first NMOS tube N1, the source of the second NMOS tube N3, and the source of the third NMOS tube N3, and the current I flowing through the second PMOS tube P2 is P2 The current I flowing through the third PMOS tube P3 P3 The sum is equal to the current I flowing through the second NMOS tube N2 N2 and the current I flowing through the fourth NMOS tube N4 N4 The sum of the currents, combined with the matching voltages V1 and V2, generates an entropy source voltage V in the PUF mode at the connection node of the drain of the second PMOS tube P2, the drain of the third PMOS tube P3, the drain of the second NMOS tube N2, and the drain of the third NMOS tube N3. M , V M It is related to the process parameters of the first PMOS tube P1, the second PMOS tube P2, the third PMOS tube P3, the first NMOS tube N1, the second NMOS tube N2 and the third NMOS tube N3. Due to the inevitable introduction of process deviations in the actual chip manufacturing process, these process parameters will change randomly, especially the difference in threshold voltage is the most obvious. These offsets are amplified by the source barrier lowering effect, which leads to V M After each PUF unit in the PUF array generates an entropy source voltage, all pre-charging modules of the PUF array perform a pre-charging operation to refresh the charge of all left bit lines and right bit lines of the PUF array, so that the voltages of all left bit lines and right bit lines of the PUF array remain equal. Then all pre-charging modules stop performing the pre-charging operation, and the decoding circuit outputs an m-bit row selection signal to select one row of n PUF units in the PUF array. The entropy source voltage V generated by each selected PUF unit is MThe data is transmitted to a left bit line and a right bit line connected to the PUF unit through the fifth NMOS tube N5 and the sixth NMOS tube N6. At this time, the i-th right bit line and the i-th left bit line of the PUF array are connected to the entropy source voltage generated by the PUF unit located in the i-th column of the selected row of n PUF units. Each left input port of the readout circuit is connected and each right input port is respectively connected to the corresponding entropy source voltage. The readout circuit digitizes the entropy source voltage currently connected to its n left input ports and n right input ports, respectively, to obtain the PUF response output. After completing the current PUF response output, all pre-charging modules of the PUF array perform the pre-charging operation again, and refresh the charges of all left bit lines and right bit lines of the PUF array, so that the voltages of all left bit lines and right bit lines of the PUF array remain equal. Then all pre-charging modules stop performing the pre-charging operation, and then the decoding circuit outputs the m-bit row selection signal again, and repeats the cycle until the required number of PUF responses are output;

[0027] When the PUF array is configured as a conventional SRAM storage mode, the n first mode output ports of the mode configuration circuit all output a low level 0, and the n second mode output ports all output a high level 1. At this time, the first mode configuration ports of all PUF units in the PUF array are connected to a low level 0, and the second mode configuration ports of all PUF units in the PUF array are connected to a high level 1. At this time, the first PMOS tube P1 and the first NMOS tube N1 are fully turned on, which is equivalent to a wire. Each PUF unit in the PUF array works in the conventional SRAM storage mode, and its equivalent circuit is as follows: Figure 5As shown, the second PMOS tube P2, the third PMOS tube P3, the second NMOS tube N2 and the third NMOS tube N3 in the PUF unit form a pair of cross-coupled inverters with positive feedback function, wherein the connection point between the drain of the second PMOS tube P2 and the drain of the second NMOS tube N2 is the left data storage node, denoted as Q, wherein the connection point between the drain of the third PMOS tube P3 and the drain of the third NMOS tube N3 is the right data storage node, denoted as QB, the PUF unit is equivalent to a conventional SRAM unit, when performing a data write operation, the external write circuit transmits the n-bit data signal to the n left bit lines and n right bit lines of the PUF array, and the decoding circuit outputs m A row selection signal is sent to select a row of n PUF units in the PUF array. Each selected PUF unit transmits data to the left storage node Q and the right storage node QB of the PUF unit working in the conventional SRAM storage mode through the fifth NMOS tube N5 and the sixth NMOS tube N6. When performing the hold operation, the decoding circuit has no signal output, and the fifth NMOS tube and the sixth NMOS tube N6 of all PUF units in the PUF array are turned off. Under the action of the positive feedback of the cross-coupled inverter, the data (i.e., the voltage) of the left storage node Q and the right storage node QB are maintained. Before the data is read, all pre-charge modules of the PUF array perform a pre-charge operation. , refresh the charges of all left bit lines and right bit lines of the PUF array to keep the voltages of all left bit lines and right bit lines of the PUF array equal, then all pre-charging modules stop performing pre-charging operations, the decoding circuit outputs an m-bit row selection signal, selects one row of n PUF units in the PUF array, in each selected PUF unit, the data of the left storage node Q and the data of the right storage node QB are transmitted to a left bit line and a right bit line connected to the PUF unit through the fifth NMOS tube N5 and the sixth NMOS tube N6, at this time, the i-th left bit line and the i-th right bit line of the PUF array are connected to the PUF located in the i-th column of the selected row of n PUF units. The data of the left storage node Q and the data of the right storage node QB of the unit are respectively connected to the corresponding data by each left input port and each right input port of the readout circuit. The readout circuit digitizes the data currently connected to its n left input ports and n right input ports into corresponding data outputs. After this data output, all pre-charging modules of the PUF array perform the pre-charging operation again, and refresh the charges of all left bit lines and right bit lines in the PUF array to keep the voltages of all left bit lines and right bit lines of the PUF array equal. Then all pre-charging modules stop performing the pre-charging operation, and then the decoding circuit outputs the m-bit row selection signal again, and repeats the cycle until all data are read out.

[0028] Embodiment 2: This embodiment is basically the same as Embodiment 1, except that: Figure 6As shown, in this embodiment, each pre-charging module includes a fourth PMOS tube P4, a fifth PMOS tube P5 and a sixth PMOS tube P6, the gate of the fourth PMOS tube P4, the gate of the fifth PMOS tube P5 and the gate of the sixth PMOS tube P6 are connected, and the connection end thereof is the pre-charging control port of the pre-charging module, the source of the fourth PMOS tube P4 and the source of the fifth PMOS tube P5 are both connected to the half power supply voltage VDD / 2, the drain of the fourth PMOS tube P4 is connected to the source of the sixth PMOS tube P6, and the connection end thereof is the left pre-charging port of the pre-charging module, and the drain of the fifth PMOS tube P5 is connected to the drain of the sixth PMOS tube P6, and the connection end thereof is the right pre-charging port of the pre-charging module.

[0029] In this embodiment, when the PUF array is to be precharged, the precharge control port of the PUF array is connected to a low level 0, that is, the precharge control port of each precharge module is connected to a low level 0, and in each precharge module, the fourth PMOS tube P4, the fifth PMOS tube P5 and the sixth PMOS tube P6 are all turned on, and the half power supply voltage VDD / 2 is transmitted to the left precharge port and the right precharge port, that is, the left precharge port and the right precharge port of each precharge module output the half power supply voltage VDD / 2. Thus, the n precharge modules refresh the voltages of the n left bit lines and the n right bit lines of the PUF array to the half power supply voltage VDD / 2.

[0030] Embodiment 3: This embodiment is basically the same as Embodiment 2, except that: Figure 7 As shown, in this embodiment, the mode configuration circuit includes a bias voltage source and n mode selectors, the bias voltage source has a first bias voltage output port and a second bias voltage output port, each mode selector has a low level access port, a high level access port, a first bias voltage access port, a second bias voltage access port, a mode selection signal port, a first mode signal output port and a second mode signal output port, the low level access port of each mode selector is connected to a low level 0, and the high level access port is connected to a high level 1, the first bias voltage output port of the bias voltage source is connected to the first bias voltage access ports of the n mode selectors, the second bias voltage output port of the bias voltage source is connected to the second bias voltage access ports of the n mode selectors, the mode selection signal ports of the n mode selectors are connected, and their connection ends are the mode selection ports of the mode configuration circuit, the first mode signal output ports of the n mode selectors serve as the n first mode signal output ports of the mode configuration circuit, and the second mode signal output ports of the n mode selectors serve as the n second mode signal output ports of the mode configuration circuit.

[0031] In this embodiment, when the mode selection port of the mode configuration circuit is connected to a low level 0, the first mode signal output port of each mode selector of the mode configuration circuit outputs a low level 0, and the second mode signal output port of each mode selector of the mode configuration circuit outputs a high level 1, so that the PUF array is configured into a conventional SRAM mode; when the mode selection port of the mode configuration circuit is connected to a high level 1, the first bias voltage output port of the bias voltage source outputs a voltage signal V b1 , the second bias voltage output port of the bias voltage source outputs a voltage signal V b2 At this time, the first mode signal output port of each mode selector outputs a voltage signal V b1 The second mode signal output port of each mode selector outputs a voltage signal V b2 , the PUF array is configured into a PUF mode that can generate an entropy source voltage.

[0032] Embodiment 4: This embodiment is basically the same as Embodiment 3, except that: Figure 8 As shown, in this embodiment, the bias voltage source includes a seventh PMOS tube P7, an eighth PMOS tube P8, a seventh NMOS tube N7 and an eighth NMOS tube N8, the source of the seventh PMOS tube P7 is connected to the power supply voltage VDD, the gate of the seventh PMOS tube P7, the drain of the seventh PMOS tube P7 and the source of the eighth PMOS tube P8 are connected, and the connection end thereof is a first bias voltage output port of the bias voltage source, the gate of the eighth PMOS tube P8, the drain of the eighth PMOS tube P8, the drain of the eighth NMOS tube N8 and the gate of the eighth NMOS tube N8 are connected, the gate of the seventh NMOS tube N7, the drain of the seventh NMOS tube N7 and the source of the eighth NMOS tube N8 are connected, and the connection end thereof is a second bias voltage output port of the bias voltage source, and the source of the seventh NMOS tube is connected to the ground VSS.

[0033] In the bias voltage source of the present embodiment, the bias voltage source, the seventh PMOS tube P7, the eighth PMOS tube P8, the seventh NMOS tube N7 and the eighth NMOS tube N8 are stacked in series, so the currents flowing through the seventh PMOS tube P7, the eighth PMOS tube P8, the seventh NMOS tube N7 and the eighth NMOS tube N8 are equal. Under the TSMC 65nm process used by the current-starved PUF circuit using SRAM of the present invention, the threshold voltages of all PMOS tubes and NMOS tubes are greater than 400mv, and the power supply voltage VDD is usually 1.2V. Therefore, the sum of the threshold voltages of the bias voltage source, the seventh PMOS tube P7, the eighth PMOS tube P8, the seventh NMOS tube N7 and the eighth NMOS tube N8 is less than the voltage value of the power supply voltage VDD, so the currents flowing through the seventh PMOS tube P7, the eighth PMOS tube P8, the seventh NMOS tube N7 and the eighth NMOS tube N8 are all subthreshold currents. Under the action of the subthreshold current, a voltage signal V is generated at the first bias voltage output port of the bias voltage source. b1 And the second bias voltage output port generates a voltage signal V b2 .

[0034] Embodiment 5: This embodiment is basically the same as Embodiment 3, except that: Fig. 9 As shown, the mode selectors are two multiplexers, each of which has a first input port, a second input port, a selection end and an output end. When the selection end is connected to a high level, the first input end is connected to the output end, and when the selection end is connected to a low level, the second input end is connected to the output end. The two multiplexers are respectively called the first multiplexer D1 and the second multiplexer D2. The first input port of the first multiplexer D1 is the first bias voltage access port of the mode selector, and the second input port of the first multiplexer D1 is the low level access port of the mode selector. The first input port of the second multiplexer D2 is the second bias voltage access port of the mode selector, and the second input port of the second multiplexer D2 is the high level access port of the mode selector.

[0035] In this embodiment, when the selection terminal of the mode selector is connected to a high level, the output signal of the output terminal of the first multiplexer D1 is a voltage signal V b1 , the output signal of the output terminal of the second multiplexer D2 is a voltage signal V b2 When the selection end of the mode selector is connected to a low level, the output signal of the output end of the first multiplexer D1 is a low level, and the output signal of the output end of the second multiplexer D2 is a high level.

[0036] In order to verify the performance of the current-starved PUF circuit using SRAM of the present invention, the current-starved PUF circuit using SRAM of the present invention was designed using Cadence virtuoso software under TSMC 65nm process, and the current-starved PUF circuit using SRAM of the present invention was simulated using SPECTRE tool. The experimental results use three common evaluation indicators of randomness, uniqueness and reliability to evaluate the current-starved PUF circuit using SRAM of the present invention.

[0037] 1. Randomness

[0038] Randomness is usually evaluated by the National Institute of Standards and Technology (NIST) test. In the NIST test, the p value is usually used to evaluate the randomness of the PUF circuit output response. If the p value of the test is greater than 0.01, the PUF response is considered to be random in the test. The higher the p value, the higher the confidence level of the data randomness. The current starved PUF circuit using SRAM of the present invention is tested by NIST (due to the limitation of the number of PUF response bits, some tests with too high requirements for bit string length cannot be performed), and the test results are shown in Table 1:

[0039] Table 1 NIST test results

[0040]

[0041] From the analysis of the data in Table 1, it can be seen that the current-starved PUF circuit using SRAM of the present invention has passed all applicable NIST tests with a high average p-value, showing excellent randomness.

[0042] 2. Uniqueness

[0043] Uniqueness indicates the degree of difference between different PUF circuit entities, which is usually evaluated by the inter-chip Hamming distance. Ideally, each PUF circuit entity is independent of each other, that is, the Hamming distance is 50%. The average Hamming distance of K PUF circuit entities can be calculated by (1):

[0044]

[0045] Where K represents the number of PUF circuit entities, Ru and Rv represent the n-bit PUF responses generated by the u-th and v-th PUF circuit entities under the same stimulus, respectively.

[0046] Under nominal conditions (1.2V, 27°C), the inter-chip Hamming distance results of the PUF response output by 40 Monte Carlo simulations of the current-starved PUF circuit using SRAM of the present invention are statistically analyzed. Fig.10 Analysis Fig.10 It can be seen that the mathematical expectation of the uniqueness of the current-starved PUF circuit using SRAM of the present invention is 50.17%, and the standard deviation is 0.0639, which shows that the current-starved PUF circuit using SRAM of the present invention has good discrimination.

[0047] 3. Reliability

[0048] Reliability is particularly important in PUF circuits because it ensures that the PUF circuit can produce consistent output even under environmental changes (such as temperature and voltage fluctuations) and aging caused by long-term use. The bit error rate of the current-starved PUF circuit using SRAM of the present invention varies with temperature and voltage. Fig.11 Analysis Fig.11 It can be seen that, under the condition of large changes in temperature and voltage, the worst bit error rates of the current-starved PUF circuit using SRAM of the present invention are 3.27% and 2.05% respectively, which has good reliability.

Claims

1. A current-starved PUF circuit using SRAM, characterized in that The invention comprises a mode configuration circuit, a decoding circuit, a PUF array and a readout circuit. The PUF array has a conventional SRAM storage mode and a PUF mode capable of generating an entropy source voltage. The PUF array comprises m*n PUF units and n pre-charging modules, wherein * is a multiplication symbol and m=2 P , n = 2 K , P and K are both positive integers; m*n PUF units are distributed according to m rows and n columns, n pre-charging modules are distributed according to 1 row and n columns, each PUF unit has a left bit line port, a right bit line port, a first mode configuration port, a second mode configuration port, a third mode configuration port and a word line port; each pre-charging module has a left pre-charging port, a right pre-charging port and a pre-charging control port; the left bit line ports of the m PUF units located in the i-th column are connected to the left pre-charging port of the pre-charging module located in the i-th column, and the connecting line forms the i-th left bit line of the PUF array, denoted as BL[i-1], i=1,2,…,n, the right bit line ports of the m PUF units located in the i-th column are connected to the right pre-charging port of the pre-charging module located in the i-th column, and the connecting line forms The i-th right bit line of the PUF array is denoted as BLB[i-1], the first mode configuration ports of the m PUF units located in the i-th column are connected, and the connection line forms the i-th first mode configuration line of the PUF array, denoted as Vu[i-1], the second mode configuration ports of the m PUF units located in the i-th column are connected, and the connection line forms the i-th second mode configuration line of the PUF array, denoted as Vd[i-1], the third mode configuration ports of the m PUF units located in the i-th column are connected, and the connection line forms the i-th third mode configuration line of the PUF array, denoted as E[i-1], the word line ports of the n PUF units located in the j-th row are connected, and the connection line forms the j-th word line of the PUF array, denoted as WL[j-1], j=1, 2, ..., m; The precharge control ports of n precharge modules are connected, and the connection end thereof is the precharge control port of the PUF array; the mode configuration circuit has a mode selection port, n first mode signal output ports and n second mode signal output ports, the mode selection port of the mode configuration circuit is used to access the mode selection signal S, under the control of the mode selection signal S, the n first mode signal output ports and the n second mode signal output ports of the mode configuration circuit can respectively generate corresponding n-bit mode configuration signal outputs; when S is low level 0 and the signals accessed by the n third mode configuration lines of the PUF array are all low level 0, the PUF array is configured as a conventional SRAM storage mode, at this time each PUF The units all work in a conventional SRAM storage mode; when S is a high level 1 and the signals connected to the n third mode configuration lines of the PUF array are all high level 1, the PUF array is configured as a PUF mode capable of generating an entropy source voltage, and at this time, each PUF unit works in a PUF mode capable of generating an entropy source voltage; the decoding circuit has an m-bit output terminal, and the decoding circuit is used to convert an external address signal input thereto into an m-bit row selection signal and output it through its m-bit output terminal in a one-to-one correspondence, and only one bit of the m-bit row selection signal is a high level 1, and the other bits are all low level 0; the readout circuit has a reference voltage input terminal, n left input ports, n right input ports, n left output ports, and n right output ports;The n first mode signal output ports of the mode configuration circuit are connected to the n first mode configuration lines of the PUF array in a one-to-one correspondence, the n second mode signal output ports of the mode configuration circuit are connected to the n second mode configuration lines of the PUF array in a one-to-one correspondence, the n third mode configuration lines of the PUF array are used to access external n-bit mode configuration signals, the m-bit output end of the decoding circuit is connected to the m word lines of the PUF array in a one-to-one correspondence, the n left input ports of the readout circuit are connected to the n left bit lines of the PUF array in a one-to-one correspondence, the n right input ports of the readout circuit are connected to the n right bit lines of the PUF array in a one-to-one correspondence, when a word line of the PUF array is connected to a high level 1, a row of PUF units corresponding to the word line is selected, and the i-th PUF in the row The unit outputs the voltage value of its left bit line port to the i-th left input port of the readout circuit through the i-th left bit line, and the i-th PUF unit in the row outputs the voltage value of its right bit line port to the i-th right input port of the readout circuit through the i-th right bit line. The readout circuit compares the voltage value connected to its i-th left input port and the voltage value connected to its i-th right input port with the reference voltage connected to its reference voltage input terminal, respectively. If the voltage value connected to its i-th left input port is greater than the reference voltage connected to its reference voltage input terminal, then the digital signal 0 is output at its i-th left output port, otherwise the digital signal 1 is output. If the voltage value connected to its i-th right input port is greater than the reference voltage connected to its reference voltage input terminal, then the digital signal 1 is output at its i-th right output port, otherwise the digital signal 0 is output. Each of the PUF units includes a first PMOS tube, a second PMOS tube, a third PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube and a sixth NMOS tube. The gate of the first PMOS tube is the first mode configuration port of the PUF unit. The source of the first PMOS tube is connected to the power supply voltage VDD. The drain of the first PMOS tube, the source of the second PMOS tube and the source of the third PMOS tube are connected. The gate of the second PMOS tube, the gate of the second NMOS tube, the drain of the third PMOS tube, the drain of the third NMOS tube, the drain of the fourth NMOS tube and the drain of the sixth NMOS tube are connected. The drain of the second PMOS tube, the gate of the second NMOS tube, the drain of the third PMOS tube, the drain of the third NMOS tube, the drain of the fourth NMOS tube and the drain of the sixth NMOS tube are connected. The drain of the third PMOS tube, the gate of the third NMOS tube, the source of the fourth NMOS tube and the drain of the fifth NMOS tube are connected, the source of the first NMOS tube is grounded VSS, the drain of the first NMOS tube, the source of the second NMOS tube and the source of the third NMOS tube are connected, the gate of the first NMOS tube is the second mode configuration port of the PUF unit, the gate of the fourth NMOS tube is the third mode configuration port of the PUF unit, the gate of the fifth NMOS tube is connected to the gate of the sixth NMOS tube, and the connection end thereof is the word line port of the PUF unit, the source of the fifth NMOS tube is the left bit line port of the PUF unit, and the source of the sixth NMOS tube is the right bit line port of the PUF unit.

2. The current-starved PUF circuit using SRAM according to claim 1, characterized in that Each of the pre-charging modules includes a fourth PMOS tube, a fifth PMOS tube and a sixth PMOS tube, the gate of the fourth PMOS tube is connected to the gate of the fifth PMOS tube and the gate of the sixth PMOS tube, and the connection end thereof is the pre-charging control port of the pre-charging module, the source of the fourth PMOS tube and the source of the fifth PMOS tube are both connected to the half power supply voltage VDD / 2, the drain of the fourth PMOS tube is connected to the source of the sixth PMOS tube, and the connection end thereof is the left pre-charging port of the pre-charging module, and the drain of the fifth PMOS tube is connected to the drain of the sixth PMOS tube, and the connection end thereof is the right pre-charging port of the pre-charging module.

3. The current-starved PUF circuit using SRAM according to claim 1, characterized in that The mode configuration circuit includes a bias voltage source and n mode selectors, wherein the bias voltage source has a first bias voltage output port and a second bias voltage output port, each mode selector has a low level access port, a high level access port, a first bias voltage access port, a second bias voltage access port, a mode selection signal port, a first mode signal output port and a second mode signal output port, the low level access port of each mode selector is connected to a low level 0, and the high level access port is connected to a high level 1, the first bias voltage output port of the bias voltage source is connected to the first bias voltage access ports of the n mode selectors, the second bias voltage output port of the bias voltage source is connected to the second bias voltage access ports of the n mode selectors, the mode selection signal ports of the n mode selectors are connected, and the connection ends thereof are the mode selection ports of the mode configuration circuit, the first mode signal output ports of the n mode selectors serve as the n first mode signal output ports of the mode configuration circuit, and the second mode signal output ports of the n mode selectors serve as the n second mode signal output ports of the mode configuration circuit.

4. The current-starved PUF circuit using SRAM according to claim 3, characterized in that The bias voltage source includes a seventh PMOS tube, an eighth PMOS tube, a seventh NMOS tube and an eighth NMOS tube, the source of the seventh PMOS tube is connected to the power supply voltage VDD, the gate of the seventh PMOS tube, the drain of the seventh PMOS tube and the source of the eighth PMOS tube are connected, and the connection end thereof is the first bias voltage output port of the bias voltage source, the gate of the eighth PMOS tube, the drain of the eighth PMOS tube, the drain of the eighth NMOS tube and the gate of the eighth NMOS tube are connected, the gate of the seventh NMOS tube, the drain of the seventh NMOS tube and the source of the eighth NMOS tube are connected, and the connection end thereof is the second bias voltage output port of the bias voltage source, and the source of the seventh NMOS tube is connected to the ground VSS.

5. The current-starved PUF circuit using SRAM according to claim 3, characterized in that Each of the mode selectors has two multiplexers, each of which has a first input port, a second input port, a selection end and an output end. When the selection end is connected to a high level, the first input end is connected to its output end, and when the selection end is connected to a low level, the second input end is connected to its output end. The two multiplexers are respectively called a first multiplexer and a second multiplexer. The first input port of the first multiplexer is a first bias voltage access port of the mode selector, the second input port of the first multiplexer is a low level access port of the mode selector, the first input port of the second multiplexer is a second bias voltage access port of the mode selector, and the second input port of the second multiplexer is a high level access port of the mode selector.

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