Camera delay detection method and device and electronic equipment

Abstract

The embodiment of the invention discloses a camera delay detection method and device and electronic equipment. A specific embodiment of the method comprises the following steps: a camera to be tested shoots a light emitting diode array to obtain an initial video frame image and transmits the initial video frame image to a video frame processor; the flash lamp control pin sends an exposure signal; adjusting the state of the light-emitting diode in response to the exposure signal received by the light-emitting diode microprocessor; in response to the exposure signal received by the video frame processor, respectively determining the corresponding timestamps as an exposure start timestamp and an exposure end timestamp; controlling each video processing module to perform data processing on the initial video frame image to obtain a corresponding image receiving timestamp and an image processing ending timestamp; performing overall delay detection on the to-be-tested camera to obtain overall delay information; and displaying. The embodiment can be used for detecting the exposure delay and the video reading delay of the camera, so that the accuracy and the effectiveness of delay detection are improved.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the technical field of testing equipment, and in particular to a camera delay detection method, device, and electronic device. Background Art

[0002] High-speed cameras are very sensitive to time delay. For example, too long a delay may make it difficult for a drone to cross an obstacle in real time; in an automatic aiming system, a delay may make it difficult for the camera to aim at a moving target. Therefore, it is very important to accurately measure and understand the time delay of a high-speed camera so that the camera parameters can be adjusted according to the actual situation to reduce the negative impact of the delay. At present, when testing the camera delay, the usual method is to use the camera to be tested to shoot the time on the display device, and then determine the difference between the time point captured by the camera to be tested and the current time point of the display device as the delay of the camera to be tested; or use the camera to be tested to shoot a marquee, and then determine the delay of the camera to be tested based on the number of illuminated marquees in each frame.

[0003] However, when the above method is used to detect camera delay, the following technical problems often occur:

[0004] First, the detected delay is usually the overall delay, but the overall delay includes the exposure delay and the delay of each video processing module in processing the video data. It is difficult to separate the specific time from the camera collecting signals to each node of the video processing based on the overall delay alone, which makes it difficult to accurately adjust the camera parameters based on the obtained delay information, thereby reducing the accuracy and effectiveness of delay detection;

[0005] Second, the display time of the display device will be affected by other processes of the processor, which may cause time drift, so the jump of the time value may be uneven. In addition, the frame rate of the display or marquee may be different from the frame rate of the camera exposure, which may cause a large error in the detected delay, thereby reducing the accuracy of delay detection.

[0006] The above information disclosed in this Background section is only for enhancement of understanding of the background of the present disclosure concept and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art. Summary of the invention

[0007] The content of this disclosure is used to introduce concepts in a brief form, which will be described in detail in the detailed implementation section below. The content of this disclosure is not intended to identify the key features or essential features of the technical solution claimed for protection, nor is it intended to limit the scope of the technical solution claimed for protection.

[0008] Some embodiments of the present disclosure propose a camera delay detection method, device, and electronic device to solve one or more of the technical problems mentioned in the above background technology section.

[0009] In a first aspect, some embodiments of the present disclosure provide a camera delay detection method, which includes: controlling a camera to be tested to shoot an LED array to obtain an initial video frame image, and transmitting the initial video frame image to a video frame processor, wherein the video frame processor is internally provided with a plurality of video processing modules, including: a video input module, an image signal processing module, a video processing subsystem, a video encoder, and a video output module; according to the exposure state of the camera to be tested, controlling a flash control pin to send an exposure signal, wherein the exposure signal includes a rising edge signal and a falling edge signal; in response to an LED microprocessor receiving the exposure signal, controlling the LED microprocessor to adjust the state of the LEDs in the LED array, wherein the state of the LEDs includes a light-emitting state and an off state; in response to the video frame processor receiving the exposure signal, controlling the video frame processor to adjust the state of the LEDs in the LED array; The timestamps corresponding to the rising edge signal and the falling edge signal received by the processor are respectively determined as the exposure start timestamp and the exposure end timestamp; each video processing module is controlled to perform data processing on the above-mentioned initial video frame image to obtain a video frame image, and obtain the image receiving timestamp and the image processing end timestamp corresponding to the above-mentioned video input module, the above-mentioned image signal processing module, the above-mentioned video processing subsystem, the above-mentioned video encoder and the above-mentioned video output module; according to the above-mentioned exposure start timestamp, the above-mentioned exposure end timestamp, each image receiving timestamp and each image processing end timestamp, an overall delay detection is performed on the camera to be tested to obtain the overall delay information, wherein the above-mentioned overall delay information includes the exposure delay and the video frame reading delay set; the above-mentioned exposure start timestamp, the above-mentioned exposure end timestamp, each image receiving timestamp, each image processing end timestamp, the above-mentioned overall delay information and the above-mentioned video frame image are sent to the display device for display.

[0010] In a second aspect, some embodiments of the present disclosure provide a camera delay detection device, which includes: a shooting unit, configured to control the camera to be tested to shoot an LED array to obtain an initial video frame image, and transmit the initial video frame image to a video frame processor, wherein the video frame processor is internally provided with a plurality of video processing modules, including: a video input module, an image signal processing module, a video processing subsystem, a video encoder, and a video output module; an exposure signal sending unit, configured to control a flash control pin to send an exposure signal according to the exposure state of the camera to be tested, wherein the exposure signal includes a rising edge signal and a falling edge signal; a state adjustment unit, configured to control the LED microprocessor to adjust the state of the LEDs in the LED array in response to the LED microprocessor receiving the exposure signal, wherein the state of the LED includes a light-emitting state and an off state; a determination unit, configured to control the above-mentioned exposure signal to be sent to the flash control pin according to the exposure state of the camera to be tested, wherein the above-mentioned exposure signal includes a rising edge signal and a falling edge signal; The timestamps corresponding to the rising edge signal and the falling edge signal received by the video frame processor are respectively determined as the exposure start timestamp and the exposure end timestamp; the acquisition unit is configured to control each video processing module to perform data processing on the initial video frame image to obtain the video frame image, and to obtain the image receiving timestamp and the image processing end timestamp corresponding to the video input module, the image signal processing module, the video processing subsystem, the video encoder and the video output module; the overall delay detection unit is configured to perform overall delay detection on the camera to be tested according to the exposure start timestamp, the exposure end timestamp, each image receiving timestamp and each image processing end timestamp to obtain the overall delay information, wherein the overall delay information includes the exposure delay and the video frame reading delay set; the display unit is configured to send the exposure start timestamp, the exposure end timestamp, each image receiving timestamp, each image processing end timestamp, the overall delay information and the video frame image to the display device for display.

[0011] In a third aspect, some embodiments of the present disclosure provide an electronic device comprising: one or more processors; a storage device on which one or more programs are stored, and when the one or more programs are executed by the one or more processors, the one or more processors implement the method described in any implementation manner of the above-mentioned first aspect.

[0012] In a fourth aspect, some embodiments of the present disclosure provide a computer-readable medium having a computer program stored thereon, wherein when the program is executed by a processor, the method described in any implementation manner of the above-mentioned first aspect is implemented.

[0013] The above-mentioned various embodiments of the present disclosure have the following beneficial effects: through the camera delay detection method of some embodiments of the present disclosure, the accuracy and effectiveness of delay detection can be improved. Specifically, the reason for the low accuracy and effectiveness of delay detection is that the detected delay is usually an overall delay, but the overall delay includes exposure delay and the delay of each video processing module processing video data. It is difficult to separate the specific time from the camera acquisition signal to each node of the video processing based on the overall delay, resulting in the inability to accurately adjust the camera settings according to the obtained delay information. Based on this, the camera delay detection method of some embodiments of the present disclosure, first, controls the camera to be tested to shoot the above-mentioned light-emitting diode array to obtain the initial video frame image, and transmits the above-mentioned initial video frame image to the above-mentioned video frame processor. Among them, the above-mentioned video frame processor is internally provided with multiple video processing modules, including: video input module, image signal processing module, video processing subsystem, video encoder, video output module. Secondly, according to the exposure state of the above-mentioned camera to be tested, the above-mentioned flash control pin is controlled to send an exposure signal. Among them, the above-mentioned exposure signal includes a rising edge signal and a falling edge signal. Thus, the exposure state of the camera to be tested can be obtained in real time. Then, in response to the light emitting diode microprocessor receiving the exposure signal, the light emitting diode microprocessor is controlled to adjust the state of the light emitting diodes in the light emitting diode array. The state of the light emitting diode includes a light emitting state and an off state. Thus, the state of the light emitting diode can be adjusted in real time according to the exposure frequency of the camera to be tested. Then, in response to the video frame processor receiving the exposure signal, the timestamps corresponding to the rising edge signal and the falling edge signal received by the video frame processor are respectively determined as the exposure start timestamp and the exposure end timestamp. Thus, accurate exposure start time and exposure end time can be obtained. Then, each video processing module is controlled to perform data processing on the initial video frame image to obtain a video frame image, and the image receiving timestamp and the image processing end timestamp corresponding to the video input module, the image signal processing module, the video processing subsystem, the video encoder and the video output module are obtained. Thus, the flow time of each frame of video image data in the entire processing link can be tracked, so that the delay of each processing link can be decomposed, and a basis for delay optimization can be provided. Afterwards, according to the exposure start timestamp, the exposure end timestamp, each image receiving timestamp and each image processing end timestamp, the overall delay detection is performed on the camera to be tested to obtain the overall delay information. The overall delay information includes the exposure delay and the video frame reading delay set. By combining all the timestamp information, the total delay from exposure to image output can be obtained.Finally, the exposure start timestamp, the exposure end timestamp, each image receiving timestamp, each image processing end timestamp, the overall delay information and the video frame image are sent to a display device for display, thereby improving the visualization of the delay detection results and facilitating analysis and adjustment. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. Throughout the accompanying drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic and that components and elements are not necessarily drawn to scale.

[0015] Figure 1 is a structural schematic diagram of a camera delay detection device according to some embodiments of the camera delay detection method disclosed herein;

[0016] Figure 2 is a flow chart of some embodiments of the camera delay detection method according to the present disclosure;

[0017] Figure 3 is a schematic structural diagram of some embodiments of the camera delay detection device according to the present disclosure;

[0018] Figure 4 is a schematic diagram of the structure of an electronic device suitable for implementing some embodiments of the present disclosure;

[0019] Figure 5 Schematic diagram of the structure of some embodiments of the improved phase-locked loop system according to the present disclosure. DETAILED DESCRIPTION

[0020] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are only for exemplary purposes and are not intended to limit the scope of protection of the present disclosure.

[0021] It should also be noted that, for ease of description, only the parts related to the invention are shown in the drawings. In the absence of conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other.

[0022] It should be noted that the concepts such as "first" and "second" mentioned in the present disclosure are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units.

[0023] It should be noted that the modifications of "one" and "plurality" mentioned in the present disclosure are illustrative rather than restrictive, and those skilled in the art should understand that unless otherwise clearly indicated in the context, it should be understood as "one or more".

[0024] The names of the messages or information exchanged between multiple devices in the embodiments of the present disclosure are only used for illustrative purposes and are not used to limit the scope of these messages or information.

[0025] The present disclosure will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.

[0026] Figure 1 A structural schematic diagram 100 of a camera delay detection device according to some embodiments of the camera delay detection method disclosed herein is shown.

[0027] like Figure 1 As shown, the structure 100 of the camera delay detection device may include a light emitting diode array 101, a light emitting diode microprocessor 102, a flash control pin 103, a video frame processor 104, a display device 105, and a camera to be tested 106.

[0028] The camera to be tested 106 is used to shoot a video of the light emitting diode array 101 to obtain initial video data. The camera to be tested 106 includes a lens 1061 and an image sensor 1062. Here, the initial video data is composed of a plurality of initial video frame images. Next, the camera to be tested 106 can transmit the initial video frame images to the video frame processor 104.

[0029] One end of the flash control pin (LED_STROBE) 103 is connected to the circuit of the camera to be tested 106, and the other end is respectively connected to the GPIO (General-Purpose Input / Output) interface of the LED microprocessor 102 and the video frame processor 104. The flash control pin 103 is used to send an exposure signal to the LED microprocessor 102 and the video frame processor 104 according to the exposure state of the camera to be tested 106. The exposure signal includes a rising edge signal and a falling edge signal.

[0030] The LED microprocessor 102 is used to receive the exposure signal and adjust the state of the LEDs in the LED array 101 according to the exposure signal. The state of the LEDs includes a light-emitting state and an off state. The LED microprocessor 102 can be any one of a microcontroller unit (MCU), a single chip microcomputer (Single Chip Microcomputer), and a microprocessor (Micro Processor Unit, MPU).

[0031] In practice, STM32 (STMicroelectronics 32, 32-bit microcontroller) can be selected as the light emitting diode microprocessor 102 .

[0032] The video frame processor 104 is used to receive the above-mentioned exposure signal, and output the exposure start timestamp and exposure end timestamp corresponding to the received rising edge signal and falling edge signal. Secondly, the video frame processor 104 is internally provided with a plurality of video processing modules, including: a video input module (Video In, VI) 1041, an image signal processing module (Image Signal Process, ISP) 1042, a video processing subsystem (Video Process Sub-System, VPSS) 1043, a video encoder (Video Encoder, VENC) 1044, and a video output module (Video Out, VO) 1045. Each of the above-mentioned plurality of video processing modules is used to perform data processing on the above-mentioned initial video frame image to obtain a video frame image. Optionally, the video frame processor 104 also includes an embedded neural network processor 1046 (Neural-network Processing Units, NPU). Among them, the embedded neural network processor 1046 is used to process the received video or image data, and can speed up the speed of the corresponding neural network processing data. The video frame processor 104 is also used to output the image receiving timestamp and image processing end timestamp corresponding to the above-mentioned video input module 1041, the above-mentioned image signal processing module 1042, the above-mentioned video processing subsystem 1043, the above-mentioned video encoder 1044, the above-mentioned video output module 1045 and the embedded neural network processor 1046.

[0033] The video frame processor 104 may be any one of a microcontroller unit (MCU), a single chip microcomputer (Single Chip Microcomputer), and a microprocessor unit (MPU).

[0034] It should be noted that the execution subject of some embodiments of the camera delay detection device according to the present disclosure can be separately set in an electronic device suitable for implementing some embodiments of the present disclosure, or can be configured in the video frame processor 104. The execution subject can be used to control the above-mentioned light-emitting diode array 101, the light-emitting diode microprocessor 102, the flash control pin 103, the video frame processor 104, the display device 105, and the camera to be tested 106. The above-mentioned execution subject can also be used to perform overall delay detection on the camera to be tested according to the above-mentioned exposure start timestamp, the above-mentioned exposure end timestamp, each image receiving timestamp and each image processing end timestamp to obtain the overall delay information. Among them, the above-mentioned overall delay information includes the exposure delay and the video frame reading delay set. Secondly, the above-mentioned execution subject can also be used to send the above-mentioned exposure start timestamp, the above-mentioned exposure end timestamp, each image receiving timestamp, each image processing end timestamp, the above-mentioned overall delay information and the above-mentioned video frame image to the display device 105.

[0035] The display device 105 is used to visualize the exposure start timestamp, the exposure end timestamp, each image receiving timestamp, each image processing end timestamp, the overall delay information and the video frame image.

[0036] Continue to refer Figure 2 , shows a process 200 of some embodiments of the camera delay detection method according to the present disclosure. The camera delay detection method comprises the following steps:

[0037] Step 201 , controlling the camera to be tested to shoot the light emitting diode array to obtain an initial video frame image, and transmitting the initial video frame image to a video frame processor.

[0038] In some embodiments, the execution subject may control the camera to be tested to shoot the light emitting diode array to obtain an initial video frame image, and transmit the initial video frame image to the video frame processor.

[0039] Step 202: According to the exposure state of the camera to be tested, the flash control pin is controlled to send an exposure signal.

[0040] In some embodiments, the execution subject can control the flash control pin to send an exposure signal according to the exposure state of the camera to be tested, wherein one end of the flash control pin is connected to the camera to be tested, and the other end is respectively connected to the light emitting diode microprocessor and the video frame processor.

[0041] In some optional implementations of some embodiments, the execution subject controls the flash control pin to send an exposure signal according to the exposure state of the camera to be tested, which may include the following steps:

[0042] In the first step, in response to the camera to be tested being in an exposure state, the flash control pin is set to a high level.

[0043] In the second step, in response to the camera to be tested being in a non-exposed state, the flash control pin is set to a low level.

[0044] In the third step, the rising edge signal generated by the high level or the falling edge signal generated by the low level is determined as an exposure signal, and the exposure signal is sent through the flash control pin.

[0045] In practice, an electronic wire of the same length is used to connect the other end of the flash control pin to the light emitting diode microprocessor and the video frame processor, respectively, wherein the propagation time of the exposure signal in the electronic wire can be ignored.

[0046] Step 203 , in response to the LED microprocessor receiving the exposure signal, controlling the LED microprocessor to adjust the states of the LEDs in the LED array.

[0047] In some embodiments, the execution subject may control the LED microprocessor to adjust the state of the LEDs in the LED array in response to the LED microprocessor receiving the exposure signal, wherein the state of the LEDs includes a light-emitting state and an off state.

[0048] In some optional implementations of some embodiments, the execution subject controls the LED microprocessor to adjust the state of the LEDs in the LED array in response to the LED microprocessor receiving the exposure signal, which may include the following steps:

[0049] The first step is to obtain the frame number corresponding to the initial video frame image, wherein the frame number indicates the position of the initial video frame image in the video frame sequence corresponding to the initial video data.

[0050] In practice, the frame number corresponding to the current initial video frame image can be determined by counting the received rising edge signals.

[0051] The second step is to control the LED microprocessor to adjust the LED corresponding to the frame number in the LED array to a light-emitting state in response to the LED microprocessor receiving the rising edge signal. If the LED microprocessor receives the rising edge signal, the frame number is compared with the number of LEDs in the LED array. Afterwards, if the frame number is less than or equal to the number of LEDs in the LED array, the LED corresponding to the frame number in the LED array can be determined as the target LED. Secondly, if the frame number is greater than the number of LEDs, the remainder between the frame number and the LED can be determined. Afterwards, the LED corresponding to the remainder in the LED array can be determined as the target LED. Finally, the LED microprocessor is controlled to adjust the target LED to a light-emitting state.

[0052] The third step is to control the LED microprocessor to adjust the LED corresponding to the frame number in the LED array to an off state in response to the LED microprocessor receiving the falling edge signal. If the LED microprocessor receives the falling edge signal, the LED microprocessor can be controlled to adjust the target LED to an off state.

[0053] Step 204 , in response to the video frame processor receiving the exposure signal, the timestamps corresponding to the rising edge signal and the falling edge signal received by the video frame processor are respectively determined as the exposure start timestamp and the exposure end timestamp.

[0054] In some embodiments, the execution subject may determine the timestamps corresponding to the rising edge signal and the falling edge signal received by the video frame processor as the exposure start timestamp and the exposure end timestamp, respectively, in response to the video frame processor receiving the exposure signal. If the video frame processor receives the exposure signal, the current timestamp may be determined by the real-time clock (RTC) of the video frame processor. Afterwards, the timestamps corresponding to the rising edge signal and the falling edge signal received may be determined as the exposure start timestamp and the exposure end timestamp, respectively.

[0055] Optionally, the video frame processor may include a temperature compensated crystal oscillator (TCXO) and an improved phase-locked loop system ( Figure 1 Here, the temperature compensated crystal oscillator and the improved phase-locked loop system can be configured to Figure 1The temperature-compensated crystal oscillator can be connected to the external high-speed crystal oscillator pin of the video frame processor as a high-speed external clock source, such as the OSC_IN pin. The improved phase-locked loop system is an improved phase-locked loop (PLL) system. Here, the input source of the improved phase-locked loop system can be selected as the output of the temperature-compensated crystal oscillator. Secondly, the improved phase-locked loop system includes an improved phase detector, a low-pass filter, a voltage-controlled oscillator and a feedback loop, such as Figure 5 shown.

[0056] Specifically, the video frame processor determines the timestamp by the following steps:

[0057] The first step is to obtain the reference clock signal output by the temperature compensated crystal oscillator. The clock signal is a level signal that changes periodically at a fixed frequency. Here, the level signal includes a high level signal and a low level signal.

[0058] The second step is to control the improved phase detector to compare the phase difference between the reference clock signal and the initial clock signal to obtain a first phase difference pulse. First, the reference clock signal can be input into the delay circuit to obtain a delayed reference clock signal. After that, the reference clock signal and the delayed reference clock signal can be logically ANDed to obtain a narrow pulse signal. Secondly, the narrow pulse signal can be input into the delay circuit to obtain a delayed narrow pulse signal. Then, the delayed narrow pulse signal and the narrow pulse signal can be logically ANDed and negated (NOT) to obtain a wide pulse signal. Finally, the wide pulse signal and the initial pulse signal can be input into the phase detector (PD) to compare the phase difference to obtain a first phase difference pulse. Here, the initial clock signal is the initial signal output by the voltage-controlled oscillator. Secondly, the first phase difference pulse is a level signal that changes periodically at a fixed frequency, and the phase difference values ​​of different clock signals are characterized by pulse width. The improved phase detector is an improved phase detector, which first performs pulse width expansion on the input reference clock signal and then inputs the phase detector.

[0059] As an example, the delay circuit includes but is not limited to at least one of the following: a precise long delay circuit, an RC (ResistorCapacitor) delay circuit, a monostable delay circuit composed of a single operational amplifier, and a transistor delay circuit.

[0060] In practice, the improved phase detector eliminates the phase difference detection distortion that may be caused by the delay in the logic elements and feedback loop by increasing the pulse width of the reference clock signal. This method compensates for the influence of the internal delay of the system by adjusting the pulse width of the signal, thereby improving the accuracy of the phase difference comparison.

[0061] The third step is to input the first phase difference pulse into the low-pass filter to generate a smooth DC voltage. The first phase difference pulse can be input into a low-pass filter (Loop Filter, LF) to obtain a smooth DC voltage.

[0062] In practice, the first phase difference pulse is a pulse signal in the form of a rectangular wave, and there is a sudden change between the high level and the low level, so the pulse signal can be smoothed by a low-pass filter.

[0063] The fourth step is to control the voltage controlled oscillator by the smooth DC voltage to obtain an adjusted clock signal. The smooth DC voltage can control the voltage controlled oscillator (VCO) to obtain an adjusted clock signal.

[0064] The fifth step is to input the adjusted clock signal into the improved phase detector through the feedback loop to obtain a second phase difference pulse. The feedback loop can connect the output signal of the voltage-controlled oscillator to the input of the improved phase detector. Here, the improved phase detector can compare the phase difference between the adjusted clock signal and the reference clock signal to obtain a second phase difference pulse.

[0065] In step 6, in response to the pulse width of the second phase difference pulse being zero, the adjusted clock signal is determined as the target clock signal. The pulse width of the second phase difference pulse is zero, that is, the phase difference between the adjusted clock signal output by the voltage-controlled oscillator and the reference clock signal is zero, which can represent the phase alignment between the adjusted clock signal and the reference clock signal.

[0066] Step 7: Determine the current timestamp of the video frame processor according to the target clock signal. The count value can be obtained by counting each clock cycle of the target clock signal. Then, the current timestamp of the video frame processor can be determined according to the frequency of the target clock signal and the count value.

[0067] For example, if the frequency of the target clock signal is 1 MHz, when the count value increases by 1000000, it means that the current timestamp changes by 1 second.

[0068] The above steps 202-204 and their related contents, as an inventive point of an embodiment of the present disclosure, solve the technical problem "reduced accuracy of delay detection" mentioned in the background technology. The factors that lead to low accuracy of delay detection are often as follows: the display time of the display device will be affected by other processes of the processor, which may cause time drift, so the jump of the time value may be uneven. In addition, the frame rate of the display or the ticker may be different from the frame rate of the camera exposure, which may cause a large error in the detected delay. If the above factors are solved, the large error in delay detection can be alleviated, thereby improving the accuracy of camera delay detection. In order to achieve this effect, first, an exposure signal is sent to the light-emitting diode microprocessor through the flash control pin to ensure that the on and off of the light-emitting diode array is synchronized with the exposure cycle of the camera to be tested in the frame rate and aligned with the phase. Therefore, the delay detection error caused by the mismatch of the frame rate between the photographed medium and the shooting camera can be avoided. At the same time, the exposure signal is sent to the video frame processor to obtain accurate exposure start time and exposure end time. Secondly, by configuring a temperature-compensated crystal oscillator as an external clock source of the video frame processor, a highly stable clock signal can be provided for the video frame processor. Compared with internal oscillators or other types of crystal oscillators, temperature-compensated crystal oscillators have higher accuracy, and their output signals are less susceptible to changes in ambient temperature, so they can maintain a more constant frequency output. In addition, the use of an improved phase-locked loop system can further reduce the inherent jitter of the clock signal, enhance the stability of the clock signal, reduce phase noise, and improve the anti-interference ability of the clock signal. Therefore, the video frame processor can obtain an accurate timestamp based on a more accurate clock signal, thereby reducing errors in delay detection and ultimately improving the accuracy of delay detection.

[0069] Step 205, control each video processing module to perform data processing on the initial video frame image to obtain a video frame image, and obtain the image receiving timestamp and image processing end timestamp corresponding to the video input module, image signal processing module, video processing subsystem, video encoder and video output module.

[0070] In some embodiments, the above-mentioned execution entity can control each video processing module to perform data processing on the above-mentioned initial video frame image to obtain a video frame image, and obtain the image receiving timestamp and image processing end timestamp corresponding to the above-mentioned video input module, the above-mentioned image signal processing module, the above-mentioned video processing subsystem, the above-mentioned video encoder and the above-mentioned video output module.

[0071] In some optional implementations of some embodiments, the execution subject controls each video processing module to perform data processing on the initial video frame image to obtain a video frame image, and obtains an image receiving timestamp and an image processing end timestamp corresponding to the video input module, the image signal processing module, the video processing subsystem, the video encoder, and the video output module, which may include the following steps:

[0072] The first step is to control the video input module to parse the initial video frame image, obtain the parsed video frame image, and obtain the corresponding image receiving timestamp. Among them, the MIPI (Mobile Industry Processor Interface) transmission protocol can be used between the video input module and the image sensor of the camera to be tested. First, the video input module parses the MIPI transmission content, and when it starts to parse the information of the initial video frame image, it outputs the corresponding interrupt signal. Finally, according to the time point when the above interrupt signal is output, the timestamp of the current video frame processor is obtained as the image receiving timestamp corresponding to the video input module.

[0073] The second step is to control the image signal processing module to perform signal processing on the parsed video frame image to obtain a signal-processed video frame image and obtain a corresponding image receiving timestamp. The image signal processing module can process the raw format parsed video frame image data output by the image sensor into a signal-processed video frame image in yuv format. Secondly, the image receiving timestamp corresponding to the image signal processing module can be obtained by the timestamp determination method.

[0074] The third step is to control the video processing subsystem to perform video frame preprocessing on the signal processing video frame image to obtain the preprocessed video frame image and obtain the corresponding image receiving timestamp. Among them, through the video processing subsystem, the signal processing video frame image can be cropped, denoised, fisheye corrected and other operations can be performed to obtain the preprocessed video frame image. Secondly, the image receiving timestamp corresponding to the video processing subsystem can be obtained through the timestamp determination method.

[0075] The fourth step is to control the video encoder to encode the preprocessed video frame image to obtain the encoded video frame image and obtain the corresponding image receiving timestamp. The preprocessed video frame image can be encoded by the video encoder to obtain the encoded video frame image. Secondly, the image receiving timestamp corresponding to the video encoder can be obtained by the timestamp determination method.

[0076] Step 5: Determine the timestamp of the video encoder outputting the encoded video frame image as the corresponding image processing end timestamp. After the video encoder completes encoding the pre-processed video frame image, it outputs a corresponding interrupt signal. Afterwards, the timestamp of the current video frame processor can be obtained according to the time point when the interrupt signal is output as the image processing end timestamp corresponding to the video encoder.

[0077] Step 6: Control the video output module to perform video output processing on the preprocessed video frame image to obtain a video frame image and obtain a corresponding image receiving timestamp. The video output module can perform video output processing on the preprocessed video frame image to obtain a video frame image. Secondly, the image receiving timestamp corresponding to the video output module can be obtained by the timestamp determination method.

[0078] Step 7: Determine the timestamp corresponding to the video frame image output by the video output module as the corresponding image processing end timestamp. After the video output module completes the processing of the pre-processed video frame image, it outputs the corresponding interrupt signal. Afterwards, the timestamp of the current video frame processor can be obtained according to the time point when the interrupt signal is output as the image processing end timestamp corresponding to the video output module.

[0079] Optionally, the embedded neural network processor may be controlled to perform neural network processing on the preprocessed video frame image, and an image receiving timestamp corresponding to the embedded neural network processor may be obtained.

[0080] Step 206 , performing overall delay detection on the camera to be tested according to the exposure start timestamp, the exposure end timestamp, each image receiving timestamp and each image processing end timestamp to obtain overall delay information.

[0081] In some embodiments, the execution subject may perform overall delay detection on the camera to be tested according to the exposure start timestamp, the exposure end timestamp, each image receiving timestamp, and each image processing end timestamp to obtain overall delay information, wherein the overall delay information includes exposure delay and video frame reading delay set.

[0082] In some optional implementations of some embodiments, the execution subject performs overall delay detection on the camera to be tested according to the exposure start timestamp, the exposure end timestamp, each image receiving timestamp, and each image processing end timestamp to obtain overall delay information, which may include the following steps:

[0083] In the first step, the delay time period between the exposure start timestamp and the exposure end timestamp is determined as the exposure delay. The difference between the exposure start timestamp and the exposure end timestamp can be determined as the delay time period. Secondly, the delay time period is determined as the exposure delay of the camera to be tested.

[0084] In the second step, the delay time period between the image processing end timestamp corresponding to the above-mentioned video encoder and the above-mentioned video output module and the above-mentioned exposure end timestamp is respectively determined as the video frame reading delay, and a video frame reading delay set is obtained. Among them, the time period between the image processing end timestamp corresponding to the video encoder and the exposure end timestamp can be determined as the video frame encoding delay. Here, the above-mentioned video frame encoding delay represents the time period from the image sensor of the camera to be tested completing data acquisition to the video encoder completing encoding. Secondly, the time period between the image processing end timestamp corresponding to the video output module and the exposure end timestamp can be determined as the video frame readout delay. Here, the above-mentioned video frame readout delay represents the time period from the image sensor completing image acquisition to the video output module completing video output. Finally, the above-mentioned video frame encoding delay and the above-mentioned video frame readout delay are respectively used as the video frame reading delay to obtain a video frame reading delay set.

[0085] In the third step, the exposure delay and the video frame reading delay set are determined as the overall delay information.

[0086] Optionally, the overall delay information also includes a video frame reception delay set. The time period between the image reception timestamp and the exposure end timestamp corresponding to the video input module, the image signal processing module, the video processing subsystem, the video encoder, the video output module, and the embedded neural network processor can be respectively determined as the video frame reception delay to obtain the video frame reception delay set. Here, the above-mentioned video frame reception delay represents the time period from the completion of data acquisition by the image sensor to the arrival of the data at each video processing module.

[0087] Step 207 , sending the exposure start timestamp, the exposure end timestamp, each image receiving timestamp, each image processing end timestamp, the overall delay information and the video frame image to a display device for display.

[0088] In some embodiments, the execution entity may send the exposure start timestamp, the exposure end timestamp, each image reception timestamp, each image processing end timestamp, the overall delay information and the video frame image to a display device for display.

[0089] In some optional implementations of some embodiments, the execution subject sends the exposure start timestamp, the exposure end timestamp, each image reception timestamp, each image processing end timestamp, the overall delay information and the video frame image to a display device for display, which may include the following steps:

[0090] The first step is to obtain the frame number corresponding to the above video frame image. The frame number corresponding to the above video frame image can be obtained by counting the received rising edge signals through the above video frame processor.

[0091] In the second step, the video frame image is marked according to the frame number, the exposure start timestamp, the exposure end timestamp, the image receiving timestamp, the image processing end timestamp and the overall delay information to obtain an image containing delay information. The frame number, the exposure start timestamp, the exposure end timestamp, the image receiving timestamp, the image processing end timestamp and the overall delay information can be superimposed on the video frame image through OSD (On-Screen Display) technology to obtain an image containing delay information.

[0092] The third step is to send the above-mentioned image containing delay information to the above-mentioned display device for display.

[0093] In practice, if the light emitting diode corresponding to the frame number in the image is in a light emitting state, the above overall delay information is valid. Otherwise, the above steps 201-207 are executed again.

[0094] The above-mentioned various embodiments of the present disclosure have the following beneficial effects: through the camera delay detection method of some embodiments of the present disclosure, the accuracy and effectiveness of delay detection can be improved. Specifically, the reason for the low accuracy and effectiveness of delay detection is that the detected delay is usually an overall delay, but the overall delay includes exposure delay and the delay of each video processing module processing video data. It is difficult to separate the specific time from the camera acquisition signal to each node of the video processing based on the overall delay, resulting in the inability to accurately adjust the camera settings according to the obtained delay information. Based on this, the camera delay detection method of some embodiments of the present disclosure, first, controls the camera to be tested to shoot the above-mentioned light-emitting diode array to obtain the initial video frame image, and transmits the above-mentioned initial video frame image to the above-mentioned video frame processor. Among them, the above-mentioned video frame processor is internally provided with multiple video processing modules, including: video input module, image signal processing module, video processing subsystem, video encoder, video output module. Secondly, according to the exposure state of the above-mentioned camera to be tested, the above-mentioned flash control pin is controlled to send an exposure signal. Among them, the above-mentioned exposure signal includes a rising edge signal and a falling edge signal. Thus, the exposure state of the camera to be tested can be obtained in real time. Then, in response to the light emitting diode microprocessor receiving the exposure signal, the light emitting diode microprocessor is controlled to adjust the state of the light emitting diodes in the light emitting diode array. The state of the light emitting diode includes a light emitting state and an off state. Thus, the state of the light emitting diode can be adjusted in real time according to the exposure frequency of the camera to be tested. Then, in response to the video frame processor receiving the exposure signal, the timestamps corresponding to the rising edge signal and the falling edge signal received by the video frame processor are respectively determined as the exposure start timestamp and the exposure end timestamp. Thus, accurate exposure start time and exposure end time can be obtained. Then, each video processing module is controlled to perform data processing on the initial video frame image to obtain a video frame image, and the image receiving timestamp and the image processing end timestamp corresponding to the video input module, the image signal processing module, the video processing subsystem, the video encoder and the video output module are obtained. Thus, the flow time of each frame of video image data in the entire processing link can be tracked, so that the delay of each processing link can be decomposed, and a basis for delay optimization can be provided. Afterwards, according to the exposure start timestamp, the exposure end timestamp, each image receiving timestamp and each image processing end timestamp, the overall delay detection is performed on the camera to be tested to obtain the overall delay information. The overall delay information includes the exposure delay and the video frame reading delay set. By combining all the timestamp information, the total delay from exposure to image output can be obtained.Finally, the exposure start timestamp, the exposure end timestamp, each image receiving timestamp, each image processing end timestamp, the overall delay information and the video frame image are sent to a display device for display, thereby improving the visualization of the delay detection results and facilitating analysis and adjustment.

[0095] Further references Figure 3 As an implementation of the methods shown in the above figures, the present disclosure provides some embodiments of a camera delay detection device. These device embodiments are similar to Figure 2 Corresponding to the method embodiments shown, the device can be specifically applied to various electronic devices.

[0096] like Figure 3As shown, the camera delay detection device 300 of some embodiments includes: a shooting unit 301, an exposure signal sending unit 302, a state adjustment unit 303, a determination unit 304, an acquisition unit 305, an overall delay detection unit 306, and a display unit 307. Among them, the shooting unit 301 is configured to control the camera to be tested to shoot the light-emitting diode array, obtain an initial video frame image, and transmit the above-mentioned initial video frame image to the video frame processor, wherein the above-mentioned video frame processor is internally provided with multiple video processing modules, including: a video input module, an image signal processing module, a video processing subsystem, a video encoder, and a video output module; the exposure signal sending unit 302 is configured to control the flash control pin to send an exposure signal according to the exposure state of the above-mentioned camera to be tested, wherein the above-mentioned exposure signal includes a rising edge signal and a falling edge signal; the state adjustment unit 303 is configured to control the above-mentioned light-emitting diode microprocessor to adjust the state of the light-emitting diodes in the above-mentioned light-emitting diode array in response to the light-emitting diode microprocessor receiving the above-mentioned exposure signal, wherein the state of the above-mentioned light-emitting diode includes a light-emitting state and an off state; the determination unit 304 is configured to control the above-mentioned video frame processor to receive the above-mentioned exposure signal. The timestamps corresponding to the rising edge signal and the falling edge signal are respectively determined as the exposure start timestamp and the exposure end timestamp; the acquisition unit 305 is configured to control each video processing module to perform data processing on the initial video frame image to obtain the video frame image, and to obtain the image receiving timestamp and the image processing end timestamp corresponding to the video input module, the image signal processing module, the video processing subsystem, the video encoder and the video output module; the overall delay detection unit 306 is configured to perform overall delay detection on the camera to be tested according to the exposure start timestamp, the exposure end timestamp, each image receiving timestamp and each image processing end timestamp to obtain the overall delay information, wherein the overall delay information includes the exposure delay and the video frame reading delay set; the display unit 307 is configured to send the exposure start timestamp, the exposure end timestamp, each image receiving timestamp, each image processing end timestamp, the overall delay information and the video frame image to the display device for display.

[0097] It is understood that the units described in the device 300 are similar to those described in the reference Figure 2 Therefore, the operations, features and beneficial effects described above for the method are also applicable to the device 300 and the units contained therein, and will not be described in detail here.

[0098] Reference below Figure 4, which shows a structural schematic diagram of an electronic device (eg, a computing device) 400 suitable for implementing some embodiments of the present disclosure. Figure 4 The electronic device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0099] like Figure 4 As shown, the electronic device 400 may include a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 401, which can perform various appropriate actions and processes according to a program stored in a read-only memory 402 or a program loaded from a storage device 408 into a random access memory 403. Various programs and data required for the operation of the electronic device 400 are also stored in the random access memory 403. The processing device 401, the read-only memory 402, and the random access memory 403 are connected to each other via a bus 404. An input / output interface 405 is also connected to the bus 404.

[0100] Typically, the following devices may be connected to the I / O interface 405: input devices 306 including, for example, a touch screen, a touch pad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; output devices 407 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; storage devices 408 including, for example, a magnetic tape, a hard disk, etc.; and communication devices 409. The communication devices 409 may allow the electronic device 400 to communicate with other devices wirelessly or by wire to exchange data. Although Figure 4 The electronic device 400 is shown with various devices, but it should be understood that it is not required to implement or possess all the devices shown. More or fewer devices may be implemented or possessed instead. Figure 4 Each block shown in the figure may represent one device, or may represent multiple devices as required.

[0101] In particular, according to some embodiments of the present disclosure, the process described above with reference to the flowchart can be implemented as a computer software program. For example, some embodiments of the present disclosure include a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a program code for executing the method shown in the flowchart. In some such embodiments, the computer program can be downloaded and installed from the network through the communication device 409, or installed from the storage device 408, or installed from the read-only memory 402. When the computer program is executed by the processing device 401, the above-mentioned functions defined in the method of some embodiments of the present disclosure are executed.

[0102] It should be noted that the computer-readable medium recorded in some embodiments of the present disclosure may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In some embodiments of the present disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in combination with an instruction execution system, device or device. In some embodiments of the present disclosure, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries a computer-readable program code. This propagated data signal may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. The computer readable signal medium may also be any computer readable medium other than a computer readable storage medium, which may send, propagate or transmit a program for use by or in conjunction with an instruction execution system, apparatus or device. The program code contained on the computer readable medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.

[0103] In some embodiments, the client and the server may communicate using any currently known or future developed network protocol such as HTTP (Hyper Text Transfer Protocol), and may be interconnected with any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network ("LAN"), a wide area network ("WAN"), an internet (e.g., the Internet), and a peer-to-peer network (e.g., an ad hoc peer-to-peer network), as well as any currently known or future developed network.

[0104] The computer-readable medium may be included in the electronic device; or it may exist independently without being assembled into the electronic device. The computer-readable medium carries one or more programs. When the one or more programs are executed by the electronic device, the electronic device: controls the camera to be tested to shoot the light-emitting diode array to obtain an initial video frame image, and transmits the initial video frame image to the video frame processor, wherein the video frame processor is internally provided with a plurality of video processing modules, including: a video input module, an image signal processing module, a video processing subsystem, a video encoder, and a video output module; controls the flash control pin to send an exposure signal according to the exposure state of the camera to be tested, wherein the exposure signal includes a rising edge signal and a falling edge signal; controls the light-emitting diode microprocessor to adjust the state of the light-emitting diodes in the light-emitting diode array in response to the light-emitting diode microprocessor receiving the exposure signal, wherein the state of the light-emitting diode includes a light-emitting state and an off state; controls the video frame processor to receive the exposure signal; exposure signal, determining the timestamps corresponding to the rising edge signal and the falling edge signal received by the video frame processor as the exposure start timestamp and the exposure end timestamp respectively; controlling each video processing module to perform data processing on the initial video frame image to obtain a video frame image, and obtaining the image receiving timestamp and the image processing end timestamp corresponding to the video input module, the image signal processing module, the video processing subsystem, the video encoder and the video output module; performing overall delay detection on the camera to be tested according to the exposure start timestamp, the exposure end timestamp, each image receiving timestamp and each image processing end timestamp to obtain overall delay information, wherein the overall delay information includes an exposure delay and a video frame reading delay set; sending the exposure start timestamp, the exposure end timestamp, each image receiving timestamp, each image processing end timestamp, the overall delay information and the video frame image to a display device for display.

[0105] Computer program code for performing the operations of some embodiments of the present disclosure may be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0106] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some implementations as replacements, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0107] The units described in some embodiments of the present disclosure may be implemented by software or by hardware. The described units may also be provided in a processor, for example, may be described as: a processor including a shooting unit, an exposure signal sending unit, a state adjustment unit, a determination unit, an acquisition unit, an overall delay detection unit, and a display unit. The names of these units do not, in some cases, constitute limitations on the units themselves, for example, the state adjustment unit may also be described as a "unit for adjusting the state of a light-emitting diode".

[0108] The functions described above herein may be performed at least in part by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), and the like.

[0109] The above descriptions are only some preferred embodiments of the present disclosure and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the embodiments of the present disclosure is not limited to the technical solutions formed by a specific combination of the above-mentioned technical features, but should also cover other technical solutions formed by any combination of the above-mentioned technical features or their equivalent features without departing from the above-mentioned inventive concept. For example, the above-mentioned features are replaced with the technical features with similar functions disclosed in the embodiments of the present disclosure (but not limited to) and the technical solutions formed.

Claims

1. A camera delay detection method, used for a camera delay detection device, wherein: The camera delay detection device comprises: a light emitting diode array, a light emitting diode microprocessor, a flash control pin, a video frame processor and a display device, including: Control the camera to be tested to shoot the light-emitting diode array to obtain an initial video frame image, and transmit the initial video frame image to the video frame processor, wherein the video frame processor is internally provided with a plurality of video processing modules, including: a video input module, an image signal processing module, a video processing subsystem, a video encoder, and a video output module; According to the exposure state of the camera to be tested, controlling the flash control pin to send an exposure signal, wherein the exposure signal includes a rising edge signal and a falling edge signal; In response to the light emitting diode microprocessor receiving the exposure signal, controlling the light emitting diode microprocessor to adjust the state of the light emitting diodes in the light emitting diode array, wherein the state of the light emitting diodes includes a light emitting state and an extinguishing state; In response to the video frame processor receiving the exposure signal, determining timestamps corresponding to the rising edge signal and the falling edge signal received by the video frame processor as exposure start timestamps and exposure end timestamps respectively; Controlling each video processing module to perform data processing on the initial video frame image to obtain a video frame image, and obtaining an image receiving timestamp and an image processing end timestamp corresponding to the video input module, the image signal processing module, the video processing subsystem, the video encoder, and the video output module; According to the exposure start timestamp, the exposure end timestamp, each image receiving timestamp and each image processing end timestamp, an overall delay detection is performed on the camera to be tested to obtain overall delay information, wherein the overall delay information includes an exposure delay and a video frame reading delay set; The exposure start timestamp, the exposure end timestamp, each image receiving timestamp, each image processing end timestamp, the overall delay information and the video frame image are sent to the display device for display.

2. The method according to claim 1, wherein: One end of the flash control pin is connected to the camera circuit to be tested, and the other end is connected to the light emitting diode microprocessor and the video frame processor respectively; as well as The step of controlling the flash control pin to send an exposure signal according to the exposure state of the camera to be tested comprises: In response to the camera to be tested being in an exposure state, setting the flash control pin to a high level; In response to the camera to be tested being in a non-exposed state, setting the flash control pin to a low level; The rising edge signal generated by the high level or the falling edge signal generated by the low level is determined as an exposure signal, and the exposure signal is sent through the flash control pin.

3. The method according to claim 1, wherein: In response to the light emitting diode microprocessor receiving the exposure signal, controlling the light emitting diode microprocessor to adjust the state of the light emitting diodes in the light emitting diode array includes: Obtaining a frame sequence number corresponding to the initial video frame image; In response to the light emitting diode microprocessor receiving the rising edge signal, controlling the light emitting diode microprocessor to adjust the light emitting diode corresponding to the frame sequence number in the light emitting diode array to a light emitting state; In response to the LED microprocessor receiving the falling edge signal, the LED microprocessor is controlled to adjust the LED corresponding to the frame number in the LED array to an off state.

4. The method according to claim 1, wherein: The controlling each video processing module to perform data processing on the initial video frame image to obtain a video frame image, and obtaining an image receiving timestamp and an image processing end timestamp corresponding to the video input module, the image signal processing module, the video processing subsystem, the video encoder, and the video output module, includes: Controlling the video input module to parse the initial video frame image to obtain a parsed video frame image, and acquiring a corresponding image receiving timestamp; Controlling the image signal processing module to perform signal processing on the parsed video frame image to obtain a signal-processed video frame image, and acquiring a corresponding image receiving timestamp; Controlling the video processing subsystem to perform video frame preprocessing on the signal processing video frame image to obtain a preprocessed video frame image, and acquiring a corresponding image receiving timestamp; Controlling the video encoder to encode the preprocessed video frame image to obtain an encoded video frame image, and obtaining a corresponding image receiving timestamp; Determine the timestamp of the video encoder outputting the encoded video frame image as the corresponding image processing end timestamp; Controlling the video output module to perform video output processing on the preprocessed video frame image to obtain a video frame image and obtain a corresponding image receiving timestamp; The timestamp corresponding to the video frame image output by the video output module is determined as the corresponding image processing end timestamp.

5. The method according to claim 1, wherein: The overall delay detection is performed on the camera to be tested according to the exposure start timestamp, the exposure end timestamp, each image receiving timestamp and each image processing end timestamp to obtain the overall delay information, including: Determine a delay period between the exposure start timestamp and the exposure end timestamp as an exposure delay; Determine the delay time period between the image processing end timestamp corresponding to the video encoder and the video output module and the exposure end timestamp as the video frame reading delay respectively, and obtain a video frame reading delay set; The exposure delay and the video frame reading delay set are determined as overall delay information.

6. The method according to claim 1, wherein: The step of sending the exposure start timestamp, the exposure end timestamp, each image receiving timestamp, each image processing end timestamp, the overall delay information and the video frame image to the display device for display includes: Obtaining a frame number corresponding to the video frame image; Mark the video frame image according to the frame sequence number, the exposure start timestamp, the exposure end timestamp, each image receiving timestamp, each image processing end timestamp and the overall delay information to obtain an image containing delay information; The image containing the time delay information is sent to the display device for display.

7. A camera delay detection device, comprising: A shooting unit is configured to control the camera to be tested to shoot the light-emitting diode array, obtain an initial video frame image, and transmit the initial video frame image to a video frame processor, wherein the video frame processor is internally provided with a plurality of video processing modules, including: a video input module, an image signal processing module, a video processing subsystem, a video encoder, and a video output module; An exposure signal sending unit is configured to control the flash control pin to send an exposure signal according to the exposure state of the camera to be tested, wherein the exposure signal includes a rising edge signal and a falling edge signal; a state adjustment unit, configured to control the LED microprocessor to adjust the state of the LEDs in the LED array in response to the LED microprocessor receiving the exposure signal, wherein the state of the LEDs includes a light-emitting state and an extinguished state; a determining unit configured to determine, in response to the video frame processor receiving the exposure signal, timestamps corresponding to the rising edge signal and the falling edge signal received by the video frame processor as exposure start timestamps and exposure end timestamps, respectively; an acquisition unit, configured to control each video processing module to perform data processing on the initial video frame image to obtain a video frame image, and to acquire an image receiving timestamp and an image processing end timestamp corresponding to the video input module, the image signal processing module, the video processing subsystem, the video encoder, and the video output module; an overall delay detection unit, configured to perform overall delay detection on the camera to be tested according to the exposure start timestamp, the exposure end timestamp, each image receiving timestamp and each image processing end timestamp, to obtain overall delay information, wherein the overall delay information includes an exposure delay and a video frame reading delay set; The display unit is configured to send the exposure start timestamp, the exposure end timestamp, each image reception timestamp, each image processing end timestamp, the overall delay information and the video frame image to a display device for display.

8. An electronic device comprising: one or more processors; a storage device having one or more programs stored thereon; When the one or more programs are executed by the one or more processors, the one or more processors implement the method according to any one of claims 1 to 6.

9. A computer readable medium having a computer program stored thereon, wherein: When the program is executed by a processor, the method according to any one of claims 1 to 6 is implemented.

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