Image sensor and control method

Abstract

The invention provides an image sensor and a control method. The image sensor comprises a signal generation unit, a cache unit, a storage unit and a signal output unit, the signal generation unit generates a low-gain image signal, a high-gain reset signal, and a high-gain image signal based on different conversion gain modes. The cache unit is coupled with the signal generation unit and is at least used for caching the low-gain image signal; the storage unit is coupled with the signal generation unit and the cache unit and is used for storing a low-gain image signal, a high-gain reset signal and a high-gain image signal, the low-gain image signal is provided by the cache unit, and other signals are provided by the signal generation unit; the signal output unit is coupled with the storage unit and used for outputting the low-gain image signal, the high-gain reset signal and the high-gain image signal. According to the image sensor and the control method provided by the invention, the problem of high circuit design difficulty caused by the fact that excessive storage parts occupy a large amount of pixel space in an existing image sensor is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of image sensors, and in particular to an image sensor and a control method thereof. Background Art

[0002] According to actual application requirements, some image sensors require dual gain conversion to quantize image signals separately, and use conversions with different gains to compensate each other to obtain images with a higher dynamic range.

[0003] To achieve this effect, the pixel needs to perform high gain conversion and low gain conversion on the photodiode respectively during quantization; and, in order to achieve a better mutual compensation effect, there should be no actual signal loss between the two gain conversions. At the same time, since the noise reduction function of correlated double sampling is required when reading pixels, in order to achieve mutual compensation of different gain conversions, the signal quantization order is usually LCG_RST (reset signal for low gain conversion), HCG_RST (reset signal for high gain conversion), HCG_SIG (image signal for high gain conversion), LCG_SIG (image signal for low gain conversion); among which LCG_RST and LCG_SIG are actually incomplete correlated double sampling.

[0004] In conventional rolling shutter exposure image sensors, LCG_RST can be temporarily stored through the design of the back-end circuit to complete the subsequent incomplete correlated double sampling with LCG_SIG. However, in global exposure image sensors, the signal storage part is set in the pixel, which requires the global exposure sensor pixel to have multiple storage parts (usually ≥4), which greatly occupies the pixel space and increases the design difficulty. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide an image sensor and a control method for solving the problem that the circuit design of the prior image sensor is difficult due to too many storage units occupying a large amount of pixel space.

[0006] To achieve the above-mentioned object and other related objects, the present invention provides an image sensor, comprising: a signal generating unit, a buffer unit, a storage unit and a signal output unit; wherein:

[0007] The signal generating unit generates a low gain image signal, a high gain reset signal and a high gain image signal based on different conversion gain modes;

[0008] The buffer unit is coupled to the signal generating unit and is at least used to buffer the low-gain image signal;

[0009] The storage unit is coupled to the signal generating unit and the buffer unit, and is used to store the low-gain image signal, the high-gain reset signal, and the high-gain image signal; wherein the low-gain image signal is provided by the buffer unit, and the remaining signals are provided by the signal generating unit;

[0010] The signal output unit is coupled to the storage unit, and is configured to output the low-gain image signal, the high-gain reset signal, and the high-gain image signal.

[0011] Optionally, the signal generating unit also generates a low gain reset signal; in this case, the cache unit is used to cache the low gain reset signal or the low gain image signal; the storage unit is used to store the low gain reset signal, the low gain image signal, the high gain reset signal and the high gain image signal, wherein the low gain reset signal or the low gain image signal is provided by the cache unit, and the remaining signals are provided by the signal generating unit; the signal output unit is used to output the low gain reset signal, the low gain image signal, the high gain reset signal and the high gain image signal.

[0012] Optionally, the cache unit includes: a first control transistor, a second control transistor and a first storage device;

[0013] The control terminal of the first control transistor receives a first control signal, the first terminal is coupled to the output terminal of the signal generating unit, and the second terminal is coupled to the first storage device and the first terminal of the second control transistor;

[0014] The second terminal of the first storage device is coupled to a first reference potential;

[0015] A control terminal of the second control transistor receives a second control signal, and a second terminal serves as an output terminal of the cache unit.

[0016] Optionally, the storage unit includes: a third control transistor, a fourth control transistor, a second storage device and a third storage device;

[0017] The control terminal of the third control transistor receives a third control signal, the first terminal is coupled to the output terminal of the signal generating unit, and the second terminal is coupled to the second storage device and the first terminal of the fourth control transistor;

[0018] The second terminal of the second storage device is coupled to a second reference potential;

[0019] The control terminal of the fourth control transistor receives a fourth control signal, and the second terminal is coupled to the first terminal of the third storage device;

[0020] A first terminal of the third storage device is coupled to the output terminal of the cache unit and serves as the output terminal of the storage unit, and a second terminal of the third storage device is coupled to a third reference potential.

[0021] Optionally, the storage unit further includes: a fifth control transistor and / or a sixth control transistor;

[0022] The control terminal of the fifth control transistor receives a fifth control signal, the first terminal is coupled to the output terminal of the signal generating unit, and the second terminal is coupled to the first terminal of the third storage device;

[0023] The control terminal of the sixth control transistor receives a sixth control signal, the first terminal is coupled to the first variable potential, and the second terminal is coupled to the first terminal of the third storage device.

[0024] Optionally, the signal generating unit comprises: a photosensitive unit, a floating diffusion node, a reset unit, a gain control unit and an amplifying output unit; wherein:

[0025] The photosensitive unit receives a light signal and generates a charge signal based on the light signal and transfers it to the floating diffusion node;

[0026] The reset unit is coupled to the floating diffusion node and is used to reset the floating diffusion node;

[0027] The gain control unit is coupled to the floating diffusion node and is used to switch different conversion gain modes to generate the low gain image signal, the high gain reset signal and the high gain image signal based on the floating diffusion node;

[0028] The amplifying output unit is coupled to the floating diffusion node, and is configured to output the low-gain image signal, the high-gain reset signal, and the high-gain image signal.

[0029] Optionally, the photosensitive unit includes at least one photosensitive element and a transmission transistor corresponding thereto; a control end of the transmission transistor receives a transmission control signal, a first end is coupled to the floating diffusion node, a second end is coupled to a first end of the photosensitive element, and a second end of the photosensitive element is coupled to a fourth reference potential;

[0030] And / or, the reset unit comprises a reset transistor, a control terminal receiving a reset control signal, a first terminal coupled to a first power supply potential, and a second terminal coupled to the floating diffusion node;

[0031] And / or, the amplifying output unit includes a first source follower transistor, a control end of which is coupled to the floating diffusion node, a first end of which is coupled to a second variable potential, and a second end of which serves as an output end of the signal generating unit.

[0032] Optionally, the gain control unit includes a first gain transistor and an overflow capacitor; wherein the first gain transistor is coupled between the reset unit and the floating diffusion node, and the overflow capacitor is coupled between a coupling node between the reset unit and the first gain transistor and a fifth reference potential; or, the first gain transistor and the overflow capacitor are coupled in series to the floating diffusion node.

[0033] Optionally, the gain control unit also includes: at least one second gain transistor; when the first gain transistor is coupled between the reset unit and the floating diffusion node, the second gain transistor is coupled between the first gain transistor and the floating diffusion node; when the first gain transistor and the overflow capacitor are coupled in series to the floating diffusion node, the second gain transistor is coupled between the reset unit and the floating diffusion node.

[0034] Optionally, the image sensor further comprises: a storage unit matched with the second gain transistor, for storing a reset signal and an image signal in a corresponding conversion gain mode; wherein the matched storage unit comprises: a seventh control transistor, an eighth control transistor, a ninth control transistor, a fourth storage device and a fifth storage device;

[0035] The control end of the seventh control transistor receives the seventh control signal, the first end is coupled to the output end of the signal generating unit, and the second end is coupled to the fourth storage device and the first end of the eighth control transistor; the second end of the fourth storage device is coupled to the sixth reference potential; the control end of the eighth control transistor receives the eighth control signal, the second end is coupled to the fifth storage device and the first end of the ninth control transistor; the second end of the fifth storage device is coupled to the seventh reference potential; the control end of the ninth control transistor receives the ninth control signal, and the second end serves as the output end of the matching storage unit.

[0036] Optionally, the signal output unit includes: a second source follower transistor and a selection transistor; the control end of the second source follower transistor is coupled to the output end of the storage unit, the first end is coupled to the second power supply potential, and the second end is coupled to the first end of the selection transistor; the control end of the selection transistor receives a selection control signal, and the second end serves as the output end of the signal output unit to be coupled to the column line;

[0037] Alternatively, the signal output unit includes two sub-units, which are respectively coupled to the output ends of the cache unit and the storage unit to output corresponding signals, wherein the two sub-units are coupled to the same or different column lines; at this time, the storage unit is not coupled to the cache unit, and the storage unit no longer stores the signal in the cache unit.

[0038] Optionally, the image sensor further includes: a rolling exposure transistor coupled between the output terminal of the signal generating unit and the column line.

[0039] The present invention also provides a control method for the image sensor as described in any one of the above items, comprising: storing the high-gain reset signal and the high-gain image signal respectively based on the storage unit, and caching the low-gain image signal based on the cache unit; wherein the low-gain image signal includes an overflow signal.

[0040] Optionally, when the signal generating unit includes a photosensitive unit, a reset unit, a gain control unit and an amplifying output unit, the method includes:

[0041] performing global exposure on the image sensor;

[0042] Controlling the reset unit and the gain control unit to be turned on and then turned off to obtain the high-gain reset signal;

[0043] storing the high-gain reset signal based on the storage unit;

[0044] Controlling the photosensitive unit to transfer charges to obtain the high-gain image signal, and storing the high-gain image signal based on the storage unit;

[0045] The gain control unit is controlled to open and the photosensitive unit is controlled to perform charge transfer to obtain the low-gain image signal, and the low-gain image signal is cached based on the cache unit.

[0046] Optionally, when the cache unit includes a first storage device and the storage unit includes a second storage device and a third storage device, the method further includes:

[0047] Before obtaining the high-gain reset signal, a step of resetting signals of the first storage device, the second storage device and the third storage device;

[0048] and / or, before storing the high-gain image signal, performing a signal resetting step on the second storage device;

[0049] and / or, before storing the overflow signal, performing a signal resetting step on the first storage device;

[0050] And / or, when the storage unit includes a sixth control transistor, after the high-gain reset signal is read out and before the low-gain image signal is read out, the method further includes:

[0051] Acquire a low-gain reset signal based on the sixth control transistor and store it in the third storage device;

[0052] After the low-gain reset signal is read out, the low-gain image signal is charged and redistributed based on the first storage device and the third storage device and read out.

[0053] The present invention also provides a control method for the image sensor as described in any one of the above items, comprising: based on the cache unit caching the low gain reset signal or the low gain image signal, based on the signal generation unit and the cache unit jointly providing the low gain reset signal, the low gain image signal, the high gain reset signal and the high gain image signal to the storage unit.

[0054] Optionally, the method comprises: a first operation: generating the low gain reset signal, the high gain reset signal, the high gain image signal and the low gain image signal based on the signal generating unit; caching the low gain reset signal based on the cache unit; storing and outputting the high gain reset signal provided by the signal generating unit, storing and outputting the high gain image signal provided by the signal generating unit, storing and outputting the low gain reset signal provided by the cache unit, and storing and outputting the low gain image signal provided by the signal generating unit based on the storage unit and the signal output unit;

[0055] And / or, a second operation: generating the low-gain image signal, the high-gain reset signal, the high-gain image signal and the low-gain reset signal based on the signal generating unit; caching the low-gain image signal based on the cache unit; storing and outputting the high-gain reset signal provided by the signal generating unit, storing and outputting the high-gain image signal provided by the signal generating unit, storing and outputting the low-gain image signal provided by the cache unit, and storing and outputting the low-gain reset signal provided by the signal generating unit based on the storage unit and the signal output unit.

[0056] Optionally, when the signal generating unit includes a photosensitive unit, a reset unit, a gain control unit and an amplifying output unit, the method includes:

[0057] Corresponding to the first operation, performing global exposure on the image sensor;

[0058] Controlling the gain control unit to be turned on and the reset unit to be turned on to obtain the low gain reset signal, and caching the low gain reset signal based on the cache unit;

[0059] Controlling the gain control unit to be turned off to obtain the high-gain reset signal, and storing and outputting the high-gain reset signal based on the storage unit and the signal output unit;

[0060] Controlling the photosensitive unit to transfer the charge signal to obtain the high-gain image signal, and storing and outputting the high-gain image signal based on the storage unit and the signal output unit;

[0061] storing and outputting the low-gain reset signal in the cache unit based on the storage unit and the signal output unit;

[0062] Control the gain control unit to turn on and control the photosensitive unit to transfer the charge signal to obtain the low-gain image signal, and store and output the low-gain image signal based on the storage unit and the signal output unit;

[0063] and / or, corresponding to the second operation, controlling the gain control unit to turn on and performing global exposure on the image sensor;

[0064] Controlling the photosensitive unit to transfer the charge signal to obtain the low-gain image signal, and caching the low-gain image signal based on the cache unit;

[0065] Controlling the reset unit to be turned on and then turned off, and then controlling the gain control unit to be turned off to obtain the high-gain reset signal, and storing and outputting the high-gain reset signal based on the storage unit and the signal output unit;

[0066] Controlling the photosensitive unit to transfer the charge signal to obtain the high-gain image signal, and storing and outputting the high-gain image signal based on the storage unit and the signal output unit;

[0067] storing and outputting the low-gain image signal in the buffer unit based on the storage unit and the signal output unit;

[0068] The gain control unit is controlled to be turned on and the reset unit is controlled to be turned on and then turned off to obtain the low gain reset signal, and the low gain reset signal is stored and output based on the storage unit and the signal output unit.

[0069] As described above, in an image sensor and a control method of the present invention, a cache unit is used in conjunction with a storage unit. The cache unit is used to cache signals, which can realize the reuse of storage devices in the storage unit, thereby reducing the number of storage devices required in a single pixel circuit. The PGHDR operation of the image sensor under global exposure can be realized by at least three storage devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0070] Figure 1-Figure 9 Shown are schematic diagrams of different structures of the image sensor of the present invention; wherein, Figure 1 and Figure 2Schematic diagrams showing different coupling modes between the first gain control transistor and the overflow capacitor in the gain control unit, Figure 3 and Figure 4 Shown in Figure 1 and Figure 2 Based on the schematic diagram of the gain control unit including a second gain control transistor, Figure 5 A schematic diagram showing a memory cell including a fifth control transistor, Figure 6 A schematic diagram showing a memory cell including a sixth control transistor, Figure 7 and Figure 8 A schematic diagram showing the corresponding same and different column lines when the cache unit and the storage unit are coupled to different signal output units, Fig. 9 Schematic diagram showing an image sensor including a rolling exposure transistor.

[0071] Fig.10 The display is a timing diagram corresponding to the control method in the first embodiment.

[0072] Fig.11 The display is a timing diagram corresponding to the control method under the first operation in the third embodiment.

[0073] Fig.12 It shows a timing diagram corresponding to the control method under the second operation in the third embodiment.

[0074] Component number description

[0075] 10 Image Sensor

[0076] 100 Signal generation unit

[0077] 110 Photosensitive unit

[0078] 120 Reset unit

[0079] 130 Gain control unit

[0080] 140 Amplified output unit

[0081] 200 Cache Units

[0082] 300 storage units

[0083] 300' matching storage unit

[0084] 400 Signal output unit

[0085] 410 First Subunit

[0086] 420 Second subunit DETAILED DESCRIPTION

[0087] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0088] See also Figures 1 to 12 It should be noted that the illustrations provided in this embodiment are only schematic illustrations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation, the form, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.

[0089] Embodiment 1

[0090] like Figure 1 As shown, this embodiment provides an image sensor 10 , including: a signal generating unit 100 , a buffer unit 200 , a storage unit 300 and a signal output unit 400 .

[0091] The signal generating unit 100 generates a low gain image signal LCG_SIG, a high gain reset signal HCG_RST, and a high gain image signal HCG_SIG based on different conversion gain modes.

[0092] Specifically, the signal generating unit 100 includes: a photosensitive unit 110, a floating diffusion node FD, a reset unit 120, a gain control unit 130 and an amplifying output unit 140. Among them:

[0093] The photosensitive unit 110 receives a light signal and generates a charge signal based on the light signal and transfers the charge signal to the floating diffusion node FD.

[0094] As an example, the photosensitive unit 110 includes at least one photosensitive element PD and a corresponding transfer transistor M1; the control end of the transfer transistor M1 receives a transmission control signal TX, the first end is coupled to the floating diffusion node FD, the second end is coupled to the first end of the photosensitive element PD, and the second end of the photosensitive element PD is coupled to a fourth reference potential.

[0095] The photosensitive element PD may be any one of a photodiode, a grating or a photoconductor, and the transfer transistor M1 may be any one of an NMOS tube or a PMOS tube. In this embodiment, the photosensitive element PD is a photodiode, such as a pin-type photodiode, and the transfer transistor M1 is an NMOS tube; at this time, the first end of the photosensitive element PD refers to the cathode end of the photodiode, the second end refers to the anode end of the photodiode, the control end of the transfer transistor M1 refers to the gate end of the NMOS tube, the first end refers to the drain end of the NMOS tube, and the second end refers to the source end of the NMOS tube.

[0096] In practical applications, the number of photosensitive elements PD and transmission transistors M1 included in the photosensitive unit 110 can be designed according to specific needs. For example, the photosensitive element PD can be one, or a shared structure formed by two, four, eight, etc., and this embodiment does not limit this. In addition, the fourth reference potential is usually a reference ground potential. Of course, in other embodiments, the fourth reference potential can also be a negative potential.

[0097] The reset unit 120 is coupled to the floating diffusion node FD and is used to reset the floating diffusion node FD.

[0098] As an example, the reset unit 120 includes a reset transistor M2 , a control terminal of which receives a reset control signal RST, a first terminal of which is coupled to a first power supply potential VDD, and a second terminal of which is coupled to a floating diffusion node FD.

[0099] Among them, the reset transistor M2 can be any one of an NMOS tube or a PMOS tube; in this embodiment, the reset transistor M2 is an NMOS tube. At this time, the control end of the reset transistor M2 refers to the gate end of the NMOS tube, the first end refers to the drain end of the NMOS tube, and the second end refers to the source end of the NMOS tube.

[0100] In practical applications, the first power supply potential is usually the potential of the working voltage, which is always a high potential. At this time, the reset control signal RST is used to control the opening and closing of the reset transistor M2. Of course, in other embodiments, the first power supply potential can also be a variable potential. At this time, the opening and closing of the reset transistor M2 is controlled by controlling the first power supply potential and the reset control signal.

[0101] The gain control unit 130 is coupled to the floating diffusion node FD for switching different conversion gain modes to generate a low gain image signal LCG_SIG, a high gain reset signal HCG_RST and a high gain image signal HCG_SIG based on the floating diffusion node FD.

[0102] As an example, the gain control unit 130 includes a first gain transistor M3 and an overflow capacitor C1;

[0103] In a possible implementation, Figure 1 As shown, the first gain transistor M3 is coupled between the reset unit 120 and the floating diffusion node FD, and the overflow capacitor C1 is coupled between the coupling node of the reset unit 120 and the first gain transistor M3 and the fifth reference potential; for example, the control end of the first gain transistor M3 receives the overflow control signal CG1, the first end is coupled to the second end of the reset transistor M2 and the first end of the overflow capacitor C1, the second end is coupled to the floating diffusion node FD, and the second end of the overflow capacitor C1 is coupled to the fifth reference potential.

[0104] In another possible implementation, Figure 2 As shown, the first gain transistor M3 and the overflow capacitor C1 are coupled in series to the floating diffusion node FD; for example, the control end of the first gain transistor M3 receives the overflow control signal CG1, the first end is coupled to the floating diffusion node FD, the second end is coupled to the first end of the overflow capacitor C1, and the second end of the overflow capacitor C1 is coupled to the fifth reference potential.

[0105] The first gain transistor M3 can be any one of an NMOS tube or a PMOS tube; in this embodiment, the first gain transistor M3 is an NMOS tube, at this time, the control end of the first gain transistor M3 refers to the gate end of the NMOS tube, the first end refers to the drain end of the NMOS tube, and the second end refers to the source end of the NMOS tube. In practical applications, the fifth reference potential is usually a reference ground potential. Of course, in other embodiments, the fifth reference potential can also be a non-reference ground potential, such as a negative potential or a positive potential, so as to facilitate rapid access to charge.

[0106] In a further example, the gain control unit 130 further includes: at least one second gain transistor M4;

[0107] In a possible implementation, Figure 3 As shown, when the first gain transistor M3 is coupled between the reset unit 120 and the floating diffusion node FD, the second gain transistor M4 is coupled between the first gain transistor M3 and the floating diffusion node FD; for example, the control end of the second gain transistor M4 receives the gain control signal CG2, the first end is coupled to the second end of the first gain transistor M3, and the second end is coupled to the floating diffusion node FD.

[0108] In another possible implementation, Figure 4 As shown, when the first gain transistor M3 and the overflow capacitor C1 are coupled in series to the floating diffusion node FD, the second gain transistor M4 is coupled between the reset unit 120 and the floating diffusion node FD; for example, the control end of the second gain transistor M4 receives the gain control signal CG2, the first end is coupled to the second end of the reset transistor M2, and the second end is coupled to the floating diffusion node FD.

[0109] Of course, the above two embodiments only show the case where the number of the second gain transistor M4 is one. When the number of the second gain transistors M4 is greater than or equal to 2, multiple second gain transistors M4 are connected in series and then coupled to the circuit in the above coupling manner.

[0110] Among them, the second gain transistor M4 can be any one of an NMOS tube or a PMOS tube; in this embodiment, the second gain transistor M4 is an NMOS tube. At this time, the control end of the second gain transistor M4 refers to the gate end of the NMOS tube, the first end refers to the drain end of the NMOS tube, and the second end refers to the source end of the NMOS tube.

[0111] In this embodiment, both the first gain transistor M3 and the second gain transistor M4 can be used to control the switching of different conversion gain modes; when the gain control unit 130 includes the first gain transistor M3 and / or the second gain transistor M4, by controlling the opening timing of the first gain transistor M3, the overflow capacitor C1 can be used to store the overflow charge of the photosensitive element PD, and by controlling the opening and closing of the second gain transistor M4, the image sensor 10 can be operated under HCG or LCG. It should be noted that the high conversion gain and low conversion gain described in this application are not limited to a specific single value, but are relative high gain and low gain obtained based on the regulation of the gain control unit, which can be understood by those skilled in the art.

[0112] The amplifying output unit 140 is coupled to the floating diffusion node FD, and is used to output signals corresponding to the floating diffusion node FD, such as the low gain image signal LCG_SIG, the high gain reset signal HCG_RST, and the high gain image signal HCG_SIG.

[0113] As an example, the amplification output unit 140 includes a first source follower transistor M5, a control terminal coupled to the floating diffusion node FD, a first terminal coupled to the second variable potential VRSF, and a second terminal as the output terminal of the signal generating unit 100. Whether the second terminal of the first source follower transistor M5 has an output is controlled by controlling the second variable potential VRSF, for example, when the second variable potential VRSF is a high potential, the second terminal of the first source follower transistor M5 has an output.

[0114] Among them, the first source follower transistor M5 can be any one of an NMOS tube or a PMOS tube; in this embodiment, the first source follower transistor M5 is an NMOS tube. At this time, the control end of the first source follower transistor M5 refers to the gate end of the NMOS tube, the first end refers to the drain end of the NMOS tube, and the second end refers to the source end of the NMOS tube.

[0115] The buffer unit 200 is coupled to the signal generating unit 100 and is at least used to buffer the low-gain image signal LCG_SIG.

[0116] As an example, the cache unit 200 includes: a first control transistor M6, a second control transistor M7 and a first storage device C2; ​​the control end of the first control transistor M6 receives a first control signal of_store, the first end is coupled to the output end of the signal generating unit 100, and the second end is coupled to the first storage device C2 and the first end of the second control transistor M7; the second end of the first storage device C2 is coupled to the first reference potential; the control end of the second control transistor M7 receives a second control signal of_read, and the second end serves as the output end of the cache unit 200.

[0117] Among them, the first control transistor M6 can be any one of an NMOS tube or a PMOS tube, the second control transistor M7 can be any one of an NMOS tube or a PMOS tube, and the first storage device C1 can be a MIM capacitor or a MOS capacitor, etc. In this embodiment, the first control transistor M6 and the second control transistor M7 are NMOS tubes; at this time, the control end of the first control transistor M6 and the second control transistor M7 refers to the gate end of each NMOS tube, the first end refers to the drain end of each NMOS tube, and the second end refers to the source end of each NMOS tube; the first end of the first storage device C2 refers to the upper plate of the capacitor, and the second end refers to the lower plate of the capacitor. In practical applications, the first reference potential is usually a reference ground potential. Of course, in other embodiments, the first reference potential can also be a non-reference ground potential, such as a negative potential or a positive potential, to facilitate rapid access to charge, etc.

[0118] In this embodiment, when the second variable potential VRSF coupled to the first end of the first source follower transistor M5 is a low potential, the charge of the first storage device C2 is cleared by controlling the first control transistor M6 to turn on; when the second variable potential VRSF coupled to the first end of the first source follower transistor M5 is a high potential, the low gain image signal LCG_SIG is cached in the first storage device C2 by controlling the first control transistor M6 to turn on, and the low gain image signal LCG_SIG is transferred from the first storage device C2 to the storage unit 300 by controlling the second control transistor M7 to turn on.

[0119] The storage unit 300 is coupled to the signal generating unit 100 and the buffer unit 200 , and is used to store the low gain image signal LCG_SIG, the high gain reset signal HCG_RST and the high gain image signal HCG_SIG; wherein the low gain image signal LCG_SIG is provided by the buffer unit 200 , and the remaining signals are provided by the signal generating unit 100 .

[0120] As an example, the storage unit 300 includes: a third control transistor M8, a fourth control transistor M9, a second storage device C3 and a third storage device C4; the control end of the third control transistor M8 receives the third control signal gs_sig, the first end is coupled to the output end of the signal generating unit 100, and the second end is coupled to the second storage device C3 and the first end of the fourth control transistor M9; the second end of the second storage device C3 is coupled to the second reference potential; the control end of the fourth control transistor M9 receives the fourth control signal gs_rst, and the second end is coupled to the first end of the third storage device C4; the first end of the third storage device C4 is coupled to the output end of the cache unit 200 and serves as the output end of the storage unit 300, and the second end is coupled to the third reference potential. As an optional solution, the capacitance values ​​of the first storage device C1, the second storage device C3 and the third storage device C4 are the same, which is convenient for allocating charge readout.

[0121] Among them, the third control transistor M8 can be any one of an NMOS tube or a PMOS tube, the fourth control transistor M9 can be any one of an NMOS tube or a PMOS tube, the second storage device C3 can be a MIM capacitor or a MOS capacitor, etc., and the third storage device C4 can be a MIM capacitor or a MOS capacitor, etc. In this embodiment, the third control transistor M8 and the fourth control transistor M9 are NMOS tubes; at this time, the control end of the third control transistor M8 and the fourth control transistor M9 refers to the gate end of each NMOS tube, the first end refers to the drain end of each NMOS tube, and the second end refers to the source end of each NMOS tube; the first end of the second storage device C3 and the third storage device C4 refers to the upper plate of each capacitor, and the second end refers to the lower plate of each capacitor.

[0122] In practical applications, the second reference potential and the third reference potential are usually reference ground potentials. Of course, in other embodiments, the second reference potential and the third reference potential may also be non-reference ground potentials, such as negative potentials or positive potentials, to facilitate rapid access to charge.

[0123] In this embodiment, when the second variable potential VRSF coupled to the first end of the first source follower transistor M5 is at a low potential, the third control transistor M8 and the fourth control transistor M9 are controlled to be turned on, so that the second storage device C3 and the third storage device C4 are cleared from charge, and the third control transistor M8 is controlled to be turned on, so that the second storage device C3 is cleared from charge;

[0124] When the second variable potential VRSF coupled to the first end of the first source follower transistor M5 is a high potential, the high gain reset signal HCG_RST is stored in the third storage device C4 by controlling the third control transistor M8 and the fourth control transistor M9 to be turned on, and the high gain image signal HCG_SIG is stored in the second storage device C3 by controlling the third control transistor M8 to be turned on; of course, before storing the high gain image signal HCG_SIG, the charge of the second storage device C3 may be cleared to clear the high gain reset signal HCG_RST stored in the second storage device C3 in the previous step;

[0125] When the signal is read out, for the high gain reset signal HCG_RST, the high gain reset signal HCG_RST is directly read out from the third storage device C4 through the signal output unit 400; for the high gain image signal HCG_SIG, the fourth control transistor M9 is controlled to be turned on to redistribute the charge of the high gain image signal HCG_SIG based on the second storage device C3 and the third storage device C4, and then the distributed charge signal stored in the third storage device C4 is read out through the signal output unit 400;

[0126] When the low gain image signal LCG_SIG cached in the first storage device C2 is to be transferred to the third storage device C4, the fourth control transistor M9 is controlled to be turned off and the second control transistor M7 in the cache unit 200 is controlled to be turned on to transfer the low gain image signal LCG_SIG from the first storage device C2 and store it in the third storage device C4.

[0127] In a further example, Figure 5 As shown, the memory unit 300 further includes a fifth control transistor M10 , a control terminal of which receives a fifth control signal CTL1 , a first terminal of which is coupled to the output terminal of the signal generating unit 100 , and a second terminal of which is coupled to the first terminal of the third memory device C4 .

[0128] Among them, the fifth control transistor M10 can be any one of an NMOS tube or a PMOS tube; in this embodiment, the fifth control transistor M10 is an NMOS tube. At this time, the control end of the fifth control transistor M10 refers to the gate end of the NMOS tube, the first end refers to the drain end of the NMOS tube, and the second end refers to the source end of the NMOS tube.

[0129] In this embodiment, the high gain reset signal HCG_RST is stored in the third storage device C4 by controlling the fifth control transistor M10 to turn on, instead of controlling the third control transistor M8 and the fourth control transistor M9 to turn on, so as to achieve fast charge storage and simplify the complexity of the control timing.

[0130] In a further example, Figure 6 As shown, the memory unit 300 further includes a sixth control transistor M11 , a control terminal of which receives a sixth control signal CTL2 , a first terminal of which is coupled to a first variable potential, and a second terminal of which is coupled to a first terminal of a third memory device C4 .

[0131] Among them, the sixth control transistor M11 can be any one of an NMOS tube or a PMOS tube; in this embodiment, the sixth control transistor M11 is an NMOS tube. At this time, the control end of the sixth control transistor M11 refers to the gate end of the NMOS tube, the first end refers to the drain end of the NMOS tube, and the second end refers to the source end of the NMOS tube.

[0132] In this embodiment, when the first variable potential is a low potential, the charge of the third storage device C4 is cleared by controlling the sixth control transistor M11 to turn on, instead of controlling the third control transistor M8 and the fourth control transistor M9 to turn on. This allows the third storage device C4 to perform a charge clearing operation independently, thereby achieving rapid charge clearing and simplifying the complexity of the control timing.

[0133] In addition, by setting the potential value of the first variable potential, it is also possible to obtain a corresponding reset signal (such as a low-gain reset signal LCG_RST) based on the sixth control transistor M11 and store it in the third storage device C4, and after the low-gain reset signal LCG_RST is read out, the low-gain image signal LCG_SIG cached in the first storage device C2 is read out after charge redistribution based on the first storage device C2 and the third storage device C3, so as to realize correlated double sampling of the signal.

[0134] In practical applications, the first variable potential and the second variable potential are usually set to be different potential signals. Of course, in other embodiments, the first variable potential and the second variable potential can also be set to be the same potential signal.

[0135] As an alternative, Figure 3 and Figure 4 As shown, when the gain control unit 130 includes the second gain transistor M4, the image sensor 10 of this embodiment further includes: a storage unit 300' matched with the second gain transistor M4, for storing the reset signal and the image signal in the corresponding conversion gain mode.

[0136] As an example, the matching storage unit 300' includes: a seventh control transistor M12, an eighth control transistor M13, a ninth control transistor M14, a fourth storage device C5 and a fifth storage device C6; the control end of the seventh control transistor M12 receives the seventh control signal CTL3, the first end is coupled to the output end of the signal generating unit 100, and the second end is coupled to the fourth storage device C5 and the first end of the eighth control transistor M13; the second end of the fourth storage device C5 is coupled to the sixth reference potential; the control end of the eighth control transistor M13 receives the eighth control signal CTL4, the second end is coupled to the fifth storage device C6 and the first end of the ninth control transistor M14; the second end of the fifth storage device C6 is coupled to the seventh reference potential; the control end of the ninth control transistor M14 receives the ninth control signal CTL5, and the second end serves as the output end of the matching storage unit 300'.

[0137] Among them, the seventh control transistor M12 can be any one of an NMOS tube or a PMOS tube, the eighth control transistor M13 can be any one of an NMOS tube or a PMOS tube, the ninth control transistor M14 can be any one of an NMOS tube or a PMOS tube, the fourth storage device C5 can be a MIM capacitor or a MOS capacitor, etc., and the fifth storage device C6 can be a MIM capacitor or a MOS capacitor, etc.

[0138] In this embodiment, the seventh control transistor M12, the eighth control transistor M13 and the ninth control transistor M14 are NMOS transistors; at this time, the control end of the seventh control transistor M12, the eighth control transistor M13 and the ninth control transistor M14 refers to the gate end of each NMOS transistor, the first end refers to the drain end of each NMOS transistor, and the second end refers to the source end of each NMOS transistor; the first end of the fourth storage device C5 and the fifth storage device C6 refers to the upper plate of each capacitor, and the second end refers to the lower plate of each capacitor.

[0139] In practical applications, the sixth reference potential and the seventh reference potential are usually reference ground potentials. Of course, in other embodiments, the sixth reference potential and the seventh reference potential may also be non-reference ground potentials, such as negative potentials or positive potentials, to facilitate rapid access to charge, etc.

[0140] In this embodiment, when the second variable potential VRSF coupled to the first end of the first source follower transistor M5 is at a low potential, the seventh control transistor M12 and the eighth control transistor M13 are controlled to be turned on, so that the fourth storage device C5 and the fifth storage device C6 are cleared, and the seventh control transistor M12 is controlled to be turned on, so that the fourth storage device C5 is cleared;

[0141] When the second variable potential VRSF coupled to the first end of the first source follower transistor M5 is a high potential, the reset signal in the corresponding conversion gain mode is stored in the fifth storage device C6 by controlling the seventh control transistor M12 and the eighth control transistor M13 to be turned on, and the image signal in the corresponding conversion gain mode is stored in the fourth storage device C5 by controlling the seventh control transistor M12 to be turned on; of course, before storing the corresponding image signal, the fourth storage device C5 may be charged to zero to clear the corresponding reset signal stored in the fourth storage device C5 in the previous step;

[0142] When the signal is read out, for the reset signal, the ninth control transistor M14 is controlled to be turned on, and the reset signal is directly read out from the fifth storage device C6 through the signal output unit 400; for the image signal, the eighth control transistor M13 is controlled to be turned on to redistribute the charge of the image signal based on the fourth storage device C5 and the fifth storage device C6, and then the ninth control transistor M14 is controlled to be turned on, and the distributed charge signal stored in the fifth storage device C6 is read out through the signal output unit 400.

[0143] The signal output unit 400 is coupled to the storage unit 300 and is at least configured to output a low gain image signal LCG_SIG, a high gain reset signal HCG_RST, and a high gain image signal HCG_SIG.

[0144] In a possible implementation, Figure 1-Figure 6 As shown, the signal output unit 400 includes: a second source follower transistor M15 and a selection transistor 16; the control end of the second source follower transistor M15 is coupled to the output end of the storage unit 300, the first end is coupled to the second power supply potential, and the second end is coupled to the first end of the selection transistor M16; the control end of the selection transistor M16 receives the selection control signal RS, and the second end serves as the output end of the signal output unit 400 to be coupled to the column line.

[0145] Among them, the second source follower transistor M15 can be any one of an NMOS tube or a PMOS tube, and the selection transistor 16 can be any one of an NMOS tube or a PMOS tube; in this embodiment, the second source follower transistor M15 and the selection transistor 16 are NMOS tubes. At this time, the control end of the second source follower transistor M15 and the selection transistor 16 refers to the gate end of each NMOS tube, the first end refers to the drain end of each NMOS tube, and the second end refers to the source end of each NMOS tube.

[0146] In this embodiment, the second power supply potential is controlled to control whether the second end of the second source follower transistor M15 has an output, for example, when the second power supply potential is a high potential, the second end of the second source follower transistor M15 has an output; in practical applications, the second power supply potential is usually the potential of the working voltage, which is always a high potential. At this time, by controlling the opening and closing of the selection transistor M16, the signals stored in the storage unit 300 are controlled to be serially read out through the column line in sequence. In other embodiments, the signal output unit 400 may also include only the second source follower transistor M15, excluding the selection transistor 16, and the source of the second source follower transistor M15 is connected to the column line as an output terminal.

[0147] In another possible implementation, Figure 7 and Figure 8 As shown, the signal output unit 400 includes two subunits (i.e., a first subunit 410 and a second subunit 420), which are respectively coupled to the output ends of the storage unit 300 and the cache unit 200 to output corresponding signals; wherein the two subunits are coupled to the same or different column lines. At this time, the storage unit 300 is no longer coupled to the cache unit 200, and the storage unit 300 no longer stores the signal in the cache unit 200. It should be noted that the circuits of the first subunit 410 and the second subunit 420 are the same, and are both composed of corresponding source follower transistors and selection transistors. Similarly, they can also be composed of only source follower transistors. The specific device connection can be found in the previous text and will not be repeated here.

[0148] In the present embodiment, when the cache unit 200 and the storage unit 300 respectively read out signals through different sub-units, the cache unit 200 no longer needs to transfer and store the low-gain image signal LCG_SIG cached in the first storage device C2 to the storage unit 300, but can directly read it out through the corresponding sub-unit. At this time, the cache unit 200 can also omit the second control transistor M7; in addition, when the two sub-units are coupled to the same column line, the signals in the cache unit 200 and the storage unit 300 are serially read out through the column line in turn; when the two sub-units are coupled to different column lines, the signals in the cache unit 200 and the storage unit 300 can be read out in parallel through their respective column lines.

[0149] like Fig. 9 As shown, the image sensor 10 of this embodiment further includes: a rolling exposure transistor M19, coupled between the output terminal of the signal generating unit 100 and the column line, such as a control terminal of the rolling exposure transistor M19 receiving a rolling control signal CTL6, a first terminal coupled to the output terminal of the signal generating unit 100, and a second terminal coupled to the column line. It should be noted that when the signal output unit 400 is coupled to different column lines, the second terminal of the rolling exposure transistor M19 can be coupled to any column line.

[0150] Among them, the rolling exposure transistor M19 can be any one of an NMOS tube or a PMOS tube; in this embodiment, the rolling exposure transistor M19 is an NMOS tube. At this time, the control end of the rolling exposure transistor M19 refers to the gate end of the NMOS tube, the first end refers to the drain end of the NMOS tube, and the second end refers to the source end of the NMOS tube.

[0151] In this embodiment, the image sensor 10 is controlled to operate in different exposure modes by controlling the opening and closing of the rolling exposure transistor M19; for example, when the rolling exposure transistor M19 is turned on, the image sensor 10 operates in the rolling exposure mode, and when the rolling exposure transistor M19 is turned off, the image sensor 10 operates in the global exposure mode.

[0152] Accordingly, this embodiment also provides a control method of the image sensor 10 as described above. Figure 1 Taking the image sensor 10 shown as an example, the control method includes: storing the high-gain reset signal HCG_RST and the high-gain image signal HCG_SIG respectively based on the storage unit 300, and caching the low-gain image signal LCG_SIG based on the cache unit 200; wherein the low-gain image signal LCG_SIG includes the overflow signal OF_SIG. Specifically as follows:

[0153] The high-gain reset signal HCG_RST, the high-gain image signal HCG_SIG and the overflow signal OF_SIG are generated based on the signal generating unit 100; the high-gain reset signal HCG_RST and the high-gain image signal HCG_SIG are respectively stored based on the storage unit 300, and the overflow signal OF_SIG is cached based on the buffer unit 200. Further, the high-gain reset signal HCG_RST and the high-gain image signal HCG_SIG provided by the storage unit 300 are output based on the signal output unit 400, and the overflow signal OF_SIG provided by the buffer unit is stored and output based on the storage unit 300 and the signal output unit 400.

[0154] In one possible implementation, the high gain reset signal HCG_RST and the high gain image signal HCG_SIG are first stored in the storage unit 300 in sequence (e.g., the high gain reset signal HCG_RST is first stored in the third storage device C4, and then the high gain image signal HCG_SIG is stored in the second storage device C3), and then the overflow signal OF_SIG is stored in the cache unit 200 (e.g., the overflow signal OF_SIG is stored in the first storage device C2).

[0155] As an example, when the signal generating unit 100 includes a photosensitive unit 110, a reset unit 120, a gain control unit 130, and an amplifying output unit 140, Fig.10, the control method is described in detail. The control method includes:

[0156] Step 1) performing global exposure on the image sensor 10 .

[0157] In one example, the moment of the falling edge of the overflow control signal CG1 is defined as the moment when exposure ends. At this time, during the exposure process, the reset unit 120 and the gain control unit 130 are controlled to be turned on and then turned off to obtain a high gain reset signal HCG_RST, such as controlling the reset transistor M2 and the first gain transistor M3 to be turned on and then turned off to reset the floating diffusion node FD to obtain a high gain reset signal HCG_RST.

[0158] Further, when the cache unit 200 includes a first storage device C2 and the storage unit 300 includes a second storage device C3 and a third storage device C4, before obtaining the high gain reset signal HCG_RST after the exposure is completed, the step also includes resetting the signals of the first storage device C2, the second storage device C3 and the third storage device C4.

[0159] For example, the second variable potential VRSF is set to a low potential, the first control transistor M6, the second control transistor M7, the third control transistor M8 and the fourth control transistor M9 are controlled to be turned on, the charge of the first storage device C2, the second storage device C3 and the third storage device C4 is cleared, and the signals of the three are reset. After that, the second variable potential is changed to a high potential, and the first control transistor M6 and the second control transistor M7 are controlled to be turned off.

[0160] Step 2) storing the high gain reset signal HCG_RST based on the storage unit 300, such as storing the high gain reset signal HCG_RST in the third storage device C4 based on the turned-on third control transistor M8 and fourth control transistor M9, and then controlling the fourth control transistor M9 to be turned off to complete the transfer of the high gain reset signal HCG_RST.

[0161] Step 3) Control the photosensitive unit 110 to transfer charges to obtain a high-gain image signal HCG_SIG, and store the high-gain image signal HCG_SIG based on the storage unit 300. Further, before the high-gain image signal HCG_SIG is stored, this step also includes resetting the signal of the second storage device C3; further, this step also includes resetting the signal of the first storage device C2.

[0162] For example, the second variable potential is set to a low potential, the first control transistor M6 and the second control transistor M7 are controlled to be turned on, and then combined with the turned-on third control transistor M8, the charge of the first storage device C2 and the second storage device C3 is cleared to achieve signal resetting of the two, and then the second variable potential is set to a high potential, and the first control transistor M6, the second control transistor M7 and the third control transistor M8 are controlled to be turned off.

[0163] Then, the transfer transistor M1 is controlled to turn on, and the charge signal stored in the photosensitive element PD is transferred to the floating diffusion node FD to obtain the high-gain image signal HCG_SIG, and the third control transistor M8 is controlled to turn on, and the high-gain image signal HCG_SIG is stored in the second storage device C3. After that, the third control transistor M8 is controlled to turn off to complete the transfer of the high-gain image signal HCG_SIG.

[0164] Step 4) Control the gain control unit 130 to turn on and control the photosensitive unit 110 to transfer charges to obtain an overflow signal OF_SIG, and cache the overflow signal OF_SIG based on the cache unit 200. Furthermore, before storing the overflow signal OF_SIG, this step also includes resetting the signal of the first storage device C2.

[0165] For example, the second variable potential is set to a low potential, the first control transistor M6 and the second control transistor M7 are controlled to be turned on, the charge of the first storage device C2 is cleared, and the signal is reset. Then, the second variable potential is set to a high potential, and the first control transistor M6 and the second control transistor M7 are controlled to be turned off.

[0166] Then, the first gain transistor M3 is controlled to be turned on and the transfer transistor M1 is controlled to be turned on, so as to transfer the charge signal stored in the photosensitive unit PD and the overflow signal OF_SIG obtained in the overflow capacitor C1 to the floating diffusion point FD;

[0167] Finally, the first control transistor M6 is controlled to be turned on, and the corresponding overflow signal OF_SIG is stored in the first storage device C2, thereby completing the transfer of the overflow signal OF_SIG, which may include the residual charge in the photosensitive unit PD.

[0168] When the signal is read:

[0169] Control the selection transistor M16 to be turned on and then turned off, and read out the high-gain reset signal HCG_RST stored in the third storage device C4;

[0170] Control the fourth control transistor M9 and the selection transistor M16 to turn on, redistribute and read out the charge of the high-gain image signal HCG_SIG based on the second storage device C3 and the third storage device C4, and then control the fourth control transistor M9 and the selection transistor M16 to turn off;

[0171] The second variable potential is set to a low potential, and the third control transistor M8 and the fourth control transistor M9 are controlled to be turned on, the charges of the second storage device C3 and the third storage device C4 are cleared, and the signals of the two are reset. After that, the second variable potential is set to a high potential, and the third control transistor M8 and the fourth control transistor M9 are controlled to be turned off; then, the second control transistor M7 and the selection transistor M16 are controlled to be turned on, and the overflow signal OF_SIG cached in the first storage device C2 is transferred and stored in the third storage device C4 and read out, and then, the second control transistor M7 and the selection transistor M16 are controlled to be turned off.

[0172] In a further example, when the storage unit 300 includes a sixth control transistor M11, after the high gain reset signal HCG_RST is read out and before the low gain image signal LCG_SIG is read out (further, such as, after the high gain image signal HCG_SIG is read out and before the low gain image signal LCG_SIG is read out), the method further includes: acquiring the low gain reset signal LCG_RST based on the sixth control transistor M11 and storing it in the third storage device C4; after reading out the low gain reset signal LCG_RST, redistributing and reading out the low gain image signal LCG_SIG (i.e., the overflow signal OF_SIG) based on the first storage device C2 and the third storage device C4, so as to realize correlated double sampling of the signal.

[0173] Embodiment 2

[0174] This embodiment provides an image sensor 10, which is different from the first embodiment in that the signal generating unit 100 also generates a low gain reset signal LCG_RST; at this time, the cache unit 200 is used to cache the low gain reset signal LCG_RST or the low gain image signal LCG_SIG. In one embodiment, the cache unit 200 is multiplexed, and after the low gain image signal LCG_SIG is read out, the reset unit 120 and the gain control unit 130 are controlled to be opened to generate the low gain reset signal LCG_RST, and further cache it in the cache unit 200, and finally output it through the signal output unit 400; of course, in other embodiments, the low gain reset signal LCG_RST can also be stored in the storage unit 300, and finally output through the signal output unit 400. In addition, the storage unit 300 is used to store a low gain reset signal LCG_RST, a low gain image signal LCG_SIG, a high gain reset signal HCG_RST and a high gain image signal HCG_SIG, wherein the low gain image signal LCG_SIG is provided by the cache unit 200, the low gain reset signal LCG_RST is provided by the cache unit 200 or the signal generating unit 100, and the remaining signals are provided by the signal generating unit 100. The signal output unit 400 is used to output a low gain reset signal LCG_RST, a low gain image signal LCG_SIG, a high gain reset signal HCG_RST and a high gain image signal HCG_SIG. In one embodiment, the output sequence is high gain reset signal HCG_RST, high gain image signal HCG_SIG, low gain image signal LCG_SIG, and gain reset signal LCG_RST. It should be noted that the circuits of the above units are the same as those in the first embodiment and will not be described in detail herein.

[0175] Embodiment 3

[0176] This embodiment provides an image sensor 10, which is different from the first embodiment in that the signal generating unit 100 also generates a low gain reset signal LCG_RST; at this time, the buffer unit 200 is used to buffer the low gain reset signal LCG_RST or the low gain image signal LCG_SIG; the storage unit 300 is used to store the low gain reset signal LCG_RST, the low gain image signal LCG_SIG, the high gain reset signal HCG_RST and the high gain image signal HCG_SIG, wherein the low gain reset signal LCG_RST or the low gain image signal LCG_SIG is provided by the buffer unit 200, and the other signals are provided by the signal generating unit 100; the signal output unit 400 is used to output the low gain reset signal LCG_RST, the low gain image signal LCG_SIG, the high gain reset signal HCG_RST and the high gain image signal HCG_SIG. It should be noted that the circuits of the above units are the same as those in the first embodiment, and will not be repeated here.

[0177] Accordingly, this embodiment also provides a control method of the image sensor 10 as described above. Figure 1 Taking the image sensor 10 shown as an example, the control method includes: based on the cache unit 200 caching the low gain reset signal LCG_RST or the low gain image signal LCG_SIG, based on the signal generation unit 100 and the cache unit 200 jointly providing the storage unit 300 with the low gain reset signal LCG_RST, the low gain image signal LCG_SIG, the high gain reset signal HCG_RST and the high gain image signal HCG_SIG. The details are as follows:

[0178] In the first operation (e.g., operation adapted to low illumination):

[0179] Based on the signal generating unit 100, a low gain reset signal LCG_RST, a high gain reset signal HCG_RST, a high gain image signal HCG_SIG and a low gain image signal LCG_SIG are generated; based on the cache unit 200, the low gain reset signal LCG_RST is cached; based on the storage unit 300 and the signal output unit 400, the high gain reset signal HCG_RST provided by the signal generating unit 100 is stored and output, the high gain image signal HCG_SIG provided by the signal generating unit 100 is stored and output, the low gain reset signal LCG_RST provided by the cache unit 200 is stored and output, and the low gain image signal LCG_SIG provided by the signal generating unit 100 is stored and output.

[0180] As an example, when the signal generating unit 100 includes a photosensitive unit 110, a reset unit 120, a gain control unit 130, and an amplifying output unit 140, Fig.11 , the control method under the first operation is described in detail. The control method under this operation includes:

[0181] Step 1) performing global exposure on the image sensor 10 .

[0182] Further, when the cache unit 200 includes a first storage device C2 and the storage unit 300 includes a second storage device C3 and a third storage device C4, before storing the low gain reset signal LCG_RST after exposure, the step also includes resetting the signals of the first storage device C2, the second storage device C3 and the third storage device C4.

[0183] For example, the second variable potential is set to a low potential, the first control transistor M6, the second control transistor M7, the third control transistor M8 and the fourth control transistor M9 are controlled to be turned on, the charge of the first storage device C2, the second storage device C3 and the third storage device C4 is cleared, and the signals of the three are reset. After that, the second variable potential is changed to a high potential, and the second control transistor M7, the third control transistor M8 and the fourth control transistor M9 are controlled to be turned off.

[0184] Step 2) Control the gain control unit 130 to be turned on and the reset unit 120 to be turned on to obtain the low gain reset signal LCG_RST, and cache the low gain reset signal LCG_RST based on the cache unit 200 .

[0185] For example, the first gain transistor M3 is controlled to be turned on, so that the image sensor 10 enters the LCG mode; the reset transistor M2 is controlled to be turned on and then turned off, the floating diffusion node FD is reset to obtain a low gain reset signal LCG_RST, and the low gain reset signal LCG_RST is cached in the first storage device C2 through the turned-on first control transistor M6, and then the first control transistor M6 is controlled to be turned off.

[0186] Step 3) Control the gain control unit 130 to be turned off to obtain the high gain reset signal HCG_RST, and store and output the high gain reset signal HCG_RST based on the storage unit 300 and the signal output unit 400.

[0187] For example, the first gain transistor M3 is controlled to be turned off, so that the image sensor 10 enters the HCG mode and obtains the high gain reset signal HCG_RST; then, the third control transistor M8 and the fourth control transistor M9 are controlled to be turned on, and the high gain reset signal HCG_RST is stored in the third storage device C4, and then the third control transistor M8 and the fourth control transistor M9 are controlled to be turned off; finally, the selection transistor M16 is controlled to be turned on, and the high gain reset signal HCG_RST is read out from the third storage device C4, and then the selection transistor M16 is controlled to be turned off.

[0188] Step 4) Control the photosensitive unit 110 to transfer the charge signal to obtain the high-gain image signal HCG_SIG, and store and output the high-gain image signal HCG_SIG based on the storage unit 300 and the signal output unit 400. Furthermore, before storing the high-gain image signal HCG_SIG, this step also includes resetting the signal of the second storage device C3.

[0189] For example, the second variable potential is set to a low potential, the third control transistor M8 is controlled to be turned on, the charge of the second storage device C3 is cleared to achieve signal resetting, and then the second variable potential is changed to a high potential.

[0190] Afterwards, the control transfer transistor M1 is turned on and then turned off, and the charge signal stored in the photosensitive element PD is transferred to the floating diffusion node FD to obtain a high-gain image signal HCG_SIG, and the high-gain image signal HCG_SIG is stored in the second storage device C3 through the turned-on third control transistor M8, and then the third control transistor M8 is turned off.

[0191] Finally, the fourth control transistor M9 and the selection transistor M16 are controlled to be turned on, and the high-gain image signal HCG_SIG is charge redistributed and read out based on the second storage device C3 and the third storage device C4 , and then the selection transistor M16 is controlled to be turned off.

[0192] Step 5) Based on the storage unit 300 and the signal output unit 400, the low gain reset signal LCG_RST in the cache unit 100 is stored and output. Further, before the low gain reset signal LCG_RST is stored, this step also includes resetting the signals of the second storage device C3 and the third storage device C4.

[0193] For example, the second variable potential is set to a low potential, the third control transistor M8 is controlled to be turned on, and then combined with the turned-on fourth control transistor M9, the charges of the second storage device C3 and the third storage device C4 are cleared to achieve signal resetting of the two. After that, the second variable potential is set to a high potential, and the third control transistor M8 and the fourth control transistor M9 are controlled to be turned off.

[0194] Then, the second control transistor M7 and the selection transistor M16 are controlled to be turned on, and the low gain reset signal LCG_RST buffered in the first storage device C2 is transferred and stored in the third storage device C4 and read out, and then the second control transistor M7 and the selection transistor M16 are controlled to be turned off.

[0195] Step 6) Control the gain control unit 130 to turn on and control the photosensitive unit 110 to transfer the charge signal to obtain a low-gain image signal LCG_SIG, and store and output the low-gain image signal LCG_SIG based on the storage unit 300 and the signal output unit 400.

[0196] For example, the first gain transistor M3 is controlled to be turned on, so that the image sensor 10 enters the LCG mode; the transfer transistor M1 is controlled to be turned on and then turned off, and the charge signal stored in the photosensitive element PD is transferred to the floating diffusion node FD to obtain the low gain image signal LCG_SIG, and the third control transistor M8 is controlled to be turned on, and the low gain image signal LCG_SIG is stored in the second storage device C3, and then the first gain transistor M3 and the third control transistor M8 are controlled to be turned off.

[0197] Finally, the fourth control transistor M9 and the selection transistor M16 are controlled to be turned on, and the low gain image signal LCG_SIG is charge redistributed and read out based on the second storage device C3 and the third storage device C4, and then the fourth control transistor M9 and the selection transistor M16 are controlled to be turned off.

[0198] In the second operation (e.g., operation adapted to high-illuminance light range):

[0199] Based on the signal generating unit 100, a low gain image signal LCG_SIG, a high gain reset signal HCG_RST, a high gain image signal HCG_SIG and a low gain reset signal LCG_RST are generated; based on the cache unit 200, the low gain image signal LCG_SIG is cached; based on the storage unit 300 and the signal output unit 400, the high gain reset signal HCG_RST provided by the signal generating unit 100 is stored and output, the high gain image signal HCG_SIG provided by the signal generating unit 100 is stored and output, the low gain image signal LCG_SIG provided by the cache unit 200 is stored and output, and the low gain reset signal LCG_RST provided by the signal generating unit 100 is stored and output.

[0200] As an example, when the signal generating unit 100 includes a photosensitive unit 110, a reset unit 120, a gain control unit 130, and an amplifying output unit 140, Fig.12 , the control method under the second operation is described in detail. The control method under this operation includes:

[0201] Step 1) Control the gain control unit 130 to turn on and perform global exposure on the image sensor 10 .

[0202] Further, when the cache unit 200 includes a first storage device C2 and the storage unit 300 includes a second storage device C3 and a third storage device C4, before storing the low gain image signal LCG_SIG after exposure, the step also includes resetting the signals of the first storage device C2, the second storage device C3 and the third storage device C4.

[0203] For example, the second variable potential is set to a low potential, the first control transistor M6, the second control transistor M7, the third control transistor M8 and the fourth control transistor M9 are controlled to be turned on, the charge of the first storage device C2, the second storage device C3 and the third storage device C4 is cleared, and the signals of the three are reset. After that, the second variable potential is changed to a high potential, and the second control transistor M7, the third control transistor M8 and the fourth control transistor M9 are controlled to be turned off.

[0204] Step 2) Control the photosensitive unit 110 to transfer the charge signal to obtain the low-gain image signal LCG_SIG, and cache the low-gain image signal LCG_SIG based on the cache unit 200.

[0205] For example, the transfer transistor M1 is controlled to be turned on and then turned off, and the charge signal stored in the photosensitive element PD is transferred to the floating diffusion node FD to obtain a low-gain image signal LCG_SIG; the low-gain image signal LCG_SIG is cached in the first storage device C2 through the turned-on first control transistor M6, and then the first control transistor M6 is controlled to be turned off.

[0206] Step 3) Control the reset unit 120 to be turned on and then turned off, and then control the gain control unit 130 to be turned off to obtain a high gain reset signal HCG_RST, and store and output the high gain reset signal HCG_RST based on the storage unit 300 and the signal output unit 140.

[0207] For example, the reset transistor M2 is controlled to be turned on and then turned off to reset the floating diffusion node FD, and then the first gain transistor M3 is controlled to be turned off to make the image sensor 10 enter the HCG mode and obtain the high gain reset signal HCG_RST;

[0208] Then, the third control transistor M8 and the fourth control transistor M9 are controlled to be turned on and then turned off, and the high gain reset signal HCG_RST is stored in the third storage device C4;

[0209] Finally, the selection transistor M16 is controlled to be turned on, and the high gain reset signal HCG_RST is read out from the third storage device C4 , and then the selection transistor M16 is controlled to be turned off.

[0210] Step 4) Control the photosensitive unit 110 to transfer the charge signal to obtain the high-gain image signal HCG_SIG, and store and output the high-gain image signal HCG_SIG based on the storage unit 300 and the signal output unit 400. Furthermore, before storing the high-gain image signal HCG_SIG, this step also includes resetting the signal of the second storage device C3.

[0211] For example, the second variable potential is set to a low potential, the third control transistor M8 is controlled to be turned on, the charge of the second storage device C3 is cleared to achieve signal resetting, and then the second variable potential is set to a high potential;

[0212] Then, the transfer transistor M1 is controlled to be turned on, and the charge signal stored in the photosensitive element PD is transferred to the floating diffusion node FD to obtain a high-gain image signal HCG_SIG, and the high-gain image signal HCG_SIG is stored in the second storage device C3 through the turned-on third control transistor M8, and then the third control transistor M8 is controlled to be turned off;

[0213] Finally, the fourth control transistor M9 and the selection transistor M16 are controlled to be turned on, and the high-gain image signal HCG_SIG is charge redistributed and read out based on the second storage device C3 and the third storage device C4 , and then the selection transistor M16 is controlled to be turned off.

[0214] Step 5) storing and outputting the low gain image signal LCG_SIG in the cache unit 200 based on the storage unit 300 and the signal output unit 400. Furthermore, before storing the low gain image signal LCG_SIG, this step also includes resetting the signals of the second storage device C3 and the third storage device C4.

[0215] For example, the second variable potential is set to a low potential, the third control transistor M8 is controlled to be turned on, and then combined with the turned-on fourth control transistor M9, the charges of the second storage device C3 and the third storage device C4 are cleared to achieve signal resetting of the two. After that, the second variable potential is set to a high potential, and the third control transistor M8 and the fourth control transistor M9 are controlled to be turned off.

[0216] Then, the second control transistor M7 and the selection transistor M16 are controlled to be turned on, and the low gain image signal LCG_SIG buffered in the first storage device C2 is transferred and stored in the third storage device C4 and read out, and then the second control transistor M7 and the selection transistor M16 are controlled to be turned off.

[0217] Step 6) Control the gain control unit 130 to be turned on and the reset unit 120 to be turned on and then turned off to obtain a low gain reset signal LCG_RST, and store and output the low gain reset signal LCG_RST based on the storage unit 300 and the signal output unit 400.

[0218] For example, the first gain transistor M3 is controlled to be turned on, so that the image sensor 10 enters the LCG mode; the reset transistor M2 is controlled to be turned on and then turned off, the floating diffusion node FD is reset and the low gain reset signal LCG_RST is obtained, and then the first gain transistor M3 is controlled to be turned off;

[0219] Then, the third control transistor M8 is controlled to be turned on and then turned off, and the low gain reset signal LCG_RST is stored in the second storage device C3;

[0220] Finally, the fourth control transistor M9 and the selection transistor M16 are controlled to be turned on, and the low gain reset signal LCG_RST is charged and redistributed and read out based on the second storage device C3 and the third storage device C4, and then the fourth control transistor M9 and the selection transistor M16 are controlled to be turned off.

[0221] It should be noted that those skilled in the art may perform the first operation and the second operation on the image sensor according to actual needs, and may apply different operations separately, or may combine different operations to obtain a final signal to improve the dynamic range.

[0222] In summary, in an image sensor and control method of the present invention, a cache unit is used in conjunction with a storage unit, and the cache unit is used to cache signals, so that the reuse of storage devices in the storage unit can be realized, thereby reducing the number of storage devices required in a single pixel circuit, and the PGHDR operation of the image sensor under global exposure can be realized with at least three storage devices. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0223] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. An image sensor, characterized in that: include: A signal generating unit, a cache unit, a storage unit and a signal output unit; wherein: The signal generating unit generates a low gain image signal, a high gain reset signal and a high gain image signal based on different conversion gain modes; The buffer unit is coupled to the signal generating unit and is at least used to buffer the low-gain image signal; The storage unit is coupled to the signal generating unit and the buffer unit, and is used to store the low-gain image signal, the high-gain reset signal, and the high-gain image signal; wherein the low-gain image signal is provided by the buffer unit, and the remaining signals are provided by the signal generating unit; The signal output unit is coupled to the storage unit, and is configured to output the low-gain image signal, the high-gain reset signal, and the high-gain image signal.

2. The image sensor according to claim 1, characterized in that The signal generating unit also generates a low gain reset signal; at this time, the cache unit is used to cache the low gain reset signal or the low gain image signal; the storage unit is used to store the low gain reset signal, the low gain image signal, the high gain reset signal and the high gain image signal, wherein the low gain reset signal or the low gain image signal is provided by the cache unit, and the remaining signals are provided by the signal generating unit; the signal output unit is used to output the low gain reset signal, the low gain image signal, the high gain reset signal and the high gain image signal.

3. The image sensor according to claim 1, characterized in that The cache unit includes: a first control transistor, a second control transistor and a first storage device; The control terminal of the first control transistor receives a first control signal, the first terminal is coupled to the output terminal of the signal generating unit, and the second terminal is coupled to the first storage device and the first terminal of the second control transistor; The second terminal of the first storage device is coupled to a first reference potential; A control terminal of the second control transistor receives a second control signal, and a second terminal serves as an output terminal of the cache unit.

4. The image sensor according to claim 1, characterized in that The storage unit comprises: a third control transistor, a fourth control transistor, a second storage device and a third storage device; The control terminal of the third control transistor receives a third control signal, the first terminal is coupled to the output terminal of the signal generating unit, and the second terminal is coupled to the second storage device and the first terminal of the fourth control transistor; The second terminal of the second storage device is coupled to a second reference potential; The control terminal of the fourth control transistor receives a fourth control signal, and the second terminal is coupled to the first terminal of the third storage device; A first terminal of the third storage device is coupled to the output terminal of the cache unit and serves as the output terminal of the storage unit, and a second terminal of the third storage device is coupled to a third reference potential.

5. The image sensor according to claim 4, characterized in that: The storage unit further includes: a fifth control transistor and / or a sixth control transistor; The control terminal of the fifth control transistor receives a fifth control signal, the first terminal is coupled to the output terminal of the signal generating unit, and the second terminal is coupled to the first terminal of the third storage device; The control terminal of the sixth control transistor receives a sixth control signal, the first terminal is coupled to the first variable potential, and the second terminal is coupled to the first terminal of the third storage device.

6. The image sensor according to claim 1, characterized in that: The signal generating unit comprises: a photosensitive unit, a floating diffusion node, a reset unit, a gain control unit and an amplifying output unit; wherein: The photosensitive unit receives a light signal and generates a charge signal based on the light signal and transfers it to the floating diffusion node; The reset unit is coupled to the floating diffusion node and is used to reset the floating diffusion node; The gain control unit is coupled to the floating diffusion node and is used to switch different conversion gain modes to generate the low gain image signal, the high gain reset signal and the high gain image signal based on the floating diffusion node; The amplifying output unit is coupled to the floating diffusion node, and is configured to output the low-gain image signal, the high-gain reset signal, and the high-gain image signal.

7. The image sensor according to claim 6, characterized in that: The photosensitive unit includes at least one photosensitive element and a transmission transistor corresponding thereto; a control end of the transmission transistor receives a transmission control signal, a first end is coupled to the floating diffusion node, a second end is coupled to a first end of the photosensitive element, and a second end of the photosensitive element is coupled to a fourth reference potential; And / or, the reset unit comprises a reset transistor, a control terminal receiving a reset control signal, a first terminal coupled to a first power supply potential, and a second terminal coupled to the floating diffusion node; And / or, the amplifying output unit includes a first source follower transistor, a control end of which is coupled to the floating diffusion node, a first end of which is coupled to a second variable potential, and a second end of which serves as an output end of the signal generating unit.

8. The image sensor according to claim 6, characterized in that: The gain control unit includes a first gain transistor and an overflow capacitor; wherein the first gain transistor is coupled between the reset unit and the floating diffusion node, and the overflow capacitor is coupled between a coupling node between the reset unit and the first gain transistor and a fifth reference potential; or, the first gain transistor and the overflow capacitor are coupled in series to the floating diffusion node.

9. The image sensor according to claim 8, characterized in that: The gain control unit also includes: at least one second gain transistor; when the first gain transistor is coupled between the reset unit and the floating diffusion node, the second gain transistor is coupled between the first gain transistor and the floating diffusion node; when the first gain transistor and the overflow capacitor are coupled in series to the floating diffusion node, the second gain transistor is coupled between the reset unit and the floating diffusion node.

10. The image sensor according to claim 9, characterized in that: The image sensor further includes: a storage unit matched with the second gain transistor, for storing a reset signal and an image signal in a corresponding conversion gain mode; wherein the matched storage unit includes: a seventh control transistor, an eighth control transistor, a ninth control transistor, a fourth storage device and a fifth storage device; The control end of the seventh control transistor receives the seventh control signal, the first end is coupled to the output end of the signal generating unit, and the second end is coupled to the fourth storage device and the first end of the eighth control transistor; the second end of the fourth storage device is coupled to the sixth reference potential; the control end of the eighth control transistor receives the eighth control signal, the second end is coupled to the fifth storage device and the first end of the ninth control transistor; the second end of the fifth storage device is coupled to the seventh reference potential; the control end of the ninth control transistor receives the ninth control signal, and the second end serves as the output end of the matching storage unit.

11. The image sensor according to claim 1, characterized in that: The signal output unit comprises: a second source follower transistor and a selection transistor; the control end of the second source follower transistor is coupled to the output end of the storage unit, the first end is coupled to the second power supply potential, and the second end is coupled to the first end of the selection transistor; the control end of the selection transistor receives a selection control signal, and the second end serves as the output end of the signal output unit to be coupled to the column line; Alternatively, the signal output unit includes two sub-units, which are respectively coupled to the output ends of the cache unit and the storage unit to output corresponding signals, wherein the two sub-units are coupled to the same or different column lines; at this time, the storage unit is not coupled to the cache unit, and the storage unit no longer stores the signal in the cache unit.

12. The image sensor according to any one of claims 1 to 11, characterized in that: The image sensor further includes a rolling exposure transistor coupled between the output terminal of the signal generating unit and the column line.

13. A method for controlling an image sensor according to any one of claims 1 to 12, characterized in that: include: The high-gain reset signal and the high-gain image signal are stored separately based on the storage unit, and the low-gain image signal is cached based on the cache unit; wherein the low-gain image signal includes an overflow signal.

14. The control method according to claim 13, characterized in that: When the signal generating unit includes a photosensitive unit, a reset unit, a gain control unit and an amplifying output unit, the method includes: performing global exposure on the image sensor; Controlling the reset unit and the gain control unit to be turned on and then turned off to obtain the high-gain reset signal; storing the high-gain reset signal based on the storage unit; Controlling the photosensitive unit to transfer charges to obtain the high-gain image signal, and storing the high-gain image signal based on the storage unit; The gain control unit is controlled to open and the photosensitive unit is controlled to perform charge transfer to obtain the low-gain image signal, and the low-gain image signal is cached based on the cache unit.

15. The control method according to claim 14, characterized in that: When the cache unit includes a first storage device and the storage unit includes a second storage device and a third storage device, the method further includes: Before obtaining the high-gain reset signal, a step of resetting signals of the first storage device, the second storage device and the third storage device; and / or, before storing the high-gain image signal, performing a signal resetting step on the second storage device; and / or, before storing the overflow signal, performing a signal resetting step on the first storage device; And / or, when the storage unit includes a sixth control transistor, after the high-gain reset signal is read out and before the low-gain image signal is read out, the method further includes: Acquire a low-gain reset signal based on the sixth control transistor and store it in the third storage device; After the low-gain reset signal is read out, the low-gain image signal is charged and redistributed based on the first storage device and the third storage device and read out.

16. A method for controlling an image sensor according to any one of claims 1 to 12, characterized in that: include: The cache unit caches the low gain reset signal or the low gain image signal, and the signal generating unit and the cache unit jointly provide the storage unit with the low gain reset signal, the low gain image signal, the high gain reset signal and the high gain image signal.

17. The control method according to claim 16, characterized in that: include: First operation: generating the low gain reset signal, the high gain reset signal, the high gain image signal and the low gain image signal based on the signal generating unit; caching the low gain reset signal based on the cache unit; Based on the storage unit and the signal output unit, the high-gain reset signal provided by the signal generating unit is stored and output, the high-gain image signal provided by the signal generating unit is stored and output, the low-gain reset signal provided by the buffer unit is stored and output, and the low-gain image signal provided by the signal generating unit is stored and output; And / or, second operation: The low-gain image signal, the high-gain reset signal, the high-gain image signal and the low-gain reset signal are generated based on the signal generating unit; the low-gain image signal is cached based on the cache unit; based on the storage unit and the signal output unit, the high-gain reset signal provided by the signal generating unit is stored and output, the high-gain image signal provided by the signal generating unit is stored and output, the low-gain image signal provided by the cache unit is stored and output, and the low-gain reset signal provided by the signal generating unit is stored and output.

18. The control method according to claim 17, characterized in that: When the signal generating unit includes a photosensitive unit, a reset unit, a gain control unit and an amplifying output unit, the method includes: Corresponding to the first operation, performing global exposure on the image sensor; Controlling the gain control unit to be turned on and the reset unit to be turned on to obtain the low gain reset signal, and caching the low gain reset signal based on the cache unit; Controlling the gain control unit to be turned off to obtain the high-gain reset signal, and storing and outputting the high-gain reset signal based on the storage unit and the signal output unit; Controlling the photosensitive unit to transfer the charge signal to obtain the high-gain image signal, and storing and outputting the high-gain image signal based on the storage unit and the signal output unit; storing and outputting the low-gain reset signal in the cache unit based on the storage unit and the signal output unit; Control the gain control unit to turn on and control the photosensitive unit to transfer the charge signal to obtain the low-gain image signal, and store and output the low-gain image signal based on the storage unit and the signal output unit; and / or, corresponding to the second operation, controlling the gain control unit to turn on and performing global exposure on the image sensor; Controlling the photosensitive unit to transfer the charge signal to obtain the low-gain image signal, and caching the low-gain image signal based on the cache unit; Controlling the reset unit to be turned on and then turned off, and then controlling the gain control unit to be turned off to obtain the high-gain reset signal, and storing and outputting the high-gain reset signal based on the storage unit and the signal output unit; Controlling the photosensitive unit to transfer the charge signal to obtain the high-gain image signal, and storing and outputting the high-gain image signal based on the storage unit and the signal output unit; storing and outputting the low-gain image signal in the buffer unit based on the storage unit and the signal output unit; The gain control unit is controlled to be turned on and the reset unit is turned on and then turned off to obtain the low gain reset signal, and the low gain reset signal is stored and output based on the storage unit and the signal output unit.

Images