Semiconductor structure, memory and method of manufacturing thereof

Abstract

The present disclosure relates to a semiconductor structure, a memory and a preparation method thereof, comprising an active pillar, two channel layers, two gates and two insulating layers, the two channel layers are respectively located on two surfaces of the active pillar opposite along a first direction, the channel layer comprises a first surface facing away from the active pillar along the first direction and a second surface and a third surface opposite along a second direction, the first direction intersects the second direction; the two gates respectively cover the first surface, the second surface and the third surface of one channel layer; the two insulating layers are respectively located on the surfaces of the active pillar opposite along the second direction and between the two gates, at least the width of the transistor channel in a single storage unit structure can be increased without reducing the number of storage units per unit volume.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuit design and manufacturing, and in particular to a semiconductor structure, a memory and a preparation method thereof. Background Art

[0002] With the continuous advancement of integrated circuit manufacturing processes, the market has placed higher demands on the storage capacity and performance of semiconductor memory products. The miniaturization of two-dimensional memory arrays poses significant challenges to both process and manufacturing equipment. Vertically stacking multiple layers of two-dimensional memory cell arrays has become a key technological development direction to achieve high-density storage.

[0003] However, the volume and spacing of memory cells in three-dimensional stacked memories continue to decrease, resulting in increasing complexity in the preparation of memory cells, and the performance and reliability need to be improved urgently. Summary of the Invention

[0004] Based on this, the present disclosure provides a semiconductor structure, a memory and a method for preparing the same, which can at least increase the width of the transistor channel in a single memory cell structure while ensuring that the number of memory cells per unit volume does not decrease, thereby reducing the complexity of the preparation process and improving the performance and reliability of the prepared product.

[0005] According to various embodiments of the present disclosure, on the one hand, a semiconductor structure is provided, including an active pillar, two channel layers, two gates and two insulating layers, the two channel layers are respectively located on two surfaces of the active pillar opposite to each other along a first direction, the channel layer includes a first surface facing away from the active pillar along the first direction and a second surface and a third surface opposite to each other along a second direction, and the first direction intersects with the second direction; the two gates respectively cover the first surface, the second surface and the third surface of a channel layer; the two insulating layers are respectively located on surfaces of the active pillar opposite to each other along the second direction, and are located between the two gates.

[0006] In the semiconductor structure of the above embodiment, corresponding channel layers are formed on two surfaces of the active pillar that are opposite to each other along the first direction. The channel layer includes a first surface facing away from the active pillar along the first direction and a second surface and a third surface that are opposite to each other along the second direction. The first direction intersects with the second direction. The two gates respectively cover the first surface, the second surface and the third surface of a channel layer, effectively increasing the channel width and the contact area between the gate and the channel layer, thereby effectively improving the performance of the prepared transistor; by arranging two insulating layers respectively located on the surfaces of the active pillar that are opposite to each other along the second direction and located between the two gates, the gate conductive layers of the two gates are isolated by the two insulating layers located on the two opposite sides of the active pillar along the second direction, and the two gates share a channel layer, which can reduce the volume of the prepared semiconductor device while reducing the power consumption of the device; the threshold voltage of the other gate can be modulated by applying a bias voltage to one gate, which can effectively improve the performance and reliability of the semiconductor structure.

[0007] According to some embodiments, the gate includes a gate dielectric layer and a gate conductive layer. The gate dielectric layer is located on the same side of two insulating layers along a first direction and covers the first, second, and third surfaces of a channel layer. The gate conductive layer is located on the same side of the two insulating layers along the first direction and covers the outer surface of the gate dielectric layer. For example, two gates can be provided to cover the outer surface of corresponding channel layers, effectively increasing the channel width and the contact area between the gate and the channel layer, thereby effectively improving the performance of the fabricated transistor.

[0008] According to some embodiments, the channel layer and the active pillar have the same doping type; the doping concentration of the channel layer is 1E17 cm -3 -1E18cm -3 .

[0009] According to some embodiments, the channel layer has a thickness of 5 nm-10 nm.

[0010] According to some embodiments, the semiconductor structure further includes a bit line and a capacitor located on opposite sides of the gate along a third direction; the third direction intersects with both the first direction and the second direction; the capacitor is located at one end of the active column away from the bit line along the third direction; the cross-section of the capacitor parallel to the first direction and the second direction is "H"-shaped.

[0011] According to some embodiments, the portion of the active column covered by the capacitor includes a first surface and a fourth surface opposite to each other along a first direction, and a second surface and a third surface opposite to each other along a second direction; the semiconductor structure also includes two insulating capping layers, the two insulating capping layers are respectively located on the second surface and the third surface of the portion of the active column covered by the capacitor, the insulating capping layer includes two extensions spaced apart along the first direction and a first insulating capping layer located between the two extensions, the two first insulating capping layers respectively cover the second surface and the third surface of the portion of the active column covered by the capacitor; the capacitor covers the first surface, the fourth surface of the active column, the surface of the extension away from the first insulating capping layer along the first direction, and the surface close to the active column along the second direction.

[0012] According to some embodiments, a length of a portion of the active pillar covered by the channel layer along the first direction is smaller than a length of a portion of the active pillar covered by the capacitor along the first direction.

[0013] According to some embodiments, the capacitor includes a first electrode layer, an intermediate dielectric layer and a second electrode layer, the first electrode layer covers at least the first surface, the fourth surface, and the surface of the extension portion close to the active column along the second direction of the active column; the intermediate dielectric layer covers the outer surface of the first electrode layer, the surface of the extension portion along the first direction away from the active column, and the surface of the active column along the third direction away from the gate; the second electrode layer covers the outer surface of the intermediate dielectric layer.

[0014] According to some embodiments, the material of the first insulating capping layer includes silicon oxide; and / or the material of the extension portion includes silicon nitride.

[0015] According to some embodiments, the present disclosure provides a memory on the other hand, including a target layer stacked along a second direction; the target layer includes a plurality of semiconductor structures of any one of the embodiments of the present disclosure arranged at intervals along a first direction; adjacent gates along the second direction are electrically connected; adjacent semiconductor structures along the first direction in the target layer share a bit line extending along the first direction; semiconductor structures in different target layers are connected to different bit lines.

[0016] According to some embodiments, the present disclosure provides a method for preparing a memory device on another aspect, comprising: providing a substrate, forming a target stacked structure arranged at intervals along a first direction and a double-gate fence located on opposite sides of the target stacked structure along the first direction on the substrate, the target stacked structure comprising insulating layers and active pillars arranged alternately along a second direction, the active pillars being located between adjacent insulating layers along the second direction; the double-gate fence defines double-gate trenches located on opposite sides of the active pillars along the first direction; the portion of the insulating layer located within the double-gate trenches covers the opposite surfaces of the portion of the active pillars located within the double-gate trenches along the second direction; the first direction intersects with the second direction; channel layers are formed on the opposite surfaces of the active pillars in the double-gate trenches along the first direction; a gate corresponding to the channel layer is formed in the double-gate trenches, a gate covering the first surface of the corresponding channel layer facing away from the active pillar along the first direction and the second surface and third surface opposite along the second direction, and the gates adjacent to each other along the second direction are electrically connected.

[0017] In the method for preparing the semiconductor structure in the above embodiment, corresponding channel layers are formed on two surfaces of the active pillar that are opposite to each other along the first direction, and the channel layer includes a first surface facing away from the active pillar along the first direction and a second surface and a third surface that are opposite to each other along the second direction. The first direction intersects with the second direction, and the two gates respectively cover the first surface, the second surface and the third surface of a channel layer, effectively increasing the channel width and the contact area between the gate and the channel layer, thereby effectively improving the performance of the prepared transistor; by arranging two insulating layers respectively located on the surfaces of the active pillar that are opposite to each other along the second direction and between the two gates of the common channel layer, the gate conductive layers of the two gates of the common channel layer are isolated by the two insulating layers located on the two opposite sides of the active pillar along the second direction, thereby reducing the volume of the prepared semiconductor device while reducing the power consumption of the device; the threshold voltage of the other gate can be modulated by applying a bias voltage to one gate, thereby effectively improving the performance and reliability of the semiconductor structure.

[0018] According to some embodiments, forming channel layers on opposite surfaces of active pillars in a dual-gate trench along a first direction includes:

[0019] forming an epitaxial layer on the exposed surface of the active pillar in the dual-gate trench by adopting a selective epitaxial growth process;

[0020] Ion implantation is performed on the epitaxial layer to form a channel layer.

[0021] According to some embodiments, forming a target stacked structure and a dual-gate trench on a substrate includes:

[0022] forming, on a substrate, target stacked structures arranged at intervals along a first direction, frame isolation structures adjacent to the target stacked structures on opposite sides along the first direction, and an intermediate isolation structure located between the frame isolation structures adjacent to each other along the first direction, wherein the frame isolation structure includes interlayer isolation layers and interlayer insulating layers alternately arranged along a second direction, and the interlayer insulating layer is located between the interlayer isolation layers adjacent to each other along the second direction;

[0023] Etching the middle isolation structure to obtain a double-gate wall gap;

[0024] forming a double-gate fence within the gap between the double-gate fences;

[0025] The middle isolation structure, the interlayer insulating layer and the interlayer isolation layer surrounded by the double-gate wall are removed to obtain the double-gate trench.

[0026] According to some embodiments, before forming the channel layer, the method further includes: reducing the length of the portion of the active pillar used to form the channel layer along the first direction.

[0027] According to some embodiments, before or after forming a gate corresponding to the channel layer in the dual-gate trench, the method further includes:

[0028] forming a conductive portion on the substrate and located on one side of the target stacked structure along the third direction, the conductive portion including a vertical conductive portion extending along the second direction and a horizontal conductive portion located between the vertical conductive portion and the active pillar, the horizontal conductive portion extending along the third direction, being disposed corresponding to the active pillar and electrically connecting the vertical conductive portion and the corresponding horizontal conductive portion; the third direction intersects both the first direction and the second direction;

[0029] Removing the vertical conductive portion to obtain a vertical groove;

[0030] forming a vertical insulating portion in the vertical groove;

[0031] The intermediate isolation structure located between adjacent frame isolation structures along the first direction, as well as the portion of the frame isolation structure on the same layer as the active pillar, is removed to expose the surfaces of the active pillar outside the dual-gate enclosure that are opposite to each other in the first direction, thereby forming a second groove. The frame isolation structure remaining on the two opposite outer surfaces of the active pillar along the first direction for forming a capacitor portion is used to form two extension portions. The capacitor portion of the active pillar is the portion of the active pillar located along the third direction of the dual-gate enclosure away from the vertical insulating portion.

[0032] A target doping process is performed on the active pillar through the second groove to obtain a doped active pillar; the target doping process includes a plasma doping process and / or an atomic layer deposition doping process.

[0033] According to some embodiments, portions of the insulating layer located on two outer surfaces of the active pillar for forming a capacitor portion along the second direction constitute a first insulating cap layer, and two adjacent extensions along the first direction and the first insulating cap layer located between the two extensions constitute an insulating cap layer; after forming the doped active pillar, the method further includes:

[0034] forming a first electrode layer, the first electrode layer covering two outer surfaces of the doped active pillar located in a portion of the double gate wall away from the vertical insulating portion in the third direction and facing each other in the first direction, and a surface of the extension portion close to the doped active pillar in the second direction;

[0035] forming an intermediate dielectric layer covering the outer surface of the first electrode layer, wherein different first electrode layers are insulated from each other via an insulating cap layer;

[0036] A second electrode layer is formed to cover the outer surface of the intermediate dielectric layer; the first electrode layer, the intermediate dielectric layer covering the outer surface of the first electrode layer, and the second electrode layer are used to jointly form a capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0038] Figure 1 A schematic flow chart of a preparation method provided in one embodiment of the present disclosure;

[0039] Figure 2 is a schematic three-dimensional cross-sectional view of forming an initial stacked structure on a substrate in some embodiments of the present disclosure;

[0040] Figure 3a For Figure 2 The etching stop lines L1 and L2 shown in FIG are etching end points. After side etching the two opposite surfaces of the sacrificial layer along the oz direction, the cross-sectional structure of the obtained three-dimensional structure along the AA' direction is schematically shown.

[0041] Figure 3b For Figure 2 The etching stop lines L3 and L4 shown in FIG are etching end points. After the surfaces of the sacrificial layer opposite to each other along the ox direction are laterally etched, the cross-sectional structure of the obtained three-dimensional structure along the BB' direction is shown.

[0042] Figure 4a For Figure 3b The corresponding three-dimensional structure along Figure 2 Schematic diagram of the cross-sectional structure obtained in the AA' direction shown in FIG;

[0043] Figure 4b For Figure 3b The corresponding three-dimensional structure along Figure 2 Schematic diagram of the cross-sectional structure obtained in the BB' direction shown in FIG;

[0044] Figure 5a For the general Figure 4a and Figure 4b After the sacrificial layer corresponding to the three-dimensional structure is removed, an interlayer dielectric layer is formed in the internal gap obtained, and the three-dimensional structure obtained is along the Figure 2 Schematic diagram of the cross-sectional structure obtained in the AA' direction shown in FIG;

[0045] Figure 5b for Figure 5a Corresponding to the three-dimensional structure Figure 2 Schematic diagram of the cross-sectional structure obtained in the BB' direction shown in FIG;

[0046] Figure 6a For Figure 5a 、 Figure 5b After the three-dimensional structure shown in the figure is provided with the first groove and the middle insulating layer and the middle active column conformally stacked along the second direction, the obtained three-dimensional structure is formed along the Figure 2 Schematic diagram of the cross-sectional structure obtained in the AA' direction shown in FIG;

[0047] Figure 6b for Figure 6a Corresponding to the three-dimensional structure Figure 2 Schematic diagram of the cross-sectional structure obtained in the BB' direction shown in FIG;

[0048] Figure 7a For Figure 6a 、 Figure 6b After forming a sacrificial insulating layer in the first groove of the three-dimensional structure shown in FIG, the obtained three-dimensional structure is formed along Figure 2 Schematic diagram of the cross-sectional structure obtained in the AA' direction shown in FIG;

[0049] Figure 7b for Figure 7a Corresponding to the three-dimensional structure Figure 2 Schematic diagram of the cross-sectional structure obtained in the BB' direction shown in FIG;

[0050] Figure 8a For Figure 7a 、 Figure 7b After forming the first insulating layer, active pillars and interlayer isolation layers on the corresponding three-dimensional structure, the obtained three-dimensional structure is Figure 2 Schematic diagram of the cross-sectional structure obtained in the AA' direction shown in FIG;

[0051] Figure 8b for Figure 8a Corresponding to the three-dimensional structure Figure 2Schematic diagram of the cross-sectional structure obtained in the BB' direction shown in FIG;

[0052] Figure 9a For Figure 8a 、 Figure 8b After the first groove and the insulating column are formed on the corresponding three-dimensional structure, the obtained three-dimensional structure is formed along Figure 2 Schematic diagram of the cross-sectional structure obtained in the AA' direction shown in FIG;

[0053] Figure 9b for Figure 9a Corresponding to the three-dimensional structure Figure 2 Schematic diagram of the cross-sectional structure obtained in the BB' direction shown in FIG;

[0054] Figure 10 For Figure 9a 、 Figure 9b Schematic diagram of the three-dimensional structure obtained after forming active pillars on the corresponding three-dimensional structure;

[0055] Figure 11a for Figure 10 A schematic diagram of the cross-sectional structure of the three-dimensional structure shown along the AA' direction;

[0056] Figure 11b for Figure 10 A schematic diagram of the cross-sectional structure of the three-dimensional structure shown along the BB' direction;

[0057] Figure 12 For Figure 10 A schematic diagram of the three-dimensional structure obtained after forming the target stacked structure, the frame isolation structure and the double-gate wall on the three-dimensional structure shown;

[0058] Figure 13a for Figure 12 A schematic diagram of the cross-sectional structure of the three-dimensional structure shown along the BB' direction;

[0059] Figure 13b for Figure 12 The schematic diagram of the cross-sectional structure of the three-dimensional structure shown in FIG. 1 is obtained along the CC' direction; wherein, Figure 12 The schematic diagram of the cross-sectional structure of the three-dimensional structure along the AA' direction is as follows Figure 11a As shown;

[0060] Figure 14 For Figure 10 A schematic diagram of a three-dimensional structure obtained after forming a double-gate trench on the three-dimensional structure shown;

[0061] Figure 15 for Figure 14 The schematic diagram of the cross-sectional structure of the three-dimensional structure shown in FIG. 1 is obtained along the CC' direction; wherein, Figure 14 The schematic diagram of the cross-sectional structure along the AA' direction of the three-dimensional structure shown is as follows Figure 11a As shown, Figure 14 The schematic diagram of the cross-sectional structure along the BB' direction of the three-dimensional structure shown in FIG. Figure 13a As shown;

[0062] Figure 16 For Figure 14 A schematic diagram of the three-dimensional structure obtained after a gate is formed on the three-dimensional structure shown;

[0063] Figure 17 for Figure 16 The schematic diagram of the cross-sectional structure of the three-dimensional structure shown in FIG. 1 is obtained along the CC' direction; wherein, Figure 16 The schematic diagram of the cross-sectional structure along the AA' direction of the three-dimensional structure shown is as follows Figure 11a As shown, Figure 14 The schematic diagram of the cross-sectional structure along the BB' direction of the three-dimensional structure shown in FIG. Figure 13a As shown;

[0064] Figure 18 For Figure 16 A schematic diagram of the three-dimensional structure obtained after forming the horizontal conductive portion and the vertical insulating portion on the three-dimensional structure shown;

[0065] Figure 19 for Figure 18 The schematic diagram of the cross-sectional structure of the three-dimensional structure shown in FIG. 1 is obtained along the AA' direction; wherein, Figure 18 The schematic diagram of the cross-sectional structure along the BB' direction of the three-dimensional structure shown in FIG. Figure 13a As shown; Figure 18 The schematic diagram of the cross-sectional structure of the three-dimensional structure along the CC' direction is as follows Figure 17 As shown;

[0066] Figure 20 For Figure 18 A schematic diagram of the three-dimensional structure obtained after forming a second groove on the three-dimensional structure;

[0067] Figure 21 for Figure 20 Schematic diagram of the cross-sectional structure of the three-dimensional structure shown along the DD' direction or the EE' direction;

[0068] Figure 22 For Figure 20 Schematic diagram of the three-dimensional structure obtained after forming a protective layer on the three-dimensional structure and removing part of the protective layer and the insulating pillars to expose the protrusions;

[0069] Figure 23a for Figure 22 A schematic diagram of the cross-sectional structure of the three-dimensional structure shown along the AA' direction;

[0070] Figure 23b for Figure 22 The schematic diagram of the cross-sectional structure of the three-dimensional structure shown in FIG. 1 is obtained along the DD' direction; wherein, Figure 22 The schematic diagram of the cross-sectional structure along the BB' direction of the three-dimensional structure shown in FIG. Figure 13a As shown; Figure 22 The schematic diagram of the cross-sectional structure of the three-dimensional structure along the CC' direction is as follows Figure 17 As shown;

[0071] Figure 24 For Figure 22 A schematic diagram of a three-dimensional structure obtained after forming a first electrode layer on the three-dimensional structure shown;

[0072] Figure 25 for Figure 24 The schematic diagram of the cross-sectional structure of the three-dimensional structure shown in FIG. 1 is obtained along the DD' direction; wherein, Figure 24 The schematic diagram of the cross-sectional structure along the AA' direction of the three-dimensional structure shown is as follows Figure 23a As shown; Figure 24 The schematic diagram of the cross-sectional structure along the BB' direction of the three-dimensional structure shown in FIG. Figure 13a As shown; Figure 22 The schematic diagram of the cross-sectional structure of the three-dimensional structure along the CC' direction is as follows Figure 17 As shown;

[0073] Figure 26 For Figure 24 A schematic diagram of the three-dimensional structure obtained after forming an intermediate dielectric layer and a second electrode layer on the three-dimensional structure shown;

[0074] Figure 27a for Figure 26 A schematic diagram of the cross-sectional structure of the three-dimensional structure shown along the AA' direction;

[0075] Figure 27b for Figure 26 The schematic diagram of the cross-sectional structure of the three-dimensional structure shown in FIG. 1 is obtained along the DD' direction; wherein, Figure 26 The schematic diagram of the cross-sectional structure along the BB' direction of the three-dimensional structure shown in FIG. Figure 13a As shown; Figure 26 The schematic diagram of the cross-sectional structure of the three-dimensional structure along the CC' direction is as follows Figure 17 As shown;

[0076] Figure 28 A schematic diagram of a three-dimensional structure of a semiconductor structure provided in some embodiments of the present disclosure;

[0077] Figure 29a for Figure 28 A schematic diagram of the cross-sectional structure of the three-dimensional structure shown along the BB' direction;

[0078] Figure 29b for Figure 28 A schematic diagram of the cross-sectional structure of the three-dimensional structure shown along the DD' direction;

[0079] Figure 30 A schematic diagram of the three-dimensional structure of a memory provided in some embodiments of the present disclosure.

[0080] Description of reference numerals:

[0081] 100, target stack structure; 100', initial stack structure; 101, insulating layer; 300, frame isolation structure; 301, interlayer insulating layer; 302, interlayer insulating layer; 400, intermediate isolation structure; 402, double gate wall; 501, horizontal conductive portion; 10, substrate; 11, sacrificial layer; 12, cap layer; 13, first hole; 20', active layer; 201, initial active pillar; 202, first active portion; 203, second active portion; 204, insulating material layer; 2041, interlayer dielectric layer; 2042, intermediate insulating layer; 205, isolation material; 20 7. First groove; 2071. Sacrificial insulating layer; 20a. Protrusion; 209. Interlayer isolation layer; 210. First groove; 211. Insulating pillar; 20. Active pillar; 212. Double-gate trench; 30. Channel layer; 40. Gate; 41. Gate dielectric layer; 42. Gate conductive layer; 213. Doped active pillar; 60. Insulating cap layer; 61. Extension; 62. First insulating cap layer; 601. Vertical insulating portion; 602. Second groove; 603. Protective layer; 70. Capacitor; 71. First electrode layer; 72. Intermediate dielectric layer; 73. Second electrode layer; 80. Bit line. DETAILED DESCRIPTION

[0082] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present disclosure. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0083] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0084] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0085] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0086] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0087] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present disclosure. Although the illustrations only show components related to the present disclosure and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation can be changed arbitrarily, and the component layout type may also be more complex.

[0088] Please note that the mutual insulation between the two described in the embodiments of the present disclosure includes but is not limited to at least one of the presence of an insulating material layer, an insulating atmosphere or a gap between the two; the "conformal superposition" of A and B formed on the substrate described in the embodiments of the present disclosure is intended to express the following meaning: the orthographic projection of A on the top surface of the substrate and the orthographic projection of B on the top surface of the substrate completely overlap.

[0089] Please refer to Figure 1 In some embodiments of the present disclosure, a preparation method is provided, comprising the following steps:

[0090] Step S10: providing a substrate, and forming on the substrate a target stacked structure arranged at intervals along a first direction and dual-gate walls located on opposite sides of the target stacked structure along the first direction, wherein the target stacked structure includes insulating layers and active pillars alternately arranged along a second direction, wherein the active pillars are located between adjacent insulating layers along the second direction; the dual-gate walls define dual-gate trenches located on opposite sides of the active pillars along the first direction; portions of the insulating layers located within the dual-gate trenches cover surfaces of portions of the active pillars located within the dual-gate trenches that are opposite to each other along the second direction; and the first direction intersects the second direction.

[0091] Step S20: forming channel layers on opposite surfaces of the active pillars in the dual-gate trenches along a first direction;

[0092] Step S30: forming gates corresponding to the channel layers in the dual-gate trenches, one gate covering a first surface of the corresponding channel layer away from the active pillar along a first direction and a second surface and a third surface opposite along a second direction, and electrically connecting adjacent gates along the second direction.

[0093] Specifically, please refer to Figure 1Since corresponding channel layers are formed on two surfaces of the active pillar that are opposite to each other along the first direction, the channel layer includes a first surface facing away from the active pillar along the first direction and a second surface and a third surface that are opposite to each other along the second direction, the first direction intersects with the second direction, and the two gates respectively cover the first surface, the second surface and the third surface of a channel layer. Compared with the case where the gate only covers the first surface of the channel layer, the contact area between the gate and the channel layer is increased, and the channel width is effectively increased, thereby effectively improving the performance of the fabricated transistor; by arranging two insulating layers respectively located on the surfaces of the active pillar that are opposite to each other along the second direction and located between the two gates of the common channel layer, the gate conductive layers of the two gates of the common channel layer are isolated by the two insulating layers located on the two opposite sides of the active pillar along the second direction, thereby reducing the volume of the fabricated semiconductor device and reducing the energy consumption of the device; the two gates of the common channel layer can be simultaneously fabricated in the same process step, reducing the complexity of the fabrication process and reducing the fabrication cost; the threshold voltage of one gate can be modulated by applying a bias voltage to the other gate, thereby effectively improving the performance and reliability of the semiconductor structure.

[0094] For example, as shown in the following figure, the ox direction is parallel to the first direction, the oy direction is parallel to the second direction, and the oz direction is parallel to the third direction. The first direction can be set to be parallel to the bit line extension direction, the second direction is perpendicular to the top surface of the substrate, and the third direction is parallel to the top surface of the substrate and intersects with the first direction.

[0095] As an example, see Figure 1-Figure 2 The substrate 10 provided in step S10 can be composed of a semiconductor material, an insulating material layer, a conductor material or any combination thereof. The substrate 10 can be a single-layer structure or a multi-layer structure. For example, the substrate 10 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 10 can be a layered substrate including Si / SiGe, Si / SiC, silicon on insulator (SOI) or silicon germanium on insulator. Therefore, the type of substrate 10 should not limit the scope of protection of the present disclosure.

[0096] As an example, please refer to Figure 1-Figure 2 In step S10, a target stacked structure 100 arranged at intervals along a first direction is formed on a substrate 10, comprising:

[0097] Step S101: providing a substrate 10, and forming an initial stacked structure 100' on the substrate 10, wherein the initial stacked structure 100' comprises a sacrificial layer 11 and an active layer 20' which are sequentially conformally stacked along the second direction, and a cap layer 12 located on the top surface of the top active layer 20'; the orthographic projection of the active layer 20' on the top surface of the substrate 10 completely overlaps with the orthographic projection of the sacrificial layer 11 on the top surface of the substrate 10, and the orthographic projection of the cap layer 12 on the top surface of the substrate 10 completely overlaps with the orthographic projection of the sacrificial layer 11 on the top surface of the substrate 10; the active layer 20' comprises an initial active column 201 extending along the third direction, a first active portion 202 extending along the first direction, and a second active portion 203 extending along the first direction. 203, first active portions 202 are arranged one-to-one with initial active pillars 201, and the first active portions 202 intersect the middle portion of the corresponding initial active pillar 201; initial active pillars 201 adjacent in the first direction share a second active portion 203 extending in the first direction, and the second active portion 203 intersects the initial active pillar 201; an insulating material layer 204 is filled between initial active pillars 201 adjacent in the first direction and between first active portions 202 and second active portions 203 adjacent in the third direction; first active portions 202 adjacent in the first direction are isolated by first holes 13, and the first holes 13 extend along the second direction to the top surface of the substrate 10. The insulating material layer 204 may include, but is not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide nitride.

[0098] As an example, please refer to Figure 2 and Figure 3a , the etching rate and time can be controlled to Figure 2 The etching stop lines L1 and L2 shown in the figure are the etching end points, and the surfaces of the two opposite sides of the sacrificial layer 11 along the third direction are laterally etched so that the length of the remaining sacrificial layer 11 along the third direction is less than the length of the initial active pillar 201 along the third direction, so as to facilitate the subsequent formation of a support frame on the two opposite sides of the sacrificial layer 11 along the third direction, thereby realizing the process of removing the sacrificial layer 11 and filling the interlayer dielectric layer. The etching process may include but is not limited to a dry etching process and / or a wet etching process. The dry etching process may include but is not limited to at least one of reactive ion etching (RIE), inductively coupled plasma etching (ICP), and high concentration plasma etching (HDP).

[0099] As an example, please refer to Figure 2 and Figure 3b , the etching rate and time can be controlled to Figure 2The etching stop lines L3 and L4 shown in the figure are the etching end points, and the two side surfaces of the sacrificial layer 11 opposite to each other along the first direction are laterally etched so that the length of the remaining sacrificial layer 11 along the first direction is smaller than the length of the first active portion 202 along the first direction, so as to facilitate the subsequent formation of a support frame on the two sides opposite to each other along the first direction of the sacrificial layer 11, thereby realizing the process of removing the sacrificial layer 11 and filling the interlayer dielectric layer.

[0100] As an example, in Figure 3b The isolation material 205 is formed in the gap of the obtained three-dimensional structure to obtain a first intermediate structure (not shown) along Figure 2 The schematic diagrams of the cross-sectional structures obtained in the AA' and BB' directions are shown in FIG. Figure 4a and Figure 4b shown.

[0101] As an example, please refer to Figure 5a and Figure 5b , the sacrificial layer 11 in the first intermediate structure is removed to obtain an internal gap (not shown), and then an interlayer dielectric layer 2041 is formed in the internal gap to obtain a second intermediate structure (not shown), which facilitates the subsequent formation of a double-gate trench based on the second intermediate structure to prepare two gates sharing an active pillar.

[0102] As an example, please refer to Figure 5a 、 Figure 5b 、 Figure 6a and Figure 6b ,by Figure 5a 、 Figure 5b In the three-dimensional structure shown in FIG, the interlayer dielectric layer 2041 between the initial active pillars 201 adjacent in the second direction is used as an etch stop layer. The isolation material 205 and part of the initial active pillars 201 on two opposite sides of the second intermediate structure along the third direction are laterally etched and removed. The interlayer dielectric layer 2041 is also used as an etch stop layer. The isolation material 205 and part of the initial active pillars 201 on two opposite sides of the interlayer dielectric layer 2041 along the first direction are laterally etched and removed, thereby obtaining a first groove 207 and a middle insulating layer 2042 and a middle active pillar 206 conformally stacked in the second direction. The orthographic projection of the middle active pillar 206 on the top surface of the substrate 10 completely overlaps with the orthographic projection of the middle insulating layer 2042 on the top surface of the substrate 10. Figure 6a and Figure 6b A sacrificial insulating layer 2071 is formed in the first groove 207 of the corresponding three-dimensional structure, so that the three-dimensional structure is obtained. Figure 2 The schematic diagrams of the cross-sectional structures obtained in the AA' and BB' directions are shown in FIG. Figure 7a and Figure 7b The material of the sacrificial insulating layer 2071 may include, but is not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride.

[0103] As an example, lateral etching and removal Figure 7a and Figure 7b The sacrificial insulating layer 2071 on the two opposite sides of the three-dimensional structure along the third direction is further laterally etched on the two opposite sides of the middle active pillar 206 along the third direction to reduce the length of the middle active pillar 206 along the third direction; after removing the sacrificial insulating layer 2071 on the two opposite sides of the middle active pillar 206 along the first direction, the two opposite sides of the middle insulating layer 2042 along the first direction are further laterally etched to obtain a middle groove (not shown), the remaining middle insulating layer 2042 is used to form the insulating layer 101, and the remaining middle active pillar 206 is used to form the active pillar 20, the length of the insulating layer 101 along the first direction is less than the length of the active pillar 20 along the first direction, the orthographic projection of the insulating layer 101 on the top surface of the substrate 10 is located inside the orthographic projection of the active pillar 20 on the top surface of the substrate 10, and then an interlayer isolation layer 209 is formed in the middle groove to obtain the three-dimensional structure along the third direction. Figure 2 The schematic diagrams of the cross-sectional structures obtained in the AA' and BB' directions are shown in FIG. Figure 8a and Figure 8b The material of the interlayer isolation layer 209 may include but is not limited to at least one of silicon oxide, silicon nitride, silicon oxynitride or silicon carbide nitride.

[0104] As an example, lateral etching and removal Figure 8a and Figure 8b The first trench 210 is obtained by forming the portion of the interlayer isolation layer 209 located on opposite sides of the active pillar 20 along the first direction in the corresponding three-dimensional structure; the portion of the remaining interlayer isolation layer 209 on the side away from the active pillar 20 along the third direction is further removed by lateral etching, and one end of the insulating layer 101 along the third direction is further etched, so that the active pillar 20 has a protrusion 20a protruding away from the insulating layer 101 along the third direction relative to the remaining insulating layer 101, and then an insulating pillar 211 covering the protrusion 20a is formed, so that the three-dimensional structure is obtained. Figure 2 The schematic diagrams of the cross-sectional structures obtained in the AA' and BB' directions are shown in FIG. Figure 9a and Figure 9b shown.

[0105] As an example, the insulating layer 101 is used as an etching stop layer, and the side etching is performed to remove Figure 9a and Figure 9b The active pillars 20 of the corresponding three-dimensional structure are etched on opposite sides along the first direction to reduce the length of the active pillars 20 along the first direction. The orthographic projection of the active pillars 20 on the top surface of the substrate 10 after etching is completely overlapped with the orthographic projection of the insulating layer 101 on the top surface of the substrate 10, and the following is obtained: Figure 10 The three-dimensional structure shown in Figure 10 The schematic cross-sectional structures of the three-dimensional structure shown in FIG are shown in FIG. Figure 11a and Figure 11b shown.

[0106] As an example, a deposition process may be employed in Figure 11a Insulating material is filled in the gaps of the corresponding three-dimensional structures to form on the substrate 10 a target stacked structure 100 spaced apart along the first direction, frame isolation structures 300 adjacent to the target stacked structure 100 on opposite sides along the first direction, and an intermediate isolation structure 400 located between the frame isolation structures 300 adjacent to each other along the first direction; wherein the insulating material between the interlayer isolation layers 209 adjacent to each other along the second direction is used to form an interlayer insulation layer 301, and the interlayer isolation layers 209 and the interlayer insulation layers 301 conformally stacked along the second direction are used to form the frame isolation structure 300; the target stacked structure 100 includes insulating layers 101 and active pillars 20 alternately arranged along the second direction, and the active pillars 20 are located between the insulating layers 101 adjacent to each other along the second direction; the insulating material located between the frame isolation structures 300 adjacent to each other along the first direction is used to form the intermediate isolation structure 400; then, a double-gate fence 402 for defining a double-gate trench is formed in the intermediate isolation structure 400, to obtain the following: Figure 12 The three-dimensional structure shown in Figure 12 The schematic cross-sectional structures of the three-dimensional structure shown in FIG are shown in FIG. Figure 13a and Figure 13b As shown. The insulating material includes but is not limited to silicon oxide. The deposition process may include but is not limited to at least one of a chemical vapor deposition process (CVD), an atomic layer deposition process (ALD), a high density plasma deposition (HDP), a plasma enhanced deposition process, and a spin-on dielectric layer (SOD) process.

[0107] As an example, please refer to Figure 1 、 Figure 14-15In step S10, a target stacked structure 100 arranged at intervals along a first direction and a double-gate fence 402 located on opposite sides of the target stacked structure 100 along the first direction are formed on the substrate 10. The target stacked structure 100 includes insulating layers 101 and active pillars 20 alternately arranged along a second direction. The active pillars 20 are located between adjacent insulating layers 101 along the second direction. The double-gate fence 402 defines double-gate trenches 201 located on opposite sides of the active pillars 20 along the first direction. The portion of the insulating layer 101 located in the double-gate trenches 201 covers the surfaces of the active pillars 20 located in the double-gate trenches 201 that are opposite to each other along the second direction. The first direction intersects with the second direction, which facilitates the subsequent formation of two gates sharing a common active pillar 20 in the double-gate trenches 201, thereby reducing the complexity of the manufacturing process while reducing the manufacturing cost and the volume of the manufactured memory cell.

[0108] As an example, please refer to Figure 12-15 In step S10, a target stacked structure 100 and a dual-gate trench 201 are formed on the substrate 10, including:

[0109] Step S12: forming on the substrate 10 a target stacked structure 100 arranged at intervals along a first direction, a frame isolation structure 300 adjacent to the target stacked structure 100 on two opposite sides along the first direction, and an intermediate isolation structure 400 located between adjacent frame isolation structures 300 along the first direction, wherein the frame isolation structure 300 includes interlayer isolation layers 209 and interlayer insulating layers 301 alternately arranged along a second direction, and the interlayer insulating layers 301 are located between adjacent interlayer isolation layers 209 along the second direction;

[0110] Step S14: etching the middle isolation structure 400 to obtain a double-gate wall gap (not shown);

[0111] Step S16: forming a double-gate wall 402 in the gap between the double-gate walls;

[0112] Step S18 : removing the intermediate isolation structure 400 , the interlayer insulating layer 301 and the interlayer isolation layer 209 surrounded by the dual-gate walls 402 to obtain the dual-gate trenches 201 .

[0113] As an example, please refer to Figure 12-15In step S14, a dry etching process can be used to etch the middle isolation structure 400 to obtain a double-gate wall gap (not shown) that exposes a portion of the top surface of the substrate 10. The double-gate wall gap is used to define the shape and position of the double-gate trench 201. Then, a deposition process can be used to form a double-gate wall 402 in the double-gate wall gap. In step S18, a wet etching process can be used to remove the middle isolation structure 400 and the interlayer insulating layer 301 surrounded by the double-gate wall 402, and a dry etching process can be used to remove the interlayer insulating layer 209 surrounded by the double-gate wall 402, to obtain a double-gate trench 201 that exposes a portion of the top surface of the substrate.

[0114] As an example, please refer to Figure 16-17 In step S20, channel layers 30 are formed on surfaces of the active pillars 20 in the dual-gate trenches 201 that are opposite to each other along the first direction, including:

[0115] Step S22 : forming an epitaxial layer (not shown) on the exposed surface of the active pillar 20 in the dual-gate trench 201 ;

[0116] Step S24 : doping the epitaxial layer to form a channel layer 30 .

[0117] As an example, please refer to Figure 16-17 In step S22, a selective epitaxial growth process can be used to form an epitaxial layer on the exposed surface of the active pillar 20 in the dual-gate trench 201 to effectively reduce the process complexity of preparing the channel layer 30 and avoid damage to the channel layer 30 by the etching process; in step S24, ion implantation can be performed on the epitaxial layer to form the channel layer 30. The channel layer 30 and the active pillar 20 can have the same doping type, for example, both are P-type doped, and the doping concentration of the channel layer 30 can be set to 1E 17 cm -3 -1E 18 cm -3 The thickness of the channel layer 30 is 5 nm-10 nm. For example, the thickness of the channel layer 30 may be 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, or 10 nm.

[0118] As an example, please refer to Figure 16-17 Step S30: forming a gate 40 corresponding to the channel layer 30 in the dual-gate trench 201, including:

[0119] Step S32 : forming a gate dielectric layer 41 in the dual-gate trench 201 to cover the outer surface of the channel layer 30 ;

[0120] Step S34 : forming a gate conductive layer 42 in the dual-gate trench 201 to cover the outer surface of the gate dielectric layer 41 .

[0121] As an example, please refer to Figure 16-17In step S32, at least one of an in-situ steam generation (ISSG) process, an atomic layer deposition (ALD) process, a plasma vapor deposition (PDP) process, and a rapid thermal oxidation (RTO) process may be used to form a gate dielectric layer 41. The gate dielectric layer 41 covers the first surface 30a of the corresponding channel layer 30 that faces away from the active pillar 20 in the first direction, and the second surface 30b and the third surface 30c that face each other in the second direction. The material of the gate dielectric layer 41 may include, but is not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide. In step S1225, a deposition process may be used to form a gate conductive layer 42. The deposition process may include, but is not limited to, at least one of CVD, ALD, HDP, and SOD. The gate dielectric layer 41 and the gate conductive layer 42 formed on the channel layer 30 are used to form a gate 40. The material of the gate dielectric layer 41 can be selected from silicon dioxide (SiO2), silicon oxynitride (SiON), silicon nitride, aluminum oxide (Al2O3), aluminum oxynitride (AlON), and combinations thereof. The gate dielectric layer 41 can also be a high-k dielectric material (a dielectric material with a dielectric constant greater than or equal to 3.9), a low-k dielectric material (a dielectric constant greater than or equal to 2.5 and less than 3.9), an ultra-low-k dielectric material (a dielectric constant less than 2.5), a ferroelectric material, an anti-ferroelectric material, silicon carbide (SiC), or any combination thereof. The material of the gate conductive layer 42 can be selected from indium tin oxide, polysilicon, copper, tungsten, aluminum, copper alloy, titanium, titanium nitride, palladium nitride, tantalum nitride, and combinations thereof.

[0122] As an example, see Figures 18-21 , before or after forming the gate 40 corresponding to the channel layer 30 in the dual-gate trench 201, further comprising:

[0123] Step S281: forming a conductive portion on the substrate 10 on one side of the target stacked structure 100 along the third direction, the conductive portion including a vertical conductive portion (not shown) extending along the second direction and a horizontal conductive portion 501 located between the vertical conductive portion and the active pillar 20, the horizontal conductive portion 501 extending along the third direction, the horizontal conductive portion 501 corresponding to the active pillar 20 and electrically connecting the vertical conductive portion and the corresponding horizontal conductive portion 501; the third direction intersects both the first direction and the second direction;

[0124] Step S282: removing the vertical conductive portion to obtain a vertical groove (not shown);

[0125] Step S283: forming a vertical insulating portion 601 in the vertical groove;

[0126] Step S284: removing the intermediate isolation structure 400 between the frame isolation structures 300 adjacent to each other along the first direction, and laterally etching the portion of the frame isolation structure 300 on the same layer as the active pillar 20 to expose the opposite side surfaces of the active pillar 20 outside the dual-gate fence 402 along the first direction, thereby forming a second recess 602; the frame isolation structure 300 remaining on the opposite outer side surfaces of the active pillar 20 along the first direction for forming the capacitor portion is used to form two extensions 61; the capacitor portion of the active pillar 20 is the portion of the active pillar 20 located on the dual-gate fence 402 along the third direction away from the vertical insulating portion 601;

[0127] Step S285 : performing a target doping process on the active pillar 20 through the second groove 602 to obtain a doped active pillar 213 .

[0128] As an example, please refer to Figures 18-21 The vertical insulating portion 601 in the current step can serve as a supporting and protective structure. The vertical insulating portion 601 can be removed in a subsequent process to form a bit line in the corresponding gap; the horizontal conductive portion 501 can be used to form a bit line contact plug. The insulating layer 101 is located on the two outer surfaces of the active pillar 20 that are opposite to each other along the second direction and used to form the capacitor portion, and is used to form a first insulating cap layer 62. The two adjacent extensions 61 along the first direction and the first insulating cap layer 62 located between the two extensions 61 are used to form an insulating cap layer 60. The material of the first insulating cap layer 62 includes, but is not limited to, silicon oxide; the material of the extension 61 includes, but is not limited to, silicon nitride. The target doping process in step S285 can include a plasma doping process and / or an atomic layer deposition doping process to meet the process requirements of various different application scenarios.

[0129] As an example, see Figure 22 After the doped active pillar 213 is formed in step S285 , a protection layer 603 is formed in the second groove 602 . The protection layer 603 covers the doped active pillar to prevent the doped active pillar from being damaged in subsequent process steps.

[0130] As an example, please refer to Figure 22-23b The protective layer 603 and the insulating pillar 211 located between the insulating pillar 211 and the double-gate fence 402 are removed to expose the portion of the doped active pillar 213 located on the side of the double-gate fence 402 away from the vertical insulating portion 601 along the third direction, as well as the protruding portion 20a of the active pillar 20, so as to form a capacitor on the exposed surface of the doped active pillar 213 and the outer surface of the protruding portion 20a.

[0131] As an example, please refer to Figure 24-25 ,At Figure 23aThe first electrode layer 71 is formed on the exposed surface of the doped active pillar 213 and the surface of the extension 61 along the second direction close to the doped active pillar 213. A deposition process can be used to form an electrode material layer on the exposed surface of the doped active pillar 213, the surface of the extension 61 along the first direction away from the first insulating cap layer 62, the surface of the extension 61 along the second direction close to the doped active pillar 213, and the outer surface of the protrusion 20a. Then, at least a portion of the electrode material layer located on the surface of the extension 61 along the first direction away from the first insulating cap layer 62 and the portion of the electrode material layer located on the outer surface of the protrusion 20a are at least partially removed. The remaining electrode material layer is used to form the first electrode layer 71.

[0132] Please continue to refer to Figure 26-27b , forming an intermediate dielectric layer 72 covering the outer surface of the first electrode layer 71, the first electrode layers 71 of different layers are insulated from each other via the insulating cover layer 60, forming a second electrode layer 73 covering the outer surface of the intermediate dielectric layer 72, the first electrode layer 71 and the intermediate dielectric layer 72 and the second electrode layer 73 covering the outer surface of the first electrode layer 71 are used to constitute a capacitor 70, and the cross-section of the capacitor 70 parallel to the first direction and the second direction is "H"-shaped.

[0133] It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. In addition, Figure 1 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The order of execution of these steps or stages is not necessarily one by one, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0134] As an example, see Figure 28-29b A semiconductor structure includes an active pillar 20, two channel layers 30, two gates 40 and two insulating layers 101. The two channel layers 30 are respectively located on two surfaces of the active pillar 20 opposite to each other along a first direction. The channel layer 30 includes a first surface 30a facing away from the active pillar 20 along the first direction and a second surface 30b and a third surface 30c opposite to each other along a second direction. The first direction intersects with the second direction; the two gates 40 respectively cover the first surface 30a, the second surface 30b and the third surface 30c of a channel layer 30; the two insulating layers 101 are respectively located on surfaces of the active pillar 20 opposite to each other along the second direction and are located between the two gates 40.

[0135] As an example, please refer to Figure 28-29b Since corresponding channel layers 30 are formed on two surfaces of the active pillar 20 that are opposite to each other along the first direction, the channel layer 30 includes a first surface 30a facing away from the active pillar 20 along the first direction and a second surface 30b and a third surface 30c that are opposite to each other along the second direction, the first direction intersects with the second direction, and the two gates 40 respectively cover the first surface 30a, the second surface 30b and the third surface 30c of one channel layer 30, effectively increasing the channel width and the contact area between the gate 40 and the channel layer 30, thereby effectively improving the performance of the fabricated transistor; by providing two insulating layers 101 respectively located on the surfaces of the active pillar 20 that are opposite to each other along the second direction and located between the two gates 40, the gate conductive layers 42 of the two gates 40 are isolated by the two insulating layers 101 located on the two opposite sides of the active pillar 20 along the second direction, and the two gates 40 share a channel layer 30, which can reduce the volume of the fabricated semiconductor device while reducing the power consumption of the device; the threshold voltage of the other gate 40 can be modulated by applying a bias voltage to one gate 40, which can effectively improve the performance and reliability of the semiconductor structure.

[0136] As an example, please refer to Figure 28-29b The gate 40 includes a gate dielectric layer 41 and a gate conductive layer 42. The gate dielectric layer 41 is located on the same side of the two insulating layers 101 along the first direction and covers the first, second, and third surfaces of a channel layer 30. The gate conductive layer 42 is located on the same side of the two insulating layers 101 along the first direction and covers the outer surface of the gate dielectric layer 41. For example, two gates 40 can be provided, each covering the outer surface of a corresponding channel layer 30, effectively increasing the channel width and the contact area between the gate 40 and the channel layer 30, thereby effectively improving the performance of the fabricated transistor.

[0137] As an example, please refer to Figure 28-29b , the channel layer 30 has the same doping type as the active pillar 20; the doping concentration of the channel layer 30 is 1E 17 cm -3 -1E 18 cm -3 The thickness of the channel layer 30 is 5 nm-10 nm. For example, the thickness of the channel layer 30 may be 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, or 10 nm.

[0138] As an example, please refer to Figure 28-29b The semiconductor structure further includes a bit line 80 and a capacitor 70 located on opposite sides of the gate 40 along the third direction; the third direction intersects with both the first direction and the second direction, for example, the first direction, the second direction and the third direction are mutually perpendicular; the capacitor 70 is located at one end of the active pillar 20 away from the bit line 80 along the third direction; the cross-section of the capacitor 70 parallel to the first direction and the second direction is "H"-shaped.

[0139] As an example, please refer to Figure 28-29b The portion of the active pillar 20 covered by the capacitor 70 includes a first surface 20a and a fourth surface 20d opposite to each other along the first direction, and a second surface 20b and a third surface 20c opposite to each other along the second direction; the semiconductor structure also includes two insulating capping layers 60; the two insulating capping layers 60 are respectively located on the second surface 20b and the third surface 20c of the portion of the active pillar 20 covered by the capacitor 70, the insulating capping layer 60 includes two extensions 61 spaced apart along the first direction and a first insulating capping layer 62 located between the two extensions 61, the two first insulating capping layers 62 respectively cover the second surface 20b and the third surface 20c of the portion of the active pillar covered by the capacitor; the capacitor 70 covers the first surface 20a and the fourth surface 20d of the active pillar 20, as well as the surface 61a of the extension 61 close to the active pillar 20 along the second direction and the surface 61b of the extension 61 away from the first insulating capping layer 62 along the first direction.

[0140] As an example, please refer to Figure 28-29b , the length of the portion of the active pillar 20 covered by the channel layer 30 along the first direction is shorter than the length of the portion of the active pillar 20 covered by the capacitor 70 along the first direction.

[0141] As an example, please refer to Figure 28-29b The capacitor 70 includes a first electrode layer 71, an intermediate dielectric layer 72 and a second electrode layer 73. The first electrode layer 71 covers at least the first surface 20a and the fourth surface 20d of the active pillar 20, and the surface 61a of the extension portion 61 close to the active pillar 20 along the second direction; the intermediate dielectric layer 72 covers the outer surface of the first electrode layer 71, the surface 61b of the extension portion 61 away from the active pillar 20 along the first direction, and the surface 20e of the active pillar 20 away from the gate 40 along the third direction; the second electrode layer 73 covers the outer surface of the intermediate dielectric layer 72.

[0142] As an example, see Figure 30 A memory includes a target layer stacked along a second direction; the target layer includes a plurality of semiconductor structures of any one of the disclosed embodiments arranged at intervals along a first direction; and gates 40 adjacent to each other along the second direction are electrically connected.

[0143] As an example, see Figure 30 Semiconductor structures adjacent to each other along the first direction in the target layer share a bit line 80 extending along the first direction; semiconductor structures in different target layers are connected to different bit lines 80 .

[0144] Please note that the above embodiments are for illustrative purposes only and are not intended to limit the present disclosure.

[0145] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0146] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0147] The above embodiments merely illustrate several implementations of the present disclosure, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the disclosed patent. It should be noted that a person of ordinary skill in the art would be able to make numerous variations and improvements without departing from the scope of the present disclosure, all of which fall within the scope of protection of the present disclosure. Therefore, the scope of protection of the disclosed patent shall be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that include: Active columns; Two channel layers, respectively located on two surfaces of the active pillar opposite to each other along a first direction, the channel layer including a first surface facing away from the active pillar along the first direction and a second surface and a third surface opposite to each other along a second direction, wherein the first direction intersects the second direction; Two gates, covering the first surface, the second surface and the third surface of the channel layer respectively; Two insulating layers, respectively located on surfaces of the active pillar that are opposite to each other along the second direction and between the two gates; It also includes bit lines and capacitors located on opposite sides of the gate along a third direction; the third direction intersects both the first direction and the second direction; The capacitor is located at one end of the active pillar away from the bit line along the third direction.

2. The semiconductor structure according to claim 1, wherein: The gate includes: a gate dielectric layer, located on the same side of the two insulating layers along the first direction and covering the first surface, the second surface, and the third surface of the channel layer; The gate conductive layer is located on the same side of the two insulating layers along the first direction and covers the outer surface of the gate dielectric layer.

3. The semiconductor structure according to claim 2, wherein: The channel layer and the active pillar have the same doping type; the doping concentration of the channel layer is 1E17cm-3-1E18cm-3; and / or The thickness of the channel layer is 5nm-10nm.

4. The semiconductor structure according to any one of claims 1 to 3, characterized in that: A cross section of the capacitor parallel to the first direction and the second direction is "H" shaped.

5. The semiconductor structure according to claim 4, wherein: The portion of the active pillar covered by the capacitor includes a first surface and a fourth surface opposite to each other along the first direction, and a second surface and a third surface opposite to each other along the second direction; The semiconductor structure further comprises: Two insulating cap layers, respectively located on the second surface and the third surface of the portion of the active pillar covered by the capacitor, the insulating cap layer comprising two extensions spaced apart along the first direction and a first insulating cap layer located between the two extensions, the two first insulating cap layers respectively covering the second surface and the third surface of the portion of the active pillar covered by the capacitor; The capacitor covers the first surface, the fourth surface, a surface of the extension portion away from the first insulating capping layer along the first direction, and a surface close to the active pillar along the second direction of the active pillar. The semiconductor structure according to claim 4 , wherein: A length of a portion of the active pillar covered by the channel layer along the first direction is smaller than a length of a portion of the active pillar covered by the capacitor along the first direction.

7. The semiconductor structure according to claim 5, wherein: The capacitor includes: a first electrode layer covering at least the first surface and the fourth surface of the active pillar, and a surface of the extension portion close to the active pillar along the second direction; an intermediate dielectric layer covering an outer surface of the first electrode layer, a surface of the extension portion away from the active pillar along the first direction, and a surface of the active pillar away from the gate along the third direction; The second electrode layer covers the outer surface of the intermediate dielectric layer.

8. The semiconductor structure according to claim 5, wherein: The material of the first insulating cap layer includes silicon oxide; and / or The material of the extension portion includes silicon nitride.

9. A memory, characterized in that: including target layers stacked along a second direction; The target layer comprises a plurality of semiconductor structures according to any one of claims 1 to 8 arranged at intervals along a first direction; The gates adjacent to each other along the second direction are electrically connected; The semiconductor structures adjacent to each other along the first direction in the target layer share a bit line extending along the first direction; The semiconductor structures of different target layers are connected to different bit lines.

10. A method for preparing a memory, characterized in that: include: providing a substrate; forming, on the substrate, a target stacked structure arranged at intervals along a first direction and dual-gate walls located on opposite sides of the target stacked structure along the first direction, wherein the target stacked structure includes insulating layers and active pillars alternately arranged along a second direction, the active pillars being located between adjacent insulating layers along the second direction; and the dual-gate walls defining dual-gate trenches located on opposite sides of the active pillars along the first direction; The portion of the insulating layer located in the dual-gate trench covers the surface of the portion of the active pillar located in the dual-gate trench that is opposite to the surface along the second direction; the first direction intersects the second direction; forming channel layers on surfaces of active pillars in the dual-gate trenches that are opposite to each other along the first direction; A gate corresponding to the channel layer is formed in the dual-gate trench. One gate covers the first surface of the corresponding channel layer away from the active column along the first direction and the second and third surfaces opposite along the second direction. The adjacent gates along the second direction are electrically connected.

11. The preparation method according to claim 10, characterized in that: The surfaces of the active pillars in the dual-gate trenches that are opposite to each other along the first direction are both formed with channel layers, including: forming an epitaxial layer on the exposed surface of the active pillar in the dual-gate trench by a selective epitaxial growth process; Ion implantation is performed on the epitaxial layer to form the channel layer.

12. The preparation method according to claim 10 or 11, characterized in that: Forming the target stacked structure and the dual-gate trench on the substrate, comprising: forming, on the substrate, the target stacked structures arranged at intervals along the first direction, frame isolation structures adjacent to the target stacked structures on opposite sides along the first direction, and an intermediate isolation structure located between the frame isolation structures adjacent to each other along the first direction, wherein the frame isolation structure includes interlayer isolation layers and interlayer insulating layers alternately arranged along the second direction, and the interlayer insulating layers are located between the interlayer isolation layers adjacent to each other along the second direction; Etching the intermediate isolation structure to obtain a double-gate wall gap; forming a double-gate fence within the gap between the double-gate fences; The intermediate isolation structure, the interlayer insulating layer and the interlayer isolation layer surrounded by the dual-gate fence are removed to obtain the dual-gate trench.

13. The preparation method according to claim 10 or 11, characterized in that: Before forming the channel layer, the method further includes: The length of a portion of the active pillar for forming a channel layer along the first direction is reduced.

14. The preparation method according to claim 12, characterized in that Before or after forming a gate corresponding to the channel layer in the dual-gate trench, the method further includes: forming a conductive portion on the substrate and located on one side of the target stacked structure along a third direction, the conductive portion comprising a vertical conductive portion extending along the second direction and a horizontal conductive portion located between the vertical conductive portion and the active pillar, the horizontal conductive portion extending along the third direction, the horizontal conductive portion being disposed corresponding to the active pillar and electrically connecting the vertical conductive portion and the corresponding horizontal conductive portion; the third direction intersects both the first direction and the second direction; removing the vertical conductive portion to obtain a vertical groove; forming a vertical insulating portion in the vertical groove; The intermediate isolation structure located between the adjacent frame isolation structures along the first direction and the portion of the frame isolation structure on the same layer as the active pillar are removed to expose the surfaces of the active pillar outside the dual-gate fence that are opposite to each other along the first direction, thereby forming a second groove; the frame isolation structure remaining on the two opposite outer surfaces of the active pillar along the first direction for forming the capacitor portion is used to form two extension portions, and the capacitor portion of the active pillar is the portion of the active pillar located on the dual-gate fence along the third direction away from the vertical insulating portion; A target doping process is performed on the active pillar through the second groove to obtain a doped active pillar; the target doping process includes a plasma doping process and / or an atomic layer deposition doping process.

15. The preparation method according to claim 14, characterized in that The insulating layer is located on two opposite outer surfaces of the active pillar along the second direction for forming the capacitor portion and is used to form a first insulating cap layer, and two adjacent extensions along the first direction and the first insulating cap layer located between the two extensions are used to form an insulating cap layer; after forming the doped active pillar, the method further includes: forming a first electrode layer, the first electrode layer covering two outer surfaces of the doped active pillar located in a portion of the double-gate fence away from the vertical insulating portion along the third direction and facing each other along the first direction, and a surface of the extension portion close to the doped active pillar along the second direction; forming an intermediate dielectric layer covering the outer surface of the first electrode layer, wherein different first electrode layers are insulated from each other via the insulating cover layer; A second electrode layer is formed to cover the outer surface of the intermediate dielectric layer; the first electrode layer, the intermediate dielectric layer covering the outer surface of the first electrode layer, and the second electrode layer are used to jointly constitute a capacitor.

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