Semiconductor memory device

Abstract

The invention provides a semiconductor memory device including: a substrate; a conductive line disposed on the substrate; a horizontal channel portion extending in a first direction on the conductive line and partially covering the conductive line; a separation insulating layer disposed on the horizontal channel portion; a gate insulating layer including a first portion on the conductive line and a second portion extending in a second direction perpendicular to the substrate; a vertical channel portion between the gate insulating layer and the separation insulating layer, the vertical channel portion extending in the second direction; and a spacer on the first portion of the gate insulating layer. The first material contained in the horizontal channel portion is different from the second material contained in the vertical channel portion.

Description

Technical Field

[0001] Apparatus and devices consistent with the present disclosure relate to semiconductor memory devices, and in particular, to semiconductor memory devices including vertical channel transistors. Background Art

[0002] Due to the development of electronic technology, scaling down of semiconductor devices is rapidly progressing, and thus, a transistor having a channel layer using an oxide semiconductor material has been proposed in order to reduce leakage current through a channel region. Summary of the invention

[0003] An aspect is to provide a semiconductor memory device having improved device characteristics and improved reliability by performing a channel forming process in two stages.

[0004] Another aspect is to provide a semiconductor memory device.

[0005] According to one aspect of one or more embodiments, a semiconductor memory device is provided, the semiconductor memory device comprising: a substrate; a lower conductive line disposed on the substrate; a horizontal channel portion, which contacts the upper surface of the lower conductive line and extends in a first direction parallel to the substrate; a separation insulating layer disposed on the horizontal channel portion and including a channel groove; a vertical channel portion, on the lower conductive line in the channel groove, the vertical channel portion extends along the sidewall of the separation insulating layer in a second direction perpendicular to the substrate and contacts the horizontal channel portion and the lower conductive line; a first gate insulating layer formed on the upper surface of the lower conductive line and comprising a first material; a second gate insulating layer, in the channel groove and covering the vertical channel portion in the second direction, the second gate insulating layer comprising a second material that is the same as the first material; an upper conductive line, disposed on the second gate insulating layer in the channel groove; a conductive contact pattern on the vertical channel portion; and a capacitor structure, comprising a lower electrode connected to the conductive contact pattern. The material in the horizontal channel portion has a different composition from the material in the vertical channel portion.

[0006] According to another aspect of one or more embodiments, a semiconductor memory device is provided, the semiconductor memory device comprising: a substrate; a conductive line disposed on the substrate; a horizontal channel portion extending in a first direction on the conductive line and partially covering the conductive line; a separation insulating layer disposed on the horizontal channel portion; a gate insulating layer including a first portion on the conductive line and a second portion extending in a second direction perpendicular to the substrate; a vertical channel portion between the gate insulating layer and the separation insulating layer, the vertical channel portion extending in the second direction; and a spacer on the first portion of the gate insulating layer. A first material contained in the horizontal channel portion is different from a second material contained in the vertical channel portion.

[0007] According to another aspect of one or more embodiments, a semiconductor memory device is provided, the semiconductor memory device comprising: a substrate; a bit line extending in a first direction on the substrate; a channel structure provided on the bit line; a gate insulating layer surrounding the sidewall of the channel structure and the upper surface of the bit line; a spacer disposed on a horizontal portion of the gate insulating layer; and a word line contacting the upper surface of the spacer and extending along the sidewall of the gate insulating layer in a second direction perpendicular to the substrate; a landing pad disposed on the channel structure; and a capacitor structure comprising a lower electrode connected to the landing pad. The channel structure comprises a horizontal channel portion parallel to the bit line and a vertical channel portion protruding vertically from the upper surface of the bit line, and the composition of the vertical channel portion is different from that of the horizontal channel portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Various embodiments will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0009] Figure 1 is a plan layout showing some components of a semiconductor memory device according to an embodiment;

[0010] Figure 2A is along Figure 1 A cross-sectional view of the semiconductor memory device taken along line AA';

[0011] Figure 2B is along Figure 1 A cross-sectional view of the semiconductor memory device taken along line BB';

[0012] Figures 3A to 18 is a cross-sectional view for describing a method of manufacturing a semiconductor memory device according to an embodiment, wherein Figure 3A , Figure 4A , Figure 5A , Figure 6 ,……, Fig.18 It is along Figure 1 A cross-sectional view taken along line AA' of Figure 3B , Figure 4B and Figure 5B It is along Figure 1 A cross-sectional view taken along line BB'. DETAILED DESCRIPTION

[0013] Hereinafter, one or more embodiments will be described in detail with reference to the accompanying drawings. The same reference numerals denote the same elements in the drawings, and detailed descriptions thereof will be omitted.

[0014] Since embodiments consistent with the present disclosure allow for various changes and many embodiments, some embodiments will be shown in the drawings and described in detail in the written description. However, this is not intended to limit the embodiments to a specific mode of practice, and it should be understood that all modifications, equivalents and / or substitutes that do not depart from the spirit and technical scope of the present disclosure are included in the appended claims. In the description, when it is considered that certain detailed descriptions may unnecessarily obscure the essence of the present disclosure, these detailed descriptions are omitted.

[0015] In the specification, the vertical direction may be defined as the Z direction, and the horizontal direction may be defined as the direction perpendicular to the Z direction. The first horizontal direction and the second horizontal direction may be defined as directions intersecting each other. The first horizontal direction may be referred to as the X direction, and the second horizontal direction may be referred to as the Y direction. The XY plane is defined as a plane perpendicular to the Z direction, and the YZ plane may be defined as a plane perpendicular to the X direction. The vertical level may represent the height level in the vertical direction. As used in this specification, the phrase "at least one of A, B and C" includes "only A", "only B", "only C", "A and B", "A and C", "B and C" and "A, B and C" within its scope.

[0016] Figure 1 is a plan layout showing some components of the semiconductor memory device 1 according to the embodiment. Figure 2A is the edge of the semiconductor memory device 1 Figure 1 A cross-sectional view taken along line AA' of Figure 2B is the edge of the semiconductor memory device 1 Figure 1 A cross-sectional view taken along line BB'.

[0017] Reference Figure 1 , Figure 2A and Figure 2B , the semiconductor memory device 1 may include a substrate 102, a peripheral circuit structure PCA disposed on the substrate 102 and including a plurality of peripheral circuits, and a plurality of conductive lines 120 disposed on the peripheral circuit structure PCA. Each conductive line 120 may correspond to a bit line of the semiconductor memory device 1. In the specification, the conductive line 120 may be referred to as a lower conductive line.

[0018] In some embodiments, the substrate 102 may include silicon, such as single crystal silicon, polycrystalline silicon, or amorphous silicon. In some embodiments, the substrate 102 may include at least one selected from Ge, SiGe, SiC, GaAs, InAs, and InP. In some embodiments, the substrate 102 may include a conductive region, such as an impurity-doped well or an impurity-doped structure.

[0019] The plurality of conductive lines 120 may be connected to at least one peripheral circuit among the plurality of peripheral circuits included in the peripheral circuit structure PCA. The plurality of conductive lines 120 may be connected to at least one peripheral circuit among the plurality of peripheral circuits included in the peripheral circuit structure PCA. Figure 2B ) are insulated from each other. A plurality of conductive lines 120 may pass through the interlayer insulating layer 106C in a vertical direction (Z direction). The plurality of conductive lines 120 may be connected to a peripheral circuit included in the peripheral circuit structure PCA via a plurality of conductive plugs P1 and P2 and a wiring layer M1 included in the peripheral circuit structure PCA.

[0020] The peripheral circuit structure PCA may include a plurality of core circuits 104. The plurality of core circuits 104 may include a first conductive pattern C1 and a second conductive pattern C2 sequentially disposed on a substrate 102. The first conductive pattern C1 and the second conductive pattern C2 may form various circuit elements for controlling functions of semiconductor elements disposed on the peripheral circuit structure PCA. In some embodiments, the peripheral circuit structure PCA may further include various active elements (such as transistors) and various passive elements (such as capacitors, resistors, inductors, etc.).

[0021] In some embodiments, the plurality of peripheral circuits included in the peripheral circuit structure PCA may include a sub-word line driver, a sense amplifier block, and / or a control logic, but the embodiments are not limited thereto. The plurality of peripheral circuits included in the peripheral circuit structure PCA may include an NMOS transistor and a PMOS transistor. The plurality of peripheral circuits may be electrically connected to a conductive line (e.g., a bit line) disposed on the peripheral circuit structure PCA via a plurality of conductive plugs P1 and P2 and a wiring layer M1.

[0022] In the peripheral circuit structure PCA, due to the plurality of interlayer insulating layers 106A, 106B, and 106C, the portions to be insulated from each other among the plurality of core circuits 104, the plurality of conductive plugs P1 and P2, and the wiring layer M1 can maintain an insulating distance. The plurality of interlayer insulating layers 106A, 106B, and 106C may each include an oxide layer or a nitride layer or a combination thereof, but the embodiment is not limited thereto.

[0023] In some embodiments, the peripheral circuit structure PCA may be omitted. In this case, the peripheral circuit structure PCA may be disposed in another region on the substrate 102 that is separate from the substrate 102. Figure 2A and Figure 2B In some embodiments, the peripheral circuit structure PCA may be arranged in another region spaced apart from the cell array region in the axial direction.

[0024] A plurality of conductive lines 120 may be spaced apart from each other in a first horizontal direction (X direction) on the substrate 102, and may extend longer in a second horizontal direction (Y direction). A plurality of conductive lines 120 may extend parallel to each other in the second horizontal direction (Y direction). In some embodiments, each conductive line 120 may include Ti, TiN, Ta, TaN, Mo, Ru, W, WN, Co, La, Pd, Ni, TiSi, TiSiN, WSi, WSiN, TaSi, TaSiN, RuTiN, CoSi, NiSi, ITO (InSnO) or polysilicon or a combination thereof. However, embodiments are not limited thereto.

[0025] The separation insulating layer 115 may be disposed on the plurality of conductive lines 120. For example, the separation insulating layer 115 may be disposed on each channel structure 133 provided on the plurality of conductive lines 120. In some embodiments, a lower surface of the separation insulating layer 115 may contact an upper surface of a horizontal channel portion 133H in each channel structure 133.

[0026] The separation insulating layer 115 may have a plurality of channel trenches 115t extending in the first horizontal direction (X direction) (see FIG. Figure 6 ). The plurality of channel trenches 115t may each define a transistor region in which the channel structure 133 is accommodated. In some embodiments, the horizontal width of the channel trenches 115t may be several nm to several tens of nm. For example, in some embodiments, the horizontal width of the channel trenches 115t may be about 3 nm to about 10 nm. The channel trenches 115t may extend from the upper surface to the lower surface of the separation insulating layer 115.

[0027] The separation insulating layer 115 may include, for example, at least one of silicon oxide, silicon oxynitride, silicon nitride, and a low-k material having a dielectric constant smaller than that of silicon oxide, but the embodiment is not limited thereto. In some embodiments, a stacked structure in which an etch stop layer 117 is thinly formed on the separation insulating layer 115 may be provided. In some embodiments, the etch stop layer 117 may include SiN.

[0028] A plurality of channel structures 133 may be provided in a plurality of channel trenches 115t of the separation insulating layer 115. The plurality of channel structures 133 may be respectively disposed on the corresponding conductive wires 120. For example, in some embodiments, a plurality of channel structures 133 may be provided on each of the plurality of conductive wires 120. The plurality of channel structures 133 may be spaced apart from each other in a first horizontal direction (X direction), may be spaced apart from each other in a second horizontal direction (Y direction), and may be arranged in a matrix form. The lower surface of each channel structure 133 may face the upper surface of the conductive wire 120. In some embodiments, the uppermost surface of each channel structure 133 may be at a vertical level lower than the vertical level of the upper surface of the stacked structure formed by stacking the separation insulating layer 115 and the etching stop layer 117. In other words, the uppermost surface of each channel structure 133 may be at a vertical level lower than the uppermost surface of the etching stop layer 117 in the Z direction.

[0029] Each channel structure 133 may include a vertical channel portion 133V facing the sidewall of the separation insulating layer 115 (that is, the sidewall of the separation insulating layer 115 defining the channel trench 115t) and a horizontal channel portion 133H facing the upper surface of the conductive line 120. In each channel structure 133, the horizontal channel portion 133H may be in direct contact with the conductive line 120 and may extend continuously in a first horizontal direction (X direction) along the surface of the conductive line 120. In each channel structure 133, the vertical channel portion 133V may be in contact with the sidewall of the separation insulating layer 115 and may extend from the horizontal channel portion 133H along the sidewall of the separation insulating layer 115 in a vertical direction (Z direction). In other words, the vertical channel portion 133V may contact the sidewall of each separation insulating layer 115 and the sidewall of the horizontal channel portion 133H. In some embodiments, in each channel structure 133, the lower surface of the vertical channel portion 133V may be disposed on the conductive line 120. In some embodiments, the upper surface of the vertical channel portion 133V may be at a lower vertical level than the vertical level of the upper surface of the separation insulating layer 115. Each channel structure 133 may include one horizontal channel portion 133H, a vertical channel portion 133V connected to one side of the horizontal channel portion 133H, and a vertical channel portion 133V connected to the other side of the horizontal channel portion 133H. Figure 2A As shown, when viewed from the cross section, each channel structure 133 may have a U-shaped vertical cross section. That is, each channel structure 133 may have a U-shape on the YZ plane.

[0030] In some embodiments, the horizontal channel portion 133H may include IGZO (InGaZnO), ITO (InSnO), IWO (InWO), or n-type polysilicon or a combination thereof. In some embodiments, the vertical channel portion 133V may include IGZO (InGaZnO), ITO (InSnO), IWO (InWO), or polysilicon or a combination thereof. In some embodiments, the horizontal channel portion 133H and the vertical channel portion 133V may include materials different from each other. That is, in some embodiments, the material included in the horizontal channel portion 133H may be different from the material included in the vertical channel portion 133V. In some embodiments, the materials included in the horizontal channel portion 133H and the vertical channel portion 133V may exhibit different characteristics. For example, the horizontal channel portion 133H and the vertical channel portion 133V may both include IGZO, but the IGZO included in the horizontal channel portion 133H may have a high-mobility IGZO composition compared to the IGZO included in the vertical channel portion 133V. In some embodiments, horizontal channel portion 133H may include a material having higher electron mobility than that of vertical channel portion 133V. In some embodiments, a material included in horizontal channel portion 133H may have a lower contact resistivity than that of a material included in vertical channel portion 133V.

[0031] A plurality of channel structures 133 arranged in the second horizontal direction (Y direction) may be disposed on each conductive line 120. A lower surface of each horizontal channel portion 133H may be in direct contact with an upper surface of a corresponding conductive line 120.

[0032] like Figure 2A As shown, when viewed from a cross section, each horizontal channel portion 133H may have a rectangular shape, and its length in the second horizontal direction (Y direction) is greater than its length in the vertical direction (Z direction). The thickness of each horizontal channel portion 133H in the vertical direction (Z direction) may be in the range of about several nm to tens of nm. For example, in some embodiments, the thickness of each horizontal channel portion 133H in the vertical direction (Z direction) may be in the range of 3 nm to 10 nm.

[0033] like Figure 2AAs shown, when viewed from a cross section, each vertical channel portion 133V may have a rectangular shape, and its length in the vertical direction (Z direction) is greater than its length in the second horizontal direction (Y direction). The thickness of each vertical channel portion 133V in the second horizontal direction (Y direction) may be in the range of about several nm to tens of nm. For example, in some embodiments, the thickness of each vertical channel portion 133V in the second horizontal direction (Y direction) may be in the range of 3nm to 10nm. In some embodiments, the thickness of each horizontal channel portion 133H in the vertical direction (Z direction) is different from the thickness of each vertical channel portion 133V in the second horizontal direction (Y direction).

[0034] The semiconductor memory device 1 may include a vertical channel transistor (VCT). The VCT may refer to a structure in which the channel length of a channel layer (e.g., a channel structure 133) extends in a vertical direction (Z direction) perpendicular to the upper surface of the substrate 102. For example, the channel structure 133 may include a first source / drain region and a second source / drain region arranged in the vertical direction (Z direction). For example, the lower portion of the channel structure 133 may include a first source / drain region, the upper portion of the channel structure 133 may include a second source / drain region, and the channel structure 133 may include a channel region between the first source / drain region and the second source / drain region.

[0035] The gate insulating layer 140 may extend along the surface of the channel structure 133 provided in the channel trench 115t. The gate insulating layer 140 may be disposed between the channel structure 133 and the word line 150. In some embodiments, the uppermost end of the gate insulating layer 140 may be at a vertical level higher than the vertical level of the uppermost end of the word line 150. In some embodiments, the gate insulating layer 140 may extend along the upper surface of the conductive line 120 and the side surface of the vertical channel portion 133V facing the gap filling insulating layer 164. In this specification, the portion of the gate insulating layer 140 extending along the upper surface of the conductive line 120 may be referred to as a first gate insulating layer, and the portion of the gate insulating layer 140 extending along the side surface of the vertical channel portion 133V facing the gap filling insulating layer 164 may be referred to as a second gate insulating layer. In some embodiments, the thickness of the first gate insulating layer in the vertical direction (Z direction) may be equal to the thickness of the second gate insulating layer in the horizontal direction (Y direction), and the first gate insulating layer and the second gate insulating layer may be formed integrally with each other. For example, the gate insulating layer 140 formed in a U-shape on the YZ plane may be arranged along the outer surface of one channel structure forming the U-shaped vertical cross section, the outer surface of another channel structure adjacent to the above-mentioned channel structure, and the separation space between the adjacent channel structures. The gate insulating layer 140 may extend in the vertical direction (Z direction) from the lower portion thereof contacting the conductive line 120, and the uppermost end of the gate insulating layer 140 may be at a vertical level higher than the vertical level of the upper surface of the vertical channel portion 133V. The gate insulating layer 140 may include, but is not limited to, at least one of silicon oxide, silicon oxynitride, silicon nitride, and a high-k material having a dielectric constant greater than that of silicon oxide.

[0036] In some embodiments, a spacer 162 may be provided on a region formed parallel to the XY plane in the gate insulating layer 140 formed in a U-shape. Since the spacer 162 is formed on the gate insulating layer 140, the distance between the conductive line 120 and the word line 150 may be ensured, and thus, the reliability of the semiconductor memory device 1 may be improved.

[0037] The word line 150 may be provided on the gate insulating layer 140 and the spacer 162 provided in the channel trench 115t. The word line 150 may extend in a vertical direction (Z direction) along the gate insulating layer 140 provided in the channel trench 115t. The word line 150 may extend in a first horizontal direction (X direction). The word line 150 may include doped polysilicon, a metal, a conductive metal nitride, a conductive metal silicide, or a conductive metal oxide, or a combination thereof. For example, the word line 150 may include, but is not limited to, doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x or RuO x or a combination thereof.

[0038] In some embodiments, the word line 150 may include a first word line 150A and a second word line 150B facing each other in one channel trench 115t. The first word line 150A and the second word line 150B may be spaced apart from each other in the second horizontal direction (Y direction), and may extend longer in the first horizontal direction (X direction), respectively. In one channel trench 115t, the channel structure 133 and the first word line 150A are spaced apart from each other by a gate insulating layer 140 formed in a U shape, and the channel structure 133 and the second word line 150B may be spaced apart from each other by the same gate insulating layer 140. The gate insulating layer 140 arranged between the channel structure 133 and the first word line 150A and the gate insulating layer 140 arranged between the channel structure 133 and the second word line 150B may be integrally connected to each other to have a U-shaped vertical cross section. In the specification, the word line 150 may be referred to as an upper conductive line. In addition, the first word line 150A may be referred to as a first upper conductive line, and the second word line 150B may be referred to as a second upper conductive line.

[0039] In some embodiments, a gap-fill insulating layer 164 may be provided between the first word line 150A and the second word line 150B. The first word line 150A and the second word line 150B may be isolated from each other by the gap-fill insulating layer 164. The gap-fill insulating layer 164 may be provided to fill the inside of a U-shaped vertical cross section formed by the first word line 150A, the second word line 150B, and the spacer 162, and may fill the gap between the first word line 150A and the second word line 150B.

[0040] In one channel trench 115 t , the first word line 150A and the second word line 150B may be isolated from each other by a gap-fill insulating layer 164 .

[0041] The gap-fill insulating layer 164 may include, but is not limited to, at least one of silicon oxide, silicon oxynitride, silicon nitride, and combinations thereof. In some embodiments, the gap-fill insulating layer 164 may include a high-k material having a dielectric constant greater than that of silicon oxide.

[0042] The insulating capping pattern 166 may be disposed on the word line 150 and the gap-filling insulating layer 164. The insulating capping pattern 166 may be formed, for example, to cover the upper surface of the word line 150 and the upper surface of the gap-filling insulating layer 164, and to be coplanar with the upper surface of the gate insulating layer 140 while being in contact with the gate insulating layer 140. The insulating capping pattern 166 may include, but is not limited to, silicon nitride. In some embodiments, the gate insulating layer 140 may extend along the side surfaces of the word line 150 and the side surfaces of the insulating capping pattern 166, and may cover the side surfaces of the word line 150 and the insulating capping pattern 166. In some embodiments, the upper surface of the gate insulating layer 140 and the upper surface of the insulating capping pattern 166 may be at the same vertical level and may be coplanar.

[0043] A plurality of conductive contact patterns 173 may be disposed on a plurality of channel structures 133. A plurality of conductive contact patterns 173 may each be connected to a channel structure 133 among the plurality of channel structures 133. For example, a plurality of conductive contact patterns 173 may be spaced apart from each other in a first horizontal direction (X direction) and a second horizontal direction (Y direction), and may be arranged in a matrix form on an XY plane. A plurality of conductive contact patterns 173 may electrically connect the channel structure 133 to a corresponding capacitor structure 190. The conductive contact pattern 173 may include a conductive material, such as at least one of a metal, a conductive metal nitride, a conductive metal carbonitride, a conductive metal carbide, a metal silicide, a doped semiconductor material, and a conductive metal oxynitride. The conductive contact pattern 173 may contact the lower electrode 192 of the capacitor structure 190, and may be referred to as a landing pad.

[0044] The plurality of conductive contact patterns 173 may be insulated from each other by an insulating structure 175. The insulating structure 175 may be disposed on the etch stop layer 117 and the insulating capping pattern 166. In some embodiments, the insulating structure 175 may include a nitride material. Figure 2A In the embodiment, the upper surface of the insulating structure 175 and the upper surface of the plurality of conductive contact patterns 173 are at the same vertical level, but the embodiment is not limited thereto. For example, in some embodiments, the upper surface of the insulating structure 175 may be at a level higher than that of the upper surfaces of the plurality of conductive contact patterns 173. Figure 2A and Figure 2B, the lower surface of the insulating structure 175 is shown to be at the same vertical level as the upper surface of the etch stop layer 117 and the upper surface of the insulating cap pattern 166, but embodiments are not limited thereto. For example, in some embodiments, the insulating structure 175 may extend into the etch stop layer 117 and / or into the insulating cap pattern 166, so that the lower surface of the insulating structure 175 may be at a lower vertical level than the vertical level of the upper surface of the etch stop layer 117 and / or the vertical level of the upper surface of the insulating cap pattern 166.

[0045] The supporting insulating layer 180 may be disposed on the plurality of conductive contact patterns 173 and the insulating structure 175. The supporting insulating layer 180 may cover the plurality of conductive contact patterns 173 and the insulating structure 175, and may have a plurality of holes overlapping the plurality of conductive contact patterns 173. The supporting insulating layer 180 may include, for example, a silicon nitride layer or silicon boron nitride (SiBN).

[0046] A plurality of capacitor structures 190 may be disposed on the plurality of conductive contact patterns 173. The plurality of capacitor structures 190 may be respectively connected to corresponding conductive contact patterns 173 among the plurality of conductive contact patterns 173. The capacitor structures 190 may be controlled by the conductive lines 120 and the word lines 150 to store data.

[0047] The plurality of capacitor structures 190 may include a plurality of lower electrodes 192, a capacitor dielectric layer 194, and an upper electrode 196. The plurality of capacitor structures 190 may each store charges in the capacitor dielectric layer 194 by using a potential difference between the lower electrode 192 and the upper electrode 196.

[0048] The plurality of lower electrodes 192 may be connected to the plurality of conductive contact patterns 173. For example, the plurality of lower electrodes 192 may be connected to upper surfaces of the plurality of conductive contact patterns 173 exposed through the plurality of holes in the supporting insulating layer 180. Figure 2A , the lower electrode 192 is shown as having a column shape extending in a vertical direction (Z direction) from the upper surface of the conductive contact pattern 173, but the embodiment is not limited thereto. In some embodiments, the lower electrode 192 may have a cylindrical shape extending in a vertical direction (Z direction) from the upper surface of the conductive contact pattern 173. In some embodiments, a plurality of lower electrodes 192 may be arranged in a matrix formed on an XY plane. In some embodiments, a plurality of lower electrodes 192 may be arranged in a honeycomb shape on the XY plane. The lower electrode 192 may include silicon doped with impurities, a metal such as tungsten or copper, or a conductive metal compound such as titanium nitride.

[0049] The capacitor dielectric layer 194 may be formed on the plurality of lower electrodes 192. In some embodiments, the capacitor dielectric layer 194 may conformally extend along the side surfaces and upper surfaces of the plurality of lower electrodes 192 and the upper surface of the supporting insulating layer 180. The capacitor dielectric layer 194 may include, for example, TaO, TaAlO, TaON, AlO, AlSiO, HfO, HfSiO, ZrO, ZrSiO, TiO, TiAlO, BST ((Ba, Sr) TiO)), STO (SrTiO), BTO (BaTiO), PZT (Pb (Zr, Ti) O), (Pb, La) (Zr, Ti) O, Ba (Zr, Ti) O, or Sr (Zr, Ti) O, or a combination thereof.

[0050] The upper electrode 196 may be formed on the capacitor dielectric layer 194. The upper electrode 196 may include a metal material. For example, the upper electrode 196 may include W, Ru, RuO, Pt, PtO, Ir, IrO, SRO (SrRuO), BSRO ((Ba, Sr) RuO), CRO (CaRuO), BaRuO or La (Sr, Co) O or a combination thereof. In some embodiments, in addition to the metal material, the upper electrode 196 may further include at least one of a doped semiconductor material layer and an interface layer, and may have a stacked structure thereof. The doped semiconductor material may include, for example, at least one of doped polysilicon and doped polycrystalline silicon germanium (SiGe). The interface layer may include, for example, at least one of a metal oxide, a metal nitride, a metal carbide, and a metal silicide.

[0051] According to the semiconductor memory device 1, since the processes of forming the horizontal portion 133H and the vertical portion 133V of the channel structure 133 are separately performed when the process of forming the channel of the vertical channel transistor is performed, the horizontal portion 133H and the vertical portion 133V may have different doping concentrations, may have different compositions, or may include different materials, and thus, the performance of the semiconductor memory device 1 may be improved. By adding the spacer 162 between the conductive line 120 and the word line 150, the distance between the conductive line 120 and the word line 150 may be ensured, and thus, the reliability of the semiconductor memory device 1 may be improved.

[0052] Figures 3A to 18 is a cross-sectional view for describing a method of manufacturing a semiconductor memory device 1 according to some embodiments. In detail, Figures 3A to 18 It is used to describe manufacturing Figures 1 to 2B A cross-sectional view of a semiconductor memory device 1 shown in the method, Figure 3A , Figure 4A , Figure 5A , Figure 6 ,……, Fig.18 It is along Figure 1 A cross-sectional view of the semiconductor memory device 1 taken along line AA′, Figure 3B , Figure 4B and Figure 5B It is along Figure 1 1 is a cross-sectional view of the semiconductor memory device 1 taken along line BB′.

[0053] Reference Figure 3A and Figure 3B , a plurality of peripheral circuits including a plurality of core circuits 104, a plurality of conductive plugs P1 and P2, and a wiring layer M1 are formed on the substrate 102, and thus a peripheral circuit structure PCA may be formed on the substrate 102. Thereafter, an interlayer insulating layer 106C provided on the peripheral circuit structure PCA and a plurality of conductive wires 120 penetrating the interlayer insulating layer 106C may be formed. Next, a horizontal channel layer covering the plurality of conductive wires 120 and the interlayer insulating layer 106C is formed, and the horizontal channel layer is patterned to form a plurality of horizontal channel portions 133H. The plurality of horizontal channel portions 133H may be formed by having a plurality of conductive wires 120 as described above with reference to FIG. Figures 1 to 2B A first composition of materials is described.

[0054] Reference Figure 4A and Figure 4B After forming the plurality of horizontal channel portions 133H, a separation insulating film 106D covering the plurality of horizontal channel portions 133H and the interlayer insulating layer 106C is formed. In some embodiments, the separation insulating film 106D may include an oxide material.

[0055] Reference Figure 5A and Figure 5B , a separation insulating layer 115 and an etching stop layer 117 may be sequentially formed to cover Figure 4A and Figure 4B The surface of the resulting structure is shown. In some embodiments, the separation insulating layer 115 can be a first mold layer. In some embodiments, the etch stop layer 117 can include SiN.

[0056] Reference Figure 6 and Figure 7 , the etching stop layer 117, the separation insulating layer 115 and the separation insulating film 106D are sequentially etched, and then, a covering Figure 6 The preliminary vertical channel layer 133P is formed on the surface of the resultant. The preliminary vertical channel layer 133P may be formed of a material having a second composition different from the first composition, as described above with reference to Figure 1-2BThe preliminary vertical channel layer 133P may cover the upper surface of the conductive line 120, the side surface of the separation insulating layer 115, and the upper surface and side surface of the etch stop layer 117. Thereafter, a second mold layer 119 filling the space in the preliminary vertical channel layer 133P and covering the upper surface of the preliminary vertical channel layer 133P may be formed.

[0057] Reference Figure 8 as well as Figure 7 , some portions of the preliminary vertical channel layer 133P covering the etch stop layer 117 and the conductive line 120 and the second mold layer 119 (see Figure 7 The second mold layer 119 may be removed by an etch-back process (see Figure 7 ) and some portions of the preliminary vertical channel layer 133P. After the etch-back process on the preliminary vertical channel layer 133P, the remaining portions of the preliminary vertical channel layer 133P may form a plurality of vertical channel portions 133V.

[0058] Reference Fig. 9 , Fig.10 and Fig.11 , a preliminary gate insulating layer 140P conformally covering the upper surface of the conductive line 120, the upper surface of the etch stop layer 117, and the upper surface and side surfaces of the plurality of vertical channel portions 133V is formed, and a preliminary spacer layer 162P covering the preliminary gate insulating layer 140P may be formed. In some embodiments, the preliminary spacer layer 162P may include SiN. When a chemical mechanical polishing (CMP) process is performed on the preliminary spacer layer 162P by using the etch stop layer 117 as an etch stop layer, as shown in FIG. Fig.10 As shown in FIG. 1 , the gate insulating layer 140 and the preliminary spacer 162P′ coplanar with the upper surface of the gate insulating layer 140 can be obtained. Then, the preliminary spacer 162P′ is etched back to form the spacer 162, as shown in FIG. Fig.11 shown.

[0059] Reference Fig.12 and Fig.13 ,exist Fig.11A preliminary word line material layer 150P is formed on the resultant to conformally cover the upper surface of the etch stop layer 117, the upper surface of each channel structure 133, the side surface of the gate insulating layer 140, and the upper surface of the spacer 162. Thereafter, a CMP process is performed on the preliminary word line material layer 150P by using the etch stop layer 117 as an etch stop layer, and a portion of the preliminary word line material layer 150P covering the upper surface of the spacer 162 and a portion of the preliminary word line material layer 150P covering the upper side surface of the gate insulating layer 140 are removed to form the word line 150. For example, in order to remove a portion of the preliminary word line material layer 150P covering the upper surface of the spacer 162 and a portion of the preliminary word line material layer 150P covering the upper side surface of the gate insulating layer 140, anisotropic etching may be performed on the preliminary word line material layer 150P. In some embodiments, the word line 150 may be formed to include a first word line 150A and a second word line 150B facing each other on one gate insulating layer 140 .

[0060] Reference Fig.14 , a gap-filling insulating layer 164 covering the word line 150 and the spacer 162 is formed to fill the space defined by the word line 150 and the spacer 162 in the channel trench 115t. Thereafter, an insulating capping pattern 166 covering the upper side surface of the gate insulating layer 140, the upper surface of the gap-filling insulating layer 164, and the upper surface of the word line 150 may be formed on the gap-filling insulating layer 164.

[0061] Reference Fig.15 ,from Fig.14 The resultant partially removes the upper side of the vertical portion 133V in the channel structure 133. When the upper side of the vertical portion 133V is partially removed, the uppermost end of the channel structure 133 may be at a vertical level lower than that of the uppermost end of the word line 150.

[0062] Reference Fig.16 ,exist Fig.15 A contact material layer 173P is formed on the resultant. The contact material layer 173P may fill a space defined between the sidewall of the etch stop layer 117 and the gate insulating layer 140 and contact an upper surface of the vertical portion 133V of the channel structure 133. The contact material 173P may cover an upper surface of the etch stop layer 117 and an upper surface of the insulating cap pattern 166.

[0063] Reference Fig.17, the contact material layer 173P may be partially removed. For example, a mask pattern is formed on the contact material layer 173P, and the contact material layer 173P may be partially removed by using the mask pattern as an etching mask. The contact material layer 173P is partially removed to form a plurality of conductive contact patterns 173. The insulating structure 175 is formed in a space obtained by partially removing the contact material layer 173P.

[0064] Reference Fig.18 , a supporting insulating layer 180 is formed on the plurality of conductive contact patterns 173 and the insulating structure 175. The supporting insulating layer 180 may have a plurality of holes exposing the plurality of conductive contact patterns 173. Thereafter, a plurality of lower electrodes 192 are formed on the plurality of conductive contact patterns 173. The plurality of lower electrodes 192 may be formed to extend in a vertical direction (Z direction) from the upper surfaces of the conductive contact patterns 173 exposed through the plurality of holes of the supporting insulating layer 180.

[0065] Next, refer to Figure 2A and Figure 2B , capacitor dielectric layers 194 and upper electrodes 196 are sequentially formed on the plurality of lower electrodes 192 , and a semiconductor memory device 1 including a plurality of capacitor structures 190 may be formed.

[0066] Although various embodiments have been particularly shown and described with reference to the accompanying drawings, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

[0067] CROSS-REFERENCE TO RELATED APPLICATIONS

[0068] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0087397 filed in the Korean Intellectual Property Office on July 5, 2023, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor memory device, comprising: substrate; a lower conductive line disposed on the substrate; a horizontal channel portion contacting an upper surface of the lower conductive line and extending in a first direction parallel to the substrate; a separation insulating layer disposed on the horizontal channel portion and including a channel trench; a vertical channel portion in the channel trench on the lower conductive line, the vertical channel portion extending in a second direction perpendicular to the substrate along a sidewall of the separation insulating layer and contacting the horizontal channel portion and the lower conductive line; A first gate insulating layer formed on the upper surface of the lower conductive line and comprising a first material; a second gate insulating layer in the channel trench and covering the vertical channel portion in the second direction, the second gate insulating layer comprising a second material that is the same as the first material; an upper conductive line, disposed on the second gate insulating layer and in the channel trench; a conductive contact pattern on the vertical channel portion; as well as a capacitor structure comprising a lower electrode connected to the conductive contact pattern, Wherein the material in the horizontal channel portion has a different composition than the material in the vertical channel portion. 2 . The semiconductor memory device according to claim 1 , wherein a thickness of the horizontal channel portion in the second direction is different from a thickness of the vertical channel portion in the first direction.

3. The semiconductor memory device according to claim 2, wherein: The thickness of the horizontal channel portion in the second direction is in the range of 3 nm to 10 nm, and The thickness of the vertical channel portion in the first direction is in a range of 3 nm to 10 nm. 4 . The semiconductor memory device according to claim 1 , wherein the material in the horizontal channel portion comprises IGZO (InGaZnO), ITO (InSnO), IWO (InWO), or n-type polysilicon, or a combination thereof. 5 . The semiconductor memory device according to claim 1 , wherein the material in the vertical channel portion comprises IGZO (InGaZnO), ITO (InSnO), IWO (InWO), or polysilicon, or a combination thereof. 6 . The semiconductor memory device according to claim 1 , further comprising a spacer disposed on the first gate insulating layer. 7 . The semiconductor memory device according to claim 1 , wherein a thickness of the first gate insulating layer in the second direction is equal to a thickness of the second gate insulating layer in the first direction, and the first gate insulating layer and the second gate insulating layer are formed integrally with each other.

8. The semiconductor memory device according to claim 1, wherein: A height of an uppermost surface of the upper conductive line in the second direction is equal to a height of an uppermost surface of the vertical channel portion in the second direction.

9. The semiconductor memory device according to claim 1, wherein: A height of an uppermost surface of the second gate insulating layer in the second direction is greater than a height of an uppermost surface of the vertical channel portion in the second direction. 10 . The semiconductor memory device according to claim 1 , wherein an uppermost surface of the second gate insulating layer contacts the conductive contact pattern in the second direction.

11. A semiconductor memory device comprising: substrate; A conductive line disposed on the substrate; a horizontal channel portion extending in a first direction on the conductive line and partially covering the conductive line; a separation insulating layer disposed on the horizontal channel portion; A gate insulating layer including a first portion on the conductive line and a second portion extending in a second direction perpendicular to the substrate; a vertical channel portion between the gate insulating layer and the separation insulating layer, the vertical channel portion extending in the second direction; as well as a spacer on the first portion of the gate insulating layer, A first material contained in the horizontal channel portion is different from a second material contained in the vertical channel portion. 12 . The semiconductor memory device according to claim 11 , wherein the first material comprises IGZO (InGaZnO), ITO (InSnO), IWO (InWO), or n-type polysilicon, or a combination thereof. 13 . The semiconductor memory device according to claim 11 , wherein the second material comprises IGZO (InGaZnO), ITO (InSnO), IWO (InWO), or polysilicon, or a combination thereof. 14 . The semiconductor memory device according to claim 11 , wherein a thickness of the horizontal channel portion in the second direction is different from a thickness of the vertical channel portion in the first direction.

15. The semiconductor memory device according to claim 14, wherein: The thickness of the horizontal channel portion in the second direction is in the range of 3 nm to 10 nm, and The thickness of the vertical channel portion in the first direction is in a range of 3 nm to 10 nm.

16. The semiconductor memory device according to claim 11, wherein: A height of an uppermost surface of the gate insulating layer in the second direction is greater than a height of an uppermost surface of the vertical channel portion in the second direction.

17. A semiconductor memory device comprising: substrate; A bit line extending along a first direction on the substrate; providing a channel structure on the bit line; a gate insulating layer surrounding the sidewalls of the channel structure and the upper surface of the bit line; a spacer disposed on a horizontal portion of the gate insulating layer; as well as a word line contacting an upper surface of the spacer and extending along a sidewall of the gate insulating layer in a second direction perpendicular to the substrate; A landing pad disposed on the channel structure; a capacitor structure including a lower electrode connected to the landing pad, wherein the channel structure includes a horizontal channel portion parallel to the bit line and a vertical channel portion protruding vertically from the upper surface of the bit line, and The composition of the vertical channel portion is different from the composition of the horizontal channel portion. 18 . The semiconductor memory device according to claim 17 , wherein a material included in the horizontal channel portion has a lower contact resistivity than a material included in the vertical channel portion. 19 . The semiconductor memory device according to claim 17 , wherein a thickness of the horizontal channel portion in the second direction is different from a thickness of the vertical channel portion in the first direction.

20. The semiconductor memory device according to claim 17, wherein: The horizontal channel portion includes IGZO (InGaZnO), ITO (InSnO), IWO (InWO) or n-type polysilicon or a combination thereof, The vertical channel portion includes IGZO (InGaZnO), ITO (InSnO), IWO (InWO) or polysilicon or a combination thereof.

Images