Method for forming silicon carbide ldmos structure, silicon carbide ldmos structure and silicon carbide ldmos device

Abstract

The application discloses a structure of a silicon carbide LDMOS and a forming method thereof, and comprises the following steps: forming a first well region; forming a second well region, the second well region partially overlaps the first well region, and the injection depth of the second well region is smaller than that of the first well region; forming a third region, the third region is contained in the first well region, partially overlaps the second well region, and the injection depth of the third region is smaller than that of the second well region; forming a source region on the surface of the second well region, wherein the source region comprises an N+ region and a P+ region, and the source region partially overlaps the first well region; forming a drain region on the surface of the third region; forming a gate region on the surface between the source region and the third region, and forming electrodes of the gate, the source and the drain. The application has the advantages that the LDMOS obtained by the method has high voltage resistance and small size, the manufacturing process is simple, and the yield of finished products is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and in particular to a method for forming a silicon carbide LDMOS semiconductor device structure, a silicon carbide LDMOS device structure, and a silicon carbide LDMOS semiconductor device. Background Technology

[0002] A half-bridge circuit is a common electronic circuit structure, typically consisting of two transistors and a load. Depending on the circuit requirements, a Zener diode or a Zener diode may be added. In a half-bridge circuit, the two transistors typically conduct alternately, generating an oscillating signal as the output voltage supplied to the load.

[0003] Based on the conventional drawing method of circuit diagrams, the two transistors are usually referred to as High Side MOS (also known as the upper transistor) and Low Side MOS (also known as the lower transistor). In power supply or motor drive applications, it is difficult to integrate the upper and lower transistors that can withstand voltages above 600V (especially above 1200V). Even if it is made, its size is very large and the process is very complex. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention, taking into account the characteristics of the lower transistor in a half-bridge circuit, utilizes the high critical breakdown electric field characteristics of SiC material to design a structure for the lower transistor and a corresponding manufacturing method, thereby achieving the characteristics of the lower transistor in a half-bridge circuit being resistant to high voltage and high current density.

[0005] First, this application provides a method for forming a silicon carbide LDMOS structure, including:

[0006] An epitaxial layer is grown on a substrate, wherein the epitaxial layer is P-type;

[0007] N-type ions are implanted at the central position on the surface of the epitaxial layer to form a first well region;

[0008] P-type ions are implanted at the edge of the surface of the epitaxial layer to form a second well region. The second well region partially overlaps with the first well region, and the implantation depth of the second well region is less than that of the first well region.

[0009] N-type ions are implanted on the surface of the epitaxial layer to form a third region. The third region is contained within the first well region and partially overlaps with the second well region. The implantation depth of the third region is less than the implantation depth of the second well region, and the implantation concentration of the third region matches the implantation concentration of the second well region.

[0010] A source region is fabricated on the surface of the second well region, wherein,

[0011] The source region includes an N+ region and a P+ region, and

[0012] The source region partially overlaps with the first well region;

[0013] A drain region is formed on the surface of the third region;

[0014] A gate region is formed on the surface between the source region and the third region, and electrodes for the gate, source, and drain are formed.

[0015] In the above method, the injection depth of the first well region is 1μm-5μm.

[0016] In the above method, the injection depth of the second well region is 1μm-4μm.

[0017] In the above method, the injection depth of the third region is 0μm-2μm.

[0018] In the above method, the net doping concentration ratio of the third region, the second well region, the first well region, and the epitaxial layer is 1:2:2:1.

[0019] In the above method, the substrate material includes silicon carbide (SiC).

[0020] This application also provides a silicon carbide LDMOS device structure, including:

[0021] Substrate;

[0022] A P-type epitaxial layer grown on the substrate;

[0023] The first well region is located in the middle of the P-type epitaxial layer and its depth is less than that of the P-type epitaxial layer;

[0024] The second well region is located on one side of the P-type epitaxial layer and partially overlaps with the first well region. The depth of the second well region is less than the depth of the first well region. A source region is formed on the surface of the second well region. The source region includes an N+ region and a P+ region, and the N+ region partially overlaps with the first well region.

[0025] A third region is located within the first well region and partially overlaps with the second well region. The depth of the third region is less than the depth of the second well region. A drain region is formed on the surface of the third region.

[0026] A gate region is formed on the surface between the source region and the third region, and electrodes for the gate, source, and drain are formed.

[0027] In the above device structure, the first well region is formed by ion implantation, and the implantation depth is 1μm-5μm.

[0028] In the device structure described above, the second well region is formed by ion implantation, with an implantation depth of 1 μm-4 μm.

[0029] In the above-described device structure, the third region is formed by ion implantation, with an implantation depth of 0 μm-2 μm.

[0030] In the above device structure, the net doping concentration ratio of the third region, the second well region, the first well region, and the epitaxial layer is 1:2:2:1.

[0031] This application also provides a silicon carbide LDMOS device, including the above-described semiconductor device structure.

[0032] Compared with the prior art, the semiconductor device structure formation method proposed in this invention has a simple and efficient manufacturing process, and the semiconductor device structure produced has the characteristics of high voltage resistance and small size. In terms of process, it is easy to integrate with the upper transistor in a half-bridge circuit to obtain a high voltage resistance and high current density LDMOS (Laterally Diffused Metal Oxide Semiconductor). Attached Figure Description

[0033] Figure 1 A flowchart of a forming method according to some embodiments of this application is shown;

[0034] Figure 2-7 It shows according to Figure 1 This diagram illustrates the structural changes of a semiconductor device during its fabrication using the method shown. Detailed Implementation

[0035] Various exemplary embodiments, features, and aspects of this application will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0036] In the description of this application, it should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0037] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise explicitly specified, "multiple" means two or more.

[0038] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0039] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0040] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist.

[0041] In addition, the term "at least one" in this document means any combination of at least two of any one or more of a plurality of elements, such as including at least one of A, B, and C, and may mean including any one or more elements selected from the set consisting of A, B, and C.

[0042] Furthermore, to better illustrate this application, numerous specific details are provided in the following detailed description. Those skilled in the art should understand that this application can be implemented without certain specific details. In some instances, methods, means, components, and circuits well-known to those skilled in the art have not been described in detail in order to highlight the main points of this application.

[0043] The embodiments of this application will now be described in further detail with reference to the accompanying drawings.

[0044] Figure 1 A flowchart of a method for forming a silicon carbide LDMOS structure according to some embodiments of this application is shown.

[0045] As shown in the figure, the method for forming a semiconductor device structure proposed in this application includes the following steps S1-S5:

[0046] S1, please refer to the reference. Figure 2 An epitaxial layer 1 is grown on a substrate 8 to obtain a substrate for fabricating a MOSFET device. The material of the substrate 8 can be either an N-type or P-type substrate depending on the type of semiconductor device; this application does not impose any particular limitation on this. For example, in some embodiments, the material of the substrate 8 may include any one of silicon (Si), silicon carbide (SiC), gallium nitride (GaN), and gallium arsenide (GaAs). Preferably, this application uses silicon carbide (SiC) as the material of the substrate 8, thereby utilizing the high critical breakdown electric field characteristics of SiC material to further improve the high voltage and high current density characteristics of the SiC device. The material of the epitaxial layer 1 can be a P-type epitaxial material, and the doping concentration of the P-type material can be set according to the design intent. Furthermore, a dielectric layer 2 can be grown on the surface of the epitaxial layer 1 to serve as a masking layer for subsequent implantation processes. This application does not limit the material type or thickness of the dielectric layer 2; those skilled in the art can set it according to actual conditions and needs. For example, the material of the dielectric layer 2 can be silicon dioxide, and the thickness of the silicon dioxide layer can be [missing information]. In other embodiments, other materials may be used to form the masking layer. For example, an injection mask may be formed on the surface region of the epitaxial layer 1. This application does not limit the specific type of injection mask. For example, the injection mask may be photoresist or a hard mask.

[0047] S2, pattern the dielectric layer 2, and etch its central region to expose the epitaxial layer 1. In the exposed epitaxial layer 1 region (combined with...) Figure 3 It can be seen that N-type ions are implanted into the region (basically the central position of the surface of epitaxial layer 1) at a depth of 1 micrometer to 5 micrometers, thereby forming the first well region (N-WELL) 3. In order to ensure that the implanted ions are evenly distributed, a process of multiple implantations (e.g., 3 times) can be used.

[0048] S3, at the edge position of the surface of the epitaxial layer 1 (see reference). Figure 4P-type ions are implanted to form a second well region (P-WELL) 4. It is understood that the described edge position is intended to indicate that the first well region 3 and the second well region 4 overlap, and this overlap can be severe, meaning that the second well region 4 extends into more than half of the first well region 3. The portion of the second well region 4 that does not overlap with the first well region 3 is located on one side of the first well region 3, and its outermost edge can overlap with the sidewall of the epitaxial layer 1; that is, one side of the second well region 4 is in the first well region 3, and the other side is the sidewall of the epitaxial layer 1. Furthermore, the implantation depth of the second well region 4 is less than the implantation depth of the first well region 3, typically ranging from 1 micrometer to 4 micrometers.

[0049] S4, please refer to the reference. Figure 5 N-type ions are implanted onto the surface of the epitaxial layer 1 to form a third region (N-TOP) 5. The third region 5 is entirely located within the first well region 3 and partially overlaps with the second well region 4. The implantation depth of the third region 5 is less than the implantation depth of the second well region 4. Specifically, its implantation depth can be 0-2 micrometers. Furthermore, the implantation concentration of the third region 5 is matched with the implantation concentration of the second well region 4 so that the N-type and P-type ions in the overlapping region of the third region 5 and the second well region 4 can partially cancel each other out, thereby allowing the overlapping region to exhibit the characteristics of N-type ions. Similarly, the ion implantation concentrations in the overlapping portion of the second well region 4 and the first well region 3 also need to be matched to allow the overlapping region to exhibit the characteristics of P-type ions.

[0050] Furthermore, the doping concentrations of the third region 5, the second well region 4, the first well region 3, and the epitaxial layer 1 can be adjusted in a suitable concentration ratio to achieve charge balance between the regions. Preferably, the net doping concentration ratio can be 1:2:2:1.

[0051] S5, a source region is fabricated on the surface of the second well region 4. Specifically, the ion concentration in a small area of ​​the surface of the second well region 4 is changed by implanting N-type and P-type ions, so that a metal-like conductive surface can be fabricated in the source region in subsequent process steps by means of depositing / sputtering Ni (nickel) metal, annealing, etc.

[0052] a. The source region includes N+ region 6 and P+ region 7, and the source region partially overlaps with the first well region 3. (See reference) Figure 6As shown, partial overlap means that the side 31 of the first well region 3 can intersect with the N+ region 6 or the P+ region 7, but the side 31 will not coincide with the outer boundary of the N+ region 6 or the P+ region 7. In this way, the P+ region 7 implanted with P-type ions, the second well region 4, and the epitaxial layer 1 can remain continuous and uninterrupted, thereby ensuring that the source of the silicon carbide LDMOS structure proposed in this application is effectively and reliably connected to the "GND" of the integrated half-bridge circuit after integration as a low-side LDMOS and a high-side LDMOS.

[0053] b. A drain region 10 is formed on the surface of the third region 5. Similarly, this step alters the ion concentration in a small portion of the surface of the third region 5 by injecting N-type ions into the drain region, thereby enabling the drain of this structure to form a better ohmic contact.

[0054] c. The gate region 11 is fabricated using conventional processes, and the source and drain regions 10 are subjected to metallization and metal deposition processes, respectively, to form a structure as shown in the figure. Figure 7 The source electrode 12 and drain electrode 13 are shown.

[0055] The above describes a basic semiconductor device structure that is simple in structure yet possesses high current density and high voltage resistance. Based on this, it can be further packaged to form an independent semiconductor device. It is particularly suitable for packaging a low-side MOSFET (lower-side MOSFET, as the bottom transistor) and a high-side MOSFET (upper-side MOSFET, as the top transistor) together to form a half-bridge circuit, and then packaged as an integrated chip. The half-bridge chip obtained through this method has the characteristics of high voltage resistance (typically 600V-3300V) and small size.

[0056] In addition, the manufacturing process is simple and efficient, which helps to improve the yield rate of finished products.

[0057] It should be noted that in the examples and description of this patent, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0058] Although this application has been illustrated and described with reference to certain preferred embodiments thereof, those skilled in the art should understand that various changes in form and detail may be made thereto without departing from the spirit and scope of this application.

Claims

1. A method for forming a silicon carbide LDMOS structure, characterized in that, include: An epitaxial layer is grown on a substrate, wherein the epitaxial layer is P-type; N-type ions are implanted at the central position on the surface of the epitaxial layer to form a first well region; P-type ions are implanted at the edge of the surface of the epitaxial layer to form a second well region. The second well region partially overlaps with the first well region, and the implantation depth of the second well region is less than that of the first well region. N-type ions are implanted on the surface of the epitaxial layer to form a third region. The third region is contained within the first well region and partially overlaps with the second well region. The implantation depth of the third region is less than the implantation depth of the second well region, and the implantation concentration of the third region matches the implantation concentration of the second well region. A source region is fabricated on the surface of the second well region, wherein, The source region includes an N+ region and a P+ region, and the source region partially overlaps with the first well region. The partial overlap means that the side of the first well region intersects with the N+ region or the P+ region, but the side does not coincide with the outer boundary of the N+ region or the P+ region. A drain region is formed on the surface of the third region; A gate region is formed on the surface between the source region and the third region, and electrodes for the gate, source, and drain are formed.

2. The method according to claim 1, characterized in that, The injection depth of the first well region is 1µm-5µm.

3. The method according to claim 1, characterized in that, The injection depth of the second well region is 1µm-4µm.

4. The method according to claim 1, characterized in that, The injection depth in the third region is 0µm - 2µm.

5. The method according to claim 1, characterized in that, The net doping concentration ratio of the third region, the second well region, the first well region, and the epitaxial layer is 1:2:2:

1.

6. The method according to claim 1, characterized in that, The substrate material includes silicon carbide (SiC).

7. A silicon carbide LDMOS structure, characterized in that, include: Substrate; A P-type epitaxial layer grown on the substrate; The first well region is located in the middle of the P-type epitaxial layer and its depth is less than that of the P-type epitaxial layer; The second well region is located on one side of the P-type epitaxial layer and partially overlaps with the first well region. The depth of the second well region is less than the depth of the first well region. A source region is formed on the surface of the second well region. The source region includes an N+ region and a P+ region. The source region partially overlaps with the first well region. The partial overlap means that the side of the first well region intersects with the N+ region or the P+ region, but the side does not coincide with the outer boundary of the N+ region or the P+ region. A third region is located within the first well region and partially overlaps with the second well region. The depth of the third region is less than the depth of the second well region. A drain region is formed on the surface of the third region. A gate region is formed on the surface between the source region and the third region, and electrodes for the gate, source, and drain are formed.

8. The silicon carbide LDMOS structure according to claim 7, characterized in that, The first well region is formed by ion implantation, with an implantation depth of 1µm-5µm.

9. The silicon carbide LDMOS structure according to claim 7, characterized in that, The second well region is formed by ion implantation to a depth of 1µm-4µm.

10. The silicon carbide LDMOS structure according to claim 7, characterized in that, The third region is formed by ion implantation at a depth of 0µm-2µm.

11. The silicon carbide LDMOS structure according to claim 7, characterized in that, The net doping concentration ratio of the third region, the second well region, the first well region, and the epitaxial layer is 1:2:2:

1.

12. A silicon carbide LDMOS device, characterized in that, Includes the silicon carbide LDMOS structure as described in any one of claims 7-11.

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