A Micro-LED micro display array and preparation method thereof

Abstract

The present invention discloses a Micro-LED micro display array and a preparation method thereof, which relates to the field of semiconductor technology, and comprises: a first stress release layer, the first stress release layer comprising a first Ti layer (thickness A) stacked in sequence; 1 )、The first Pt layer (thickness B 1 ) and the first Au layer (thickness C 1 ); a second stress release layer, the second stress release layer comprises a second Ti layer (thickness A) stacked in sequence 2 )、The second Pt layer (thickness B 2 ) and the second Au layer (thickness C 2 ), 0.3A 1 ≤A 2 ≤0.5A 1 , 2B 1 ≤B 2 ≤3B 1 , 2C 1 ≤C 2 ≤3C 1 The present invention can effectively improve the internal stress regulation effect of the sapphire substrate GaN epitaxial wafer and the silicon-based CMOS driver wafer during the wafer-level bonding process, and can effectively reduce the risk of wafer breakage, thereby ensuring the production yield of the Micro-LED micro display array.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a Micro-LED micro display array and a preparation method thereof. Background Art

[0002] At present, Micro-LED micro display arrays can be produced by wafer-level bonding, substrate transfer and photolithography of GaN epitaxial wafers and CMOS driver wafers; Micro-LED micro display arrays have many significant advantages, including ultra-high brightness, excellent contrast, fast response time, low energy consumption and long service life, etc. With these outstanding advantages, Micro-LED micro display arrays have been widely used in the micro display field of AR and VR.

[0003] However, GaN epitaxial wafers usually use sapphire wafers as substrates, and CMOS driver wafers usually use silicon wafers as substrates. The thermal expansion coefficients of sapphire wafers and silicon wafers are very different; therefore, during the wafer-level bonding process of GaN epitaxial wafers and CMOS driver wafers, temperature changes will cause severe internal stress between the wafers, which can easily lead to wafer breakage, which seriously affects the production yield of Micro-LED micro display arrays. Summary of the invention

[0004] The purpose of the present invention is to overcome the shortcomings of the prior art. The present invention provides a Micro-LED micro display array and a preparation method thereof, which can effectively improve the internal stress regulation effect of sapphire substrate GaN epitaxial wafers and silicon-based CMOS driver wafers during wafer-level bonding, and can effectively reduce the risk of wafer breakage, thereby ensuring the production yield of the Micro-LED micro display array.

[0005] The present invention provides a method for preparing a Micro-LED micro display array, comprising the following steps:

[0006] S1, depositing an ITO layer, a first adhesion layer, a first stress release group layer and a first bonding layer in sequence on a GaN epitaxial layer of a sapphire substrate GaN epitaxial wafer to obtain a first preliminary bonding wafer;

[0007] The first stress release layer group includes a first Ti layer, a first Pt layer and a first Au layer stacked in sequence, the thickness of the first Ti layer is A1, the thickness of the first Pt layer is B1, and the thickness of the first Au layer is C1;

[0008] S2, sequentially depositing a second adhesion layer, a second stress release group layer and a second bonding layer on the driving circuit layer of the silicon-based CMOS driving wafer to obtain a second preliminary bonding wafer;

[0009] The second stress release layer group includes a second Ti layer, a second Pt layer and a second Au layer stacked in sequence, the thickness of the second Ti layer is A2, 0.3A1≤A2≤0.5A1; the thickness of the second Pt layer is B2, 2B1≤B2≤3B1; the thickness of the second Au layer is C2, 2C1≤C2≤3C1;

[0010] S3, performing hot pressing eutectic bonding on the first preliminary bonding sheet and the second preliminary bonding sheet to obtain a eutectic bonding sheet;

[0011] S4, peeling off the sapphire substrate of the eutectic bonded wafer to obtain an epitaxial transfer wafer;

[0012] S5. Perform photolithography processing on the epitaxial transfer sheet to obtain a Micro-LED micro display array.

[0013] Specifically, the thickness of the ITO layer is controlled to be 5 to 25 nm;

[0014] The material of the first adhesion layer is Cr, and the thickness of the first adhesion layer is controlled to be 1-5 nm;

[0015] Controlling the thickness of the first Ti layer to be 5 to 60 nm;

[0016] Controlling the thickness of the first Pt layer to be 1 to 150 nm;

[0017] Controlling the thickness of the first Au layer to be 5 to 50 nm;

[0018] The material of the first bonding layer includes one or more of Cu, Au, Ag, Pb, and Sn;

[0019] The material of the second adhesion layer is Cr, and the thickness of the second adhesion layer is controlled to be 1-5 nm;

[0020] The material of the second bonding layer includes one or more of Cu, Au, Ag, Pb, and Sn.

[0021] Specifically, the first bonding layer is a first AuSnAu laminated structure, the first AuSnAu laminated structure includes a first thick Au element sublayer, a first Sn element sublayer and a first thin Au element sublayer stacked in sequence, the thickness of the first thick Au element sublayer is controlled to be 50-100nm, the thickness of the first Sn element sublayer is controlled to be 50-100nm, and the thickness of the first thin Au element sublayer is controlled to be 2-5nm;

[0022] The second bonding layer is a second AuSnAu stacked structure, which includes a second thick Au element sublayer, a second Sn element sublayer and a second thin Au element sublayer stacked in sequence. The thickness of the second thick Au element sublayer is controlled to be 100 to 300 nm, the thickness of the second Sn element sublayer is controlled to be 100 to 300 nm, and the thickness of the second thin Au element sublayer is controlled to be 5 to 10 nm.

[0023] Specifically, before forming the first stress release group layer, the method further includes:

[0024] An insertion layer is deposited on the first adhesion layer. The material of the insertion layer is Mo or W. The thickness of the insertion layer is controlled to be 1-20 nm.

[0025] Specifically, the hot pressing eutectic bonding includes:

[0026] Pre-pressing and bonding the first preliminary bonding sheet and the second preliminary bonding sheet to obtain a pre-bonded sheet;

[0027] Under the condition of 200-300° C., a pressure of 2500-3500 kgf is applied to the pre-bonded sheet for 10-20 minutes to obtain the eutectic bonded sheet.

[0028] Specifically, a laser is used to peel off the sapphire substrate of the eutectic bonded wafer, the laser power is controlled to be 0.2-0.8 watts, and the heating temperature for peeling off the sapphire substrate is controlled to be 50-150°C.

[0029] Specifically, the photolithography processing of the epitaxial transfer sheet includes:

[0030] S51, dry-etching the GaN epitaxial layer on the epitaxial transfer wafer to flatten the exposed surface after peeling off the sapphire substrate to obtain a shaped wafer;

[0031] S52, performing pattern etching on the GaN epitaxial layer on the shaped wafer to form a plurality of light-emitting units arranged in an array on the ITO layer;

[0032] S53, etching downward from the ITO layer on the shaping wafer to the silicon-based CMOS driving wafer to form a plurality of anode units arranged in an array;

[0033] Any of the anode units is electrically connected to the driving circuit layer of the silicon-based CMOS driving wafer, and each of the anode units and the corresponding light-emitting unit form a light-emitting particle;

[0034] S54, growing and forming a passivation layer along the surface of each of the luminescent particles;

[0035] S55, etching the passivation layer on the top of each of the light-emitting particles to form a window, wherein the window exposes the top of the light-emitting unit;

[0036] S56, depositing an ITO transparent conductive layer on the passivation layer and the window along the surface of each of the light-emitting particles;

[0037] The ITO transparent conductive layer is connected to the top of all light-emitting units to serve as a transparent common cathode;

[0038] S57, depositing a metal reflective layer on the ITO transparent conductive layer, wherein the metal reflective layer fills the gaps between the light-emitting particles and avoids the tops of the light-emitting particles, to obtain a Micro-LED micro display array.

[0039] Specifically, in step S51, the GaN epitaxial layer on the epitaxial transfer wafer is etched and thinned by at least 2 μm;

[0040] In step S52, the top size of each light-emitting unit is 2-3 μm, the bottom size of each light-emitting unit is 4-5 μm, and the spacing between adjacent light-emitting units is 1-3 μm;

[0041] In step S54, the thickness of the passivation layer is controlled to be 100-120 nm, and the material of the passivation layer includes SiO2, TiO2, Al2O3, SiN x 、AlN x One or more of;

[0042] In step S55, the size of the window is controlled to be 1-2 μm;

[0043] In step S56, the thickness of the ITO transparent conductive layer is controlled to be 150-250 nm;

[0044] In step S57, the material of the metal reflective layer is Al or Ag.

[0045] Specifically, a Ti adhesion layer is deposited on the metal reflection layer, and a Pt conductive layer is deposited on the Ti adhesion layer. The Ti adhesion layer and the Pt conductive layer form a top reflection structure, and the top reflection structure avoids the top of the light-emitting particle.

[0046] The present invention also provides a Micro-LED micro display array, and the Micro-LED micro display array is prepared by the preparation method of the Micro-LED micro display array.

[0047] Compared with the prior art, the present invention has the following beneficial effects:

[0048] In the preparation method of the Micro-LED micro display array of the present invention, an ITO layer, a first adhesion layer, a first stress release group layer and a first bonding layer are sequentially deposited on the GaN epitaxial layer of the sapphire substrate GaN epitaxial wafer, and a second adhesion layer, a second stress release group layer and a second bonding layer are sequentially deposited on the driving circuit layer of the silicon-based CMOS driver wafer; wherein the adhesion layer can enhance the adhesion stability of the stress release group layer on the corresponding wafer, and lay a good foundation for the stress release group layer to exert the stress release effect; the first stress release group layer and the second stress release group layer are coordinated by setting a Ti / Pt / Au layer with a specific thickness ratio, which can effectively improve the internal stress regulation effect of the sapphire substrate GaN epitaxial wafer and the silicon-based CMOS driver wafer during the wafer-level bonding process, and can effectively reduce the risk of wafer breakage, thereby ensuring the production yield of the Micro-LED micro display array. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0050] Figure 1 1 is a schematic diagram of a process for preparing a Micro-LED micro display array according to an embodiment of the present invention;

[0051] Figure 2 is a schematic structural diagram of a GaN epitaxial wafer on a sapphire substrate in an embodiment of the present invention;

[0052] Figure 3 is a first structural schematic diagram of a first preliminary bonding sheet in an embodiment of the present invention;

[0053] Figure 4 is a second structural schematic diagram of the first preliminary bonding sheet in an embodiment of the present invention;

[0054] Figure 5 is a schematic diagram of the structure of a silicon-based CMOS driver wafer in an embodiment of the present invention;

[0055] Figure 6 is a schematic structural diagram of a second preliminary bonding sheet in an embodiment of the present invention;

[0056] Figure 7 is a schematic structural diagram of a eutectic bonding sheet in an embodiment of the present invention;

[0057] Figure 8 is a schematic structural diagram of an epitaxial transfer sheet in an embodiment of the present invention;

[0058] Fig. 9 It is a schematic diagram of the process of photolithography processing of an epitaxial transfer wafer in an embodiment of the present invention;

[0059] Fig.10 is a schematic structural diagram of a shaping disc in an embodiment of the present invention;

[0060] Fig.11 is a schematic structural diagram of a light-emitting unit in an embodiment of the present invention;

[0061] Fig.12 is a schematic structural diagram of an anode unit in an embodiment of the present invention;

[0062] Fig.13 is a schematic structural diagram of a passivation layer in an embodiment of the present invention;

[0063] Fig.14 is a schematic structural diagram of a window in an embodiment of the present invention;

[0064] Fig.15 is a schematic structural diagram of an ITO transparent conductive layer in an embodiment of the present invention;

[0065] Fig.16 is a schematic structural diagram of a metal reflective layer in an embodiment of the present invention;

[0066] Fig.17 Schematic diagram of the overall structure of the Micro-LED micro display array in an embodiment of the present invention;

[0067] Fig.18 is a schematic diagram of the state of the epitaxial transfer sheet of Comparative Example 1;

[0068] Fig.19 is a schematic diagram of the state of the epitaxial transfer sheet of Example 1;

[0069] Fig. 20 is a schematic diagram of the state of the epitaxial transfer sheet of Example 2;

[0070] Fig.21 It is a schematic diagram of the state of the epitaxial transfer sheet in Example 3.

[0071] In the accompanying drawings, 100, GaN epitaxial wafer on sapphire substrate; 110, sapphire substrate; 120, GaN epitaxial layer; 121, N-GaN layer; 122, MQW light-emitting layer; 123, P-GaN layer; 200, ITO layer; 310, first adhesion layer; 320, second adhesion layer; 410, first stress release group layer; 411, first Ti layer; 412, first Pt layer; 413, first Au layer; 420, second stress release group layer; 421, second Ti layer; 422, second Pt Layer; 423, second Au layer; 500, eutectic bonding layer; 510, first bonding layer; 520, second bonding layer; 600, insertion layer; 700, silicon-based CMOS driving wafer; 710, silicon substrate; 720, driving circuit layer; 800, luminous particles; 801, passivation layer; 802, window; 803, ITO transparent conductive layer; 810, light-emitting unit; 820, anode unit; 910, metal reflective layer; 920, top reflective structure; 921, Ti adhesion layer; 922, Pt conductive layer. DETAILED DESCRIPTION

[0072] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0073] The present invention provides a method for preparing a Micro-LED micro display array. Figure 1 The schematic diagram of the process of preparing a Micro-LED micro display array in an embodiment of the present invention is shown, and the process includes the following steps:

[0074] S1, depositing an ITO layer, a first adhesion layer, a first stress release group layer and a first bonding layer in sequence on a GaN epitaxial layer of a sapphire substrate GaN epitaxial wafer to obtain a first preliminary bonding wafer;

[0075] Figure 2 A schematic structural diagram of a GaN epitaxial wafer on a sapphire substrate in an embodiment of the present invention is shown. The GaN epitaxial wafer on a sapphire substrate 100 includes a sapphire substrate 110 and a GaN epitaxial layer 120 disposed on the sapphire substrate 110; wherein the sapphire substrate 110 is a patterned sapphire substrate, and the GaN epitaxial layer 120 includes an N-GaN layer 121, an MQW light-emitting layer 122, and a P-GaN layer 123 sequentially stacked on the patterned sapphire substrate.

[0076] Figure 3The first structural schematic diagram of the first preliminary bonding sheet in the embodiment of the present invention is shown, where the ITO layer 200 , the first adhesion layer 310 , the first stress release group layer 410 and the first bonding layer 510 are sequentially stacked on the P-GaN layer 123 .

[0077] As an ohmic contact layer, the ITO layer 200 not only provides good electrical properties, but also can serve as an additional stress buffer layer. Specifically, the thickness of the ITO layer 200 is controlled to be 5 to 25 nm; preferably, the thickness of the ITO layer 200 is controlled to be 10 to 20 nm, which is conducive to maintaining light transmittance.

[0078] In some specific embodiments, the ITO layer 200 is deposited by magnetron sputtering technology; after the ITO layer 200 is formed, it is heat-treated in an oxygen atmosphere for 1 to 5 minutes; the tin element in the ITO layer 200 can react with oxygen to form a more stable oxide structure, which is also conducive to reducing defects and impurities that may exist in the ITO layer 200, thereby improving the overall performance. Preferably, after the ITO layer 200 is formed, it is heat-treated in an oxygen atmosphere for 3 to 4 minutes, and the performance of ITO is excellent.

[0079] Specifically, the heat treatment temperature range of the ITO layer 200 is 200-500° C., which can improve the conductivity, light transmittance and stability of the ITO layer 200. Preferably, the heat treatment temperature range of the ITO layer 200 is 330-370° C., which has little effect on the sapphire substrate GaN epitaxial wafer 100.

[0080] In some specific embodiments, the first adhesion layer 310 is formed by deposition using electron beam melting molding technology (EBM technology); the material of the first adhesion layer 310 is Cr, and the thickness of the first adhesion layer 310 is controlled to be 1-5 nm, which is conducive to forming good adhesion between the ITO layer 200 and the first stress release group layer 410, that is, improving the adhesion stability of the first stress release group layer 410 on the sapphire substrate GaN epitaxial wafer 100, and laying a good foundation for the first stress release group layer 410 to exert stress release effect. Preferably, the thickness of the first adhesion layer 310 is controlled to be 2-3 nm, which produces a good adhesion effect, and is thin enough not to have a significant impact on the stress state of the overall structure.

[0081] In some specific embodiments, see Figure 3 The first stress release layer 410 includes a first Ti layer 411 (thermal expansion coefficient 8.2×10 -6 / ℃), the first Pt layer 412 (thermal expansion coefficient 9.0×10 -6 / ℃) and the first Au layer 413 (thermal expansion coefficient 14×10 -6 / ℃), the first Ti layer 411 has a good interface bonding effect with other materials, can provide good adhesion, and ensure the firm connection between the first stress release group layer 410 and the first adhesion layer 310; the first Pt layer 412 mainly plays a blocking role, which can effectively block the diffusion of the first Au layer 413 and prevent the first Au layer 413 from contaminating or affecting the underlying materials; at the same time, the blocking effect of the first Pt layer 412 helps to reduce the stress caused by material diffusion during the wafer-level bonding process; the first Au layer 413 can enhance the bonding performance of the first bonding layer 510.

[0082] Specifically, the thickness of the first Ti layer 411 is controlled to be 5 to 60 nm, the thickness of the first Pt layer 412 is controlled to be 1 to 150 nm, and the thickness of the first Au layer 413 is controlled to be 5 to 50 nm, which is conducive to releasing thermal stress and preventing warping and cracking during bonding. Preferably, the thickness of the first Ti layer 411 is controlled to be 30 to 50 nm, the thickness of the first Pt layer 412 is controlled to be 5 to 10 nm, and the thickness of the first Au layer 413 is controlled to be 5 to 15 nm, and the effect of stress release is excellent.

[0083] Figure 4 The second structural schematic diagram of the first preliminary bonding sheet in the embodiment of the present invention is shown. Before forming the first stress release group layer 410, it also includes: depositing an insertion layer 600 on the first adhesion layer 310. The material of the insertion layer 600 is Mo (thermal expansion coefficient 5.2×10 -6 / ℃) or W (thermal expansion coefficient 4.5×10 -6 / ℃), and the thickness of the insertion layer 600 is controlled to be 1-20nm. Mo and W both have a low thermal expansion coefficient and a high bonding force. On the one hand, they can be used as transition metals and have good compatibility with the first adhesion layer 310 (Cr) and the bottom material (Ti) of the first stress release group layer 410. This compatibility ensures that the insertion layer 600 can form a stable interface with the adjacent layers, thereby enhancing the stability of the overall structure; on the other hand, the insertion layer 600 can further promote stress release and reduce stress concentration between the first adhesion layer 310 and the first stress release group layer 410.

[0084] Preferably, the thickness of the insertion layer 600 is controlled to be 10-14 nm, which has an excellent stress release effect.

[0085] In some specific embodiments, the material of the first bonding layer 510 includes one or more of Cu, Au, Ag, Pb, and Sn, which have good electrical conductivity and bonding properties.

[0086] Preferably, the first bonding layer 510 is a first AuSnAu laminated structure, which includes a first thick Au element sublayer, a first Sn element sublayer and a first thin Au element sublayer stacked in sequence, and the thickness of the first thick Au element sublayer is controlled to be 50-100nm, the thickness of the first Sn element sublayer is controlled to be 50-100nm, and the thickness of the first thin Au element sublayer is controlled to be 2-5nm. The first thick Au element sublayer provides good conductivity and adhesion, which helps to enhance the bonding strength; the first Sn element sublayer, as an intermediate layer, can form a gold-tin alloy with Au, reduce the bonding temperature, and improve the bonding effect; the first thin Au element sublayer can prevent Sn oxidation and protect the bonding interface; by accurately controlling the thickness of each sublayer, the overall performance of the first bonding layer 510 can be optimized.

[0087] S2, sequentially depositing a second adhesion layer, a second stress release group layer and a second bonding layer on the driving circuit layer of the silicon-based CMOS driving wafer to obtain a second preliminary bonding wafer;

[0088] Figure 5 The schematic diagram of the structure of the silicon-based CMOS driver wafer in the embodiment of the present invention is shown. The silicon-based CMOS driver wafer 700 includes a silicon substrate 710 and a driver circuit layer 720 disposed in the silicon substrate 710 .

[0089] Figure 6 It shows a schematic structural diagram of the second preliminary bonding sheet in an embodiment of the present invention, in which the second adhesion layer 320 , the second stress release group layer 420 and the second bonding layer 520 are sequentially stacked on the driving circuit layer 720 .

[0090] In some specific embodiments, the second adhesion layer 320 is formed by deposition using electron beam melting molding technology (EBM technology); the material of the second adhesion layer 320 is Cr, and the thickness of the second adhesion layer 320 is controlled to be 1-5nm, which is conducive to forming good adhesion between the driving circuit layer 720 and the second stress release layer 420, that is, improving the adhesion stability of the second stress release layer 420 on the silicon-based CMOS driving wafer 700, and laying a good foundation for the second stress release layer 420 to exert stress release effect. Preferably, the thickness of the second adhesion layer 320 is controlled to be 2-3nm, which produces a good adhesion effect, and is thin enough not to have a significant impact on the stress state of the overall structure.

[0091] In some specific embodiments, see Figure 6 The second stress release layer 420 includes a second Ti layer 421 (thermal expansion coefficient 8.2×10 -6 / ℃), the second Pt layer 422 (thermal expansion coefficient 9.0×10 -6 / ℃) and the second Au layer 423 (thermal expansion coefficient 14×10 -6 / ℃), the second Ti layer 421 has a good interface bonding effect with other materials, can provide good adhesion, and ensure the firm connection between the second stress release group layer 420 and the second adhesion layer 320; the second Pt layer 422 mainly plays a blocking role, which can effectively block the diffusion of the second Au layer 423 and prevent the second Au layer 423 from contaminating or affecting the underlying materials; at the same time, the blocking effect of the second Pt layer 422 helps to reduce the stress caused by material diffusion during the wafer-level bonding process; the second Au layer 423 can enhance the bonding performance of the second bonding layer 520.

[0092] Specifically, the thickness of the first Ti layer 411 is A1, the thickness of the first Pt layer 412 is B1, the thickness of the first Au layer 413 is C1, the thickness of the second Ti layer 421 is A2, the thickness of the second Pt layer 422 is B2, and the thickness of the second Au layer 423 is C2.

[0093] The constraint relationship between A1 and A2 is: 0.3A1≤A2≤0.5A1;

[0094] The constraint relationship between B1 and B2 is: 2B1≤B2≤3B1;

[0095] The constraint relationship between C1 and C2 is: 2C1≤C2≤3C1.

[0096] By precisely controlling the thickness ratio of the first stress release layer 410 and the second stress release layer 420, effective stress regulation and dispersion can be achieved in the subsequent hot pressing eutectic bonding process. Among them, the thinner second Ti layer 421 can reduce the influence of the hard metal layer on the overall flexibility, while the thicker second Pt layer 422 and the second Au layer 423 can provide better stress buffering and bonding performance.

[0097] In some specific embodiments, the material of the second bonding layer 520 includes one or more of Cu, Au, Ag, Pb, and Sn, which have good electrical conductivity and bonding properties.

[0098] Preferably, the second bonding layer 520 is a second AuSnAu laminated structure, which includes a second thick Au element sublayer, a second Sn element sublayer and a second thin Au element sublayer stacked in sequence, and the thickness of the second thick Au element sublayer is controlled to be 100-300nm, the thickness of the second Sn element sublayer is controlled to be 100-300nm, and the thickness of the second thin Au element sublayer is controlled to be 5-10nm. The second thick Au element sublayer provides good conductivity and adhesion, which helps to enhance the bonding strength; the second Sn element sublayer, as an intermediate layer, can form a gold-tin alloy with Au, reduce the bonding temperature, and improve the bonding effect; the second thin Au element sublayer can prevent Sn oxidation and protect the bonding interface; by accurately controlling the thickness of each sublayer, the overall performance of the second bonding layer 520 can be optimized.

[0099] Different from the conventional bonding layer with equal thickness design, the first AuSnAu stacked structure and the second AuSnAu stacked structure adopt different thickness designs. On the one hand, it is to adapt to the needs of different material interfaces to achieve better bonding effect; on the other hand, it is to adapt the bonding layer to the corresponding stress release group layer to produce a synergistic effect. The stress release group layer adjusts the thickness ratio of the Ti, Pt and Au layers to relieve the stress of the sapphire substrate GaN epitaxial wafer 100 and the silicon-based CMOS driver wafer 700 during the wafer-level bonding process, and the AuSnAu structure of the bonding layer further optimizes the performance of the bonding interface. This combination not only improves the bonding strength, but also helps to reduce the stress problem caused by the difference in thermal expansion coefficients, thereby improving the structural reliability of the wafers after bonding.

[0100] S3, performing hot pressing eutectic bonding on the first preliminary bonding sheet and the second preliminary bonding sheet to obtain a eutectic bonding sheet;

[0101] Figure 7 A schematic structural diagram of a eutectic bonding wafer in an embodiment of the present invention is shown, wherein the first stress release group layer 410, the second stress release group layer 420, the first bonding layer 510 and the second bonding layer 520 are fused to form a eutectic bonding layer 500, which not only improves the internal stress regulation effect of the sapphire substrate GaN epitaxial wafer 100 and the silicon-based CMOS driver wafer 700 during the wafer-level bonding process, but also enhances the bonding strength between the sapphire substrate GaN epitaxial wafer 100 and the silicon-based CMOS driver wafer 700, making the structure of the wafers after bonding reliable and stable, thereby helping to reduce the risk of breakage during subsequent processing.

[0102] In some specific embodiments, the thermal compression eutectic bonding includes:

[0103] The first preliminary bonding sheet and the second preliminary bonding sheet are pre-pressed and bonded to obtain a pre-bonded sheet; the pre-pressed bonding helps to initially align and contact the two preliminary bonding sheets, laying a foundation for subsequent formal bonding.

[0104] Under the condition of 200-300° C., a pressure of 2500-3500 kgf is applied to the pre-bonded sheet for 10-20 minutes to obtain the eutectic bonded sheet. The temperature condition of 200-300° C. is conducive to promoting the diffusion of metal atoms and the eutectic reaction; the pressure of 2500-3500 kgf can ensure that the two pre-bonded sheets are in close contact, which is conducive to forming a stable bonding interface; the holding time of 10-20 minutes can make the eutectic reaction fully proceed and form a high-quality eutectic bonding layer 500.

[0105] Moreover, this hot-pressed eutectic bonding method, with the cooperation of the first stress release layer 410 and the second stress release layer 420, can effectively reduce the internal stress during the bonding process, greatly improving the preparation yield and reliability of the eutectic bonding sheet.

[0106] Preferably, the first preliminary bonding sheet and the second preliminary bonding sheet are pre-bonded, using a pressure of 800 kgf for 2 minutes to obtain a pre-bonded sheet; then, the temperature is raised to 250°C, a pressure of 3000 kgf is applied to the pre-bonded sheet for 15 minutes, and finally naturally cooled to room temperature to obtain a eutectic bonded sheet. This set of parameter settings has shown good results in actual production, which can not only ensure the bonding quality, but also minimize the impact of thermal stress and mechanical stress on the device.

[0107] S4, peeling off the sapphire substrate of the eutectic bonded wafer to obtain an epitaxial transfer wafer;

[0108] Figure 8 A schematic diagram of the structure of an epitaxial transfer sheet in an embodiment of the present invention is shown. The sapphire substrate 110 of the eutectic bonded sheet is peeled off using a laser. The laser beam is focused by an optical system and irradiated on the interface between the sapphire substrate 110 and the GaN epitaxial layer 120. The laser energy is absorbed by the GaN epitaxial layer 120 and converted into heat energy, causing the GaN at the interface to decompose and produce nitrogen. The pressure of these gases helps to peel off the sapphire substrate 110.

[0109] In some specific embodiments, the laser power is controlled to be 0.2 to 0.8 watts. This power range can provide sufficient energy to separate the interface between the sapphire substrate 110 and the GaN epitaxial layer 120, while not easily causing thermal damage to the structure; moreover, lower power can reduce thermal stress and avoid causing material deformation or damage. Specifically, the heating temperature for stripping the sapphire substrate 110 is controlled to be 50 to 150°C, that is, while the sapphire substrate 110 is stripped with a laser, the eutectic bonded wafer is additionally heated. This temperature range not only helps to reduce the bonding force between the materials, but also promotes the decomposition of GaN at the interface to produce a large amount of nitrogen, making the stripping process easier to carry out. A good stripping process can effectively improve the phenomenon of broken pieces and warping, which is conducive to improving the yield of the obtained epitaxial transfer wafer.

[0110] In some specific embodiments, the stripped sapphire substrate 110 is immersed in a 10% dilute hydrochloric acid solution for 3 to 6 minutes to remove Ga residues on the surface of the sapphire substrate 110, and then washed in ultrapure water to remove HCl residues. The dried sapphire substrate 110 can be reused.

[0111] S5. Perform photolithography processing on the epitaxial transfer sheet to obtain a Micro-LED micro display array.

[0112] The epitaxial layer of the epitaxial transfer film is pixelated using a micro-photolithography process, which can accurately define the position and size of the array, and physically separate the pixels to achieve independent driving of individual pixels.

[0113] Fig. 9 The schematic diagram of the process of photolithography processing of the epitaxial transfer sheet in an embodiment of the present invention is shown, and the photolithography processing of the epitaxial transfer sheet includes:

[0114] S51, dry-etching the GaN epitaxial layer on the epitaxial transfer wafer to flatten the exposed surface after peeling off the sapphire substrate to obtain a shaped wafer;

[0115] Fig.10 A schematic diagram of the structure of the shaped wafer in an embodiment of the present invention is shown. The GaN epitaxial layer 120 on the epitaxial transfer wafer is etched and thinned by at least 2 μm using ICP dry etching technology, which helps to remove the damaged layer that may be generated in the N-GaN layer 121 during the stripping process, so as to improve the quality of subsequent processing.

[0116] S52, performing pattern etching on the GaN epitaxial layer on the shaped wafer to form a plurality of light-emitting units arranged in an array on the ITO layer;

[0117] Fig.11The schematic diagram of the structure of the light-emitting unit in the embodiment of the present invention is shown. The light-emitting unit 810 stands on the ITO layer 200, and a single light-emitting unit 810 corresponds to a single pixel.

[0118] The GaN epitaxial layer 120 is patterned and etched using ICP dry etching technology; the top size of each light-emitting unit 810 is 2 to 3 μm, the bottom size of each light-emitting unit 810 is 4 to 5 μm, and the spacing between adjacent light-emitting units 810 is 1 to 3 μm, which can achieve a high-density, high-uniformity array of light-emitting units 810 and improve display resolution and brightness uniformity.

[0119] S53, etching downward from the ITO layer on the shaping wafer to the silicon-based CMOS driving wafer to form a plurality of anode units arranged in an array;

[0120] Fig.12 The schematic diagram of the structure of the anode unit in the embodiment of the present invention is shown. The anode unit 820 of the array is formed by stacking and etching the ITO layer 200, the first adhesion layer 310, the eutectic bonding layer 500 and the second adhesion layer 320. Any of the anode units 820 and the driving circuit layer 720 of the silicon-based CMOS driving wafer 700 are electrically connected. Each of the anode units 820 and the corresponding light-emitting unit 810 form a light-emitting particle 800.

[0121] The driving circuit layer 720 can provide a driving signal to a single light-emitting particle 800 to control the on or off of the light-emitting particle 800. When the light-emitting particle 800 is in the on state, it can emit light; when the light-emitting particle 800 is in the off state, it does not emit light.

[0122] Specifically, the driving circuit layer 720 has a plurality of exposed control electrodes, each of which is electrically connected to the corresponding anode unit 820, thereby realizing the control function. The material of the control electrode is W, which has good thermal conductivity and electrical conductivity.

[0123] S54, growing and forming a passivation layer along the surface of each of the luminescent particles;

[0124] Fig.13 A schematic diagram of the structure of the passivation layer in an embodiment of the present invention is shown. The passivation layer 801 is grown by PECVD technology, magnetron sputtering technology or atomic deposition technology. The passivation layer 801 can passivate the etching defects on the surface of the luminescent particles 800 and form dielectric isolation to prevent short circuits between the luminescent particles 800 caused by dirt.

[0125] Furthermore, the thickness of the passivation layer 801 is controlled to be 100-120 nm, and the material of the passivation layer 801 includes SiO2, TiO2, Al2O3, SiN x 、AlNx One or more of the above makes the passivation layer 801 have excellent barrier properties, which can effectively prevent the penetration of moisture and oxygen, and is beneficial to improving the life of the luminescent particle 800.

[0126] S55, etching the passivation layer on the top of each of the light-emitting particles to form a window, wherein the window exposes the top of the light-emitting unit;

[0127] Fig.14 The schematic diagram of the structure of the window in the embodiment of the present invention is shown. The ICP dry etching technology is used to etch the passivation layer 801 on the top of each light-emitting particle 800 to form a window 802, which is convenient for the subsequent electrical connection between N-GaN and the transparent common cathode.

[0128] Furthermore, controlling the size of the window 802 to 1 to 2 μm not only improves the efficiency of current injection, but also helps to improve light extraction efficiency, ensuring good electrical contact and optical performance; the size of the window 802 is smaller than the top size of the light-emitting unit 810, which is convenient for processing.

[0129] S56, depositing an ITO transparent conductive layer on the passivation layer and the window along the surface of each of the light-emitting particles;

[0130] Fig.15 A schematic diagram of the structure of the ITO transparent conductive layer in an embodiment of the present invention is shown, wherein the ITO transparent conductive layer 803 is directly connected to the top of all the light-emitting units 810 to serve as a transparent common cathode; the ITO transparent conductive layer 803 serves as a transparent common cathode, which not only ensures uniform current distribution, but also maintains good light transmittance, thereby further improving the light-emitting performance.

[0131] Specifically, the thickness of the ITO transparent conductive layer 803 is controlled to be 150-250 nm, so as to ensure good conductivity and maintain good light transmittance.

[0132] S57, depositing a metal reflective layer on the ITO transparent conductive layer, wherein the metal reflective layer fills the gaps between the light-emitting particles and avoids the tops of the light-emitting particles, to obtain a Micro-LED micro display array;

[0133] Fig.16 The schematic diagram of the structure of the metal reflective layer in the embodiment of the present invention is shown. The metal reflective layer 910 is formed by deposition using electron beam melting molding technology (EBM technology). The metal reflective layer 910 can reflect the lateral light emitted by the luminescent particle 800 back, so that the light is emitted from the window 802 on the top of the luminescent particle 800 as much as possible, which is beneficial to increase the light intensity emitted upward by the luminescent particle 800, thereby improving the overall luminous efficiency of the Micro-LED micro display array.

[0134] Specifically, the material of the metal reflective layer 910 is Al or Ag, which can effectively reflect light.

[0135] Fig.17 The overall structure schematic diagram of the Micro-LED micro display array in the embodiment of the present invention is shown, a Ti adhesion layer 921 is deposited on the metal reflection layer 910, a Pt conductive layer 922 is deposited on the Ti adhesion layer 921, the Ti adhesion layer 921 and the Pt conductive layer 922 form a top reflection structure 920, and the top reflection structure 920 avoids the top of the light-emitting particle 800. The top reflection structure 920 can not only enhance the reflection effect of the metal reflection layer 910, but also expand the current and promote the uniform distribution of the current.

[0136] The thickness of the Ti adhesion layer 921 is in the range of 15 to 25 nm, which can not only enhance the bonding force between the metal reflective layer 910 and the Pt conductive layer 922 , but also reduce the interface stress and improve the reliability of the entire structure.

[0137] The thickness of the Pt conductive layer 922 is in the range of 25 to 35 nm, which not only optimizes the reflection characteristics but also effectively expands the current.

[0138] In the preparation method of the Micro-LED micro display array of the present invention, an ITO layer 200, a first adhesion layer 310, a first stress release group layer 410 and a first bonding layer 510 are sequentially deposited on the GaN epitaxial layer 120 of the sapphire substrate GaN epitaxial wafer 100, and a second adhesion layer 320, a second stress release group layer 420 and a second bonding layer 520 are sequentially deposited on the driving circuit layer 720 of the silicon-based CMOS driving wafer 700; wherein the ITO layer 200 as an ohmic contact layer not only provides good electrical properties, but also can serve as an additional stress buffer layer; the adhesion layer can enhance the adhesion of the stress release group layer on the corresponding wafer. The stability of the attached layer is improved, which lays a good foundation for the stress release layer to exert its stress release effect; the stress release layer is coordinated by setting a Ti / Pt / Au layer with a specific thickness ratio, which can effectively improve the internal stress regulation effect of the sapphire substrate GaN epitaxial wafer 100 and the silicon-based CMOS driver wafer 700 during the wafer-level bonding process, and can effectively reduce the risk of wafer breakage, thereby ensuring the production yield of the Micro-LED micro display array; the AuSnAu structure of the bonding layer adopts different thickness designs, which can not only improve the bonding strength, but also help reduce the stress problem caused by the difference in thermal expansion coefficient, thereby improving the structural reliability of the wafer after bonding.

[0139] The preparation method of the Micro-LED micro display array of the present invention adopts a hot pressing eutectic method to bond the sapphire substrate GaN epitaxial wafer 100 and the silicon-based CMOS driver wafer 700. Through the cooperation of the first stress release layer 410 and the second stress release layer 420, the internal stress in the bonding process can be effectively reduced, and the preparation yield and reliability of the eutectic bonded wafer are greatly improved; the sapphire substrate 110 of the eutectic bonded wafer is assisted by laser peeling by additional heating, which can significantly reduce the peeling difficulty of the sapphire substrate 110, thereby effectively improving the breakage and warping phenomena, which is beneficial to improving the yield of the obtained epitaxial transfer wafer; the epitaxial layer of the epitaxial transfer wafer is pixelated by a micro-photolithography process, which can accurately define the position and size of the array, and physically separate the pixels to realize independent driving of a single pixel, and the obtained Micro-LED micro display array has good luminous uniformity, high yield, high brightness, good contrast, quick response, low energy consumption, and long service life.

[0140] The present invention also provides a Micro-LED micro display array, wherein the Micro-LED micro display array is prepared by the preparation method of the Micro-LED micro display array, see Fig.17 The Micro-LED micro display array includes a silicon-based CMOS driving wafer 700 and a plurality of light-emitting pixel points arranged in an array on the silicon-based CMOS driving wafer 700. The silicon-based CMOS driving wafer 700 has a driving circuit layer 720. The driving circuit layer 720 can individually control the turning on or off of any of the light-emitting pixel points.

[0141] Any of the luminous pixel points includes an anode unit 820, a light-emitting unit 810, a passivation layer 801 and a cathode unit, the bottom of any of the anode units 820 is electrically connected to the driving circuit layer 720, and the top of any of the anode units 820 is connected to the bottom of the corresponding light-emitting unit 810; any of the passivation layers 801 covers the surface of the corresponding anode unit 820 and the corresponding light-emitting unit 810, and any of the passivation layers 801 opens a window 802 at the top of the corresponding light-emitting unit 810; any of the cathode units covers the surface of the corresponding passivation layer 801, and passes through the corresponding window 802 to connect to the top of the corresponding light-emitting unit 810; all cathode units are connected to form a transparent common cathode (i.e., an ITO transparent conductive layer 803); the gaps between the luminous pixel points are filled with a metal reflective layer 910, and a Ti adhesion layer 921 and a Pt conductive layer 922 are sequentially stacked on the metal reflective layer 910, and the upper surface of the Pt conductive layer 922 is flush with the top of the luminous pixel point.

[0142] The Micro-LED micro display array of the present invention has good light emission uniformity, high yield, high brightness, good contrast, quick response, low energy consumption and long service life.

[0143] Comparative Example 1

[0144] (1) depositing an ITO layer, a first adhesion layer, a first stress release layer and a first bonding layer on the GaN epitaxial layer of the sapphire substrate GaN epitaxial wafer in sequence to obtain a first preliminary bonding wafer;

[0145] The first stress release layer group includes a first Ti layer, a first Pt layer and a first Au layer stacked in sequence, the thickness of the first Ti layer is 30 nm, the thickness of the first Pt layer is 10 nm, and the thickness of the first Au layer is 20 nm;

[0146] (2) depositing a second adhesion layer, a second stress release layer, and a second bonding layer on the driving circuit layer of the silicon-based CMOS driving wafer in sequence to obtain a second preliminary bonding wafer;

[0147] The second stress release layer group includes a second Ti layer, a second Pt layer and a second Au layer stacked in sequence, the thickness of the second Ti layer is 30 nm, the thickness of the second Pt layer is 10 nm, and the thickness of the second Au layer is 20 nm;

[0148] (3) performing hot pressing eutectic bonding on the first preliminary bonding wafer and the second preliminary bonding wafer to obtain a eutectic bonding wafer of Comparative Example 1;

[0149] (5) The sapphire substrate of the eutectic bonded wafer of comparative example 1 is peeled off to obtain the epitaxial transfer wafer of comparative example 1 ( Fig.18 Schematic diagram showing the state of the epitaxial transfer sheet of comparative example 1).

[0150] Example 1

[0151] (1) depositing an ITO layer, a first adhesion layer, a first stress release layer and a first bonding layer on the GaN epitaxial layer of the sapphire substrate GaN epitaxial wafer in sequence to obtain a first preliminary bonding wafer;

[0152] The first stress release layer group includes a first Ti layer, a first Pt layer and a first Au layer stacked in sequence, the thickness of the first Ti layer is 30 nm, the thickness of the first Pt layer is 10 nm, and the thickness of the first Au layer is 20 nm;

[0153] (2) depositing a second adhesion layer, a second stress release layer, and a second bonding layer on the driving circuit layer of the silicon-based CMOS driving wafer in sequence to obtain a second preliminary bonding wafer;

[0154] The second stress release layer group includes a second Ti layer, a second Pt layer and a second Au layer stacked in sequence, the thickness of the second Ti layer is 15 nm, the thickness of the second Pt layer is 20 nm, and the thickness of the second Au layer is 40 nm;

[0155] (3) performing hot pressing eutectic bonding on the first preliminary bonding wafer and the second preliminary bonding wafer to obtain the eutectic bonding wafer of Example 1;

[0156] (5) The sapphire substrate of the eutectic bonded wafer of Example 1 is peeled off to obtain the epitaxial transfer wafer of Example 1 ( Fig.19 Schematic diagram showing the state of the epitaxial transfer sheet of Example 1).

[0157] Example 2

[0158] (1) depositing an ITO layer, a first adhesion layer, a first stress release layer and a first bonding layer on the GaN epitaxial layer of the sapphire substrate GaN epitaxial wafer in sequence to obtain a first preliminary bonding wafer;

[0159] The first stress release layer group includes a first Ti layer, a first Pt layer and a first Au layer stacked in sequence, the thickness of the first Ti layer is 30 nm, the thickness of the first Pt layer is 10 nm, and the thickness of the first Au layer is 20 nm;

[0160] (2) depositing a second adhesion layer, a second stress release layer, and a second bonding layer on the driving circuit layer of the silicon-based CMOS driving wafer in sequence to obtain a second preliminary bonding wafer;

[0161] The second stress release layer group includes a second Ti layer, a second Pt layer and a second Au layer stacked in sequence, the thickness of the second Ti layer is 10 nm, the thickness of the second Pt layer is 30 nm, and the thickness of the second Au layer is 60 nm;

[0162] (3) performing hot pressing eutectic bonding on the first preliminary bonding wafer and the second preliminary bonding wafer to obtain the eutectic bonding wafer of Example 2;

[0163] (5) The sapphire substrate of the eutectic bonded wafer of Example 2 is peeled off to obtain the epitaxial transfer wafer of Example 2 ( Fig. 20 Schematic diagram showing the state of the epitaxial transfer sheet of Example 2).

[0164] Example 3

[0165] (1) depositing an ITO layer, a first adhesion layer, an insertion layer, a first stress release layer and a first bonding layer on a GaN epitaxial layer of a sapphire substrate GaN epitaxial wafer in sequence to obtain a first preliminary bonding wafer;

[0166] The material of the insertion layer is Mo, and the thickness of the insertion layer is controlled to be 15 nm; the first stress release group layer includes a first Ti layer, a first Pt layer and a first Au layer stacked in sequence, the thickness of the first Ti layer is 30 nm, the thickness of the first Pt layer is 10 nm, and the thickness of the first Au layer is 20 nm;

[0167] (2) depositing a second adhesion layer, a second stress release layer, and a second bonding layer on the driving circuit layer of the silicon-based CMOS driving wafer in sequence to obtain a second preliminary bonding wafer;

[0168] The second stress release layer group includes a second Ti layer, a second Pt layer and a second Au layer stacked in sequence, the thickness of the second Ti layer is 10 nm, the thickness of the second Pt layer is 30 nm, and the thickness of the second Au layer is 60 nm;

[0169] (3) performing hot pressing eutectic bonding on the first preliminary bonding wafer and the second preliminary bonding wafer to obtain the eutectic bonding wafer of Example 3;

[0170] (5) The sapphire substrate of the eutectic bonded wafer of Example 3 is peeled off to obtain the epitaxial transfer wafer of Example 3 ( Fig.21 Schematic diagram showing the state of the epitaxial transfer sheet of Example 3).

[0171] The warpage of the eutectic bonded wafers of Comparative Example 1 and Examples 1 to 3 was tested, and the results are shown in Table 1

[0172]

[0173] It can be seen from Comparative Example 1, Example 1 and Example 2 that as the thickness of the Ti / Pt / Au layer of the second stress release group layer is adjusted, the stress in the eutectic bonding sheet is effectively released, and the warping of the eutectic bonding sheet is significantly reduced; it can be seen from Example 2 and Example 3 that after adding the insertion layer, the stress in the eutectic bonding sheet is effectively released, and the warping of the eutectic bonding sheet is also significantly reduced.

[0174] Combining the schematic diagrams of the epitaxial transfer sheets of Comparative Example 1, Example 1, Example 2 and Example 3, it can be seen that: Fig.18 , the GaN epitaxial layer of the epitaxial transfer sheet of comparative example 1 has a large number of splits, which is caused by the excessive internal stress of the epitaxial transfer sheet of comparative example 1 before peeling; please refer to Fig.19 , the GaN epitaxial layer of the epitaxial transfer sheet of Example 1 is split around and in the central area. Compared with the epitaxial transfer sheet of Comparative Example 1, the split area of ​​the epitaxial transfer sheet of Example 1 is effectively reduced, indicating that the internal stress of the epitaxial transfer sheet of Example 1 is effectively released before peeling; please refer to Fig. 20, the GaN epitaxial layer of the epitaxial transfer sheet of Example 2 only has splitting in the edge area. Compared with the epitaxial transfer sheet of Example 1, the splitting area of ​​the epitaxial transfer sheet of Example 2 is effectively reduced, indicating that the internal stress of the epitaxial transfer sheet of Example 2 is effectively released before peeling; please refer to Fig.21 , the GaN epitaxial layer of the epitaxial transfer sheet of Example 3 did not split, indicating that the internal stress of the epitaxial transfer sheet of Example 3 had been fully released before peeling.

[0175] The above is a detailed introduction to a Micro-LED micro display array and a preparation method thereof provided in an embodiment of the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A method for preparing a Micro-LED micro display array, characterized in that: The following steps are involved: S1, depositing an ITO layer, a first adhesion layer, a first stress release group layer and a first bonding layer in sequence on a GaN epitaxial layer of a sapphire substrate GaN epitaxial wafer to obtain a first preliminary bonding wafer; The first bonding layer is a first AuSnAu stacked structure; the first stress release group layer includes a first Ti layer, a first Pt layer and a first Au layer stacked in sequence, the thickness of the first Ti layer is A1, and the thickness of the first Ti layer is controlled to be 5 to 60 nm; the thickness of the first Pt layer is B1, and the thickness of the first Pt layer is controlled to be 1 to 150 nm; the thickness of the first Au layer is C1, and the thickness of the first Au layer is controlled to be 5 to 50 nm; S2, sequentially depositing a second adhesion layer, a second stress release group layer and a second bonding layer on the driving circuit layer of the silicon-based CMOS driving wafer to obtain a second preliminary bonding wafer; The second bonding layer is a second AuSnAu stacked structure; the second stress release group layer comprises a second Ti layer, a second Pt layer and a second Au layer stacked in sequence, the thickness of the second Ti layer is A2, 0.3A1≤A2≤0.5A1; the thickness of the second Pt layer is B2, 2B1≤B2≤3B1; the thickness of the second Au layer is C2, 2C1≤C2≤3C1; S3, performing hot pressing eutectic bonding on the first preliminary bonding sheet and the second preliminary bonding sheet to obtain a eutectic bonding sheet; S4, peeling off the sapphire substrate of the eutectic bonded wafer to obtain an epitaxial transfer wafer; S5. Perform photolithography processing on the epitaxial transfer sheet to obtain a Micro-LED micro display array.

2. The method for preparing a Micro-LED micro display array according to claim 1, characterized in that: Controlling the thickness of the ITO layer to be 5 to 25 nm; The material of the first adhesion layer is Cr, and the thickness of the first adhesion layer is controlled to be 1-5 nm; The material of the second adhesion layer is Cr, and the thickness of the second adhesion layer is controlled to be 1-5 nm.

3. The method for preparing a Micro-LED micro display array according to claim 1, characterized in that: The first AuSnAu stacked structure includes a first thick Au element sublayer, a first Sn element sublayer and a first thin Au element sublayer stacked in sequence, the thickness of the first thick Au element sublayer is controlled to be 50-100 nm, the thickness of the first Sn element sublayer is controlled to be 50-100 nm, and the thickness of the first thin Au element sublayer is controlled to be 2-5 nm; The second AuSnAu stacked structure includes a second thick Au element sublayer, a second Sn element sublayer and a second thin Au element sublayer stacked in sequence. The thickness of the second thick Au element sublayer is controlled to be 100-300nm, the thickness of the second Sn element sublayer is controlled to be 100-300nm, and the thickness of the second thin Au element sublayer is controlled to be 5-10nm.

4. The method for preparing a Micro-LED micro display array according to claim 1, characterized in that: Before forming the first stress release group layer, the method further includes: An insertion layer is deposited on the first adhesion layer. The material of the insertion layer is Mo or W. The thickness of the insertion layer is controlled to be 1-20 nm.

5. The method for preparing a Micro-LED micro display array according to claim 1, characterized in that: The thermal compression eutectic bonding comprises: Pre-pressing and bonding the first preliminary bonding sheet and the second preliminary bonding sheet to obtain a pre-bonded sheet; Under the condition of 200-300° C., a pressure of 2500-3500 kgf is applied to the pre-bonded sheet for 10-20 minutes to obtain the eutectic bonded sheet.

6. The method for preparing a Micro-LED micro display array according to claim 1, characterized in that: The sapphire substrate of the eutectic bonded sheet is peeled off by using laser, the laser power is controlled to be 0.2-0.8 watts, and the heating temperature for peeling off the sapphire substrate is controlled to be 50-150°C.

7. The method for preparing a Micro-LED micro display array according to claim 1, characterized in that: The photolithography processing of the epitaxial transfer sheet comprises: S51, dry-etching the GaN epitaxial layer on the epitaxial transfer wafer to flatten the exposed surface after peeling off the sapphire substrate to obtain a shaped wafer; S52, performing pattern etching on the GaN epitaxial layer on the shaped wafer to form a plurality of light-emitting units arranged in an array on the ITO layer; S53, etching downward from the ITO layer on the shaping wafer to the silicon-based CMOS driving wafer to form a plurality of anode units arranged in an array; Any of the anode units is electrically connected to the driving circuit layer of the silicon-based CMOS driving wafer, and each of the anode units and the corresponding light-emitting unit form a light-emitting particle; S54, growing and forming a passivation layer along the surface of each of the luminescent particles; S55, etching the passivation layer on the top of each of the light-emitting particles to form a window, wherein the window exposes the top of the light-emitting unit; S56, depositing an ITO transparent conductive layer on the passivation layer and the window along the surface of each of the light-emitting particles; The ITO transparent conductive layer is connected to the top of all light-emitting units to serve as a transparent common cathode; S57, depositing a metal reflective layer on the ITO transparent conductive layer, wherein the metal reflective layer fills the gaps between the light-emitting particles and avoids the tops of the light-emitting particles, to obtain a Micro-LED micro display array.

8. The method for preparing a Micro-LED micro display array according to claim 7, characterized in that: In step S51, the GaN epitaxial layer on the epitaxial transfer wafer is etched and thinned by at least 2 μm; In step S52, the top size of each light-emitting unit is 2-3 μm, the bottom size of each light-emitting unit is 4-5 μm, and the spacing between adjacent light-emitting units is 1-3 μm; In step S54, the thickness of the passivation layer is controlled to be 100-120 nm, and the material of the passivation layer includes SiO2, TiO2, Al2O3, SiN x 、AlN x One or more of; In step S55, the size of the window is controlled to be 1-2 μm; In step S56, the thickness of the ITO transparent conductive layer is controlled to be 150-250 nm; In step S57, the material of the metal reflective layer is Al or Ag.

9. The method for preparing a Micro-LED micro display array according to claim 7, characterized in that: A Ti adhesion layer is deposited on the metal reflection layer, and a Pt conductive layer is deposited on the Ti adhesion layer. The Ti adhesion layer and the Pt conductive layer form a top reflection structure, and the top reflection structure avoids the top of the light-emitting particle.

10. A Micro-LED micro display array, characterized in that: The Micro-LED micro display array is prepared by the preparation method of the Micro-LED micro display array according to any one of claims 1 to 9.

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