A method and system for detecting abnormal operation parameters of a power chip

Abstract

The present invention provides a method and system for detecting abnormalities in operating parameters of a power chip, which relate to the field of data processing technology. The method comprises: using an electronic device equipped with a power chip as an edge node and a cloud server as a cloud platform, establishing a communication relationship between the edge node and the cloud platform, and constructing a cloud-edge collaborative abnormality detection architecture; obtaining operating parameters of the power chip at the edge node; judging at the edge node whether the power chip in the edge node has a fault risk through a rapid fault detection model according to the operating parameters of the power chip; if so, immediately shutting down the power chip and issuing an early warning; otherwise, uploading an output signal of the power chip to the cloud platform; extracting signal features of the output signal of the power chip at the cloud platform; judging at the cloud platform whether the power chip has a chronic degradation risk through a chronic degradation detection model according to the signal features of the output signal of the power chip; if so, issuing an early warning.

Description

Technical Field

[0001] The present invention relates to the technical field of data processing, and in particular to a method and system for detecting abnormality in operating parameters of a power chip. Background Art

[0002] Power chips are semiconductor devices that process and convert electrical energy. They are widely used in various power converters, drive circuits, electric vehicles, communication equipment, consumer electronics and other fields. The main function of a power chip is to convert the input voltage or current into a voltage or current that meets the load requirements to ensure the stable operation of the system. For example, common DC-DC converters, AC-DC converters, inverters, etc. all rely on power chips to achieve efficient power conversion. Power chips often work in high temperature, high frequency, and high current environments. The reliability of the components is crucial to the stability and safety of the system. Therefore, monitoring of the operating status and fault warning are particularly important.

[0003] Existing methods for detecting abnormal operating parameters mainly use a monitoring method based on safety thresholds. When operating parameters such as temperature, current, and voltage exceed safety thresholds during operation, an alarm is issued.

[0004] The safety threshold monitoring method can only provide an alarm after a fault occurs, but cannot predict potential risks before a fault occurs. Measures are often taken only after the system has been damaged. This lag reduces the effectiveness of maintenance and control.

[0005] Furthermore, although the safety threshold monitoring method can quickly trigger an alarm when a sudden change in parameters such as temperature, current, and voltage occurs, it is not sensitive to chronic degradation (such as performance degradation of capacitors and inductors) and does not have the ability to detect chronic degradation anomalies. Summary of the invention

[0006] In order to solve the problem that the existing safety threshold monitoring method can only provide an alarm after a fault occurs, but cannot predict potential risks before a fault occurs, and measures are often taken only after the system has been damaged. This hysteresis reduces the effectiveness of maintenance and control, is insensitive to chronic degradation (such as performance degradation of capacitors and inductors), and does not have the ability to detect chronic degradation anomalies, the present invention provides a power chip operating parameter anomaly detection method and system.

[0007] The technical solution provided by the embodiment of the present invention is as follows:

[0008] First aspect:

[0009] An embodiment of the present invention provides a method for detecting abnormal operation parameters of a power chip, comprising:

[0010] S1: Using an electronic device equipped with a power chip as an edge node and a cloud server as a cloud platform, establishing a communication relationship between the edge node and the cloud platform to build a cloud-edge collaborative anomaly detection architecture;

[0011] S2: configuring a fast fault detection model based on inductor current prediction at the edge node;

[0012] S3: configuring a chronic degradation detection model based on Gaussian process regression on the cloud platform;

[0013] S4: At the edge node, obtaining operating parameters of the power chip;

[0014] S5: At the edge node, judging whether the power chip in the edge node has a failure risk through the fast fault detection model according to the operating parameters of the power chip; if so, immediately shutting down the power chip and issuing an early warning prompt; otherwise, uploading the output signal of the power chip to the cloud platform;

[0015] S6: extracting, on the cloud platform, signal characteristics of the output signal of the power chip;

[0016] S7: On the cloud platform, judging whether the power chip has a risk of chronic degradation according to the signal characteristics of the output signal of the power chip through the chronic degradation detection model; if so, issuing an early warning prompt.

[0017] Second aspect:

[0018] An embodiment of the present invention provides a power chip operating parameter abnormality detection system, comprising:

[0019] processor;

[0020] A memory having computer-readable instructions stored thereon, wherein when the computer-readable instructions are executed by the processor, the method for detecting abnormal operation parameters of a power chip as described in the first aspect is implemented.

[0021] The beneficial effects brought about by the technical solution provided by the embodiment of the present invention include at least:

[0022] (1) In the present invention, a fast fault detection model based on inductor current prediction is configured on the edge node, which can predict the inductor current of the power chip and instantly analyze whether there is a fault risk, predicting potential risks before the fault occurs. Once a sudden fault is detected, the system can respond immediately, shut down the power chip and issue an early warning, thereby preventing equipment damage or system shutdown caused by fault expansion.

[0023] (2) In the present invention, chronic degradation is generally difficult to detect through single or short-term monitoring. However, through the chronic degradation detection model of the cloud platform, the output signal characteristics of the power chip can be accumulated and analyzed over a long period of time. Using the Gaussian process regression model, the system can analyze the trend of these characteristic changes and determine whether there are signs of degradation. This improves the ability to detect chronic degradation anomalies, helps extend the service life of chips and equipment, and reduces maintenance costs caused by equipment failures. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0025] Figure 1 A schematic diagram of a flow chart of a method for detecting abnormal operation parameters of a power chip provided by an embodiment of the present invention;

[0026] Figure 2 A schematic diagram of the structure of a power chip provided by an embodiment of the present invention;

[0027] Figure 3 A schematic diagram of the structure of a power chip operating parameter abnormality detection system provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0028] The technical solution of the present invention is described below in conjunction with the accompanying drawings.

[0029] In the embodiments of the present invention, words such as "exemplarily" and "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "example" in the present invention should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of the word "example" is intended to present the concept in a specific way. In addition, in the embodiments of the present invention, the meaning expressed by "and / or" can be both, or it can be either of the two.

[0030] In order to make the technical problems, technical solutions and advantages to be solved by the present invention more clear, a detailed description will be given below with reference to the accompanying drawings and specific embodiments.

[0031] Reference Manual Attached Figure 1 , shows a flow chart of a method for detecting abnormal operation parameters of a power chip provided in an embodiment of the present invention.

[0032] The present invention provides a method for detecting abnormal operation parameters of a power chip, and the processing flow may include the following steps:

[0033] S1: Use electronic devices equipped with power chips as edge nodes and cloud servers as cloud platforms. Establish a communication relationship between edge nodes and cloud platforms to build a cloud-edge collaborative anomaly detection architecture.

[0034] It should be noted that edge nodes can monitor power chips in real time and quickly detect faults directly on the device, avoiding the delay of transmitting all data to the cloud. When a fault risk is detected, the edge node can trigger a response immediately, shut down the device in time and issue an early warning, thereby effectively preventing the fault from expanding or causing further equipment damage. At the same time, the cloud platform is mainly responsible for long-term data analysis and chronic degradation detection, and does not need to frequently participate in immediate fault judgment, thereby focusing cloud computing resources on historical data accumulation and trend analysis.

[0035] In the present invention, the cloud-edge collaborative architecture improves the accuracy of anomaly detection and the reliability of the system while maintaining real-time and resource efficiency, providing a complete monitoring solution for the operation and maintenance of power chips.

[0036] S2: At the edge node, a fast fault detection model based on inductor current prediction is configured.

[0037] S3: Configure the chronic degradation detection model based on Gaussian process regression on the cloud platform.

[0038] Among them, Gaussian Process Regression (GPR) is a non-parametric Bayesian method used in machine learning, which is particularly suitable for solving regression problems. Gaussian process regression has strong flexibility and explanatory power, and is often used for prediction and uncertainty quantification, especially in the fields of time series data, signal processing, and equipment health monitoring.

[0039] S4: At the edge node, obtain the operating parameters of the power chip.

[0040] Among them, power chips are semiconductor devices that process and convert electrical energy and are widely used in various power converters, drive circuits, electric vehicles, communication equipment, consumer electronics and other fields. The main function of power chips is to convert input voltage or current into voltage or current that meets load requirements to ensure stable operation of the system. For example, common DC-DC converters, AC-DC converters, inverters, etc. all rely on power chips to achieve efficient power conversion.

[0041] Among them, the operating parameters include: current, voltage, temperature, power, etc.

[0042] S5: At the edge node, based on the operating parameters of the power chip, the fast fault detection model is used to determine whether the power chip in the edge node has a fault risk. If so, the power chip is immediately shut down and an early warning is issued. Otherwise, the output signal of the power chip is uploaded to the cloud platform.

[0043] In a possible implementation, judging whether a power chip in an edge node has a fault risk by using a fast fault detection model in S5 specifically includes sub-steps S501 to S504:

[0044] S501: Determine the rate of change of the inductor current.

[0045] S502: Predict the inductor current based on the inductor current change rate, and determine an inductor current prediction value.

[0046] S503: Obtain an inductor current measurement value.

[0047] S504: Determine whether the difference between the predicted inductor current value and the measured inductor current value is greater than a safety threshold. If so, immediately shut down the power chip and issue a warning. Otherwise, upload the operating parameters of the power chip to the cloud platform.

[0048] In the present invention, by calculating the rate of change of the inductor current in real time at the edge node and generating a current prediction value, the abnormal changes of the power chip during operation can be quickly identified. By instantly judging the difference between the current prediction value and the measured value, the risk of sudden failure can be quickly identified. This real-time detection enables the system to respond before the failure spreads, immediately shut down the chip and issue an early warning, thereby protecting other components and preventing equipment damage and system downtime.

[0049] Reference Manual Attached Figure 2 , showing a schematic structural diagram of a power chip provided by an embodiment of the present invention.

[0050] In a possible implementation, a typical power chip structure is provided. For other power chip structures, the power chip fast fault detection method of this power chip can also be referred to. The power chip includes: an inductor L, a PWM signal generator, a first switch S1, a second switch S2, a load R and a capacitor C.

[0051] The positive electrode of the power supply V is connected to the input end of the inductor L, the output end of the inductor L is connected to the first end of the first switch S1 and the first end of the second switch S2, the second end of the first switch S1 is connected to the input end of the load R, the negative electrode of the power supply V is connected to the second end of the second switch S2 and the output end of the load R, and the capacitor C is connected in parallel across the load R.

[0052] The PWM signal generator is connected to the control terminals of the first switch S1 and the second switch S2.

[0053] The PWM signal generator sends a first control signal to the first switch S1 and sends a second control signal to the second switch S2, and power control is achieved by adjusting the duty ratios of the first control signal and the second control signal.

[0054] The power chip has a charging working state and a discharging working state.

[0055] When the power chip is in the charging working state, the first switch S1 is turned on and the second switch S2 is turned off, the power supply charges the inductor L and reduces the current of the load R.

[0056] When the power chip is in a discharging working state, the first switch S1 is turned off, the second switch S2 is turned on, and the inductor L charges the load R, thereby increasing the load R current.

[0057] It should be noted that the power regulation of the load is achieved by utilizing the charge and discharge characteristics of the inductor and the on-off control of the switch. The charging state reduces the load current, while the discharging state increases the load current, thereby achieving the purpose of stabilizing the load power output.

[0058] Furthermore, for such power chips, S5 uses a fast fault detection model to determine whether the power chip in the edge node has a fault risk, specifically including:

[0059] S501: Determine the inductor current change rate when the first switch S1 is closed and the second switch S2 is opened:

[0060] ,

[0061] Among them, I L Inductor current, ΔI L Indicates the rate of change of inductor current, (ΔI L ) S1 Indicates the rate of change of the inductor current when the first switch S1 is closed and the second switch S2 is open, V in represents the input voltage, L represents the inductance value, D represents the duty cycle of the first switch S1 being closed and the second switch S2 being opened, T SW Represents the switching cycle.

[0062] S502: Determine the inductor current change rate when the first switch S1 is opened and the second switch S2 is closed:

[0063] ,

[0064] Among them, (ΔI L ) S2 Indicates the rate of change of the inductor current when the first switch S1 is opened and the second switch S2 is closed, V orepresents the output voltage, and 1-D represents the duty cycle of the first switch S1 being opened and the second switch S2 being closed.

[0065] S503: Predict the inductor current based on the inductor current change rate to determine the inductor current prediction value:

[0066] ,

[0067] in, represents the predicted value of the inductor current, Represents the predicted value of the inductor current at time t, I L (t-1) represents the measured value of the inductor current at time t-1.

[0068] S504: Obtain an inductor current measurement value.

[0069] S505: Determine whether the difference between the predicted inductor current value and the measured inductor current value is greater than a safety threshold. If so, immediately shut down the power chip and issue a warning. Otherwise, upload the operating parameters of the power chip to the cloud platform.

[0070] Optionally, the safety threshold is specifically:

[0071] ,

[0072] Among them, Tr represents the safety threshold, I L represents the inductor current, R in Represents the internal resistance of the voltage source, R sw Represents the internal resistance of the switch, R L Inductor series resistance, T SW Represents the switching cycle.

[0073] In the present invention, since parameters such as internal resistance, current and switching cycle will change with changes in load, power supply voltage or temperature, this calculation method enables the threshold to adapt to different working conditions and maintain the reliability and stability of fault detection. Therefore, even under high load or different ambient temperature conditions, the detection system can set a suitable safety threshold according to the current working conditions and effectively deal with external fluctuations.

[0074] S6: On the cloud platform, extract the signal characteristics of the output signal of the power chip.

[0075] Optionally, the signal characteristics include: amplitude, mean, standard deviation, skewness, kurtosis, entropy and centroid.

[0076] S7: On the cloud platform, based on the signal characteristics of the output signal of the power chip, the chronic degradation detection model is used to determine whether the power chip has a chronic degradation risk. If so, an early warning is issued.

[0077] It should be noted that chronic degradation risk refers to the gradual performance degradation and functional degradation of power chips and electronic devices under long-term operation or continuous load. It usually does not manifest as an instantaneous failure, but is a slow and cumulative process. As components degrade, the reliability, efficiency and service life of the equipment gradually decrease, and may even lead to the eventual failure of the equipment.

[0078] In a possible implementation, judging whether the power chip has a chronic degradation risk by using a chronic degradation detection model in S7 specifically includes sub-steps S701 to S707:

[0079] S701: Randomly select a preset number of data points from the normal output signal of the power chip to construct multiple random variable sets.

[0080] S702: With the goal of maintaining the consistency of the probability distribution of multiple sets of random variables, a Gaussian process regression sub-model is trained:

[0081] f(t)∼GP[m(t),k(t, t ' )] ,

[0082] Where f(t) represents the output signal, t represents time, GP represents Gaussian process, Indicates that the output signal obeys the Gaussian process, m(t) represents the mean function, represents the covariance function, Represents another time corresponding to time t.

[0083] It should be noted that by constructing a Gaussian process regression model (GPR), the probability distribution of the normal behavior of the power chip output signal can be modeled to obtain its mean and variance range. This model can accurately capture the changing trend of the signal and generate a prediction range for the normal state.

[0084] Optionally, the mean function is specifically:

[0085] ,

[0086] Wherein, E represents the mathematical expectation operation.

[0087] Optionally, the covariance function is specifically:

[0088] &k(t, t ' )=c k PER (t, t ' )+(1-c) k SE (t, t ' ) &=c s 1 2 exp [- 2 l 1 2 sin 2 (π(t- t ' ) / p)]+(1-c) s 2 2 exp [ (t- t ' ) 2 2 l 2 2 ]

[0089] in, represents the periodic covariance function, represents the square exponential covariance function, γ represents the combination coefficient of the periodic covariance function, represents the vertical scaling factor in the periodic covariance function, represents the vertical scaling factor in the squared exponential covariance function, represents the horizontal scaling factor in the periodic covariance function, represents the horizontal scaling factor in the squared exponential covariance function, p represents the period adjustment parameter, and exp represents the exponential function with the natural constant e as the base.

[0090] Among them, the periodic covariance function simulates the periodic changes of the signal through the sine function, which is suitable for describing the periodic characteristics of the power chip, such as switching signals and current fluctuations. The square exponential covariance function focuses on non-periodic characteristics and can capture smooth changes and gradual trends in the signal. This combination allows the model to take into account both periodic and non-periodic changes, and more comprehensively reflect the actual situation of the chip's operating status.

[0091] It should be noted that by dynamically adjusting the proportion of periodic and non-periodic components through the combination coefficient γ, the model can flexibly adapt to different signal characteristics.

[0092] In the present invention, a composite design combining periodic and non-periodic covariance functions is used to provide a flexible and accurate modeling method for power chip chronic degradation detection. This method can capture diverse signal characteristics and has strong anti-interference ability, providing effective support for long-term health monitoring and fault prediction, and is suitable for complex and changeable power chip application scenarios.

[0093] S703: Predicting the mean and variance of the normal output signal of the power chip based on the Gaussian process regression sub-model.

[0094] S704: Determine the prediction range of the normal output signal of the power chip according to the predicted mean and variance of the normal output signal:

[0095] ,

[0096] Here, α represents the confidence factor.

[0097] It should be noted that the adjustment of the confidence factor α enables the system to find the best balance between detection sensitivity and stability. For example, in scenarios that require high sensitivity, the confidence factor α can be increased to expand the coverage of the normal interval; in scenarios that require strict control, the confidence factor α can be appropriately reduced to enhance sensitivity.

[0098] In the present invention, the prediction interval is constructed using the mean and variance, which can reflect the prediction credibility of the model at each time point. The mean provides the central value of the prediction, while the variance quantifies the uncertainty. In this way, the system can flexibly respond to signals with different fluctuation amplitudes.

[0099] S705: Based on the prediction range of the normal output signal, search and determine the minimum value and maximum value of each signal feature when the normal output signal is output.

[0100] It should be noted that after estimating the distribution of normal output signals using the Gaussian process regression (GPR) model, the predicted distribution range of normal signal output within a period of time is obtained. In order to further use it for anomaly detection, it is necessary to determine the "normal range" of each of the above statistical features, that is, the extreme values ​​of these statistical features under normal conditions.

[0101] In practical applications, all possible sampled data are often traversed for comparison to determine the extreme value, which is a huge computational task. To this end, the present invention proposes a new extreme value determination method.

[0102] Optionally, S705 specifically includes: based on the prediction range of the normal output signal, searching and determining the minimum and maximum values ​​of each signal feature when the normal output signal is output through a flower pollination optimization algorithm.

[0103] Among them, the Flower Pollination Algorithm (FPA) is a nature-inspired optimization algorithm that simulates the propagation mechanism of flower pollination in nature. It simulates the local and global search behavior of organisms in flower pollination. It is simple, fast, and effective, and is widely used in various optimization problems.

[0104] Specifically, the calculation formula of each signal feature is set as the objective function, the minimum value of the signal feature is determined by minimizing the objective function, and the maximum value of the signal feature is determined by maximizing the objective function.

[0105] Initialize the flower individuals and conversion probabilities of the flower pollination optimization algorithm, each flower individual represents a normal output signal.

[0106] Generate a random number and determine whether the conversion probability is greater than the random number. If so, perform cross-pollination. Otherwise, perform self-pollination.

[0107] Optionally, the conversion probability is specifically:

[0108] P t = P 0 -q m c ( t c ) m-1 exp [-( t c ) m ](1- t T ) ,

[0109] Among them, P t represents the transition probability at the tth iteration, P0 represents the basic transition probability, q represents the Weber influence factor, γ represents the scale parameter, m represents the shape parameter, exp represents the exponential function with the natural constant e as the base, and T represents the maximum number of iterations.

[0110] It should be noted that the conversion probability gradually decreases with the increase of the number of iterations. In the initial stage, the conversion probability is relatively large, and it tends to be global search (cross-pollination), exploring potential global optimal solutions in the search space; as the number of iterations increases, the conversion probability gradually decreases, and the algorithm gradually turns to local optimization (self-pollination), thereby finely optimizing the solution.

[0111] When cross-pollination occurs, the individual positions of flowers are updated according to the Levy flight mechanism:

[0112] ,

[0113] in, represents the position of the i-th flower individual at the t+1-th iteration, represents the position of the i-th flower individual at the t-th iteration, θ represents the step length influencing factor, Levy represents the Levy flight step length, represents the global optimal solution at the tth iteration.

[0114] ,

[0115] Where Γ represents the standard Gamma function, λ represents the exponential parameter, and s represents the random step variable.

[0116] In the present invention, by using the Levy flight mechanism in the cross-pollination stage, the flower pollination optimization algorithm can enhance the global search, avoid falling into the local optimum, reduce the number of iterations and accelerate the convergence speed.

[0117] When self-pollination occurs, the individual positions of flowers are updated according to the golden sine mechanism:

[0118] ,

[0119] in, represents the position of the jth flower individual randomly selected at the tth iteration, represents the position of the kth flower individual randomly selected at the tth iteration, r1 and r2 represent random numbers between 0 and 2π, x1 and x2 represent the self-pollination coefficients, and τ represents the golden section number .

[0120] In the present invention, the golden sine mechanism is used in the self-pollination stage to finely adjust the individual positions and enhance the stability and efficiency of local search. This mechanism avoids premature convergence to suboptimal solutions while ensuring the convergence speed, improves the accuracy of the solution and the robustness of the algorithm, and is suitable for local extreme value search and final solution optimization in complex optimization problems.

[0121] Determine whether the fitness value of the flower individual at the position of the t+1th iteration is greater than the fitness value at the position of the tth iteration. If so, replace the position of the flower individual. Otherwise, the flower individual maintains the current position.

[0122] Update the global optimal solution.

[0123] Determine whether the current number of iterations has reached the maximum number of iterations. If so, output the flower individual with the highest current fitness and obtain the extreme value (maximum or minimum) of the signal feature. Otherwise, return to continue iterating.

[0124] In the present invention, the use of the flower pollination optimization algorithm can significantly reduce the search time, allowing the system to quickly determine the extreme value range of normal signal characteristics, thereby accelerating the response speed of anomaly detection.

[0125] S706: Acquire signal characteristics of the real-time output signal.

[0126] S707: Determine whether the signal characteristic of the real-time output signal is between the minimum value and the maximum value of the normal output signal. If so, determine that the power chip does not have a risk of chronic degradation. Otherwise, determine that the power chip has a risk of chronic degradation and issue a warning prompt.

[0127] In the present invention, early warning of chronic degradation signals helps to take maintenance measures in advance to avoid further degradation of the equipment to the failure stage, thereby extending the life of the equipment and reducing maintenance costs.

[0128] The beneficial effects brought about by the technical solution provided by the embodiment of the present invention include at least:

[0129] (1) In the present invention, a fast fault detection model based on inductor current prediction is configured on the edge node, which can predict the inductor current of the power chip and instantly analyze whether there is a fault risk, predicting potential risks before the fault occurs. Once a sudden fault is detected, the system can respond immediately, shut down the power chip and issue an early warning, thereby preventing equipment damage or system shutdown caused by fault expansion.

[0130] (2) In the present invention, chronic degradation is generally difficult to detect through single or short-term monitoring. However, through the chronic degradation detection model of the cloud platform, the output signal characteristics of the power chip can be accumulated and analyzed over a long period of time. Using the Gaussian process regression model, the system can analyze the trend of these characteristic changes and determine whether there are signs of degradation. This improves the ability to detect chronic degradation anomalies, helps extend the service life of chips and equipment, and reduces maintenance costs caused by equipment failures.

[0131] Reference Manual Attached Figure 3 , showing a schematic structural diagram of a power chip operating parameter abnormality detection system provided by the present invention.

[0132] The present invention further provides a power chip operating parameter abnormality detection system 20, which is applied to the above-mentioned power chip operating parameter abnormality detection method, comprising:

[0133] Processor 201.

[0134] The memory 202 stores computer-readable instructions. When the computer-readable instructions are executed by the processor 201, the power chip operating parameter abnormality detection method of the method embodiment is implemented.

[0135] The power chip operating parameter abnormality detection system 20 provided by the present invention can execute the above-mentioned power chip operating parameter abnormality detection method and achieve the same or similar technical effects. To avoid repetition, the present invention will not go into details.

[0136] It should be understood that the processor in the embodiment of the present invention may be a central processing unit (CPU), and the processor may also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0137] It should also be understood that the memory in the embodiments of the present invention may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0138] The above embodiments can be implemented in whole or in part by software, hardware (such as circuits), firmware or any other combination. When implemented by software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, the process or function described in the embodiment of the present invention is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center by wired (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains one or more available media sets. The available medium can be a magnetic medium (for example, a floppy disk, a hard disk, a tape), an optical medium (for example, a DVD), or a semiconductor medium. The semiconductor medium can be a solid-state hard disk.

[0139] It should be understood that the term "and / or" in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. A and B can be singular or plural. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship, but it may also indicate an "and / or" relationship. Please refer to the context for specific understanding.

[0140] In the present invention, "at least one" means one or more, and "plurality" means two or more. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0141] It should be understood that in various embodiments of the present invention, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0142] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0143] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described equipment, devices and units can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0144] In the several embodiments provided by the present invention, it should be understood that the disclosed devices, apparatuses and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0145] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0146] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0147] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store program codes.

[0148] An embodiment of the present invention provides a computer-readable storage medium having a computer program stored thereon. When the program is executed by a processor, the method for detecting abnormal operation parameters of a power chip as described in the method embodiment is implemented.

[0149] A computer-readable storage medium provided by the present invention can implement the steps and effects of the power chip operating parameter abnormality detection method of the above method embodiment. To avoid repetition, the present invention will not go into details.

[0150] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

[0151] There are a few points to note:

[0152] (1) The drawings of the embodiments of the present invention only involve structures related to the embodiments of the present invention. Other structures may refer to conventional designs.

[0153] (2) For the sake of clarity, in the drawings used to describe the embodiments of the present invention, the thickness of layers or regions is exaggerated or reduced, that is, these drawings are not drawn according to the actual scale. It is understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element or there may be intermediate elements.

[0154] (3) In the absence of conflict, the embodiments of the present invention and the features therein may be combined with each other to obtain new embodiments.

[0155] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. The protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A method for detecting abnormal operation parameters of a power chip, characterized in that: include: S1: Using an electronic device equipped with a power chip as an edge node and a cloud server as a cloud platform, establishing a communication relationship between the edge node and the cloud platform to build a cloud-edge collaborative anomaly detection architecture; S2: configuring a fast fault detection model based on inductor current prediction at the edge node; S3: configuring a chronic degradation detection model based on Gaussian process regression on the cloud platform; S4: At the edge node, obtaining operating parameters of the power chip; S5: At the edge node, judging whether the power chip in the edge node has a failure risk through the fast fault detection model according to the operating parameters of the power chip; if so, immediately shutting down the power chip and issuing an early warning prompt; Otherwise, uploading the output signal of the power chip to the cloud platform; S6: extracting, on the cloud platform, signal characteristics of the output signal of the power chip; S7: on the cloud platform, judging whether the power chip has a risk of chronic degradation according to the signal characteristics of the output signal of the power chip and using the chronic degradation detection model; if so, issuing an early warning prompt; The step S5, judging whether the power chip in the edge node has a fault risk by using the fast fault detection model, specifically includes: S501: Determine the rate of change of the inductor current; S502: predicting the inductor current based on the inductor current change rate, and determining an inductor current prediction value; S503: Obtaining an inductor current measurement value; S504: Determine whether the difference between the predicted inductor current value and the measured inductor current value is greater than a safety threshold; if so, immediately shut down the power chip and issue a warning prompt; otherwise, upload the operating parameters of the power chip to the cloud platform.

2. The method for detecting abnormal operation parameters of a power chip according to claim 1, characterized in that: The power chip includes: an inductor, a PWM signal generator, a first switch, a second switch, a load and a capacitor; The positive electrode of the power supply is connected to the input end of the inductor, the output end of the inductor is connected to the first end of the first switch and the first end of the second switch, the second end of the first switch is connected to the input end of the load, the negative electrode of the power supply is connected to the second end of the second switch and the output end of the load, and the capacitor is connected in parallel at both ends of the load; The PWM signal generator is connected to the control ends of the first switch and the second switch; The PWM signal generator sends a first control signal to the first switch and sends a second control signal to the second switch, and power control is achieved by adjusting the duty ratio of the first control signal and the second control signal.

3. The method for detecting abnormal operation parameters of a power chip according to claim 2, characterized in that: The step S5 of determining whether the power chip in the edge node has a fault risk by using the fast fault detection model specifically includes: S501: Determine the inductor current change rate when the first switch is closed and the second switch is open: ， Among them, I L Inductor current, ΔI L Indicates the rate of change of inductor current, (ΔI L ) S1 It represents the rate of change of inductor current when S1 is closed and S2 is open, V in represents the input voltage, L represents the inductance value, D represents the duty cycle of S1 closed and S2 open, T SW represents the switching cycle; S502: Determine the inductor current change rate when the first switch is opened and the second switch is closed: ， Among them, (ΔI L ) S2 It represents the rate of change of the inductor current when S1 is open and S2 is closed, V o represents the output voltage, 1-D represents the duty cycle of S1 open and S2 closed; S503: Predict the inductor current based on the inductor current change rate to determine the inductor current prediction value: ， in, represents the predicted value of the inductor current, Represents the predicted value of the inductor current at time t, I L (t-1) represents the measured value of the inductor current at time t-1; S504: Obtaining an inductor current measurement value; S505: Determine whether the difference between the predicted inductor current value and the measured inductor current value is greater than a safety threshold; if so, immediately shut down the power chip and issue a warning prompt; otherwise, upload the operating parameters of the power chip to the cloud platform.

4. The method for detecting abnormal operation parameters of a power chip according to claim 1, characterized in that: The signal characteristics include: amplitude, mean, standard deviation, skewness, kurtosis, entropy and centroid.

5. The method for detecting abnormal operation parameters of a power chip according to claim 1, characterized in that: The step of determining whether the power chip has a chronic degradation risk by using the chronic degradation detection model in S7 specifically includes: S701: randomly selecting a preset number of data points from the normal output signal of the power chip to construct a plurality of random variable sets; S702: With the goal of maintaining the consistency of the probability distribution of multiple sets of random variables, a Gaussian process regression sub-model is trained: ， Where f(t) represents the output signal, t represents time, GP represents Gaussian process, Indicates that the output signal obeys the Gaussian process, m(t) represents the mean function, represents the covariance function, represents another time corresponding to time t; S703: Predicting the mean and variance of the normal output signal of the power chip based on the Gaussian process regression sub-model; S704: Determine a prediction range of the normal output signal of the power chip according to the predicted mean and variance of the normal output signal: ， Among them, α represents the confidence factor; S705: searching and determining the minimum and maximum values ​​of each signal feature when the normal output signal is output based on the predicted range of the normal output signal; S706: Acquire signal characteristics of the real-time output signal; S707: Determine whether the signal characteristic of the real-time output signal is between the minimum value and the maximum value of the normal output signal; if so, determine that the power chip does not have the risk of chronic degradation; otherwise, determine that the power chip has the risk of chronic degradation and issue a warning prompt.

6. The method for detecting abnormal operation parameters of a power chip according to claim 5, characterized in that: The mean function is specifically: ， Wherein, E represents the mathematical expectation operation.

7. The method for detecting abnormal operation parameters of a power chip according to claim 5, characterized in that: The covariance function is specifically: ， in, represents the periodic covariance function, represents the square exponential covariance function, γ represents the combination coefficient of the periodic covariance function, represents the vertical scaling factor in the periodic covariance function, represents the vertical scaling factor in the squared exponential covariance function, represents the horizontal scaling factor in the periodic covariance function, represents the horizontal scaling factor in the squared exponential covariance function, p represents the period adjustment parameter, and exp represents the exponential function with the natural constant e as the base.

8. The method for detecting abnormal operation parameters of a power chip according to claim 5, characterized in that: The S705 is specifically as follows: Based on the predicted range of the normal output signal, the flower pollination optimization algorithm is used to search and determine the minimum and maximum values ​​of each signal feature when the normal output signal is detected.

9. A power chip operating parameter abnormality detection system, characterized in that: include: processor; A memory having computer-readable instructions stored thereon, wherein when the computer-readable instructions are executed by the processor, the method for detecting abnormal operation parameters of a power chip according to any one of claims 1 to 8 is implemented.

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