A signal detection structure with programmable channel multiplexing

Abstract

The present invention is applicable to the field of chip technology and provides a signal detection structure for programmable channel multiplexing, comprising an input signal selector, a programmable gain amplifier, an output signal selector, a signal detection module, and a control logic module. The input signal selector selects one of a group of external input signals and transmits the input signal to the programmable gain amplifier. The amplifier processes the input signal and then sends the processed signal to the signal detection module for signal processing and use. In this structure, users can use software to control the on / off selection of input channels and the gain coefficient of the programmable gain amplifier in real time, which is highly practical. The signal detection module can be a signal processing device such as an analog-to-digital converter or a signal comparator. The control logic module obtains the operating status of the signal detection module and automatically controls the input signal selector. In certain applications with limited software resources, this can effectively reduce the complexity of software control and improve the operational efficiency of channel multiplexing.

Description

Technical Field

[0001] The present invention belongs to the field of chip technology, and in particular relates to a signal detection structure for programmable channel multiplexing. Background Art

[0002] With the emergence of more and more specialized microcontroller chips, the integration of specialized functional circuits within MCUs is increasing. Current motor control microcontrollers typically incorporate various analog signal detection modules to perform the analog-to-digital signal processing required for motor control. However, integrating operational amplifiers within a chip requires consideration of the number of operational amplifiers, input channels, and output channels. Excessive operational amplifiers and inappropriate internal analog circuit connections directly increase microcontroller production costs and overall chip size, while reducing analog signal processing efficiency. Summary of the Invention

[0003] The present invention aims to overcome the problems of the existing solutions mentioned above, such as the excessive number of operational amplifiers required, inappropriate analog circuit connection methods that increase the production cost of the entire microcontroller, and low analog signal processing efficiency. Based on this, a signal detection structure with programmable channel multiplexing is proposed.

[0004] Specific implementation method: A signal detection structure with programmable channel multiplexing includes an input signal selector, a programmable gain amplifier, a signal detection module, and a control logic module. The input end of the input signal selector is connected to several pins of an external microcontroller chip and the output end of the control logic module. The output end of the input signal selector is connected to the programmable gain amplifier. The control signal in the control logic module controls the input signal selector and selects one group of input channels in the input signal selector. The selected input channel transmits the voltage signal of the corresponding chip pin to the programmable gain amplifier.

[0005] The programmable gain amplifier is connected to a gain control register, which is used to provide a user programming channel to configure and select the amplification factor of the programmable gain amplifier for the voltage signal;

[0006] The output signal of the programmable gain amplifier enters the next-level signal detection module, which uses one or more signal processing devices such as an analog-to-digital converter or a voltage comparator;

[0007] The output end of the signal detection module is connected to the input end of the control logic module. The signal detection module synchronizes the output result to the control logic module, and the control logic module uses this as a reference to control the input signal selector to perform the next action.

[0008] Furthermore, the location of the gain control register in the memory space is determined when the microcontroller chip is designed. When the user writes a program on the programming channel provided by the gain control register, the user uses the memory assignment instruction to write data to the spatial address of the gain register through the bus matrix to configure programmable gain amplifiers with different amplification factors and select different gain resistors to be connected to the operational amplifier path.

[0009] Furthermore, after the analog-to-digital converter completes the task of sampling the current motor phase current, if no new task arrives for a long time, the analog-to-digital converter can automatically turn off the power supply and input clock to reduce power consumption.

[0010] Furthermore, the analog-to-digital converter is connected to a first status register. When the analog-to-digital converter reaches a fixed clock cycle at the time of entering the analog-to-digital conversion, the completion of the conversion is indicated by setting a flag bit in the first status register, so that the control logic module obtains a completion signal from the analog-to-digital converter.

[0011] The voltage comparator is connected to a second status register. When the time for the voltage comparator to start voltage comparison reaches a fixed clock cycle, the comparison result and the comparison completion flag are updated through the set flag of the second status register, so that the control logic module obtains the completion signal and comparison result of the voltage comparator.

[0012] Both analog-to-digital converters and voltage comparators are external op amps originally required in motor control applications. By placing both of them in a programmable channel multiplexing signal detection structure built inside the microcontroller chip, more efficient analog signal detection tasks can be achieved using a minimum number of op amps. At the same time, it more directly demonstrates the practicality of the programmable channel multiplexing signal detection structure in motor control applications. In addition, the programmable gain amplifier is connected to the gain control register, and the control logic module is connected to the selection control register. By writing software programs and using machine instructions, the user can modify the data of any register programmable by the microcontroller chip during operation. The user can control the programmable channel multiplexing signal detection structure by himself, greatly improving the usability of the entire multiplexing system. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0014] The following drawings are only intended to illustrate and explain the present invention, and are not intended to limit the scope of the present invention.

[0015] Figure 1 This is a schematic diagram of a signal detection structure with programmable channel multiplexing provided by the present invention.

[0016] Figure 2 This is a circuit connection diagram of the signal detection module provided by the present invention.

[0017] Figure 3 This is a circuit diagram of the selection control register provided by the present invention.

[0018] Explanation of the reference numerals: 1. Input signal selector; 2. Programmable gain amplifier; 3. Signal detection module; 4. Control logic module; DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0020] See also Figure 1-Figure 3 The invention discloses a signal detection structure with programmable channel multiplexing, comprising an input signal selector 1, a programmable gain amplifier 2, an output signal selector 3, a signal detection module 4, and a control logic module. The input end of the input signal selector 1 is connected to several external microcontroller chip pins and the output end of the control logic module 4, while the output end of the input signal selector 1 is connected to the programmable gain amplifier 2. The several external MCU chip pins can be defined as a first group IN1, a second group IN2, and so on, to an xth group INx, where the number of input ports depends on the chip design. Each of the x groups of pins is connected to the input end of the programmable gain amplifier 2 via the input channel selector. During this process, a control signal within the control logic module 4 controls the input signal selector 1 and selects one of the input channels in the input signal selector 1. The selected input channel transmits the voltage signal of the corresponding chip pin to the programmable gain amplifier 2. That is, during one operation cycle of the programmable gain amplifier 2, only the analog signal of one group of pins INx can be transmitted to the input end of the programmable gain amplifier 2 through the input channel selector. This prevents multiple input signals from simultaneously entering the input end of the programmable gain amplifier 2, which would cause signal interference and affect the signal amplification effect.

[0021] Furthermore, the programmable gain amplifier 2 is connected to a gain control register, which is used to provide a user programming channel to configure and select the amplification factor of the voltage signal of the programmable gain amplifier 2. The location of the gain control register in the memory space is determined during the design of the MCU chip. That is, the number of gain channels on the programmable gain amplifier 2 is already determined. When the user writes a program on the programming channel provided by the gain control register, the user uses a memory assignment instruction to write data to the spatial address of the gain register through the bus matrix to configure the programmable gain amplifier 2 with different amplification factors and select different gain resistors to connect to the op amp path. The user can freely adjust the amplification factor of the programmable gain amplifier 2 according to actual needs, allowing the entire op amp system to dynamically adjust the gain to adapt to different signal strengths and types. By adding gain resistors to the input channels, the user can achieve more precise gain adjustment through software configuration.

[0022] The signal detector uses one or more signal processing devices such as an analog-to-digital converter or a voltage comparator, and integrates multiple analog signal processing circuits internally to meet the needs of analog-to-digital conversion and voltage signal comparison.

[0023] Preferably, after the analog-to-digital converter completes the task of sampling the current motor phase current, if no new task arrives for a long time, the analog-to-digital converter can automatically turn off the power supply and input the clock to reduce power consumption. Specifically, after completing the current motor phase current sampling task and the input end of the analog-to-digital converter does not receive a voltage signal, the analog-to-digital converter performs timing through an externally connected clock circuit. When the clock circuit reaches a set time point and a voltage signal is input at the input end of the analog-to-digital converter, the clock circuit is reset to zero. When the clock circuit timing reaches a set time point and the input end of the analog-to-digital converter does not receive a voltage signal within this time period, the analog-to-digital converter turns off the power supply and the clock circuit, thereby reducing the power consumption of the entire system when it is not working.

[0024] Similarly, after the voltage comparator completes the voltage comparison task of the current motor, if no new task arrives for a long time, the voltage comparator can automatically turn off the power supply and input the clock to reduce power consumption. Specifically, after completing the voltage comparison task of the current motor and the input end of the voltage comparator does not receive a voltage signal, the voltage comparator counts through an externally connected clock circuit. When the clock circuit reaches the set time point and a voltage signal is input at the input end of the voltage comparator, the clock circuit returns to zero. When the clock circuit timing reaches the set time point and the input end of the voltage comparator does not receive a voltage signal within this time period, the voltage comparator turns off the power supply and clock circuit, thereby reducing the power consumption of the entire system when it is not working.

[0025] The analog-to-digital converter is connected to a first status register. The analog-to-digital converter requires a fixed clock cycle for analog-to-digital conversion. When the analog-to-digital converter reaches the fixed clock cycle when entering the analog-to-digital conversion, the completion of the conversion is indicated by setting a flag bit in the first status register, so that the control logic module obtains the completion signal of the analog-to-digital converter.

[0026] The voltage comparator is connected to a second status register. Similarly, the voltage comparator requires a fixed clock cycle to perform voltage comparisons. The voltages at the positive and negative inputs of the voltage comparator are always compared, but the comparison output is invalid if it is outside the fixed clock cycle. When the voltage comparator starts the voltage comparison and reaches the fixed clock cycle, the comparison result and comparison completion flag are updated through the set flag bit in the second status register, so that the control logic module receives the completion signal and comparison result from the voltage comparator.

[0027] Specifically, the user selects an input channel by controlling the internal value of the ANA_INSEL_MOD register in the logic module. For example, when the internal value is 0, the value in the ANA_INSEL register controls the software selection of the next input channel to programmable gain amplifier 2. When the internal value is 1, the hardware switches the input channels by polling the conversion completion flags of the analog-to-digital converter and voltage comparator. The order of input channel switching is determined by the value written to the ANA_INCHSEL register. For another example, if bits 0 to 3 of the ANA_INCHSEL register are 0, bits 4 to 7 are 2, and bits 8 to 11 are 1, the input channels are selected in the following order: input channel 0, input channel 2, input channel 1.

[0028] Output signal selector 3 uses the values ​​in registers ANA_ADCIN and ANA_CMPIN to control the output connectivity. When ANA_ADCIN selects input channel 1, the output signal path is disconnected after programmable gain amplifier 2 operates on input channel 0. When programmable gain amplifier 2 operates on input channel 2, the output signal path is disconnected. When programmable gain amplifier 2 operates on input channel 1, the output signal path is connected. The same applies to ANA_CMPIN.

[0029] Programmable gain amplifier 2, analog-to-digital converter and voltage comparator all have conversion end flags to indicate the current state of the system. The specific implementation method is as follows: all three have a fixed conversion cycle, that is, a fixed time, from start to end is a fixed clock cycle. When the clock cycle is reached, the result state is updated to prepare for the next round of conversion.

[0030] The user writes a software program, which is converted into memory assignment instructions that can be recognized and executed by the microcontroller through a compiler. Data is written to the spatial address of the corresponding register through the bus matrix to configure the internal value of each register, thereby achieving the effect of controlling the entire reusable op amp system.

[0031] The software allows users to define the signal processing process, which includes signal selection, amplification, conversion, and comparison. By customizing the signal processing process, users can flexibly adapt it to different scenarios and conditions, thereby enhancing the adaptability of the overall system. The program can also set specific conditions to trigger specific actions. For example, if a voltage comparator detects an overcurrent, the system can shut down the motor for enhanced safety.

[0032] In summary, the programmable gain amplifier 2 is connected to the gain control register, and the control logic module is connected to the selection control register. By writing a software program and using machine instructions, the user can modify the data of the corresponding register during operation of the microcontroller chip, so that the user can freely control the entire reusable op amp system, greatly improving the flexibility and practicality of use.

[0033] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements or improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A signal detection structure with programmable channel multiplexing, characterized by: The invention comprises an input signal selector (1), a programmable gain amplifier (2), a signal detection module (3), and a control logic module (4); the input end of the input signal selector (1) is connected to a plurality of external MCU chip pins and the output end of the control logic module (4); the output end of the input signal selector (1) is connected to the programmable gain amplifier (2); a control signal in the control logic module (4) controls the input signal selector (1) and selects one group of input channels in the input signal selector (1); the selected input channel transmits the voltage signal of the corresponding chip pin to the programmable gain amplifier (2); The programmable gain amplifier (2) has a programmable gain control register, and the gain control register is used to provide user programming to configure and select the amplification factor of the programmable gain amplifier (2) for the voltage signal; The control logic module (4) is configured so that the amplifier signal enters the next-stage signal detection module (3), and the signal detection module (3) uses one or more signal processing devices such as an analog-to-digital converter or a voltage comparator; The output end of the signal detection module (3) is connected to the input end of the control logic module (4), and the signal detection module (3) synchronizes the output result to the control logic module (4), and the control logic module (4) uses the output result as a reference to perform the next step; When the signal detection module (3) is an analog-to-digital converter, it is connected to a first state register. When the analog-to-digital converter reaches a fixed clock cycle when entering analog-to-digital conversion, the conversion is completed by setting a flag bit in the first state register, so that the control logic module (4) obtains the completion signal of the analog-to-digital converter; the control logic module (4) uses this as a reference and performs channel switching according to the conversion signal sequence configured in the control logic module (4); When the signal detection module (3) is a voltage comparator, it is connected to a second state register. When the time for the voltage comparator to start voltage comparison reaches a fixed clock cycle, the comparison result and the comparison completion flag are updated through the set flag of the second state register, so that the control logic module (4) obtains the completion signal of the voltage comparator. The control logic module (4) uses this as a reference and performs channel switching through the conversion signal sequence configured in the control logic module (4).

2. The signal detection structure of programmable channel multiplexing according to claim 1, characterized in that: When the user writes a program on the programming channel provided by the gain control register, the user uses a memory assignment instruction to write data to the spatial address of the gain control register through the bus matrix to configure different amplification factors and physically connect different gain resistors to the amplifier path.

3. The signal detection structure of programmable channel multiplexing according to claim 1, characterized in that: After the analog-to-digital converter completes the task of sampling the current motor phase current, if no new tasks arrive for a long time, the analog-to-digital converter can automatically turn off the power supply and input clock to reduce power consumption.

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