LDO circuit, power management chip, circuit board and electronic equipment

Abstract

The invention relates to the technical field of power management, and discloses an LDO circuit, which comprises an LDO main loop and a current limiting circuit, and is characterized in that the LDO main loop comprises a power tube and an error amplifier; the current limiting circuit comprises a power tube current acquisition circuit and a current limiting feedback circuit, the positive electrode of a current source of the current limiting feedback circuit is connected with the power supply end and used for providing reference current, the power tube current acquisition circuit acquires power tube current, and the current limiting feedback circuit limits the power tube current so that the power tube current is not larger than a current limiting threshold value. The current limiting threshold is configured to be related to the output end current of the error amplifier, the reference current and device parameters in the current limiting circuit; the dominant pole of the current limiting circuit is located at the output end of the current limiting circuit, the secondary pole of the current limiting circuit is located at the negative electrode of the current source, and the low-impedance unit is located between the power end and the secondary pole of the current limiting circuit and used for reducing the output impedance of the secondary pole of the current limiting circuit. According to the LDO circuit, the load regulation rate of the LDO circuit with the current limiting function is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of power management technology, and specifically to an LDO circuit, a power management chip, a circuit board, and an electronic device. Background Art

[0002] Low Dropout Regulator (LDO) is widely used in chip circuits due to its simple circuit design, low noise, low cost and small external components, providing a stable voltage source for other modules in the chip circuit. When LDO works in the high voltage domain, the gate-source voltage V GS As the load current increases, the gate-source voltage V GS When the load current increases to the power tube overvoltage threshold, the power tube and related circuits will have an overvoltage risk if the load current continues to increase. It is necessary to add a current limiting circuit to prevent the power tube from overvoltage.

[0003] In the prior art, the main pole and the secondary pole of the LDO current limiting circuit have similar frequencies, which leads to instability of the current limiting circuit. Miller compensation is usually added to separate the main pole and the secondary pole of the current limiting circuit to improve the stability of the current limiting circuit. At the same time, an equivalent series resistance (ESR) is added to the output end of the LDO to build a zero point to improve the stability of the LDO main loop. However, when the LDO drives a large current load, a large voltage drop will be generated on the ESR resistor, reducing the load regulation rate of the LDO.

[0004] Therefore, how to improve the load regulation rate of LDO while maintaining the stability of LDO is an urgent problem to be solved. Summary of the invention

[0005] In view of the above problems, the embodiments of the present application provide an LDO circuit, a power management chip, a circuit board and an electronic device, which are used to solve the problem of low load regulation rate of LDO existing in the prior art.

[0006] According to one aspect of an embodiment of the present application, a low-dropout linear regulator (LDO) circuit is provided, characterized in that it includes: an LDO main loop, including a power tube and an error amplifier, the power tube having a voltage output end, the voltage output end being used to connect an external load, the error amplifier being used to adjust the current flowing through the power tube to keep the output voltage of the voltage output end stable; and a current limiting circuit, including a power tube current acquisition circuit and a current limiting feedback circuit, the power tube current acquisition circuit being used to acquire the power tube current, the current limiting feedback circuit including a current source, the positive electrode of the current source being connected to a power supply end and being used to provide a reference current, the current limiting feedback circuit being used to limit the power tube current according to the reference current so that the power tube current is not greater than a current limiting threshold; the main pole of the current limiting circuit is located at the output end of the current limiting circuit, the secondary pole of the current limiting circuit is located at the negative pole of the current source, the current limiting feedback circuit also includes a low impedance unit located between the power supply end and the secondary pole of the current limiting circuit, the low impedance unit being used to reduce the output impedance of the secondary pole of the current limiting circuit.

[0007] In an optional manner, the low-impedance unit includes one or more low-impedance devices; when the power tube current increases to a first value, the low-impedance unit is turned on, and the current limiting feedback circuit is switched from an off state to a on state, wherein the first value is less than the current limiting threshold.

[0008] In an optional manner, the low impedance device includes one or more of a metal-oxide semiconductor field effect transistor, a bipolar junction transistor and a diode.

[0009] In an optional manner, the power tube current acquisition circuit includes a first MOS tube, a second MOS tube and a third MOS tube; the gate of the first MOS tube is connected to the gate of the power tube, the source of the first MOS tube is connected to the power supply end, and the drain of the first MOS tube is connected to the drain of the second MOS tube; the gate of the second MOS tube is connected to the gate of the third MOS tube, and the source of the second MOS tube is grounded; the drain of the third MOS tube is connected to the negative electrode of the current source, and the source of the third MOS tube is grounded.

[0010] In an optional manner, the low-impedance unit is a fourth MOS tube, and the current limiting feedback circuit also includes a fifth MOS tube; the gate and drain of the fourth MOS tube are both connected to the negative electrode of the current source, and the source of the fourth MOS tube is connected to the power supply end; the gate of the fifth MOS tube is connected to the negative electrode of the current source, the source of the fifth MOS tube is connected to the power supply end, and the drain of the fifth MOS tube is connected to the output end of the error amplifier.

[0011] In an optional manner, the current limiting threshold is related to the reference current, the tail current value of the output end of the error amplifier, the mirror ratio of the first MOS tube to the power tube, the mirror ratio of the third MOS tube to the second MOS tube, and the mirror ratio of the fifth MOS tube to the fourth MOS tube.

[0012] In an optional manner, the mirror ratio of the first MOS tube to the power tube is 1:m, the mirror ratio of the third MOS tube to the second MOS tube is 1:n, and the mirror ratio of the fifth MOS tube to the fourth MOS tube is 1:k; the current limiting threshold I limit For: I limit =(I1+k*I EA )*m*n; wherein, I1 is the reference current, I EA is the tail current value at the output end of the error amplifier.

[0013] In an optional manner, the LDO main loop also includes a first resistor and a second resistor R2; the non-inverting input terminal of the error amplifier is connected to the reference voltage, and the output terminal of the error amplifier is connected to the gate of the power tube; the source of the power tube is connected to the power supply terminal, and the drain of the power tube is connected to the inverting input terminal of the error amplifier through the first resistor, and the drain of the power tube is also connected to ground through the first resistor and the second resistor in sequence.

[0014] According to another aspect of an embodiment of the present application, a power management chip is provided, comprising the LDO circuit as described in the above embodiment.

[0015] According to another aspect of an embodiment of the present application, a circuit board is provided, on which the power management chip and an off-chip capacitor as described in the above embodiment are arranged, and the off-chip capacitor is connected to the voltage output terminal of the power tube in the power management chip.

[0016] According to another aspect of the embodiments of the present application, an electronic device is provided, and the electronic device includes the circuit board described in the above embodiments.

[0017] The embodiment of the present application increases the output impedance of the secondary pole of the current limiting circuit by adding a low impedance path to the secondary pole of the current limiting circuit, thereby increasing the secondary pole frequency of the current limiting circuit, making the secondary pole frequency of the current limiting circuit away from the main pole frequency of the current limiting circuit, and maintaining the stability of the current limiting circuit without adding Miller compensation in the circuit. Since the EA output end of the LDO main loop is not connected to the Miller capacitor, its capacitance is very small, and therefore the secondary pole frequency of the LDO main loop is very large, so the frequency difference between the main pole of the LDO main loop) and the secondary pole is large, and there is no need to add an ESR resistor at the EA output end to construct a zero point, and the LDO main loop can still remain stable, thereby improving the load regulation rate of the LDO while maintaining the stability of the LDO.

[0018] The above description is only an overview of the technical solution of the embodiment of the present application. In order to more clearly understand the technical means of the embodiment of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the embodiment of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings are only used to illustrate the embodiments and are not to be considered as limiting the present application. In addition, the same reference symbols are used to represent the same components throughout the accompanying drawings. In the accompanying drawings:

[0020] Figure 1 A structural block diagram of an LDO circuit provided by the prior art;

[0021] Figure 2a A circuit diagram of an LDO circuit provided by the prior art;

[0022] Figure 2b A circuit diagram of another LDO circuit provided by the prior art;

[0023] Figure 2c A circuit diagram of another LDO circuit provided by the prior art;

[0024] Figure 3 Bode plot of the LDO main loop before and after the current limiting circuit encryption compensation;

[0025] Figure 4 A structural block diagram of an LDO circuit provided in an embodiment of the present application;

[0026] Figure 5 A circuit diagram of an LDO circuit provided in an embodiment of the present application;

[0027] Figure 6 A structural block diagram of a power management chip provided in an embodiment of the present application;

[0028] Figure 7A structural block diagram of a circuit board provided in an embodiment of the present application;

[0029] Figure 8 A structural block diagram of an electronic device provided in an embodiment of the present application.

[0030] Reference numerals:

[0031] 100, LDO circuit; 110, LDO main loop; 120, current limiting circuit; 121, power tube current collection circuit; 122, current limiting feedback circuit;

[0032] AVDD, power supply terminal; GND, ground; Id, current source; Mp, power tube; R1, first resistor; R2, second resistor; EA, error amplifier; M1, first MOS tube; M2, second MOS tube; M3, third MOS tube; M4, fourth MOS tube; M5, fifth MOS tube;

[0033] 200. Power management chip; 300. Circuit board; 400. Electronic equipment. DETAILED DESCRIPTION

[0034] The exemplary embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments set forth herein.

[0035] LDO can maintain a small voltage difference (usually 100mV to 200mV) between the input voltage and the output voltage, thereby keeping the output voltage stable when the load current changes. LDO is widely used in chip circuits due to its simple circuit design, low noise, low cost and small external components, providing a stable voltage source for other modules in the chip circuit.

[0036] LDO usually includes an error amplifier, a reference voltage source, a power tube and a feedback network, where the power tube works in a linear mode. When the LDO is powered on, the reference voltage source establishes a stable reference voltage; when the load current changes, the output voltage will also change accordingly. The error amplifier compares the reference voltage with the output voltage divider provided by the feedback network, and compensates for the load current change by adjusting the conduction degree of the power tube to maintain a stable output voltage.

[0037] During the LDO startup process, a large current will be generated. At this time, the gate voltage of the power tube will decrease, and the gate-source voltage V GS Increase; or when the LDO drives a large current load, the larger the load current, the lower the gate voltage of the power tube, and the gate-source voltage V GS When the LDO operates in the high voltage domain, the gate-source voltage V GSAs the load current increases, the gate-source voltage V GS When the load current increases to the overvoltage threshold of the power tube, the power tube and related circuits will have an overvoltage risk if the load current continues to increase. Therefore, it is necessary to add a current limiting circuit to limit the continuous decrease of the gate voltage of the power tube to prevent the power tube from overvoltage.

[0038] Figure 1 A structural block diagram of an LDO circuit provided by the prior art, such as Figure 1 As shown, the output end of the LDO main loop (i.e., the voltage output end of the power tube, hereinafter referred to as "LDO output end") is connected to the input end of the current limiting circuit, and the output of the current limiting circuit is connected to the output end of the error amplifier (Error Amplifier, EA) of the LDO main loop to limit the continuous decrease of the gate voltage of the power tube in the LDO main loop.

[0039] Figure 2a to 2c The schematic diagram of several LDO circuits provided by the prior art shows that M1 to M4 constitute a current limiting circuit, wherein M1 collects the current of the power tube Mp, and the current source Id provides a reference current I1.

[0040] For ease of understanding, we first introduce the main pole and secondary pole in the LDO circuit. In the LDO circuit, the main pole (dominant pole) and the secondary pole (secondary pole) are key parameters for controlling the frequency response of the system, which determine the stability and dynamic performance of the circuit. Among them, the main pole is the lowest frequency pole in the LDO circuit, which is usually the slowest part of the system response. The main pole determines the response speed of the system. By adjusting the position of the main pole, the response speed of the LDO to load changes or input voltage fluctuations can be controlled; the secondary pole is usually located at a higher frequency, which helps shape the frequency response of the system, so that the LDO can maintain good performance at different frequencies. By arranging the position of the poles reasonably, sufficient phase margin can be provided to prevent the circuit from oscillating when disturbed.

[0041] In the LDO circuit, the frequencies of the main pole and the secondary pole should not be close. If the pole frequencies are close, the phase margin of the circuit will be reduced, which may cause system instability. Therefore, in the LDO circuit, it is usually necessary to ensure that the main pole frequency is much lower than the secondary pole frequency to maintain good phase margin and system stability. Usually, the secondary pole frequency should be at least one order of magnitude higher than the main pole frequency to ensure sufficient stability and good dynamic response of the system.

[0042] See first Figure 2aFor the LDO main loop, since the LDO chip is connected to a large external capacitor CL (which can improve the load transient response capability of the LDO), the main pole of the LDO main loop is located at the LDO output end (VOUT), and since the EA output end of the LDO has a small capacitor, the EA output end is set as the secondary pole of the LDO main loop (i.e. net2). For the current limiting circuit, its main pole is located at the output end of the current limiting circuit (i.e. net2), and the secondary pole is located at the negative pole of the current source Id (providing reference current) (i.e. net1). The main pole net2 and the secondary pole net1 have similar frequencies, which makes the current limiting circuit unstable.

[0043] See also Figure 2b The LDO circuit separates the main pole net2 and the secondary pole net1 of the current limiting circuit by adding Miller compensation to improve the stability of the current limiting circuit. Specifically, since the output end of the current limiting circuit is the main pole net2 of the current limiting circuit, one end of the Miller capacitor Cc is connected to the output end of the current limiting circuit. The output end of the current limiting circuit is connected to the output end of EA, so the capacitance of the output end of EA increases. According to the calculation formula of the circuit frequency It can be seen that the increase in capacitance at the EA output will reduce the frequency at the EA output, that is, the secondary pole frequency of the LDO main loop will decrease. However, the distance between the main pole and the secondary pole of the LDO main loop is too close. Even if the main pole frequency constructed by the off-chip capacitor CL is very low, the phase curve of the LDO main loop decreases too fast, and the phase continues to decrease, resulting in instability of the main loop.

[0044] Figure 3 The Bode diagram of the LDO main loop before and after the current limiting circuit encryption compensation is shown as follows: Figure 3 As shown in the figure, the waveform Wi Cc shown by the solid line is the waveform with Miller compensation, and the waveform Wo Cc shown by the dotted line is the waveform without Miller compensation. After the current limiting circuit increases the Miller capacitor Cc, the secondary pole frequency of the LDO main loop decreases. When the gain (Gain) is reduced to 0dB, the phase (Phase) drops to a too low value, and the LDO main loop is unstable.

[0045] See also Figure 2c In addition to adding Miller compensation, this LDO circuit also builds a zero point (the point where the denominator of the system transfer function is zero) by adding ESR resistor R3 at the output of the LDO. The position of the zero point can be adjusted by selecting an appropriate ESR value. By creating an additional zero point, the pole in the compensation circuit is reduced to reduce phase lag, helping to improve the phase margin of the LDO, thereby improving the stability of the LDO main loop. However, when the LDO drives a high current load, a large voltage drop will be generated on the ESR resistor, and the voltage drop will increase as the load current increases.

[0046] Ideally, the output voltage of the LDO should remain constant and not be affected by changes in the load current. The stability of the output voltage of the LDO when the load current changes is the load regulation rate. The voltage drop across the ESR resistor will cause the output voltage of the LDO to change with changes in the load current. For example, when the load current increases, the voltage drop across the ESR resistor increases, causing the output voltage of the LDO to decrease, making the load regulation rate worse and failing to maintain the stability of the output voltage.

[0047] In view of this, the present application provides an LDO circuit with a current limiting function, which can achieve current limiting of the power tube in the LDO without the need for Miller capacitors and ESR resistors, thereby improving the load regulation rate of the LDO while maintaining the stability of the LDO.

[0048] Figure 4 The structural block diagram of the LDO circuit provided in the embodiment of the present application is as follows: Figure 4 The LDO circuit 100 includes an LDO main loop 110, a power tube current acquisition circuit 121, and a current limiting feedback circuit 122. The LDO output end (i.e., the voltage output end of the power tube, VOUT) of the LDO main loop 110 is connected to an external load to provide an output voltage for the load; the power tube current acquisition circuit 121 and the current limiting feedback circuit 122 constitute the current limiting circuit 120 of the LDO, a current source for providing a reference current is provided in the current limiting feedback circuit 122, the power tube current acquisition circuit 121 is used to acquire the current flowing through the power tube in the LDO main loop 110 (hereinafter referred to as "power tube current", i.e., load current), and the current limiting feedback circuit 122 is used to limit the power tube current according to the reference current so that the power tube current is not greater than the current limiting threshold, thereby limiting the gate-source voltage V of the power tube through the current limiting feedback circuit 122. GS Further increase to achieve the purpose of current limiting. Among them, the current limiting threshold is related to the EA output current of the error amplifier, the reference current and the device parameters in the current limiting circuit.

[0049] Regarding the positions of the primary and secondary poles in the circuit, the primary pole of the LDO main loop 110 is located at the LDO output end, and the secondary pole is located at the EA output end; the primary pole of the current limiting circuit 120 is located at the output end of the current limiting circuit 120, and the secondary pole is located at the negative pole of the current source.

[0050] In the current limiting feedback circuit 122, a low impedance unit is provided between the power supply terminal AVDD and the secondary pole of the current limiting circuit 120, forming a low impedance path between the power supply terminal AVDD and the secondary pole of the current limiting circuit 120, so as to reduce the output impedance of the secondary pole of the current limiting circuit 120, increase the frequency of the secondary pole of the current limiting circuit 120, and make the frequency of the secondary pole of the current limiting circuit 120 away from the frequency of the main pole of the current limiting circuit 120. Since the frequencies of the two poles of the current limiting circuit 120 differ greatly, it is not necessary to add Miller compensation in the circuit, and the stability of the current limiting circuit 120 can be maintained.

[0051] The low impedance unit may include one or more low impedance devices. When the load current increases, the power tube current increases. When the power tube current increases to a first value, the low impedance unit is turned off / on, so that the current limiting feedback circuit 122 is turned on and started. When the power tube current continues to increase to a second value (i.e., the current limiting threshold), the power tube current collection circuit 121 and the current limiting feedback circuit 122 work together to limit the power tube current from continuing to increase, so that the power tube current is limited to the current limiting threshold.

[0052] The low impedance device may be a metal-oxide-semiconductor field-effect transistor (MOSFET, hereinafter referred to as "MOS tube"), a bipolar junction transistor (BJT), a diode, or a combination of multiple devices. As long as the device or device combination can be turned off / on when the power tube current increases to turn on the current limiting feedback circuit 122 to start, and can form a low impedance path between the power supply terminal AVDD and the secondary pole of the current limiting circuit 120 to reduce the output impedance of the secondary pole of the current limiting circuit 120, it can be used.

[0053] For the LDO main loop 110, because the LDO chip is externally connected to a large capacitor, the main pole frequency of the LDO main loop 110 is very small; the secondary pole of the LDO main loop 110 is located at the EA output end, and the capacitance of the EA output end is very small (no Miller capacitor is connected, which does not increase the capacitance of the EA output end), so the secondary pole frequency of the LDO main loop 110 is very large. Therefore, the frequency difference between the main pole and the secondary pole of the LDO main loop 110 is large, and there is no need to add an ESR resistor at the EA output end to construct a zero point, and the LDO main loop 110 can still remain stable.

[0054] The LDO circuit with current limiting function provided in the embodiment of the present application is particularly suitable for a high-voltage LDO, that is, an LDO that needs to work in a high-voltage domain.

[0055] Figure 5The circuit diagram of the LDO circuit provided in the embodiment of the present application is shown below. Figure 5 , a specific structure and current limiting working principle of the LDO circuit are explained.

[0056] As shown in the figure, the LDO main loop 110 includes a power tube Mp, a feedback network (a first resistor R1, a second resistor R2) and an error amplifier EA. The LDO main loop 110 also has a reference voltage source inside to provide a stable reference voltage VREF for the error amplifier EA.

[0057] The non-inverting input terminal of the error amplifier EA is connected to the reference voltage VREF, and the output terminal of the error amplifier EA is connected to the gate of the power tube Mp; the source of the power tube Mp is connected to the power supply terminal AVDD, and the drain of the power tube Mp is connected to the inverting input terminal of the error amplifier EA through the first resistor R1, and the drain of the power tube Mp is also connected to the ground through the first resistor R1 and the second resistor R2 in sequence.

[0058] The power tube Mp controls the current from the power supply terminal AVDD to the LDO output terminal (i.e., VOUT). The power tube Mp can be a transistor, such as a metal-oxide-semiconductor field-effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET, hereinafter referred to as "MOS tube") or a bipolar junction transistor (bipolar junction transistor, BJT). The figure shows a P-channel enhancement MOS tube.

[0059] The feedback network is composed of two voltage-dividing resistors, a first resistor R1 and a second resistor R2, which feed a fixed proportion of the output voltage of the power tube Mp back to the inverting input terminal of the error amplifier EA.

[0060] The error amplifier EA compares the feedback voltage VFB (a part of the output voltage) of the feedback network with the reference voltage VREF and amplifies their difference. When the load current changes, the output voltage of the power tube Mp will also change. If the feedback voltage VFB is lower than the reference voltage VREF, the error amplifier EA controls to increase the conduction degree of the power tube Mp, so that the power tube Mp allows more current to flow through and increases the output voltage of the power tube Mp. Otherwise, the error amplifier EA controls to reduce the conduction degree of the power tube Mp, thereby reducing the output voltage of the power tube Mp. The error amplifier EA adjusts the conduction degree of the power tube Mp to compensate for the change in the output voltage of the power tube Mp when the load current changes, so as to maintain the stability of the output voltage.

[0061] Please continue reading Figure 5The power tube current collection circuit 121 includes a first MOS tube M1, a second MOS tube M2 and a third MOS tube M3. The current limiting feedback circuit 122 includes a current source Id, a fourth MOS tube M4 and a fifth MOS tube M5.

[0062] In the power tube current acquisition circuit 121, the gate of the first MOS tube M1 is connected to the gate of the power tube Mp, the source is connected to the power supply terminal AVDD, and the drain is connected to the drain of the second MOS tube M2; the gate of the second MOS tube M2 is connected to the gate of the third MOS tube M3, and the source is grounded; the drain of the third MOS tube M3 is connected to the negative electrode of the current source Id, and the source is grounded. The second MOS tube M2 and the third MOS tube M3 form a current mirror, that is, the third MOS tube M3 mirrors the current of the second MOS tube M2.

[0063] In the current limiting feedback circuit 122, the positive electrode of the current source Id is connected to the power supply terminal AVDD; the gate and drain of the fourth MOS tube M4 are both connected to the negative electrode of the current source Id, and the source is connected to the power supply terminal AVDD; the gate of the fifth MOS tube M5 is connected to the negative electrode of the current source Id, the source is connected to the power supply terminal AVDD, and the drain is connected to the output terminal of the error amplifier EA.

[0064] The main pole of the LDO main loop 110 is located at the LDO output end (ie, VOUT), and the secondary pole is located at the EA output end (ie, net2); the main pole of the current limiting circuit 120 is located at the output end of the current limiting circuit 120 (ie, net2), and the secondary pole is located at the negative pole of the current source Id (ie, net1).

[0065] Figure 5 In the example shown, the low impedance unit is the fourth MOS transistor M4. Specifically, the fourth MOS transistor M4 is a diode-connected MOS transistor, that is, the gate and drain of the fourth MOS transistor M4 are electrically connected, which is equivalent to a three-port MOS transistor being equivalent to a two-port device, and its I / V characteristic is similar to that of a diode. The output impedance r0 of the fourth MOS transistor M4, that is, the output impedance of the secondary pole (net1) of the current limiting circuit 120 is:

[0066]

[0067] That is, the fourth MOS tube M4 can be equivalent to a The resistance of gm4 is the transconductance of the fourth MOS tube M4. The transconductance is the proportional coefficient of the change of the drain current Id of the MOS tube with the gate voltage Vgs in the saturation state. The calculation formula is:

[0068]

[0069] The frequency p1 of the main pole (net2) of the current limiting circuit 120 is calculated as follows:

[0070]

[0071] Where r1 is the output impedance of the main pole (net2) of the current limiting circuit 120, Cp EA is the parasitic capacitance of the error amplifier EA, is the capacitance between the gate and source of the fifth MOS tube M5 (gate-source capacitance), It is the total gate capacitance of the power tube Mp.

[0072] The frequency p2 of the secondary pole (net1) of the current limiting circuit 120 is calculated as follows:

[0073]

[0074] Wherein, Cgg_M5 is the total gate capacitance of the fifth MOS tube M5, and Cgg_M4 is the total gate capacitance of the fourth MOS tube M4.

[0075] It can be seen from the above formula that since the output impedance r0 of the secondary pole (net1) of the current limiting circuit 120 increases, the frequency of the secondary pole (net1) of the current limiting circuit 120 increases, so that the frequency of the secondary pole (net1) of the current limiting circuit 120 is far away from the frequency of the main pole (net2) of the current limiting circuit 120; the frequencies of the two poles are greatly different, so there is no need to add Miller compensation in the circuit, and the stability of the current limiting circuit 120 can also be maintained.

[0076] For the LDO main loop 110, because the LDO chip is externally connected to a large capacitor CL, the frequency of the main pole (VOUT) of the LDO main loop 110 is very small; the secondary pole (net2) of the LDO main loop 110 is located at the EA output end, and the capacitance at the EA output end is very small, so the frequency of the secondary pole (net2) of the LDO main loop 110 is very large. Therefore, the frequency difference between the main pole (VOUT) and the secondary pole (net2) of the LDO main loop 110 is large, and there is no need to add an ESR resistor at the EA output end to construct a zero point, and the LDO main loop 110 can still remain stable.

[0077] The current limiting working principle of the LDO circuit of the embodiment of the present application is described below:

[0078] The gates of the first MOS tube M1 and the power tube Mp are connected to form a current mirror. The first MOS tube M1 collects the current of the power tube Mp, and the collected current value is related to the mirror ratio of the two. If the mirror ratio of the first MOS tube M1 to the power tube Mp is 1:m, the current value I collected by the first MOS tube M1 is M1 Equal to I Mp / m.

[0079] The current value I flowing through the second MOS tube M2 M2 Equal to the current value I flowing through the first MOS tube M1 M1 .

[0080] The second MOS tube M2 and the third MOS tube M3 form a current mirror. If the mirror ratio of the third MOS tube M3 to the second MOS tube M2 is 1:n, the current value I flowing through the third MOS tube M3 is M3 The calculation formula is:

[0081]

[0082] When the LDO is working normally, if the load current value is not too large, the current value I flowing through the power tube Mp Mp If the current value I is not too large, the current value I is collected by the first MOS tube M1 and then mirrored to the third MOS tube M3. M3 Small, for example, the mirror ratio of the first MOS tube M1 and the power tube Mp is 1:100, when I Mp When I is 100, M3 Only 1. In I M3 When the current source Id is not greater than the reference current I1 provided by the current source Id, no excess current flows through the fourth MOS transistor M4. At this time, the fourth MOS transistor M4 is not turned on, and the fifth MOS transistor M5 and the fourth MOS transistor M4 form a current mirror, and the fifth MOS transistor M5 also has no current flowing through it and is not turned on, and the current limiting feedback circuit 122 is turned off and does not work.

[0083] When the load current increases, the gate voltage of the power tube Mp decreases, and the current value I flowing through the power tube Mp Mp Increases, and accordingly the current value I collected by the first MOS tube M1 M1 According to Formula 5, the current value I flowing through the third MOS tube M3 is M3 Also increases accordingly. M3 When it is greater than I1, the excess current will flow through the fourth MOS transistor M4, and the fifth MOS transistor M5 which is a mirror image of the fourth MOS transistor M4 will also have current flowing through it, and the fifth MOS transistor M5 will be turned on. At this time, the current limiting feedback circuit 122 will be turned on and started.

[0084] As the load current continues to increase, the current value I flowing through the third MOS tube M3 M3 Continue to increase, the current value I flowing through the fourth MOS tube M4 M4 The current value I flowing through the fifth MOS tube M5 also increases accordingly. M5 Since the drain of the fifth MOS tube M5 is connected to the EA output terminal, the current source of the fifth MOS tube M5 is the tail current extracted from the EA output terminal, so I M5It cannot be increased indefinitely, but can only be increased to the tail current value I of the EA output end. EA , that is, the current value I flowing through the fifth MOS tube M5 M5 The maximum value is limited to the tail current value I EA .

[0085] If the mirror ratio of the fifth MOS tube M5 to the fourth MOS tube M4 is 1:k, the current value I flowing through the fourth MOS tube M4 is M4 The calculation formula is:

[0086] I M4 = k * I M5 Formula 6

[0087] When I M5 Increase to I EA Even if the load current continues to increase, I M5 The maximum value is also I EA I M4 The maximum value is k*I EA .

[0088] The current value I flowing through the third MOS tube M3 M3 is the current value I1 of the current source Id and the current value I flowing through the fourth MOS transistor M4 M4 The sum of , that is:

[0089] I M3 =I1+I M4 =I1+k*I M5 Formula 7

[0090] When I M5 The maximum value is limited to I EA When M3 The maximum value is limited to 11+k*I EA .

[0091] According to formula 5, the current value I flowing through the power tube Mp is Mp For I M3 *m*n, therefore, I Mp The maximum value is limited to (I1+k*I EA )*m*n, which is the current limiting threshold I of the power tube Mp limit for:

[0092] I limit =(I1+k*I EA )*m*n Formula 8

[0093] Current limit threshold I limit The tail current value k*I at the output of the error amplifier and the reference current I1 EA, the mirror ratio of the first MOS tube M1 and the power tube Mp, the mirror ratio of the third MOS tube M3 and the second MOS tube M2, and the mirror ratio of the fifth MOS tube M5 and the fourth MOS tube M4.

[0094] In summary, after the load current increases to the point where the current limiting feedback circuit 122 is turned on and started, the current value I flowing through the power tube Mp is Mp It will not increase infinitely, but will be limited to I limit , thereby achieving current limiting for the power tube Mp.

[0095] The embodiment of the present application realizes that when the load current increases, the current value I of the power tube Mp is Mp Limited to I limit , to prevent the gate-source voltage V of the power tube Mp GS Continuously increasing, there is a risk of overvoltage, fewer devices are used, and the circuit board area is saved. By adding a low impedance path to the secondary pole (net1) of the current limiting circuit 120, the output impedance of the secondary pole (net1) of the current limiting circuit 120 is increased, and the frequency of the secondary pole (net1) of the current limiting circuit 120 is increased, so that the frequency of the secondary pole (net1) of the current limiting circuit 120 is far away from the frequency of the main pole (net2) of the current limiting circuit 120. There is no need to add Miller compensation in the circuit, and the stability of the current limiting circuit 120 can also be maintained. Since the EA output end of the LDO main loop 110 is not connected to the Miller capacitor, its capacitance is very small, and therefore the secondary pole frequency of the LDO main loop 110 is very large, so the frequency difference between the main pole (VOUT) and the secondary pole (net2) of the LDO main loop 110 is large, and there is no need to add an ESR resistor at the EA output end to construct a zero point. The LDO main loop 110 can still remain stable, thereby improving the load regulation rate of the LDO.

[0096] The present application also provides a power management chip. Figure 6 The structural block diagram of the power management chip provided in the embodiment of the present application is as follows: Figure 6 As shown, the power management chip 200 includes the LDO circuit 100 in the above embodiment. The power management chip 200 has the same beneficial effects as the above LDO circuit 100, which will not be described in detail here.

[0097] The embodiment of the present application also provides a circuit board, Figure 7 The structural block diagram of the circuit board provided in the embodiment of the present application is as follows: Figure 7As shown, the circuit board 300 is provided with the power management chip 200 provided in the above embodiment and the off-chip capacitor CL, the first end of the off-chip capacitor CL is connected to the voltage output terminal VOUT of the power management chip 200, and the second end of the off-chip capacitor CL is grounded. The voltage output terminal VOUT of the power management chip 200 is also the voltage output terminal VOUT of the power tube Mp in the power management chip. The circuit board 300 has the same beneficial effects as the above-mentioned LDO circuit 100, which will not be repeated here.

[0098] The present application also provides an electronic device, Figure 8 A structural block diagram of an electronic device provided in an embodiment of the present application, such as Figure 8 As shown, the electronic device 400 includes the circuit board 300 in the above embodiment. The electronic device 400 has the same beneficial effects as the above LDO circuit 100, which will not be described in detail here.

[0099] It should be noted that the above embodiments illustrate the present application rather than limit the present application, and that those skilled in the art may design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference symbol between brackets shall not be constructed as a limitation on the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "one" or "an" preceding an element does not exclude the presence of multiple such elements. The present application may be implemented by means of hardware including several different elements and by means of a suitably programmed computer. In the claims that list several devices, several units or modules in these devices may be embodied by the same hardware item. The use of the words first, second, and third, etc. does not indicate any order. These words may be interpreted as names. The steps in the above embodiments, unless otherwise specified, should not be understood as limitations on the order of execution.

[0100] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A low dropout linear regulator LDO circuit, characterized in that: include: The LDO main loop includes a power tube and an error amplifier, wherein the power tube has a voltage output end, the voltage output end is used to connect an external load, and the error amplifier is used to adjust the current flowing through the power tube to keep the output voltage of the voltage output end stable; as well as A current limiting circuit, comprising a power tube current acquisition circuit and a current limiting feedback circuit, wherein the power tube current acquisition circuit is used to acquire the power tube current, the current limiting feedback circuit comprises a current source, the positive electrode of the current source is connected to the power supply end, and is used to provide a reference current, and the current limiting feedback circuit is used to limit the power tube current according to the reference current, so that the power tube current is not greater than a current limiting threshold; The main pole of the current limiting circuit is located at the output end of the current limiting circuit, the secondary pole of the current limiting circuit is located at the negative pole of the current source, and the current limiting feedback circuit also includes a low impedance unit located between the power supply end and the secondary pole of the current limiting circuit, and the low impedance unit is used to reduce the output impedance of the secondary pole of the current limiting circuit.

2. The LDO circuit according to claim 1, characterized in that: The low impedance unit includes one or more low impedance devices; When the power tube current increases to a first value, the low impedance unit is turned on, and the current limiting feedback circuit is switched from an off state to an on state, wherein the first value is less than the current limiting threshold.

3. The LDO circuit according to claim 2, characterized in that: The low impedance device includes one or more of a metal-oxide semiconductor field effect transistor, a bipolar junction transistor and a diode.

4. The LDO circuit according to claim 1, characterized in that: The power tube current acquisition circuit includes a first MOS tube, a second MOS tube and a third MOS tube; The gate of the first MOS tube is connected to the gate of the power tube, the source of the first MOS tube is connected to the power supply end, and the drain of the first MOS tube is connected to the drain of the second MOS tube; The gate of the second MOS tube is connected to the gate of the third MOS tube, and the source of the second MOS tube is grounded; The drain of the third MOS tube is connected to the negative electrode of the current source, and the source of the third MOS tube is grounded.

5. The LDO circuit according to claim 4, characterized in that: The low impedance unit is a fourth MOS tube, and the current limiting feedback circuit further includes a fifth MOS tube; The gate and drain of the fourth MOS tube are both connected to the negative electrode of the current source, and the source of the fourth MOS tube is connected to the power supply end; The gate of the fifth MOS tube is connected to the negative electrode of the current source, the source of the fifth MOS tube is connected to the power supply end, and the drain of the fifth MOS tube is connected to the output end of the error amplifier.

6. The LDO circuit according to claim 5, characterized in that: The mirror image ratio of the first MOS tube to the power tube is 1:m, the mirror image ratio of the third MOS tube to the second MOS tube is 1:n, and the mirror image ratio of the fifth MOS tube to the fourth MOS tube is 1:k; The current limiting threshold I limit for: I limit =(I1+k*I EA )*m*n; Wherein, I1 is the reference current, I EA is the tail current value at the output end of the error amplifier.

7. The LDO circuit according to claim 1, characterized in that: The LDO main loop also includes a first resistor and a second resistor R2; The non-inverting input terminal of the error amplifier is connected to a reference voltage, and the output terminal of the error amplifier is connected to the gate of the power tube; The source of the power tube is connected to the power supply end, the drain of the power tube is connected to the inverting input end of the error amplifier through the first resistor, and the drain of the power tube is also connected to the ground through the first resistor and the second resistor in sequence.

8. A power management chip, characterized in that: The invention comprises the LDO circuit according to any one of claims 1 to 7.

9. A circuit board, characterized in that: The circuit board is provided with the power management chip as claimed in claim 8 and an off-chip capacitor, and the off-chip capacitor is connected to the voltage output terminal of the power tube in the power management chip.

10. An electronic device, characterized in that: The electronic device comprises the circuit board as claimed in claim 9.

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