On-vehicle sensor time synchronization system and method and field programmable gate array chip

Abstract

The present disclosure provides a vehicle-mounted sensor time synchronization system and method and a field programmable gate array chip, which relate to sensors, artificial intelligence chips, and artificial intelligence fields such as autonomous driving. The vehicle-mounted sensor time synchronization system includes: a target vehicle-mounted sensor and a field programmable gate array chip, the target vehicle-mounted sensor includes all vehicle-mounted sensors in the target vehicle that need to write timestamp information; the target vehicle-mounted sensor is connected to the field programmable gate array chip, which is used to send the collected sensor data to the field programmable gate array chip; the field programmable gate array chip is used to write timestamp information in the sensor data based on its own system time.

Description

Technical Field

[0001] The present disclosure relates to the field of artificial intelligence technology, and in particular to a vehicle-mounted sensor time synchronization system and method and a field programmable gate array chip in the fields of sensors, artificial intelligence chips, and autonomous driving. Background Art

[0002] With the development of technology, autonomous vehicles have been used more and more widely in different scenarios. The safe driving of autonomous vehicles depends on various on-board sensors, which in turn involves the time synchronization of various on-board sensors. Summary of the invention

[0003] The present disclosure provides a vehicle-mounted sensor time synchronization system and method and a field programmable gate array chip.

[0004] A vehicle-mounted sensor time synchronization system, comprising:

[0005] A target vehicle-mounted sensor and a field programmable gate array chip, wherein the target vehicle-mounted sensor includes all vehicle-mounted sensors in the target vehicle that need to write timestamp information;

[0006] The target vehicle-mounted sensor is connected to the field programmable gate array chip to send the collected sensor data to the field programmable gate array chip;

[0007] The field programmable gate array chip is used to write timestamp information into the sensor data based on its own system time.

[0008] A field programmable gate array chip, comprising: a system module and a logic module;

[0009] The system module and the logic module are respectively connected to at least one target vehicle-mounted sensor, and are used to obtain sensor data collected by the connected target vehicle-mounted sensor, and write timestamp information into the sensor data based on the system time in the field programmable gate array chip. The target vehicle-mounted sensor includes all vehicle-mounted sensors in the target vehicle that need to write timestamp information.

[0010] A vehicle-mounted sensor time synchronization method, the method is applied in a system module and a logic module, comprising:

[0011] Obtain sensor data collected by the connected target vehicle-mounted sensor;

[0012] Writing timestamp information into the sensor data based on the system time in the field programmable gate array chip;

[0013] The system module and the logic module are both located in the field programmable gate array chip, and the system module and the logic module are respectively connected to at least one of the target vehicle-mounted sensors, and the target vehicle-mounted sensors include all vehicle-mounted sensors in the target vehicle that need to write timestamp information.

[0014] An electronic device, comprising:

[0015] at least one processor; and

[0016] a memory communicatively connected to the at least one processor; wherein,

[0017] The memory stores instructions that can be executed by the at least one processor. The instructions are executed by the at least one processor to enable the at least one processor to perform the method described above.

[0018] A non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause a computer to execute the method as described above.

[0019] A computer program product comprises a computer program / instruction, wherein the computer program / instruction implements the method described above when executed by a processor.

[0020] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings are used to better understand the present solution and do not constitute a limitation of the present disclosure.

[0022] Figure 1 Schematic diagram of the composition structure of the first embodiment 100 of the vehicle-mounted sensor time synchronization system of the present disclosure;

[0023] Figure 2 It is a schematic diagram of the composition structure of the second embodiment 200 of the vehicle-mounted sensor time synchronization system of the present disclosure;

[0024] Figure 3 It is a schematic diagram of the composition structure of the third embodiment 300 of the vehicle-mounted sensor time synchronization system of the present disclosure;

[0025] Figure 4 Schematic diagram of the structure of the fourth embodiment 400 of the vehicle-mounted sensor time synchronization system of the present disclosure;

[0026] Figure 5 Schematic diagram of the composition structure of the FPGA chip 102 described in the present disclosure;

[0027] Figure 6 It is a flow chart of an embodiment of the vehicle-mounted sensor time synchronization method disclosed in the present invention;

[0028] Figure 7 A schematic block diagram of an electronic device 700 that can be used to implement an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0029] The following is a description of exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0030] In addition, it should be understood that the term "and / or" in this article is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0031] Figure 1 FIG. 1 is a schematic diagram of the composition structure of the first embodiment 100 of the vehicle-mounted sensor time synchronization system of the present disclosure. Figure 1 As shown, it includes: a target vehicle-mounted sensor 101 and a field programmable gate array (FPGA, Field Programmable Gate Array) chip 102.

[0032] The target vehicle-mounted sensor 101 includes all vehicle-mounted sensors in the target vehicle that need to write timestamp information. The target vehicle-mounted sensor 101 is connected to the FPGA chip 102, which is used to send the collected sensor data to the FPGA chip 102, and the FPGA chip 102 is used to write timestamp information in the sensor data based on its own system time. Among them, the sensor data generally refers to the sensor data collected in real time during the driving process of the autonomous driving vehicle.

[0033] The target vehicle-mounted sensor 101 may include a camera, a radar, a lidar, and an inertial measurement unit (IMU), etc. In addition, in practical applications, the vehicle-mounted sensor may also include a global positioning system (GPS), which has its own time information.

[0034] In the existing method, in order to achieve time synchronization of vehicle-mounted sensors, two chips are usually set up. The two chips can be a microcontroller unit (MCU) chip and a system on chip (SoC) chip. Among them, Camera, Lidar, IMU and GPS can be connected to the SoC chip, and Radar can be connected to the MCU chip. The timestamps of Camera, Lidar and IMU are determined by the system time of the SoC chip. GPS has its own time information, and the system time of the SoC chip can be corrected by using the time information of GPS. The timestamp of Radar is determined by the system time of the MCU chip. The time synchronization between the SoC chip and the MCU chip can be achieved through the Precision Time Protocol (PTP), the Generalized Precision Time Protocol (gPTP) or other Control Area Network (CAN) protocols.

[0035] Compared with existing implementations, the vehicle-mounted sensor time synchronization system 100 disclosed in the present invention is converted from a multi-chip solution to a single-chip solution, thereby reducing implementation costs, saving system overhead, etc.

[0036] The single chip may be an FPGA chip 102, and each target vehicle-mounted sensor 101 may be connected to the FPGA chip 102. For each target vehicle-mounted sensor 101, the collected sensor data may be sent to the FPGA chip 102 respectively. Accordingly, the FPGA chip 102 may timestamp the acquired sensor data, that is, write timestamp information into the acquired sensor data. Subsequently, data fusion and other processing may be performed based on the sensor data after the timestamp information is written.

[0037] Figure 2 FIG. 2 is a schematic diagram of the structure of the second embodiment 200 of the vehicle-mounted sensor time synchronization system of the present disclosure. Figure 2 As shown, it includes: a target vehicle-mounted sensor 101 and an FPGA chip 102 , wherein the FPGA chip 102 further includes a system (FPGA System) module 1021 and a logic (FPGA Logic) module 1022 .

[0038] The FPGA Logic module 1022 is the programmable logic part of the FPGA chip 102, which can be configured as various digital logic circuits and processor peripherals, etc. The FPGA System module 1021 is the processing system part of the FPGA chip 102, which can run the operating system, perform memory management and interrupt management, etc.

[0039] In the solution described in the present disclosure, in addition to using the FPGA System module 1021 and the FPGA Logic module 1022 to implement the original functions, the FPGA System module 1021 and the FPGA Logic module 1022 can also be used to write timestamp information.

[0040] Among them, the target vehicle-mounted sensor 101 can be divided into two groups based on the principle of load balancing. The target vehicle-mounted sensor 101 in the first group can be connected to the FPGA System module 1021, and the target vehicle-mounted sensor 101 in the second group can be connected to the FPGA Logic module 1022. The principle of load balancing may include: the difference between the data volume of the sensor data connected to the FPGA System module 1021 and the data volume of the sensor data connected to the FPGA Logic module 1022 is less than a predetermined threshold. Accordingly, the FPGA System module 1021 and the FPGA Logic module 1022 can respectively write timestamp information in the acquired sensor data based on the system time of the FPGA chip 102.

[0041] The specific value of the predetermined threshold value can be determined according to actual needs. In addition, there is no restriction on how to group the target vehicle-mounted sensors 101. For example, assuming that there are 4 target vehicle-mounted sensors 101 in total, for the convenience of description, they are respectively called sensor a, sensor b, sensor c and sensor d, assuming that the amount of sensor data generated by sensor a accounts for 45% of the total amount of data, and the total amount of data refers to the sum of the amount of sensor data generated by sensor a, sensor b, sensor c and sensor d, and assuming that the amount of sensor data generated by sensor b, sensor c and sensor d accounts for 20%, 20% and 15% of the total amount of data, respectively, then sensor a can be used as a group, such as the first group, and sensor b, sensor c and sensor d can be used as another group, such as the second group, and then sensor a in the first group can be connected to the FPGA System module 1021, and sensor b, sensor c and sensor d in the second group can be connected to the FPGA Logic module 1022.

[0042] Through the above processing, the amount of sensor data acquired by the two modules can be made as close as possible, so that the two modules can process the sensor data in a load-balanced manner, avoiding the obvious load difference between the two modules caused by writing timestamp information, thereby improving the processing efficiency and resource utilization of the two modules.

[0043] In addition, if necessary, the grouping method or the modules connected to different groups can be modified, which is very flexible and convenient. In existing multi-chip solutions, if the above modifications are to be implemented, it is usually necessary to modify the hardware connection, which takes a long time and is costly.

[0044] Figure 3 FIG. 3 is a schematic diagram of the structure of the third embodiment 300 of the vehicle-mounted sensor time synchronization system of the present disclosure. Figure 3 As shown, it includes: a target vehicle-mounted sensor 101 and an FPGA chip 102 , wherein the FPGA chip 102 further includes: an FPGA System module 1021 , an FPGA Logic module 1022 and a timestamp register 1023 .

[0045] The timestamp register 1023 may be used to store the system time of the FPGA chip 102. Accordingly, the FPGA System module 1021 and the FPGA Logic module 1022 may obtain corresponding timestamp information for the acquired sensor data by accessing the timestamp register 1023, and may write the acquired timestamp information into the sensor data.

[0046] That is to say, the FPGA System module 1021 and the FPGA Logic module 1022 can perform time synchronization between modules by accessing registers. Compared with the time synchronization method between chips in a multi-chip solution, the time synchronization method described in the present disclosure can be significantly improved in terms of reliability and real-time performance.

[0047] In addition, in a multi-chip solution, considering the time synchronization delay between chips and other reasons, the timestamp information written into the sensor data may sometimes have certain errors. However, by adopting the single-chip solution described in the present invention, the above problems can be avoided, thereby improving the accuracy of the written timestamp information.

[0048] Figure 4 FIG. 4 is a schematic diagram of the structure of the fourth embodiment 400 of the vehicle-mounted sensor time synchronization system of the present disclosure. Figure 4 As shown, it includes: a target vehicle-mounted sensor 101, a main time source 103 and an FPGA chip 102, wherein the FPGA chip 102 further includes: an FPGA System module 1021, an FPGA Logic module 1022 and a timestamp register 1023.

[0049] The primary time source may be a GPS or gPTP device, etc.

[0050] An autonomous driving vehicle usually includes a GPS, which is an on-board sensor other than the target on-board sensor 101 and has its own time information. Accordingly, the system time in the timestamp register 1023 can be determined based on the time information provided by the GPS. That is, the system time of the FPGA chip 102 can be obtained by analyzing the sensor data of the GPS. For example, when the FPGA chip 102 is powered on, the system time can be determined based on the time information of the GPS (such as correcting the original time, etc.). If necessary, the system time can be periodically corrected based on the time information of the GPS, etc., which is very simple and convenient, and ensures the accuracy of the system time, etc. In addition, in some cases, the autonomous driving vehicle will also include a gPTP device, so the system time in the timestamp register 1023 can also be determined based on the time information provided by the gPTP device.

[0051] In practical applications, the Camera can be connected to the FPGA chip 102 through the Mobile Industry Processor Interface (MIPI) protocol, the Lidar can be connected to the FPGA chip 102 through the Ethernet (eth) protocol, the IMU can be connected to the FPGA chip 102 through the Serial Peripheral Interface (SPI) protocol, the Radar can be connected to the FPGA chip 102 through the CAN protocol, and the GPS can be connected to the FPGA chip 102 through the Universal Asynchronous Receiver / Transmitter (UART) protocol.

[0052] The above is an introduction to the system embodiment. The following further illustrates the solution of the present disclosure through device and method embodiments.

[0053] Figure 5 FIG. 1 is a schematic diagram of the composition structure of the FPGA chip 102 described in the present disclosure. Figure 5 As shown, it includes: FPGA System module 1021 and FPGA Logic module 1022.

[0054] The FPGA System module 1021 and the FPGA Logic module 1022 can be respectively connected to at least one target vehicle-mounted sensor 101, and are used to obtain sensor data collected by the connected target vehicle-mounted sensor 101, and write timestamp information into the acquired sensor data based on the system time in the FPGA chip 102. The target vehicle-mounted sensor 101 includes all vehicle-mounted sensors in the target vehicle that need to write timestamp information.

[0055] In some embodiments of the present disclosure, the target vehicle-mounted sensor 101 can be divided into two groups based on the principle of load balancing. The target vehicle-mounted sensor 101 in the first group can be connected to the FPGA System module 1021, and the target vehicle-mounted sensor 101 in the second group can be connected to the FPGA Logic module 1022. The principle of load balancing may include: the difference between the amount of sensor data connected to the FPGA System module 1021 and the amount of sensor data connected to the FPGA Logic module 1022 is less than a predetermined threshold.

[0056] In addition, in some embodiments of the present disclosure, the FPGA chip 102 may also include a timestamp register 1023 .

[0057] The timestamp register 1023 may be used to store the system time of the FPGA chip 102. Accordingly, the FPGA System module 1021 and the FPGA Logic module 1022 may obtain corresponding timestamp information for the acquired sensor data by accessing the timestamp register 1023, and may write the acquired timestamp information into the sensor data.

[0058] Figure 6 The flowchart of the embodiment of the vehicle sensor time synchronization method disclosed in the present invention is shown in FIG. The method can be applied in the FPGA System module and the FPGA Logic module, such as Figure 6 As shown, the following specific implementation methods are included.

[0059] In step 601, sensor data collected by the connected target vehicle-mounted sensor is obtained.

[0060] In step 602, timestamp information is written into the acquired sensor data based on the system time in the FPGA chip; wherein the FPGA System module and the FPGA Logic module are both located in the FPGA chip, and the FPGA System module and the FPGA Logic module are respectively connected to at least one target vehicle-mounted sensor, and the target vehicle-mounted sensor includes all vehicle-mounted sensors in the target vehicle that need to write timestamp information.

[0061] In some embodiments of the present disclosure, the target vehicle-mounted sensors can be divided into two groups based on the principle of load balancing. The target vehicle-mounted sensors in the first group can be connected to the FPGA System module, and the target vehicle-mounted sensors in the second group can be connected to the FPGA Logic module. The principle of load balancing may include: the difference between the data volume of the sensor data connected to the FPGA System module and the data volume of the sensor data connected to the FPGA Logic module is less than a predetermined threshold.

[0062] In addition, in some embodiments of the present disclosure, a method of writing timestamp information in the acquired sensor data based on the system time in the FPGA chip may include: for the acquired sensor data, obtaining corresponding timestamp information by accessing a timestamp register, and writing the acquired timestamp information into the sensor data, where the timestamp register is located in the FPGA chip.

[0063] It should be noted that, for the aforementioned method embodiments, for the sake of simplicity, they are expressed as a series of action combinations, but those skilled in the art should be aware that the present disclosure is not limited by the described order of actions, because according to the present disclosure, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present disclosure.

[0064] In addition, for the above embodiments, for parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions in other embodiments.

[0065] In summary, by adopting the solution described in the present invention, the existing multi-chip solution can be converted into a single-chip solution, thereby reducing the implementation cost, saving system overhead, and improving processing efficiency and resource utilization through load balancing. In addition, the accuracy, reliability and real-time performance of the written timestamp information can be improved through the register access method inside the single chip.

[0066] The solution disclosed in the present disclosure can be applied to the field of artificial intelligence, especially to the fields of sensors, artificial intelligence chips, and autonomous driving. Artificial intelligence is a discipline that studies how computers can simulate certain human thought processes and intelligent behaviors (such as learning, reasoning, thinking, planning, etc.). It has both hardware-level and software-level technologies. Artificial intelligence hardware technologies generally include technologies such as sensors, dedicated artificial intelligence chips, cloud computing, distributed storage, and big data processing. Artificial intelligence software technologies mainly include computer vision technology, speech recognition technology, natural language processing technology, machine learning / deep learning, big data processing technology, knowledge graph technology, and other major directions.

[0067] In addition, the sensor data in the embodiments described in this disclosure are not for a specific user and cannot reflect the personal information of a specific user. In the technical solution of this disclosure, the collection, storage, use, processing, transmission, provision and disclosure of user personal information involved are in compliance with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0068] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium and a computer program product.

[0069] Figure 7 A schematic block diagram of an electronic device 700 that can be used to implement an embodiment of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or required herein.

[0070] like Figure 7 As shown, the electronic device 700 includes a computing unit 701, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 702 or a computer program loaded from a storage unit 708 to a random access memory (RAM) 703. In the RAM 703, various programs and data required for the operation of the electronic device 700 can also be stored. The computing unit 701, the ROM 702, and the RAM 703 are connected to each other via a bus 704. An input / output (I / O) interface 705 is also connected to the bus 704.

[0071] Multiple components in the electronic device 700 are connected to the I / O interface 705, including: an input unit 706, such as a keyboard, a mouse, etc.; an output unit 707, such as various types of displays, speakers, etc.; a storage unit 708, such as a disk, an optical disk, etc.; and a communication unit 709, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 709 allows the electronic device 700 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0072] The computing unit 701 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 701 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI, Artificial Intelligence) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSP, Digital Signal Processing), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 701 performs the various methods and processes described above, such as the methods described in the present disclosure. For example, in some embodiments, the methods described in the present disclosure may be implemented as a computer software program, which is tangibly included in a machine-readable medium, such as a storage unit 708. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 700 via the ROM 702 and / or the communication unit 709. When the computer program is loaded into the RAM 703 and executed by the computing unit 701, one or more steps of the methods described in the present disclosure may be performed. Alternatively, in other embodiments, the computing unit 701 may be configured to execute the method described in the present disclosure in any other appropriate manner (for example, by means of firmware).

[0073] Various embodiments of the systems and techniques described above herein may be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard parts (ASSPs), system on chip systems (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include: being implemented in one or more computer programs that may be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor that may receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0074] The program code for implementing the method of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions / operations specified in the flow chart and / or block diagram to be implemented. The program code may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0075] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or device, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory, a read-only memory, an erasable programmable read-only memory (EPROM), a flash memory, an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0076] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a cathode ray tube (CRT) or a liquid crystal display (LCD) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or a trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0077] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), and the Internet.

[0078] A computer system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The relationship of client and server is generated by computer programs running on respective computers and having a client-server relationship with each other. The server may be a cloud server, a server of a distributed system, or a server combined with a blockchain.

[0079] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

[0080] The above specific implementations do not constitute a limitation on the protection scope of the present disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A vehicle-mounted sensor time synchronization system, comprising: A target vehicle-mounted sensor and a field programmable gate array chip, wherein the target vehicle-mounted sensor includes all vehicle-mounted sensors in the target vehicle that need to write timestamp information; The target vehicle-mounted sensor is connected to the field programmable gate array chip to send the collected sensor data to the field programmable gate array chip; The field programmable gate array chip is used to write timestamp information into the sensor data based on its own system time; Wherein, the field programmable gate array chip includes: a system module and a logic module; The system module and the logic module are respectively connected to at least one of the target vehicle-mounted sensors based on the principle of load balancing, and write the timestamp information into the acquired sensor data based on the system time.

2. The vehicle-mounted sensor time synchronization system according to claim 1, wherein: The target vehicle-mounted sensors are divided into two groups based on the load balancing principle. The target vehicle-mounted sensors in the first group are connected to the system module, and the target vehicle-mounted sensors in the second group are connected to the logic module.

3. The vehicle-mounted sensor time synchronization system according to claim 1, wherein: The field programmable gate array chip also includes: a timestamp register; The timestamp register is used to store the system time; The system module and the logic module obtain corresponding timestamp information by accessing the timestamp register for the acquired sensor data, and write the timestamp information into the sensor data.

4. The vehicle-mounted sensor time synchronization system according to claim 1, 2 or 3, further comprising: A primary time source, wherein the system time is determined based on time information provided by the primary time source.

5. The vehicle-mounted sensor time synchronization system according to claim 4, wherein: The master time source includes: a global positioning system, or a universal precision time protocol device.

6. A field programmable gate array chip, comprising: System modules and logic modules; The system module and the logic module are respectively connected to at least one target vehicle-mounted sensor based on the principle of load balancing, and are used to obtain sensor data collected by the connected target vehicle-mounted sensor, and write timestamp information into the sensor data based on the system time in the field programmable gate array chip. The target vehicle-mounted sensor includes all vehicle-mounted sensors in the target vehicle that need to write timestamp information.

7. The field programmable gate array chip according to claim 6, wherein: The target vehicle-mounted sensors are divided into two groups based on the load balancing principle. The target vehicle-mounted sensors in the first group are connected to the system module, and the target vehicle-mounted sensors in the second group are connected to the logic module.

8. The field programmable gate array chip according to claim 6 or 7, further comprising: A timestamp register, used to store the system time; The system module and the logic module obtain corresponding timestamp information by accessing the timestamp register for the acquired sensor data, and write the timestamp information into the sensor data.

9. A vehicle-mounted sensor time synchronization method, the method being applied in a system module and a logic module, comprising: Obtain sensor data collected by the connected target vehicle-mounted sensor; Writing timestamp information into the sensor data based on the system time in the field programmable gate array chip; Among them, the system module and the logic module are both located in the field programmable gate array chip, and the system module and the logic module are respectively connected to at least one of the target vehicle-mounted sensors based on the principle of load balancing, and the target vehicle-mounted sensors include all vehicle-mounted sensors in the target vehicle that need to write timestamp information.

10. The vehicle-mounted sensor time synchronization method according to claim 9, wherein: The target vehicle-mounted sensors are divided into two groups based on the load balancing principle. The target vehicle-mounted sensors in the first group are connected to the system module, and the target vehicle-mounted sensors in the second group are connected to the logic module.

11. The vehicle-mounted sensor time synchronization method according to claim 9, wherein: Writing timestamp information into the sensor data based on the system time in the field programmable gate array chip comprises: For the acquired sensor data, corresponding timestamp information is acquired by accessing a timestamp register, and the timestamp information is written into the sensor data, wherein the timestamp register is located in the field programmable gate array chip.

12. An electronic device comprising: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 9 to 11.

13. A non-transitory computer-readable storage medium storing computer instructions, wherein: The computer instructions are used to make a computer execute the method according to any one of claims 9 to 11.

14. A computer program product, comprising a computer program / instruction, wherein when the computer program / instruction is executed by a processor, the method according to any one of claims 9 to 11 is implemented.

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