Multi-core processor, system and microcode loading method suitable for external microcode loading

Abstract

The present invention discloses a multi-core processor, system and microcode loading method suitable for external microcode loading, wherein the multi-core processor comprises a plurality of cores and a JTAG microcode unit electrically connected through a system interface unit, the system interface unit is electrically connected to a peripheral controller, a data cache unit in the JTAG microcode unit comprises a first cache area and a second cache area, the cache speed of the first cache area is greater than the cache speed of the second cache area; the JTAG microcode unit receives a first type of data and stores it in the first cache area, and transmits the first type of data to one or more of the plurality of cores through the system interface unit; the JTAG microcode unit receives a second type of data and stores it in the second cache area, and when the amount of the second type of data cached in the second cache area reaches a preset data amount threshold, the second type of data is transmitted to one or more of the plurality of peripheral controllers. The present invention can improve the speed of external microcode loading into a multi-core processor.

Description

Technical Field

[0001] The present invention relates to the field of processor technology, and in particular to a multi-core processor, system and microcode loading method suitable for external microcode loading. Background Art

[0002] The processor distributes, calculates and processes various information through its internal core and various levels of cache (Cache), control unit and interface electrically connected / coupled to the core. Microcode is a series of relatively simple instructions that are decomposed when executing some complex instructions under the CISC (Complex Instruction Set Computer) structure. The function of microcode is to separate machine instructions from related circuit implementations, so that machine instructions can be designed and modified more freely without considering the actual circuit architecture. The function of the processor can be changed by updating the microcode, or the processor error can be corrected by updating the microcode. For the method of updating or patching the microcode routine in the core of the processor, data and programs can generally be input through the network. However, the method of inputting data or programs through a network connection also increases the risk of malicious intrusion or loading backdoor programs on the processor.

[0003] Compared to the method of inputting data and programs into the processor through the network to update or patch the microcode routines in the core of the processor, it is safer to use JTAG (Joint Test Action Group) to test the electrical characteristics of the chip. JTAG is a standard interface and protocol widely used in electronic devices, mainly used for testing and debugging integrated circuits, especially in the development, production and maintenance stages. However, JTAG is usually not designed for high-bandwidth data transmission, and its transmission rate is relatively low. Microcode usually requires high-speed execution. If a large amount of microcode is to be transmitted, it may take a long time.

[0004] In addition, as the scale of multi-core chips becomes larger and larger, the verification and debugging of multi-core chips becomes more and more difficult and complicated. Therefore, a Chinese patent application with application publication number CN115562930A discloses a method for testing multi-core chips, which determines the test sequence corresponding to each processor type by obtaining multiple processor types of the multi-core chip, and determines the access operation sequence according to the order of operating the JTAG register in the process of the processor executing the write operation instruction. Then, according to the data to be tested, the address to be tested and the access operation sequence, the code for operating each JTAG register according to the access operation sequence is determined, so that the multi-core chip writes the first data to be tested to the first address to be tested, which can improve the efficiency of testing the multi-core chip to a certain extent.

[0005] In the technical solution disclosed in the Chinese patent application with application publication number CN112948197B, a connection module and a test module are set to select a target core for testing, and the target core is connected to the I / O port in the connection module, so that the number of I / O ports occupied by the JTAG interface of the core can be reduced, thereby reducing the chip area and PCB substrate area occupied by the core, and when the target core being tested is in a dead state, the signal at the signal receiving end or the signal generated by a register can be changed to change the target core of the test to ensure the normal conduct of the core test. In this way, the chip area and PCB substrate area occupied by the core can be reduced and the problem of being unable to continue testing when the core is dead can be solved.

[0006] In some other existing technical solutions, a local microcode unit is configured for each core of a multi-core processor, and a remote microcode unit is set for the multi-core processor. A given microcode entry point is generated for any given one of the cores. The given microcode entry point is used to determine whether a specific microcode entry is stored in the local microcode unit of the given core or whether the request should be passed to the remote microcode unit. The microcode is allocated to the local microcode unit of the core or the shared remote microcode unit of the processor in a hierarchical manner to improve the timing and power consumption of the processor.

[0007] Although the above existing technologies can improve the efficiency of testing multi-core chips, optimize chip area, ensure continuous chip testing, and improve processor timing and power consumption to a certain extent, they do not propose improvement plans for the relatively low JTAG transmission rate. When a large amount of microcode needs to be transmitted, it may still take a long time.

[0008] The disclosure of the above background technology content is only used to assist in understanding the inventive concept and technical solution of the present invention. It does not necessarily belong to the prior art of the present application, nor does it necessarily provide technical guidance. In the absence of clear evidence that the above content has been disclosed before the filing date of the present application, the above background technology should not be used to evaluate the novelty and creativity of the present application. Summary of the invention

[0009] The purpose of the present invention is to provide a multi-core processor, system and microcode loading method suitable for external microcode loading, which can improve the security and transmission efficiency of external data loading into the multi-core processor.

[0010] To achieve the above object, the technical solution adopted by the present invention is as follows:

[0011] A multi-core processor suitable for external microcode loading, comprising a plurality of cores, a system interface unit and a JTAG microcode unit, wherein the plurality of cores are electrically connected to the system interface unit respectively, and the plurality of cores are also configured to be electrically connected to a peripheral controller through the system interface unit, the system interface unit is electrically connected to the JTAG microcode unit, and the JTAG microcode unit is configured to be electrically connected to an external microcode transmission device, and is configured to receive data transmitted to it by the external microcode transmission device;

[0012] The JTAG microcode unit includes a data cache unit, the data cache unit includes a first cache area and a second cache area, and the cache speed of the first cache area is greater than the cache speed of the second cache area;

[0013] The JTAG microcode unit is configured to receive the first type of data transmitted thereto by the external microcode transmission device and store the first type of data in the first cache area, and transmit the first type of data cached in the first cache area to one or more of the plurality of cores through the system interface unit;

[0014] The JTAG microcode unit receives the second type of data transmitted to it by the external microcode transmission device and stores it in the second cache area. When the amount of the second type of data cached in the second cache area reaches a preset data amount threshold, the second type of data cached in the second cache area is transmitted to one or more of the plurality of peripheral controllers through the system interface unit.

[0015] Further, based on any one of the above-mentioned technical solutions or a combination of multiple technical solutions, the JTAG microcode unit includes an electrically connected processing module and a JTAG microcode interface;

[0016] The JTAG microcode interface includes the data cache unit and a cyclic redundancy check unit, wherein the cyclic redundancy check unit is electrically connected to the data cache unit and is configured to verify the integrity of data received by the data cache unit;

[0017] The processing module is electrically connected to the cyclic redundancy check unit, and is configured to receive data verified to be complete by the cyclic redundancy check unit, parse the data to obtain microcode data, and control the transmission and storage of the microcode data.

[0018] Further, based on any one of the above technical solutions or a combination of multiple technical solutions, the processing module includes a microcode parser, a storage manager and a data transfer controller electrically connected in sequence;

[0019] The microcode parser is electrically connected to the cyclic redundancy check unit, and the microcode parser includes an electrically connected data parser and a compiler, the data parser is configured to parse the data from the cyclic redundancy check unit to obtain microcode data, and the compiler is configured to classify the microcode data to configure a corresponding data type for the microcode data, the data type includes a first type and a second type, the data type of the first type data is the first type, and the data type of the second type data is the second type;

[0020] The storage manager is configured to configure a storage address for the microcode data according to the data type, the storage address corresponding to the first type of data is one or more of the addresses corresponding to the plurality of cores, and the storage address corresponding to the second type of data is one or more of the plurality of peripheral controllers;

[0021] The data transfer controller is electrically connected to the system interface unit, and is configured to control the order in which the microcode data is transmitted to the target storage address through the system interface unit according to the storage address, and the target location includes the core and the peripheral controller.

[0022] Further, based on any one of the technical solutions or a combination of multiple technical solutions described above, the microcode parser is further configured to determine the priority of the first type of data and the priority of the second type of data according to the length of the microcode data and the historical usage record;

[0023] The storage manager is further configured to configure a corresponding storage address for the first type of data according to a priority of the first type of data, and to configure a corresponding storage address for the second type of data according to a priority of the second type of data;

[0024] The data transmission controller is configured to determine an order of first type data transmission according to a priority of the first type data, and to determine an order of second type data transmission according to a priority of the second type data.

[0025] Further, based on any one of the technical solutions or a combination of multiple technical solutions described above, the core includes a first-level cache and a second-level cache, the storage address configured by the storage manager for the first type of data with a high priority corresponds to the address of the first-level cache, and the storage address configured by the storage manager for the first type of data with a low priority corresponds to the address of the second-level cache.

[0026] Further, based on any one of the above technical solutions or a combination of multiple technical solutions, the data transmission controller is configured to determine the order in which the microcode data is transmitted through the system interface unit according to the data type and priority of the microcode data, including:

[0027] The transmission order of the first type of data takes precedence over the transmission order of the second type of data;

[0028] The transmission order of the first type data with a higher priority takes precedence over the transmission order of the first type data with a lower priority.

[0029] Further, based on any one of the above-mentioned technical solutions or a combination of multiple technical solutions, the processing module further includes an addressing controller, the input end of the addressing controller is electrically connected to the output end of the JTAG microcode interface, and the output end of the addressing controller is electrically connected to the input end of the microcode parser;

[0030] The addressing controller includes an addressing unit and a hierarchical address mapping table. The addressing unit is configured to process and manage address resolution and address conversion. The hierarchical address mapping table is configured to store and manage a mapping relationship from a logical address to a physical address.

[0031] Further, based on any one of the above technical solutions or a combination of multiple technical solutions, the processor includes multiple core groups, each core group includes multiple cores, each core group is configured with a unique group address, and each core is configured with a unique core address;

[0032] The group address and the core address are stored in the hierarchical address mapping table, and the addressing controller is configured to hierarchically determine the storage address corresponding to the microcode data according to the group address and the core address.

[0033] Further, based on any one of the technical solutions or a combination of multiple technical solutions mentioned above, the cyclic redundancy check unit includes an electrically connected shift register and an XOR logic circuit.

[0034] Further, based on any one of the technical solutions or a combination of multiple technical solutions mentioned above, the JTAG microcode unit also includes a JTAG interface, the input end of the JTAG interface is configured to be electrically connected to the external microcode transmission device, and the output end of the JTAG interface is electrically connected to the input end of the data cache unit.

[0035] Further, based on any one of the above-mentioned technical solutions or a combination of multiple technical solutions, the core and the external microcode transmission device have a corresponding relationship, including a one-to-one correspondence between the core and the external microcode transmission device or a correspondence between one core and several external microcode transmission devices; and / or,

[0036] It also includes a third-level cache, which is electrically connected to the system interface unit and configured as a memory of the peripheral controller.

[0037] According to another aspect of the present invention, the present invention provides a computer system, comprising a multi-core processor suitable for external microcode loading as described in any one of the above technical solutions or a combination of multiple technical solutions.

[0038] According to another aspect of the present invention, the present invention provides an external microcode loading method applicable to a multi-core processor, which is applied to a multi-core processor applicable to external microcode loading as described in any one of the above technical solutions or a combination of multiple technical solutions, and the method comprises the following steps:

[0039] The JTAG microcode unit receives data transmitted to it by an external microcode transmission device, and if the data is first type data, stores the first type data in a first buffer area of ​​the data buffer unit; if the data is second type data, stores the second type data in a second buffer area of ​​the data buffer unit;

[0040] transmitting the first type of data cached in the first cache area to one or more of the plurality of cores through the system interface unit;

[0041] When the amount of the second type of data cached in the second cache area reaches a preset data amount threshold, the second type of data cached in the second cache area is transmitted to one or more of the plurality of peripheral controllers through the system interface unit.

[0042] The beneficial effects brought by the technical solution provided by the present invention are as follows:

[0043] a. The multi-core processor suitable for external microcode loading provided by the present invention designs the data buffer unit of the JTAG microcode unit as a multi-layer cache structure including a first storage area and a second storage area, stores the first type of data targeted to be transmitted to the core in the first storage area and transmits it to the corresponding core in real time through the system interface unit, stores the second type of data targeted to be transmitted to the peripheral controller in the second storage area, and transmits it to the peripheral controller for execution at one time when the amount of the stored second type of data reaches a certain amount, thereby reducing the execution delay caused by the slow microcode transmission rate, thereby improving the efficiency of microcode loading in the multi-core processor;

[0044] b. The present invention sets a cyclic redundancy check unit at the output end of the data buffer unit in the JTAG microcode unit to verify the integrity of the data received by the data buffer unit, and determines that the data is received completely before transmitting it to the processing module for parsing and classification processing, which can reduce the error rate in the microcode loading process, thereby improving the efficiency of microcode loading into the multi-core processor;

[0045] c. The present invention uses a microcode parser, a storage manager and a data transmission controller to parse and process data, classify data, configure storage addresses and determine the transmission order of each data, which can further optimize the efficiency of loading into a multi-core processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0047] Figure 1 A first partial architecture diagram of a multi-core processor provided for an exemplary embodiment of the present invention;

[0048] Figure 2 A second partial architecture diagram of a multi-core processor provided for an exemplary embodiment of the present invention;

[0049] Figure 3 A schematic diagram of the core architecture provided for an exemplary embodiment of the present invention;

[0050] Figure 4 A third partial architecture diagram of a multi-core processor provided for an exemplary embodiment of the present invention;

[0051] Figure 5 A schematic diagram of the architecture of a JTAG microcode interface in a JTAG microcode unit provided for an exemplary embodiment of the present invention;

[0052] Figure 6 A schematic diagram of the architecture of a processing module in a JTAG microcode unit provided for an exemplary embodiment of the present invention;

[0053] Figure 7 A flowchart of loading external microcode into a multi-core processor provided for an exemplary embodiment of the present invention;

[0054] Figure 8 A schematic diagram of the architecture of a multi-core processor with multiple core groups provided for an exemplary embodiment of the present invention;

[0055] Fig. 9 A schematic diagram of an architecture with an addressing controller is provided for an exemplary embodiment of the present invention.

[0056] Among them, the figure marks include: 10-processor, 12-core, 121-cache module, 122-instruction decoding unit, 123-cluster, 124-floating point operation unit, 125-core interface unit, 126-second-level cache, 14-system interface unit, 16-peripheral controller, 18-third-level cache, 30-JTAG microcode unit, 32-JTAG microcode interface, 322-interface socket, 324-data cache unit, 326-cyclic redundancy check unit, 34-processing module, 342-microcode parser, 344-storage manager, 346-data transfer controller, 40-proximal device, 42-JTAG connector. DETAILED DESCRIPTION

[0057] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0058] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, device, product or equipment that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0059] In one embodiment of the present invention, a multi-core processor suitable for external microcode loading is provided. Figure 1, the multi-core processor includes a plurality of cores, a system interface unit and a JTAG microcode unit, the plurality of cores are electrically connected to the system interface unit respectively, the plurality of cores are further configured to be electrically connected to a peripheral controller through the system interface unit, the system interface unit is electrically connected to the JTAG microcode unit, the JTAG microcode unit is configured to be electrically connected to an external microcode transmission device, and is configured to receive data transmitted thereto by the external microcode transmission device;

[0060] The JTAG microcode unit includes a data cache unit, the data cache unit includes a first cache area and a second cache area, and the cache speed of the first cache area is greater than the cache speed of the second cache area;

[0061] The JTAG microcode unit is configured to receive the first type of data transmitted thereto by the external microcode transmission device and store the first type of data in the first cache area, and transmit the first type of data cached in the first cache area to one or more of the plurality of cores through the system interface unit;

[0062] The JTAG microcode unit receives the second type of data transmitted to it by the external microcode transmission device and stores it in the second cache area. When the amount of the second type of data cached in the second cache area reaches a preset data amount threshold, the second type of data cached in the second cache area is transmitted to one or more of the plurality of peripheral controllers through the system interface unit.

[0063] In one embodiment of the present invention, Figures 1 to 6 As shown, the processor 10 has multiple cores 12, a system interface unit 14, a memory and peripheral controller 16, a JTAG microcode unit 30, and a three-level cache 18. Specifically, the multiple cores 12 include core 12a, core 12b, core 12c, and core 12d. The multiple cores are directly or indirectly coupled to a system memory 20, and each of the cores can be configured to execute instructions that can be stored in the system memory 20. The definition of the instructions can be based on a specific instruction set architecture (ISA). For example, the core can be configured as a version of the x86 ISA, but in other specific embodiments, the core 12a, core 12b, core 12c, and core 12d can be different ISA versions or a combination of several ISAs.

[0064] like Figure 1 and Figure 2As shown, the core 12a, core 12b, core 12c and core 12d of the processor 10 are used to electrically connect / couple to a system interface unit 14. Through the system interface unit 14, the plurality of cores are electrically connected to a memory and peripheral controller 16, and the memory and peripheral controller 16 can be electrically connected / coupled to one or more peripheral devices 22. The peripheral controller 16 controls the corresponding peripheral devices 22 to work. In addition, the plurality of cores are electrically connected / coupled to a level 3 cache (L3 cache) 18 through the system interface unit 14, and the plurality of cores are also electrically connected / coupled to the JTAG microcode unit 30 through the system interface unit 14. The above-mentioned electrical connection / coupling includes but is not limited to electrical connection using appropriate metal conductive wires / layers.

[0065] In the embodiment of the present invention, the cores 12a, 12b, 12c and 12d in the processor 10 are internally configured with a level 1 cache (L1 cache) and a level 2 cache (L2 cache). The peripheral device 22 includes a graphics device or a bus.

[0066] Preferably, the cores of the processor 10 have local microcode units to support microcoded operations. Generally speaking, microcode may include an implementation technology derived from the control and data storage of the processor 10 and given individual operations performed by each of the cores. For example, the x86 ISA version of the core 12a, core 12b, core 12c and core 12d may include the execution of instructions, as well as reset functions, interrupt / trap / exception functions, etc.

[0067] Additionally, microcode may be used to include a sequence of operations that place the cores 12a, 12b, 12c, and 12d in a consistent operating state after a software or hardware reset event, for example, by initializing caches, storing specific values ​​in specific architectural and non-architectural registers, causing instruction fetches to begin at a predetermined address, etc. Microcode may also be used to implement hardware testing or debugging routines for use during product manufacturing, field analysis, power-on self-test, or for other suitable applications.

[0068] Second, some instructions in the ISA can be mapped directly to individual corresponding operations. In some embodiments, microcode can be used to convert a given complex instruction into a sequence of simpler and dispatchable operations for execution, so that the operations that can be used with microcode include operations that correspond to directly executable ISA instructions. However, in some embodiments, microcode operations can also include operations that can be performed by the execution unit but are invisible to the programmer.

[0069] Figure 3The architecture of the core 12a is provided, such as Figure 3 As shown, the core 12a includes a cache module 121, an instruction decoding unit 122, a cluster (integer execution cluster) 123, a floating point unit (floating point unit) 124, a core interface unit 125, a first-level cache (not shown in the figure) and a second-level cache 126. The cache module 121 is electrically connected / coupled to the instruction decoding unit 122, and the instruction decoding unit 122 is electrically connected to the cluster (integer execution cluster) 123 and the floating point unit (floating point unit) 124 respectively. The cluster (integer execution cluster) 123 and the floating point unit (floating point unit) 124 are electrically connected / coupled to the core interface unit 125, and the core interface unit 125 is electrically connected to the first-level cache, the second-level cache 126 and the system interface unit 14 respectively. As for the other cores, such as the core 12b, the core 12c and the core 12d, the structures may be the same as the structure of the core 12a, so they will not be repeated.

[0070] In this embodiment, the cache module 121 may include an instruction cache and be coupled to provide instructions to an instruction fetch unit. The designated fetch unit may be coupled to a branch prediction unit, wherein the instruction cache unit of the cache module 121 may be electrically connected / coupled to the instruction decoding unit 122.

[0071] The instruction decoding unit 122 may provide a plurality of operations to the cluster 123 and the floating point operation unit 124. The cluster 123 may include a coupled cluster scheduler and an execution unit. The floating point operation unit 124 may include a coupled floating point scheduler and a floating point execution unit.

[0072] In this embodiment, the JTAG microcode unit 30 is electrically connected to / coupled to the system interface unit 14. The JTAG microcode unit 30 is used to receive external data and programs. In particular, the JTAG microcode unit 30 can microcode the external data and programs and transmit them to one or more of the plurality of cores 12 through the system interface unit 14.

[0073] like Figure 4The JTAG microcode unit includes an electrically connected processing module and a JTAG microcode interface. The JTAG microcode interface receives external data and programs through a JTAG connector and transmits them to the processing module, and the processing module transmits the received data to the core 12 or the peripheral controller or the corresponding storage unit through the system interface unit. The processing module 34 is electrically connected / coupled to the system interface unit 14. The processing module 34 is used to microcode the external data and programs.

[0074] Further, see Figure 5 The JTAG microcode interface includes an interface socket 322, a data cache unit 324, and a cyclic redundancy check unit 326 that are electrically connected in sequence. The interface socket 322 is used to connect to a JTAG connector 42 of a proximal device 40, and the proximal device 40 can be a storage device. For example, the JTAG connector 42 can be used to directly couple the JTAG microcode interface 32 through the interface socket 322. External microcode information, external data and / or programs can be input into the data cache unit 324 of the JTAG microcode unit 30 through the JTAG connector 42.

[0075] As described above, the data buffer unit 324 has a multi-layer cache structure, including a high-speed cache area, namely the first cache area, and a medium-speed buffer area, namely the second cache area, wherein the high-speed cache area is specifically used to store microcode to be transmitted to the core, and the medium-speed buffer area is used to store batch received data. By setting the data buffer unit as a high-speed and medium-speed multi-layer cache structure, the adverse effects of the relatively low JTAG transmission rate can be reduced and the microcode transmission efficiency can be improved. Because of this structure, on the one hand, the data required by the core can be transmitted to the core in a timely manner, and on the other hand, the data required by the peripheral controller can be transmitted to the high-speed execution unit at one time when the data accumulates to a sufficient amount of data, thereby reducing the execution delay caused by the slow transmission rate.

[0076] The data buffer unit 324 is electrically connected to the cyclic redundancy check (CRC) unit 326. The cyclic redundancy check unit 326 can be composed of a combination of a shift register and an XOR logic circuit, which is configured to verify the integrity of the data received by the data buffer unit. Only the data verified by the cyclic redundancy check unit will be further transmitted to the processing module 34 to avoid incomplete data being transmitted to the back end, causing processor operation errors, crashes, etc., to ensure that the completed microcode is successfully loaded into the processor.

[0077] The processing module 34 is configured to receive data verified to be complete via the cyclic redundancy check unit 326, parse and process the data to obtain microcode data and control the transmission and storage of the microcode data, including converting the received data into a microcode format suitable for storage or execution and determining the further transmission direction of the data in the microcode format.

[0078] See also Figure 6 The processing module 34 includes a microcode parser 342, a storage manager 344 and a data transmission controller 346 which are electrically connected in sequence. The microcode parser 342 is electrically connected to the output end of the cyclic redundancy check unit 326, and the microcode parser 342 is used to receive instructions and / or data from the cyclic redundancy check unit 326. The microcode parser 342 includes a combination of a data parser and a compiler, wherein the data parser is used to parse external data and programs into microcode instruction formats to obtain microcode data. The compiler is used to classify microcode data and microcode.

[0079] The data types include a first type and a second type, wherein the first type of data corresponds to data to be transmitted to the core, and the second type of data corresponds to data to be transmitted to the peripheral controller. Since the data buffer unit 324 is configured with the first high-speed cache area and the second medium-speed cache area, the data from the first cache area can be quickly configured as the first type of data through addressing, and the data from the second cache area can be configured as the second type of data.

[0080] In addition, the compiler is also configured to determine the priority of the first type of data and the second type of data according to the length of the microcode data and historical usage records, for example, to determine whether the microcode data is commonly used data or infrequently used data according to the historical usage frequency of the microcode data, and configure the priority of commonly used data to be higher than that of infrequently used data; to determine whether the microcode data is long instruction data or short instruction data according to the length of the microcode data, and configure the priority of short instruction data to be higher than that of long instruction data, so as to facilitate the subsequent formation of storage decisions for execution by the appropriate processor core.

[0081] The storage manager 344 is responsible for managing the storage location and storage strategy of the microcode data / microcode, and can decide to store the microcode in a local cache, a remote storage unit, or other storage areas. Specifically, the storage manager is configured to configure a storage address for the microcode data according to the data type, the storage address corresponding to the first type of data is one or more of the addresses corresponding to the multiple cores, and the storage address corresponding to the second type of data is one or more of the addresses corresponding to the multiple peripheral controllers.

[0082] The storage manager 344 includes a cache control unit, a data scheduling unit and a storage allocation unit, and the cache control unit, the storage allocation unit and the data scheduling unit are directly and / or indirectly electrically connected. The cache control unit is used to manage the cache process of the microcode data, including improving the speed of data access; the storage allocation unit is used to dynamically determine the storage location of the microcode according to the type, frequency of use and priority of the microcode; the data scheduling unit is used to coordinate the transmission order and priority of the microcode data to ensure that the key microcode is loaded first.

[0083] The data transfer controller 346 is responsible for transmitting the processed microcode data to the system interface unit 14 and then to the target core, including controlling the transmission of the microcode data to the target location according to the storage address, and the target location includes the core and the peripheral controller.

[0084] The data transmission controller 346 includes a bus control unit and a priority management unit. The bus control unit is used to control the transmission of microcode data on the system bus; the priority management unit is electrically connected to the bus control unit and is configured to dynamically adjust the order of data transmission according to the urgency and importance of the task. For example, the priority management unit assigns different microcode tasks to multiple execution units or hardware accelerators for execution, and then transmits them to the system interface unit 14.

[0085] According to the above multi-core processor suitable for external microcode loading, the external microcode can be transmitted to the designated core or peripheral controller through the JTAG microcode interface 32 of the JTAG microcode unit 30 and the processing module 34. Further, through the processor architecture provided by the present invention, the JTAG microcode unit 30 can more efficiently receive and process external data and convert it into microcode suitable for execution by the core of the processor.

[0086] In this embodiment, the process of loading the external microcode program into the multi-core processor is as follows: Figure 7 As shown, the following steps are included.

[0087] A proximal device with a JTAG connector is connected to the JTAG interface, and the proximal device is configured to transmit an external microcode to the JTAG interface. It is worth noting that the external microcode includes but is not limited to data and programs, such as control data corresponding to an external device, or control instructions for modifying the external device. For example, the multi-core processor can be applied to a car's onboard computer, and the external device can be the corresponding lights, navigation system, transmission and braking system of the car.

[0088] Execution data buffering: temporarily storing microcode data by setting up a multi-level buffer. Specifically, the data cache unit with a multi-layer cache structure is used to temporarily store the microcode data received through the JTAG interface to cope with the inconsistency and delay of the data transmission rate, thereby using the data buffer to help the microcode reception and transmission process to be smoother and avoid the degradation of system performance due to the sudden change of the data rate. It includes receiving the first type of data transmitted to it by the external microcode transmission device, i.e., the proximal transposition, and storing it in the first cache area, and receiving the second type of data transmitted to it by the external microcode transmission device and storing it in the second cache area.

[0089] Data parsing and verification: The received microcode data is parsed to confirm the integrity and format of the data. It can also decide how to process the received microcode based on information such as data type and length, and parse the data into microcode instructions or other control signals, and prepare to transmit them to the target. Since the external devices corresponding to the external microcode data and programs are different, and different external devices can be designated to be controlled by one core, data parsing and verification can be used to determine the core corresponding to the external data and program based on the information content and / or preset parameters contained in the input external data and program.

[0090] Instruction scheduling and allocation: The external microcode that has passed data parsing and verification is allocated to multiple execution units or hardware accelerators, so that the microcode that needs to be accessed immediately can be loaded and stored first through a priority scheduling mechanism. Furthermore, the selection of the storage path can be based on the classification result of the microcode and in conjunction with a certain order logic / priority, and the order logic supports a dynamic allocation strategy to optimize storage resources and access speed.

[0091] Data transmission: The parsed and scheduled microcode data is transmitted to the corresponding core or peripheral controller and other target processing units. More specifically, the bus control unit and the transmission priority management unit can control the data transmission path and rate, and ensure that the data arrives at the destination in order and correctly.

[0092] As described above, the various components of the JTAG microcode unit can work together effectively to achieve an efficient and reliable processing process from external input microcode to internal storage, and through the architectural design of the multi-core processor disclosed in this embodiment, it can be ensured that the processor's microcode management has high flexibility and scalability while meeting security and performance requirements.

[0093] The present invention can cooperate with a hierarchical addressing scheme to improve efficient data transmission, flexible address mapping and reliable data processing in a multi-core environment while ensuring security and data consistency.

[0094] See also Figure 8 The cores in the processor 10 form a group, and the cores are divided into four groups, namely G0, G1, G2 and G3, and the number of cores in each group is equal. The JTAG microcode unit 30 is electrically coupled to each group (G0, G1, G2 and G3), and each core in each group can be electrically coupled to the JTAG microcode unit 30.

[0095] See also Fig. 9 In order to implement the hierarchical addressing mode, the processing module 34 also includes an addressing controller 348, the input end of the addressing controller 348 is electrically connected to the output end of the JTAG microcode interface 32, and the output end of the controller 348 is electrically connected to the input end of the microcode parser 342.

[0096] The addressing controller 348 includes an addressing unit and a hierarchical address mapping table. The addressing unit is responsible for processing and managing address resolution and address translation, and the hierarchical address mapping table is usually a multi-level structure organization, which can be composed of multi-level page tables, segment tables, TLBs and other caches, and is used to store and manage the mapping relationship between logical addresses and physical addresses.

[0097] When any external microcode data is input through the JTAG microcode unit 30, the external microcode can be transmitted to the corresponding group designated core, and the external microcode is transmitted to the memory location designated by the core, for example, the microcode is loaded into the FF00 location of the flash memory (FLASH MEMORY). Secondly, the memory is any form of memory electrically coupled to the core. Since the external microcode of this embodiment is transmitted in a manner of first locating to the group and then to the core, and finally to the designated memory location, a multi-level addressing method is formed.

[0098] According to the implementation of the embodiment of the present invention, external data and programs can be quickly transmitted to the corresponding core of the processor 10 through the proximal physical connection provided by the Joint Test Group (JTAG) microcode unit 30, thereby reducing the risk of malicious intrusion and loading of backdoor programs, and the process of external data and program loading can be separately and directly transmitted to the corresponding core or the corresponding external controller, which has the effect of reducing the time required for data and program loading and updating.

[0099] In one embodiment of the present invention, a computer system is provided, comprising a multi-core processor suitable for external microcode loading as described in any one embodiment or a combination of multiple embodiments.

[0100] In one embodiment of the present invention, a method for loading an external microcode for a multi-core processor is provided, which is applied to the multi-core processor for loading an external microcode as described in any one of the above embodiments or a combination of multiple embodiments, and the method comprises the following steps:

[0101] The JTAG microcode unit receives data transmitted to it by an external microcode transmission device, and if the data is first type data, stores the first type data in a first buffer area of ​​the data buffer unit; if the data is second type data, stores the second type data in a second buffer area of ​​the data buffer unit;

[0102] transmitting the first type of data cached in the first cache area to one or more of the plurality of cores through the system interface unit;

[0103] When the amount of the second type of data cached in the second cache area reaches a preset data amount threshold, the second type of data cached in the second cache area is transmitted to one or more of the plurality of peripheral controllers through the system interface unit.

[0104] It should be noted that the computer system and the external microcode loading method suitable for a multi-core processor provided by the present invention are the same as the inventive concept of the above-mentioned multi-core processor embodiment suitable for external microcode loading, and all the contents of the multi-core processor embodiment suitable for external microcode loading are incorporated into the computer system and the external microcode loading method embodiment suitable for a multi-core processor by introduction.

[0105] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0106] The above is only a specific implementation of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A multi-core processor suitable for external microcode loading, characterized in that: The system comprises a plurality of cores, a system interface unit and a JTAG microcode unit, wherein the plurality of cores are electrically connected to the system interface unit respectively, and the plurality of cores are also configured to be electrically connected to a peripheral controller through the system interface unit, the system interface unit is electrically connected to the JTAG microcode unit, and the JTAG microcode unit is configured to be electrically connected to an external microcode transmission device, and is configured to receive data transmitted thereto by the external microcode transmission device; The JTAG microcode unit includes a data cache unit, the data cache unit includes a first cache area and a second cache area, and the cache speed of the first cache area is greater than the cache speed of the second cache area; The JTAG microcode unit is configured to receive the first type of data transmitted thereto by the external microcode transmission device and store the first type of data in the first cache area, and transmit the first type of data cached in the first cache area to one or more of the plurality of cores through the system interface unit; The JTAG microcode unit receives the second type of data transmitted to it by the external microcode transmission device and stores it in the second cache area. When the amount of the second type of data cached in the second cache area reaches a preset data amount threshold, the second type of data cached in the second cache area is transmitted to one or more of the plurality of peripheral controllers through the system interface unit.

2. The multi-core processor suitable for external microcode loading according to claim 1, characterized in that: The JTAG microcode unit includes an electrically connected processing module and a JTAG microcode interface; The JTAG microcode interface includes the data cache unit and a cyclic redundancy check unit, wherein the cyclic redundancy check unit is electrically connected to the data cache unit and is configured to verify the integrity of data received by the data cache unit; The processing module is electrically connected to the cyclic redundancy check unit, and is configured to receive data verified to be complete by the cyclic redundancy check unit, parse the data to obtain microcode data, and control the transmission and storage of the microcode data.

3. The multi-core processor suitable for external microcode loading according to claim 2, characterized in that: The processing module includes a microcode parser, a storage manager and a data transfer controller electrically connected in sequence; The microcode parser is electrically connected to the cyclic redundancy check unit, and the microcode parser includes an electrically connected data parser and a compiler, the data parser is configured to parse the data from the cyclic redundancy check unit to obtain microcode data, and the compiler is configured to classify the microcode data to configure a corresponding data type for the microcode data, the data type includes a first type and a second type, the data type of the first type data is the first type, and the data type of the second type data is the second type; The storage manager is configured to configure a storage address for the microcode data according to the data type, the storage address corresponding to the first type of data is one or more of the addresses corresponding to the plurality of cores, and the storage address corresponding to the second type of data is one or more of the plurality of peripheral controllers; The data transfer controller is electrically connected to the system interface unit, and is configured to control the order in which the microcode data is transmitted to the target storage address through the system interface unit according to the storage address, and the target location includes the core and the peripheral controller.

4. The multi-core processor suitable for external microcode loading according to claim 3, characterized in that: The microcode parser is further configured to determine the priority of the first type of data and the priority of the second type of data according to the length of the microcode data and the historical usage record; The storage manager is further configured to configure a corresponding storage address for the first type of data according to a priority of the first type of data, and to configure a corresponding storage address for the second type of data according to a priority of the second type of data; The data transmission controller is configured to determine an order of first type data transmission according to a priority of the first type data, and to determine an order of second type data transmission according to a priority of the second type data.

5. The multi-core processor suitable for external microcode loading according to claim 4, characterized in that: The core includes a first-level cache and a second-level cache. The storage address configured by the storage manager for the first type of data with a high priority corresponds to the address of the first-level cache, and the storage address configured by the storage manager for the first type of data with a low priority corresponds to the address of the second-level cache.

6. The multi-core processor suitable for external microcode loading according to claim 5, characterized in that: The data transfer controller is configured to determine the order in which the microcode data is transmitted through the system interface unit according to the data type and priority of the microcode data, including: The transmission order of the first type of data takes precedence over the transmission order of the second type of data; The transmission order of the first type data with a higher priority takes precedence over the transmission order of the first type data with a lower priority.

7. The multi-core processor suitable for external microcode loading according to claim 6, characterized in that: The processing module further comprises an addressing controller, an input end of the addressing controller is electrically connected to an output end of the JTAG microcode interface, and an output end of the addressing controller is electrically connected to an input end of the microcode parser; The addressing controller includes an addressing unit and a hierarchical address mapping table. The addressing unit is configured to process and manage address resolution and address conversion. The hierarchical address mapping table is configured to store and manage a mapping relationship from a logical address to a physical address.

8. The multi-core processor suitable for external microcode loading according to claim 7, characterized in that: The processor includes a plurality of core groups, each core group includes a plurality of cores, each core group is configured with a unique group address, and each core is configured with a unique core address; The group address and the core address are stored in the hierarchical address mapping table, and the addressing controller is configured to hierarchically determine the storage address corresponding to the microcode data according to the group address and the core address.

9. The multi-core processor suitable for external microcode loading according to claim 2, characterized in that: The cyclic redundancy check unit includes a shift register and an XOR logic circuit which are electrically connected.

10. The multi-core processor suitable for external microcode loading according to claim 1, characterized in that: The JTAG microcode unit further includes a JTAG interface, an input end of the JTAG interface is configured to be electrically connected to the external microcode transmission device, and an output end of the JTAG interface is electrically connected to an input end of the data cache unit.

11. The multi-core processor suitable for external microcode loading according to claim 1, characterized in that: The core has a corresponding relationship with the external microcode transmission device; and / or, It also includes a third-level cache, which is electrically connected to the system interface unit and configured as a memory of the peripheral controller.

12. A computer system, characterized in that: It comprises a multi-core processor suitable for external microcode loading as described in any one of claims 1-11.

13. A method for loading external microcode for a multi-core processor, characterized in that: Applied to a multi-core processor suitable for external microcode loading as claimed in any one of claims 1 to 11, the method comprises the following steps: The JTAG microcode unit receives data transmitted to it by an external microcode transmission device, and if the data is first type data, stores the first type data in a first buffer area of ​​the data buffer unit; if the data is second type data, stores the second type data in a second buffer area of ​​the data buffer unit; transmitting the first type of data cached in the first cache area to one or more of the plurality of cores through the system interface unit; When the amount of the second type of data cached in the second cache area reaches a preset data amount threshold, the second type of data cached in the second cache area is transmitted to one or more of the plurality of peripheral controllers through the system interface unit.

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