A method and system for implementing MIPID-PHY low-speed mode readback based on FPGA

Abstract

The present application discloses a method and system for implementing MIPID-PHY low-speed mode readback based on FPGA, realizing data transmission and reception between FPGA chip and TCON IC unit in low-speed mode. It includes: FPGA chip sends data to TCON IC unit, FPGA chip switches to transmission mode, and sends data to TCON IC unit through transmission differential pair of FPGA chip and high-speed RF switch unit; in low-speed mode, FPGA chip reads back target data from TCON IC unit, FPGA chip switches to reception mode, and the data channel of high-speed RF switch switches to the dedicated reception path from TCON IC unit to FPGA chip; TCON IC unit sends target data to FPGA chip through dedicated reception path and reception differential pair of FPGA chip, and FPGA chip receives target data to complete the readback operation.

Description

Technical Field

[0001] The present application relates to the technical field of mura defect detection, and in particular to a method and system for implementing MIPID-PHY low-speed mode readback based on FPGA. Background Art

[0002] In the field of panel detection, MIPID-PHY protocol, as an important communication interface standard, is widely used in the data transmission process. This protocol not only supports synchronous data transmission in high-speed mode (HS), but also has asynchronous data transmission capabilities in low-speed mode (LP). However, many FPGA devices on the market currently have functional limitations when supporting MIPID-PHY protocol.

[0003] That is, these FPGA devices can support data transmission in high-speed mode (HS) and low-speed mode (LP) of the MIPID-PHY protocol, but cannot implement data readback function in low-speed mode (LP). Since the functions of FPGA devices in MIPID-PHY protocol applications are not comprehensive, the display panel industry faces a narrow selection problem when selecting FPGA devices, and the development is difficult and costly, which cannot meet the needs of the panel industry. Summary of the invention

[0004] The present application provides a method and system for implementing MIPID-PHY low-speed mode readback based on FPGA, which solves the problem that FPGA does not support two-way data communication in low-speed mode and realizes data transmission and reception between FPGA chip and TCON IC unit in low-speed mode.

[0005] In a first aspect, the present application provides a method for implementing MIPID-PHY low-speed mode readback based on FPGA, the method is applied to a readback system, the readback system includes: an FPGA chip, a high-speed RF switch unit and a TCON IC unit, the method includes:

[0006] When the FPGA chip sends data to the TCON IC unit, the FPGA chip switches to a sending mode, and sends the data to the TCON IC unit through the sending differential pair of the FPGA chip and the high-speed RF switch unit;

[0007] In the low-speed mode, when the FPGA chip reads back the target data from the TCON IC unit, the FPGA chip switches to the receiving mode, and the data channel of the high-speed RF switch switches to the dedicated receiving path from the TCON IC unit to the FPGA chip;

[0008] The TCON IC unit sends the target data to the FPGA chip through the dedicated receiving path and the receiving differential pair of the FPGA chip, so that the FPGA chip receives the target data and completes the read-back operation.

[0009] Optionally, the FPGA chip is provided with a transmitting differential pair and a receiving differential pair, the transmitting differential pair is used for data transmission in high-speed mode and low-speed mode, and the receiving differential pair is used for data reception in low-speed mode.

[0010] Optionally, the high-speed RF switch unit is provided with a group of CLK differential pairs and four groups of Data differential pairs.

[0011] Optionally, the high-speed RF switch unit is integrated between the FPGA chip and the TCON IC unit.

[0012] Optionally, the TCON IC unit supports data reception in high-speed mode and data transmission or data reception in low-speed mode.

[0013] Optionally, before sending the data to the TCON IC unit through the transmission differential pair of the FPGA chip and the high-speed RF switch unit, the method further includes:

[0014] The transmit differential pair of the FPGA chip is turned on, and the receive differential pair of the FPGA chip is turned off.

[0015] Optionally, before the TCON IC unit sends the target data to the FPGA chip through the dedicated receiving path and the receiving differential pair of the FPGA chip, the method further includes:

[0016] The receiving differential pair of the FPGA chip is turned on, and the transmitting differential pair of the FPGA chip is turned on.

[0017] Optionally, when the FPGA chip sends data to the TCON IC unit, the FPGA chip is switched to a sending mode, and the multiple groups of data are sent to the TCON IC unit through a sending differential pair of the FPGA chip and the high-speed RF switch unit, including:

[0018] In high-speed mode, when the FPGA chip sends multiple groups of data to the TCON IC unit, the FPGA chip is switched to a sending mode, and the data is sent to the TCON IC unit through the sending differential pair of the FPGA chip and the differential pair of the high-speed RF switch unit.

[0019] Optionally, when the FPGA chip sends data to the TCON IC unit, the FPGA chip is switched to a sending mode, and the data is sent to the TCON IC unit through a sending differential pair of the FPGA chip and the high-speed RF switch unit, including:

[0020] In low-speed mode, when the FPGA chip sends multiple groups of data to the TCON IC unit, the FPGA chip is switched to a sending mode, and the first group of data among the multiple groups of data is sent to the TCON IC unit through the sending differential pair of the FPGA chip and the differential pair of the high-speed RF switch unit.

[0021] A second aspect of the present application provides a system for implementing MIPID-PHY low-speed mode readback based on FPGA, the system comprising: an FPGA chip, a high-speed RF switch unit and a TCON IC unit;

[0022] The FPGA chip is used to switch to a sending mode when sending data to the TCON IC unit, and send the data to the TCON IC unit through a sending differential pair and the high-speed RF switch unit;

[0023] The FPGA chip is used to switch to a receiving mode when reading back target data from the TCON IC unit in a low-speed mode;

[0024] The high-speed RF switch is used to switch the data channel to a dedicated receiving path from the TCON IC unit to the FPGA chip;

[0025] The TCON IC unit is used to send the target data to the FPGA chip through the dedicated receiving path and the receiving differential pair of the FPGA chip, so that the FPGA chip receives the target data and completes the readback operation.

[0026] A third aspect of the present application provides a device for implementing MIPID-PHY low-speed mode readback based on FPGA, the device comprising:

[0027] processor, memory, input-output unit, and bus;

[0028] The processor is connected to the storage, the input and output unit, and the bus;

[0029] The storage stores a program, and the processor calls the program to execute the first aspect and any optional method in the first aspect.

[0030] A fourth aspect of the present application provides a computer-readable storage medium, on which a program is stored. When the program is executed on a computer, the program executes the first aspect and any optional method in the first aspect.

[0031] It can be seen from the above technical solutions that this application has the following advantages:

[0032] (1) This application can flexibly configure the sending and receiving modes to adapt to different communication needs, so that it can easily cope with various complex scenarios and improve the overall adaptability and reliability.

[0033] (2) By integrating a high-speed RF switch unit, it is able to quickly switch between transmit and receive modes.

[0034] (3) In low-speed mode, data is transmitted from the TCON IC unit to the FPGA chip through a dedicated receiving path, ensuring accurate reception and readback of data, effectively avoiding data loss or errors during transmission, and improving the reliability and stability of communication.

[0035] (4) Through the coordinated work of FPGA chip, high-speed RF switch unit and TCON IC unit, bidirectional data transmission is achieved without the need for additional data processing or conversion equipment, thus reducing costs.

[0036] (5) Solve the problem that FPGA does not support two-way data communication in low-speed mode, and realize data sending and receiving between FPGA chip and TCON IC unit in low-speed mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solution in the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0038] Figure 1 This is a flow chart of an embodiment of a method for implementing MIPID-PHY low-speed mode readback based on FPGA in this application;

[0039] Figure 2 A schematic diagram of an embodiment of a system for implementing MIPID-PHY low-speed mode readback based on FPGA in the present application;

[0040] Figure 3 A schematic diagram of an embodiment of a device for implementing MIPID-PHY low-speed mode readback based on FPGA in the present application;

[0041] Figure 4This is a schematic diagram of the implementation method of the MIPID-PHY low-speed mode readback method based on FPGA in this application;

[0042] Figure 5 It is a schematic diagram of data transmission and data reception of FPGA chip;

[0043] Figure 6 It is a structural schematic diagram of a high-speed radio frequency switch unit;

[0044] Figure 7 This is a schematic diagram of the FPGA chip sending data to the TCON IC unit in high-speed mode;

[0045] Figure 8 This is a schematic diagram of the FPGA chip sending data to the TCON IC unit in low-speed mode;

[0046] Fig. 9 This is a schematic diagram of the FPGA chip reading back data from the TCON IC unit in low-speed mode. DETAILED DESCRIPTION

[0047] The present application provides a method and system for implementing MIPID-PHY low-speed mode readback based on FPGA, which solves the problem that FPGA does not support two-way data communication in low-speed mode and realizes data transmission and reception between FPGA chip and TCON IC unit in low-speed mode.

[0048] See also Figure 1 In a first aspect, the present application provides an embodiment of a method for implementing MIPID-PHY low-speed mode readback based on FPGA, wherein the method is applied to a readback system, the readback system comprising: an FPGA chip, a high-speed RF switch unit and a TCON IC unit, a high-speed RF switch unit is integrated between the FPGA chip and the TCON IC unit, and the method comprises:

[0049] 101. When the FPGA chip sends data to the TCON IC unit, the FPGA chip switches to a sending mode, and sends the data to the TCON IC unit through the sending differential pair of the FPGA chip and the high-speed RF switch unit;

[0050] 102. In the low-speed mode, when the FPGA chip reads back the target data from the TCON IC unit, the FPGA chip switches to the receiving mode, and the data channel of the high-speed RF switch switches to the dedicated receiving path from the TCON IC unit to the FPGA chip;

[0051] 103. The TCON IC unit sends the target data to the FPGA chip through the dedicated receiving path and the receiving differential pair of the FPGA chip, so that the FPGA chip receives the target data and completes a read-back operation.

[0052] In an embodiment of the present application, when the FPGA chip sends data to the TCON IC unit, the FPGA chip switches to the sending mode, and sends the data to the TCON IC unit through the sending differential pair of the FPGA chip and the high-speed RF switch unit; after the FPGA chip sends data to the TCON IC unit, in the low-speed mode, when the FPGA chip reads back the target data from the TCON IC unit, the FPGA chip switches to the receiving mode, and the data channel of the high-speed RF switch is switched to the dedicated receiving path from the TCON IC unit to the FPGA chip. The TCON IC unit sends the target data to the FPGA chip through the dedicated receiving path and the receiving differential pair of the FPGA chip, so that the FPGA chip receives the target data and completes the readback operation.

[0053] In step 101, the FPGA chip sends data to the TCON IC unit. Before executing the sending operation, the FPGA chip first needs to switch to the sending mode to ensure that the data can be correctly output from the sending port of the FPGA chip through the configuration of the internal logic of the FPGA chip.

[0054] The FPGA chip outputs data through its differential pair. The high-speed RF switch unit plays the role of path selection in the whole process. The high-speed RF switch unit connects the output of the FPGA chip to the input of the TCON IC unit according to the control signal. After the path is established, the FPGA chip starts to send data to the TCON IC unit. The transmitted data may include control instructions, configuration information, or any data that the TCON IC unit needs to process. The data transmitted is not specifically limited here and can be set according to actual conditions.

[0055] In step 102, in low speed mode, the FPGA chip reads back the target data from the TCON IC unit.

[0056] When data needs to be read back from the TCON IC unit, the FPGA chip first switches to the receiving mode, and the internal logic of the FPGA chip is reconfigured to ensure that the data from the TCON IC unit can be correctly received.

[0057] The data channel of the high-speed RF switch unit needs to be switched to the dedicated receiving path from the TCON IC unit to the FPGA chip according to the control signal. The purpose of this step is to ensure that the data can be transmitted from the TCON IC unit to the FPGA chip without error.

[0058] The data transmission speed in the low-speed mode is relatively low to meet the needs of the read-back operation or due to the output rate limitation of the TCONIC unit.

[0059] In step 103, the TCON IC unit sends data to the FPGA chip through a dedicated receiving path. The TCON IC unit supports data reception in high-speed mode and data transmission or data reception in low-speed mode. After receiving the read-back request, the TCON IC unit can send the data back to the FPGA chip through the established dedicated receiving path, that is, the path switched by the high-speed RF switch unit.

[0060] The FPGA chip receives data from the TCON IC unit through its receiving differential pair, which helps reduce noise and interference during signal transmission and improves the accuracy of data reception.

[0061] Once the FPGA chip successfully receives the data, the read-back operation is completed, and the data can then be used by the FPGA chip for further processing, analysis or storage.

[0062] In summary, this solution realizes the sending and reading of data in low-speed mode through the collaborative work of FPGA chip, high-speed RF switch unit and TCON IC unit, effectively solving the problem that FPGA does not support two-way data communication in low-speed mode, and realizes the sending and receiving of data between FPGA chip and TCON IC unit in low-speed mode. For the principle block diagram of the solution, please refer to Figure 4 .

[0063] The FPGA chip is provided with a transmit differential pair and a receive differential pair, the transmit differential pair is used for data transmission in high-speed mode and low-speed mode, and the receive differential pair is used for data reception in low-speed mode. For the schematic diagram of data transmission and data reception of the FPGA chip in high-speed mode and low-speed mode, please refer to Figure 5 .

[0064] In an embodiment of the present application, in high-speed mode, the FPGA chip sends data to the TCON IC unit by sending a differential pair, where the differential pair consists of a pair of signal lines, usually marked as positive (such as TX+) and negative (such as TX-), and the voltage difference between the two represents the data to be transmitted.

[0065] Data transmission in high-speed mode requires the FPGA chip to have a higher clock frequency and data processing capabilities to ensure accurate data transmission. Sending differential pairs helps reduce signal attenuation and interference during transmission and improve signal integrity and reliability.

[0066] In addition to high-speed mode, the transmit differential pair is also used for data transmission in low-speed mode. In low-speed mode, although the data transmission speed is reduced, the requirements for signal quality and stability are not reduced. The transmit differential pair can provide stable signal transmission in low-speed mode to ensure that the data can reach the receiving end accurately. At this time, the FPGA chip will adjust its internal logic and clock settings to adapt to the data transmission requirements in low-speed mode.

[0067] In low-speed mode, the FPGA chip receives data from the TCON IC unit through a receiving differential pair. The receiving differential pair also consists of a pair of signal lines, usually marked as positive (such as RX+) and negative (such as RX-), which are used to capture the differential signal transmitted by the transmitter. The data transmission channel of the FPGA chip is a common channel in high-speed mode and low-speed mode, and is switched through the instruction register inside the FPGA chip.

[0068] In low-speed mode, the FPGA chip accurately identifies and processes the received signal. The receiving differential pair helps to filter out noise and interference, improve the signal-to-noise ratio, and thus ensure accurate data reception.

[0069] It should be noted that the selection of the two differential pairs of the FPGA chip must meet the following conditions:

[0070] 1. Only one pair of the transmitting differential pair and the receiving differential pair works respectively. In the data transmitting mode, the transmitting differential pair works and the receiving differential pair is turned off. In the data receiving mode, the receiving differential pair works and the transmitting differential pair is turned off.

[0071] Specifically, before sending data to the TCON IC unit through the FPGA chip's transmit differential pair and the high-speed RF switch unit, it is necessary to turn on the FPGA chip's transmit differential pair and at the same time turn off the FPGA chip's receive differential pair, thereby satisfying the condition that when the FPGA chip sends data to the TCON IC unit, the transmit differential pair is working and the receive differential pair is turned off.

[0072] Before the TCON IC unit sends the target data to the FPGA chip through the dedicated receiving path and the receiving differential pair of the FPGA chip, it is necessary to turn on the receiving differential pair of the FPGA chip and the transmitting differential pair of the FPGA chip, so as to meet the condition that when the FPGA chip receives data from the TCON IC unit, the receiving differential pair is working and the transmitting differential pair is closed.

[0073] 2. The transmit differential pair and the receive differential pair must be adjacent pins inside the FPGA chip to reduce signal reflection caused by the stub being too long in a certain working state. The reflection calculation conditions are as follows:

[0074]

[0075] Where: L represents the stub length, ZC represents the characteristic impedance, ZI represents the load impedance, and f represents the signal frequency. By changing the stub length L, impedance matching can be achieved, thereby reducing signal reflection.

[0076] Among them, when the FPGA chip sends data to the TCON IC unit, the FPGA chip is switched to the sending mode, and the data is sent to the TCON IC unit through the FPGA chip's sending differential pair and the high-speed RF switch unit. In this process, it can be divided into low-speed mode and high-speed mode. The data transmission from the FPGA chip to the TCON IC unit in low-speed mode and high-speed mode is now explained:

[0077] 1. In high-speed mode, when the FPGA chip sends multiple groups of data to the TCON IC unit, the FPGA chip is switched to the sending mode, and the data is sent to the TCON IC unit through the sending differential pair of the FPGA chip and the differential pair of the high-speed RF switch unit.

[0078] 2. In low-speed mode, when the FPGA chip sends multiple groups of data to the TCON IC unit, the FPGA chip is switched to the sending mode, and the first group of data in the multiple groups of data is sent to the TCON IC unit through the sending differential pair of the FPGA chip and the differential pair of the high-speed RF switch unit.

[0079] The high-speed RF switch unit is provided with a group of CLK differential pairs and four groups of Data differential pairs.

[0080] In the embodiment of the present application, the high-speed RF switch unit is one of the key components in the readback system. The high-speed RF switch unit is responsible for switching the signal path between the FPGA chip and the TCON IC unit to ensure accurate transmission of data in different working modes. The high-speed RF switch unit has the characteristics of high-speed switching capability and low insertion loss, and can meet the needs of high-speed data transmission.

[0081] Among them, the CLK differential pair is a differential pair specially used to transmit clock signals. In high-speed data transmission systems, clock signals are the key to synchronous data transmission. The CLK differential pair transmits stable and accurate clock signals to ensure that data transmission between the FPGA chip and the TCON IC unit can be carried out synchronously. The CLK differential pair adopts a differential transmission method, which can effectively resist common-mode interference and improve the stability and reliability of signal transmission.

[0082] The Data differential pair is a differential pair used to transmit data signals. In the readback system, the FPGA chip and the TCON IC unit need to frequently exchange data, including control instructions, configuration information, and readback target data. The Data differential pair transmits these data signals to ensure that the system can operate normally and achieve the expected functions.

[0083] The high-speed RF switch unit in the present application is provided with four groups of Data differential pairs, that is, the high-speed RF switch unit has the ability to transmit multiple data signals simultaneously, thereby meeting the demand for parallel data transmission and improving the efficiency and speed of data transmission.

[0084] The high-speed RF switch unit is equipped with one CLK differential pair and four Data differential pairs. It is a 2-input 1-output high-speed switch that can ensure that the clock signal and data signal can be transmitted stably and accurately between the FPGA chip and the TCON IC unit. For the structural diagram of the high-speed RF switch unit, please refer to Figure 6 .

[0085] It should be noted that the selection of high-speed RF switch units must meet the following conditions: high bandwidth, which must pass the D-PHY signal of Max2.5G / bps in high-speed mode (HS); low loss; low intra-differential pair delay; low inter-differential pair delay. Only when the above requirements are met, the selection of high-speed RF switch units in this application is met.

[0086] Among them, the TCON IC unit is an internal module of the panel, and the TCON IC unit supports data reception in high-speed mode and data transmission and data reception in low-speed mode.

[0087] See also Figure 2 , the second aspect of the present application provides an embodiment of a system for implementing MIPID-PHY low-speed mode readback based on FPGA, including: an FPGA chip 201, a high-speed RF switch unit 202 and a TCON IC unit 203;

[0088] The FPGA chip 201 is used to switch to a sending mode when sending data to the TCON IC unit 203, and send the data to the TCON IC unit 203 through a sending differential pair and the high-speed RF switch unit;

[0089] The FPGA chip 201 is used to switch to a receiving mode in a low-speed mode when reading back target data from the TCON IC unit 203;

[0090] The high-speed RF switch 202 is used to switch the data channel to a dedicated receiving path from the TCON IC unit 203 to the FPGA chip 201;

[0091] The TCON IC unit 203 is used to send the target data to the FPGA chip 201 through the dedicated receiving path and the receiving differential pair of the FPGA chip 201, so that the FPGA chip 201 receives the target data and completes the read-back operation.

[0092] The interaction process between the FPGA chip and the TCON IC unit is divided into the following situations:

[0093] First: When sending multiple sets of data in high-speed mode, it is necessary to ensure that the data is aligned with the clock. The clock and data of the internal switching unit of the FPGA need to pass through the differential pair of the high-speed RF switch unit, and then interact with the TCON IC unit. For a specific schematic diagram, please refer to Figure 7 .

[0094] Second: In low-speed mode, the FPGA chip only uses the first set of data among multiple sets of data, and exchanges data with the TCON IC unit through the high-speed RF switch unit. For a specific schematic diagram, please refer to Figure 8 .

[0095] In actual applications, when the Sel_CH_0 of the FPGA chip outputs a high level, the RF switch unit is selected to be group A->group COM, and when the Sel_CH_0 of the FPGA chip outputs a low level, the RF switch unit is selected to be group B->group COM. When the TCON_IC unit is used as the transmitter, Sel_CH_0 is set to a low level, the high-speed RF unit is switched to group B->group COM, and the FPGA chip is switched to the data receiving mode, thereby performing low-speed readback from the TCON IC unit to the FPGA chip. For a specific schematic diagram, please refer to Fig. 9 .

[0096] See also Figure 3 , Figure 3 An embodiment of a device for implementing MIPID-PHY low-speed mode readback based on FPGA provided in this application includes:

[0097] Processor 301, memory 302, input and output unit 303 and bus 304;

[0098] The processor 301 is connected to the storage 302, the input and output unit 303 and the bus 304;

[0099] The storage 302 stores a program, and the processor 301 calls the program to execute the first aspect and any optional method in the first aspect.

[0100] The present application also relates to a computer-readable storage medium, on which a program is stored. When the program is run on a computer, the computer executes any of the above optional methods.

[0101] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0102] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0103] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0104] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0105] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, read-only memory), random access memory (RAM, random access memory), disk or optical disk, etc., which can store program code.

Claims

1. A method for implementing MIPID-PHY low-speed mode readback based on FPGA, the method is applied to a readback system, the readback system comprising: FPGA chip, high-speed radio frequency switch unit and TCON IC unit, characterized in that the method includes: When the FPGA chip sends data to the TCON IC unit, the FPGA chip switches to a sending mode, and sends the data to the TCON IC unit through the sending differential pair of the FPGA chip and the high-speed RF switch unit; In the low-speed mode, when the FPGA chip reads back the target data from the TCON IC unit, the FPGA chip switches to the receiving mode, and the data channel of the high-speed RF switch unit switches to the dedicated receiving path from the TCON IC unit to the FPGA chip. The dedicated receiving path is a signal transmission path formed after the high-speed RF switch unit switches the current contact to the target contact when the FPGA chip outputs a low level; The TCON IC unit sends the target data to the FPGA chip through the dedicated receiving path and the receiving differential pair of the FPGA chip, so that the FPGA chip receives the target data and completes the read-back operation.

2. The method for implementing MIPID-PHY low-speed mode readback based on FPGA according to claim 1, characterized in that: The FPGA chip is provided with a transmitting differential pair and a receiving differential pair, the transmitting differential pair is used for data transmission in high-speed mode and low-speed mode, and the receiving differential pair is used for data reception in low-speed mode.

3. The method for implementing MIPID-PHY low-speed mode readback based on FPGA according to claim 1, characterized in that: The high-speed radio frequency switch unit is provided with a group of CLK differential pairs and four groups of Data differential pairs.

4. The method for implementing MIPID-PHY low-speed mode readback based on FPGA according to claim 1, characterized in that: The high-speed radio frequency switch unit is integrated between the FPGA chip and the TCON IC unit.

5. The method for implementing MIPID-PHY low-speed mode readback based on FPGA according to claim 1, characterized in that: The TCON IC unit supports data reception in a high-speed mode and data transmission or data reception in a low-speed mode.

6. The method for implementing MIPID-PHY low-speed mode readback based on FPGA according to claim 2, characterized in that: Before sending the data to the TCONIC unit through the transmission differential pair of the FPGA chip and the high-speed RF switch unit, the method further includes: The transmit differential pair of the FPGA chip is turned on, and the receive differential pair of the FPGA chip is turned off.

7. The method for implementing MIPID-PHY low-speed mode readback based on FPGA according to claim 2, characterized in that: Before the TCON IC unit sends the target data to the FPGA chip through the dedicated receiving path and the receiving differential pair of the FPGA chip, the method further includes: The receiving differential pair of the FPGA chip is turned on, and the transmitting differential pair of the FPGA chip is turned on.

8. The method for implementing MIPID-PHY low-speed mode readback based on FPGA according to claim 1, characterized in that: When the FPGA chip sends data to the TCON IC unit, the FPGA chip switches to a sending mode, and sends the data to the TCON IC unit through a sending differential pair of the FPGA chip and the high-speed RF switch unit, including: In high-speed mode, when the FPGA chip sends multiple groups of data to the TCON IC unit, the FPGA chip is switched to a sending mode, and the multiple groups of data are sent to the TCON IC unit through the sending differential pair of the FPGA chip and the differential pair of the high-speed RF switch unit.

9. The method for implementing MIPID-PHY low-speed mode readback based on FPGA according to claim 1, characterized in that: When the FPGA chip sends data to the TCON IC unit, the FPGA chip is switched to a sending mode, and the data is sent to the TCON IC unit through the sending differential pair of the FPGA chip and the high-speed RF switch unit, including: In low-speed mode, when the FPGA chip sends multiple groups of data to the TCON IC unit, the FPGA chip is switched to a sending mode, and the first group of data among the multiple groups of data is sent to the TCON IC unit through the sending differential pair of the FPGA chip and the differential pair of the high-speed RF switch unit.

10. A system for implementing MIPID-PHY low-speed mode readback based on FPGA, characterized in that: The system includes: an FPGA chip, a high-speed radio frequency switch unit and a TCON IC unit; The FPGA chip is used to switch to a sending mode when sending data to the TCON IC unit, and send the data to the TCON IC unit through a sending differential pair and the high-speed RF switch unit; The FPGA chip is used to switch to a receiving mode when reading back target data from the TCON IC unit in a low-speed mode; The high-speed RF switch unit is used to switch the data channel to a dedicated receiving path from the TCON IC unit to the FPGA chip, and the dedicated receiving path is a signal transmission path formed after the high-speed RF switch unit switches the current contact to the target contact when the FPGA chip outputs a low level; The TCON IC unit is used to send the target data to the FPGA chip through the dedicated receiving path and the receiving differential pair of the FPGA chip, so that the FPGA chip receives the target data and completes the readback operation.

Images