A Method for Real-time Transmission of PCIe Data in a Multi-core Processor

Abstract

The present invention discloses a method for real-time transmission of PCIe data by a multi-core processor. In the present invention, a bare-metal / RTOS application module continuously polls the flag bit of PCIe DMA. Compared with the prior art that responds passively to PCIe DMA interrupts, the continuous polling actively initiated by the bare-metal / RTOS application module of the present invention can identify the transmission status of PCIe DMA faster, more real-time, and more stably, making the time interval for each initiation of PCIe DMA to transfer data relatively stable, thereby improving the real-time performance and stability of PCIe communication and better ensuring the real-time performance of PCIe data transmission. In addition, the present invention abandons the RPMSG framework commonly used for inter-core communication and instead adopts low-level Mailbox interrupt communication. Through Mailbox interrupt communication, the notification of the bare-metal / RTOS application module can be transmitted to the main core more quickly, thereby better ensuring that the main core reads PCIe data in a timely manner.

Description

Technical Field

[0001] The present invention relates to the technical field of PCIe communication, and specifically provides a method for a multi-core processor to transmit PCIe data in real time. Background Art

[0002] PCIe (Peripheral Component Interconnect express) is a high-speed serial computer expansion bus standard used to connect a computer's motherboard and external devices. Its original name was "3GIO", which was proposed by Intel in 2001 to replace the old PCI, PCI-X, and AGP bus standards.

[0003] As Figure 1 shown, in the commonly used PCIe communication framework on the market currently, the multi-core processor SoC includes two cores, Core0 and Core1. This multi-core processor serves as the PCIe RC (Root Complex) end and conducts PCIe data communication with external PCIe EP (Endpoint) devices. The multi-core processor runs an operating system (such as Linux). Generally, an application ( Figure 1 Linux Application1 in it) controls the PCIe DMA to transfer data (transfer PCIe data from the EP device to the memory Memory at the RC end, or transfer it from the memory at the RC end to the EP device), and responds to the interrupt of the PCIe DMA to identify whether the current PCIe data transfer is completed (receiving the interrupt indicates the transfer is completed), and decides the next PCIe DMA data transfer operation by responding to the interrupt. However, due to the numerous tasks of the operating system, the interrupt response may not be timely, resulting in an unstable time interval and large jitter for each initiation of PCIe DMA to transfer data, that is, the real-time performance of PCIe data transfer cannot be guaranteed. Summary of the Invention

[0004] (1) Technical Problems to be Solved

[0005] Aiming at the deficiencies of the prior art, the present invention provides a method for a multi-core processor to transmit PCIe data in real time, which can solve the above technical problems.

[0006] (2) Technical Solutions

[0007] To solve the above technical problems, the present invention provides the following technical solutions: A method for a multi-core processor to transmit PCIe data in real time, including the following steps:

[0008] S1. Isolate the first core and the second core of the multi-core processor to run different systems respectively, where the first core is used to run the first system and the second core is used to run the second system;

[0009] S2. The first application module of the first system controls the PCIe data access module to transmit the current PCIe data with an external PCIe EP device;

[0010] S3. The first application module continuously polls the flag bit of the PCIe data access module to determine whether the PCIe data access module has completed the transmission of the current PCIe data;

[0011] S4. If it is determined that the PCIe data access module has completed the transmission of the current PCIe data, the first application module notifies the second system to read the transmitted PCIe data, and the first application module controls the PCIe data access module to perform the next PCIe data transmission.

[0012] Preferably, the first system is a bare metal or RTOS.

[0013] Preferably, the second system is Linux.

[0014] Preferably, the PCIe data access module is a PCIe DMA.

[0015] Preferably, step S2 is specifically: the first application module sends a data transmission instruction to the PCIe DMA, and after receiving the data transmission instruction, the PCIe DMA further transmits the current PCIe data with the PCIe EP device.

[0016] Preferably, the multi-core processor includes a shared memory, and the transmission of the PCIe data includes: transmitting the PCIe data from the PCIe EP device to the shared memory through the PCIe DMA, or transmitting the PCIe data from the shared memory to the PCIe EP device through the PCIe DMA.

[0017] Preferably, after step S4, there is also step S5: the second application module of the second system reads the PCIe data transmitted to the shared memory this time, and further, the second application module processes the PCIe data.

[0018] Preferably, in step S4, the first application module uses Mailbox interrupt communication to notify the second system to read the transmitted PCIe data.

[0019] Preferably, the PCIe EP device is an FPGA acquisition card or a PCIe hard disk.

[0020] (III) Beneficial effects

[0021] Compared with the prior art, the present invention provides a method for real-time transmission of PCIe data by a multi-core processor, which has the following beneficial effects: The present invention uses a first application module to continuously poll the flag bit of the PCIe data access module. Compared with the prior art that responds passively to PCIe DMA interrupts, the continuous polling actively initiated by the first application module of the present invention can identify the transmission status of the PCIe data access module faster, more real-time, and more stably, making the time interval for each initiation of PCIe data transfer relatively stable, thereby improving the real-time performance and stability of PCIe communication and better ensuring the real-time performance of PCIe data transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 is a schematic block diagram of the principle of PCIe communication in the prior art;

[0023] Figure 2 is a schematic block diagram of a method for real-time transmission of PCIe data by a multi-core processor according to the present invention;

[0024] Figure 3 is a flowchart of a method for real-time transmission of PCIe data by a multi-core processor according to the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0025] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0026] The present invention provides a method for real-time transmission of PCIe data by a multi-core processor, including the following steps:

[0027] S1. Isolate the first core and the second core of the multi-core processor to run different systems respectively. Among them, the first core is used to run the first system, and the second core is used to run the second system. It can be understood that the multi-core processor can be specifically a CPU or a SoC (System on Chip), etc. The multi-core processor includes multiple cores Core, such as Core0, Core1, etc.

[0028] Preferably, the first system is a bare-metal machine or RTOS (bare-metal machine / RTOS): A bare-metal machine, also known as a foreground-background system, directly runs programs in an environment without the support of an operating system (OS); while RTOS (Real Time OS) is a real-time operating system, which means that when external events or data occur, it can accept and process them at a sufficient speed, and the processing results can control the production process or make a quick response to the processing system within the specified time, schedule all available resources to complete real-time tasks, and control all real-time tasks to run in coordination. In addition, the second system can be Linux, and the second system can also be other operating systems such as Windows and Android. The second core can be the main core of a multi-core processor, running the operating system core; while the first core can be a slave core.

[0029] S2. The first application module of the first system controls the PCIe data access module to transfer the current PCIe data with an external PCIe EP device.

[0030] PCIe (Peripheral Component Interconnect express) is a high-speed serial computer expansion bus standard. PCIe devices can be divided into RC (Root Complex) terminals and EP (Endpoint) devices according to their functions and roles; the multi-core processor serves as the RC terminal. Specifically, the PCIe EP device is an FPGA acquisition card or a PCIe hard disk, etc.

[0031] Preferably, the PCIe data access module is PCIe DMA (Direct Memory Access). DMA allows devices to directly exchange data with the system memory, and high-speed transmission of PCIe data can be achieved through PCIe DMA.

[0032] Step S2 is specifically as follows: The first application module sends a data transfer instruction to the PCIe DMA, and after receiving the data transfer instruction, the PCIe DMA further transfers the current PCIe data with the PCIe EP device.

[0033] Specifically, the multi-core processor includes a shared memory (Share memory); the transfer of the above-mentioned PCIe data includes: transferring the PCIe data from the PCIe EP device to the shared memory through the PCIe DMA, or transferring the PCIe data from the shared memory to the PCIe EP device through the PCIe DMA. The first application module is specifically a bare-metal machine application module or an RTOS application module (i.e., a bare-metal machine / RTOS application module).

[0034] S3. The first application module continuously polls the flag bit (TAG) of the PCIe data access module to determine whether the PCIe data access module has completed the current PCIe data transfer. That is, the first application module actively initiates and continuously polls the flag bit of the PCIe DMA. It can be understood that this flag bit is used to indicate the data transfer status of the PCIe DMA. When the first application module polls and obtains that the value of the flag bit of the PCIe DMA corresponds to the indication of the data transfer completion status, it means that the PCIe DMA has completed the current PCIe data transfer.

[0035] S4. If it is determined that the PCIe data access module has completed the current PCIe data transfer, the first application module immediately notifies the second system to read the currently transferred PCIe data, and the first application module controls the PCIe data access module to perform the next PCIe data transfer with the PCIe EP device.

[0036] Among them, preferably, in step S4, the first application module uses Mailbox interrupt communication to notify the second system to read the currently transferred PCIe data. As Figure 1 shown, in the prior art, after the current PCIe data transfer is completed, the first application program (Linux Application1) usually uses the RPMSG framework for inter-core communication with the second application program (Linux Application2) to notify the second application program to read the PCIe data transferred to the memory Memory. However, the present invention abandons the commonly used RPMSG framework for inter-core communication and instead uses the underlying Mailbox interrupt communication. Since the traditional RPMSG framework will perform function encapsulation based on Mailbox and the RPMSG framework runs relatively time-consuming, the present invention can make the notification of the first application module (bare metal / RTOS application module) be transmitted to the second system of the second core more quickly through Mailbox interrupt communication. It can be understood that Mailbox belongs to the hardware resources of the CPU and there are corresponding registers that can be operated. Therefore, a simple interrupt communication function can be constructed by directly reading and writing the registers, which can effectively improve the inter-core communication efficiency.

[0037] Furthermore, the second system includes a second application module, which is specifically a Linux application module. The above-mentioned first application module uses Mailbox interrupt communication to notify the second application module to read the PCIe data. In addition, after step S4, there is also step S5: the second application module of the second system reads the PCIe data transferred to the shared memory this time. Further, the second application module processes the PCIe data.

[0038] It can be understood that based on the AMP framework, the present invention isolates one core (i.e., the above-mentioned first core) from the multi-core processor for running the first system (bare metal or RTOS), and uses this core to control PCIe DMA for PCIe data transfer. AMP (Asymmetric Multi-Processing), that is, an asymmetric multi-processing architecture. An asymmetric system means that multiple cores run different operating systems or bare metal application programs relatively independently, such as Linux + RTOS / bare metal, but a main core is required to control the entire system and other slave cores. Each processor core is isolated from each other and has its own memory, and can not only run different tasks independently but also perform inter-core communication between multiple cores.

[0039] In addition, preferably, in other embodiments, the above step S3 may further include: the PCIe data access module sends a data transfer completion notification to the first application module. Further, when the first application module first polls and obtains the flag bit corresponding to the completion of the current PCIe data transfer or when the first application module first receives the above data transfer completion notification, it is correspondingly determined that the PCIe data access module has completed the current PCIe data transfer, so as to execute the subsequent step S4. By this method, it is possible to better avoid misjudgment and delayed judgment of the PCIe data transfer status caused by errors during the process of the first application module polling the flag bit, thereby better ensuring the real-time performance of PCIe data transfer.

[0040] Compared with the prior art, the present invention provides a method for real-time transmission of PCIe data by a multi-core processor, having the following beneficial effects: (1) The present invention uses a first application module to continuously poll the flag bit of the PCIe data access module. Compared with the prior art that passively responds to PCIe DMA interrupts, the continuous polling actively initiated by the first application module of the present invention can identify the transmission status of the PCIe data access module (PCIe DMA) faster, more real-time, and more stably, making the time interval for each initiation of PCIe DMA to transfer data relatively stable, thereby improving the real-time performance and stability of PCIe communication and better ensuring the real-time performance of PCIe data transmission. (2) By isolating a core from the multi-core processor to run a bare-metal or RTOS, and using this core to control PCIe DMA for PCIe data transfer, the independence of PCIe data transfer control is achieved. (3) By using a first application module to continuously poll the flag bit of the PCIe data access module, and the first application module corresponds to a bare-metal / RTOS application module. Since the functions of the bare-metal / RTOS are simple, the running cycle is short and fixed, it can further ensure that the PCIe DMA transmission status is identified faster, more real-time, and more stably, so as to further improve the real-time performance and stability of PCIe communication, that is, further ensure the real-time performance of PCIe data transmission. (4) The present invention abandons the RPMSG framework commonly used for inter-core communication and instead adopts low-level Mailbox interrupt communication. Since the traditional RPMSG framework will encapsulate functions based on Mailbox and the RPMSG framework takes relatively long time to run, the present invention can make the notification of the first application module (bare-metal / RTOS application module) be transmitted to the second core (main core) more quickly through Mailbox interrupt communication, so as to better ensure that the second system reads PCIe data in time.

[0041] It should be noted that the term "comprising", "including" or any other variant thereof is intended to cover a non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising a..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.

[0042] Although the embodiments of the present invention have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principle and spirit of the present invention. The scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A method for real-time transmission of PCIe data by a multi-core processor, characterized in that, It includes the following steps: S1. Isolate the first core and the second core of the multi-core processor to run different systems respectively, where the first core is used to run the first system and the second core is used to run the second system; S2. The first application module of the first system controls the PCIe data access module to transmit the current PCIe data with an external PCIe EP device; S3. The first application module continuously polls the flag bit of the PCIe data access module to determine whether the PCIe data access module has completed the current PCIe data transmission; S4. If it is determined that the PCIe data access module has completed the current PCIe data transmission, the first application module notifies the second system to read the transmitted PCIe data, and the first application module controls the PCIe data access module to perform the next PCIe data transmission; The PCIe data access module is a PCIe DMA, and the flag bit is used to indicate the data transmission status of the PCIe DMA. When the first application module polls and obtains that the value of the flag bit of the PCIe DMA corresponds to the data transmission completion status, it means that the PCIe DMA has completed the current PCIe data transmission; The multi-core processor includes a shared memory, and the transmission of the PCIe data includes: transmitting the PCIe data from the PCIe EP device to the shared memory through the PCIe DMA, or transmitting the PCIe data from the shared memory to the PCIe EP device through the PCIe DMA.

2. The method for real-time transmission of PCIe data by the multi-core processor according to claim 1, wherein: The first system is a bare machine or RTOS.

3. The method for real-time transmission of PCIe data by a multi-core processor according to claim 1, wherein: The second system is Linux.

4. The method for real-time transmission of PCIe data by the multi-core processor according to claim 1, wherein The specific operation of step S2 is: the first application module sends a data transmission instruction to the PCIe DMA, and after receiving the data transmission instruction, the PCIe DMA further transmits the current PCIe data with the PCIe EP device.

5. The method for real-time transmission of PCIe data by the multi-core processor according to claim 1, wherein After step S4, there is also step S5: the second application module of the second system reads the PCIe data transmitted to the shared memory this time, and further, the second application module processes the PCIe data.

6. The method for real-time transmission of PCIe data by the multi-core processor according to claim 1, wherein: In step S4, the first application module uses Mailbox interrupt communication to notify the second system to read the transmitted PCIe data this time.

7. The method for real-time transmission of PCIe data by the multi-core processor according to claim 1, wherein: The PCIe EP device is an FPGA acquisition card or a PCIe hard disk.

Images