Signal processing circuit and memory

Abstract

The embodiment of the invention provides a signal processing circuit and a memory. The signal processing circuit comprises an instruction decoding circuit; the instruction decoding circuit comprises a preprocessing circuit which is used for receiving a first chip selection signal corresponding to a previous period of a current chip selection signal and a first instruction signal corresponding to the previous period of the current chip selection signal, and performing logical operation on the first chip selection signal and the first instruction signal to generate a first chip selection identification signal; and the operational circuit is connected with the preprocessing circuit and is used for receiving the first chip selection identification signal and a current chip selection signal and generating a decoding command corresponding to the current chip selection signal when the current chip selection signal is in an enabled state and the first chip selection identification signal is in a non-enabled state.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and relates to but is not limited to a signal processing circuit and a memory. Background Art

[0002] With the continuous development of semiconductor technology, people have put forward higher and higher requirements for data transmission speed when manufacturing and using computers and other equipment. In order to obtain faster data transmission speed, a series of memory devices such as DDR (Double Data Rate) have emerged, which can transmit data at double the data rate.

[0003] In a dynamic random access memory (DRAM), a command address (CMD / ADD) or CA signal for short can be sampled as an address and can also be sampled and decoded as an instruction.

[0004] However, there are still many problems to be solved in the current decoding process. Summary of the invention

[0005] In view of this, the embodiments of the present disclosure provide a signal processing circuit and a memory. In one aspect, the embodiments of the present disclosure provide a signal processing circuit, the signal processing circuit comprising: an instruction decoding circuit;

[0006] The instruction decoding circuit comprises:

[0007] A preprocessing circuit, used for receiving a first chip select signal corresponding to a previous cycle of a current chip select signal and a first instruction signal corresponding to a previous cycle of the current chip select signal, and performing a logic operation on the first chip select signal and the first instruction signal to generate a first chip select identification signal;

[0008] An operation circuit is connected to the preprocessing circuit, and is used to receive the first chip select identification signal and the current chip select signal, and generate a decoding command corresponding to the current chip select signal when the current chip select signal is in an enabled state and the first chip select identification signal is in a disabled state.

[0009] In the above scheme, the preprocessing circuit is specifically used to receive the first chip select signal and the second chip select signal corresponding to the previous cycle and the previous two cycles of the current chip select signal, respectively, and the first instruction signal and the second instruction signal corresponding to the previous cycle and the previous two cycles of the current chip select signal, respectively, and perform a logic operation on the first chip select signal and the first instruction signal to generate a first chip select identification signal, and perform a logic operation on the second chip select signal and the second instruction signal to generate a second chip select identification signal;

[0010] The operation circuit is specifically used to receive the first chip select identification signal, the second chip select identification signal and the current chip select signal, and generate a decoding command corresponding to the current chip select signal when the current chip select signal is in an enabled state and at least one of the first chip select identification signal and the second chip select identification signal is in a disabled state.

[0011] In the above scheme, in the first mode, the period of the current chip select signal is equal to one preset clock period; in the second mode, the period of the current chip select signal is equal to two preset clock periods.

[0012] In the above scheme, the preprocessing circuit includes:

[0013] a first preprocessing circuit, configured to receive a first chip select signal and a first instruction signal in the first mode and a first chip select signal and a first instruction signal in the second mode, and generate first chip select identification signals corresponding to the first mode and the second mode respectively;

[0014] The second preprocessing circuit is used to receive the second chip select signal and the second instruction signal in the first mode and the second chip select signal and the second instruction signal in the second mode, and generate second chip select identification signals corresponding to the first mode and the second mode respectively.

[0015] In the above solution, the first preprocessing circuit includes:

[0016] A first chip select identification generating circuit is used to receive the first chip select signal and the first instruction signal in the first mode and the first chip select signal and the first instruction signal in the second mode, and generate first intermediate chip select identification signals corresponding to the first mode and the second mode respectively;

[0017] a first selection circuit connected to the first chip select identification generating circuit, and configured to output a first intermediate chip select identification signal corresponding to the first mode in the first mode; and output a first intermediate chip select identification signal corresponding to the second mode in the second mode;

[0018] A first sampling circuit is connected to the first selection circuit, and is used for sampling the first intermediate chip select identification signal output by the first selection circuit once to obtain the first chip select identification signal corresponding to the first mode, and sampling the first intermediate chip select identification signal output by the first selection circuit twice to obtain the first chip select identification signal corresponding to the second mode.

[0019] In the above solution, the second preprocessing circuit includes:

[0020] A second chip select identification generating circuit is used to receive the second chip select signal and the second instruction signal in the first mode and the second chip select signal and the second instruction signal in the second mode, and generate second intermediate chip select identification signals corresponding to the first mode and the second mode respectively;

[0021] a second selection circuit connected to the second chip select identification generating circuit, and configured to output a second intermediate chip select identification signal corresponding to the first mode in the first mode; and output a second intermediate chip select identification signal corresponding to the second mode in the second mode;

[0022] A second sampling circuit is connected to the second selection circuit, and is used for sampling the second intermediate chip select identification signal output by the second selection circuit once to obtain the second chip select identification signal corresponding to the first mode, and sampling the second intermediate chip select identification signal output by the second selection circuit twice to obtain the second chip select identification signal corresponding to the second mode.

[0023] In the above solution, the second chip select flag generating circuit includes:

[0024] A first NOR gate, used for performing a NOR logic operation on the second instruction signal in the first mode and the second chip selection signal;

[0025] A first NOT gate, used for performing a NOT logic operation on a logic operation result of the first NOR gate, and outputting a corresponding second intermediate chip selection identification signal under a first mode;

[0026] The second NOR gate is used to perform a NOR logic operation on the second instruction signal in the second mode and the second chip select signal, and output a corresponding second intermediate chip select identification signal in the second mode.

[0027] In the above scheme, the second chip select signal in the first mode overlaps with the first chip select signal in the second mode; the second command signal in the first mode overlaps with the first command signal in the second mode;

[0028] The first chip select flag generating circuit comprises:

[0029] a third NOR gate, used for performing a NOR logic operation on the first instruction signal in the first mode and the first chip selection signal;

[0030] A second NOT gate, used for performing a NOT logic operation on the logic operation result of the third NOR gate, and outputting a first intermediate chip selection identification signal corresponding to the first mode;

[0031] The third sampling circuit is used to perform a sampling process on the inverse signal of the second intermediate chip select identification signal generated by the second chip select identification generation circuit in the first mode to obtain the first intermediate chip select identification signal corresponding to the second mode.

[0032] In the above solution, the first chip select flag generation circuit / the second chip select flag generation circuit includes:

[0033] The third selection circuit is connected to the input end of the corresponding NOR gate, and is used to output the first command address signal corresponding to the previous cycle / previous two cycles of the current chip select signal as the first instruction signal / second instruction signal when the first layout is laid out; and to output the second command address signal corresponding to the previous cycle / previous two cycles of the current chip select signal as the first instruction signal / second instruction signal when the second layout is laid out.

[0034] In the above solution, the operation circuit includes:

[0035] a first operation circuit, connected to both the first preprocessing circuit and the second preprocessing circuit, configured to receive the first chip select identification signal and the second chip select identification signal corresponding to the first mode, the first mode flag signal, the current chip select signal and the current instruction signal, and output a decoding signal corresponding to the current chip select signal or disable the decoding signal corresponding to the current chip select signal, wherein the first mode flag signal indicates that the signal processing circuit is in the first mode;

[0036] The second operation circuit is connected to both the first preprocessing circuit and the second preprocessing circuit, and is used to receive the first chip select identification signal and the second chip select identification signal corresponding to the second mode, the second mode flag signal, the current chip select signal and the current instruction signal, and output a decoding signal corresponding to the current chip select signal or disable the decoding signal corresponding to the current chip select signal, the second mode flag signal indicates that the signal processing circuit is in the second mode.

[0037] In the above solution, the first operation circuit / the second operation circuit includes: an OR gate, a first NAND gate, a second NAND gate and a fourth NOR gate, wherein:

[0038] The input end of the OR gate is used to receive the first chip selection identification signal and the second chip selection identification signal corresponding to the first mode / second mode, and the output end is connected to an input end of the first NAND gate;

[0039] Another input end of the first NAND gate is used to receive the first mode flag signal / the second mode flag signal, and an output end is connected to the first input end of the fourth NOR gate;

[0040] The input end of the second NAND gate is used to receive the current chip selection signal and the current command signal, and the output end is connected to the second input end of the fourth NOR gate;

[0041] The output end of the fourth NOR gate is used to output the decoding signal corresponding to the current chip select signal or to disable the decoding signal corresponding to the current chip select signal.

[0042] In the above scheme, the signal processing circuit further includes: a clock processing circuit; wherein,

[0043] The clock processing circuit is used to receive a source clock signal and output an initial clock signal and an initial complementary clock signal; wherein, the clock period of the source clock signal is the same as the preset clock period, the clock periods of the initial clock signal and the initial complementary clock signal are both equal to the clock period of the source clock signal, and the phase difference between the initial clock signal and the initial complementary clock signal is 180 degrees.

[0044] In the above solution, the signal processing circuit further includes:

[0045] A first receiving circuit is used to receive the initial clock signal and the initial complementary clock signal, and output a first clock signal and a first complementary clock signal, wherein the clock periods of the first clock signal and the first complementary clock signal are both twice the clock period of the source clock signal;

[0046] A second receiving circuit, used for receiving a source command address signal and outputting the initial command address signal;

[0047] The third receiving circuit is used to receive the source chip selection signal and output the initial chip selection signal.

[0048] In the above solution, the signal processing circuit further includes:

[0049] a chip select processing circuit, connected to the first receiving circuit and the third receiving circuit, and configured to receive the initial chip select signal, sample the initial chip select signal once using the first clock signal / first complementary clock signal to obtain the second chip select signal; sample the second chip select signal once using the first clock signal / first complementary clock signal to obtain the first chip select signal; sample the first chip select signal once using the first clock signal / first complementary clock signal to obtain the current chip select signal;

[0050] A command address processing circuit is connected to the first receiving circuit and the second receiving circuit, and is used to receive the initial command address signal, sample the initial command address once using the first clock signal / first complementary clock signal to obtain the second instruction signal; sample the second chip instruction number once using the first clock signal / first complementary clock signal to obtain the first instruction signal; and sample the first instruction signal once using the first clock signal / first complementary clock signal to obtain the current instruction signal.

[0051] Another aspect of the embodiments of the present disclosure further provides a memory, which includes the signal processing circuit as described in any of the above solutions.

[0052] In the above scheme, the memory includes: the fifth generation double data rate synchronous dynamic random access memory DDR5.

[0053] In the disclosed embodiment, a preprocessing circuit receives a first chip select signal and a first instruction signal corresponding to a previous cycle of a current chip select signal, and obtains a first chip select identification signal after a logic operation. The operation circuit jointly determines whether to generate a decoding command corresponding to the current chip select signal based on the state of the first chip select identification signal and the state of the current chip select signal. That is to say, the decoding command corresponding to the current chip select signal is at least jointly determined based on the current chip select signal and the chip select signal and instruction signal corresponding to the previous cycle of the current chip select signal. This can improve the problem of incorrect decoding of the second cycle of the non-target on-chip terminal resistance command, thereby improving the success rate of decoding. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 A schematic diagram of the structure of a signal processing circuit provided in an embodiment of the present disclosure;

[0055] Figure 2 A schematic diagram of the structure of an instruction decoding circuit provided in an embodiment of the present disclosure;

[0056] Figure 3 A signal timing diagram provided in an embodiment of the present disclosure Figure 1 ;

[0057] Figure 4 A signal timing diagram provided in an embodiment of the present disclosure Figure 2 ;

[0058] Figure 5 A signal timing diagram provided in an embodiment of the present disclosure Figure 3 ;

[0059] Figure 6 A signal timing diagram provided in an embodiment of the present disclosure Figure 4 ;

[0060] Figure 7 A schematic diagram of a framework structure of a signal processing circuit provided in an embodiment of the present disclosure;

[0061] Figure 8 A signal timing diagram provided in an embodiment of the present disclosure Figure 5 ;

[0062] Fig. 9 A signal timing diagram provided in an embodiment of the present disclosure Figure 6 ;

[0063] Fig.10a A schematic diagram of the structure of a signal processing circuit provided by an embodiment of the present disclosure;

[0064] Fig.10b A detailed structural diagram of an instruction decoding circuit provided in an embodiment of the present disclosure;

[0065] Fig.11 A signal timing diagram provided in an embodiment of the present disclosure Figure 7 ;

[0066] Fig.12 A signal timing diagram provided in an embodiment of the present disclosure Figure 8 ;

[0067] Fig.13 A signal timing diagram provided in an embodiment of the present disclosure Figure 9 ;

[0068] Fig.14 A signal timing diagram 10 provided in an embodiment of the present disclosure;

[0069] Fig.15 A schematic diagram of the composition structure of a memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0070] In order to make the technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the present disclosure will be further described in detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation methods described herein. On the contrary, these implementation methods are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0071] The present disclosure is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the following description and claims. It should be noted that the drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present disclosure.

[0072] It will be understood that the meaning of “on,” “over,” and “over” in this disclosure should be interpreted in the broadest manner, so that “on” not only means that it is “on” something with no intervening features or layers (i.e., directly on something), but also includes the meaning that it is “on” something with intervening features or layers.

[0073] Additionally, for ease of description, spatially relative terms such as "on," "over," "above," "upper," and the like may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0074] In the disclosed embodiments, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. In addition, the substrate can include a variety of semiconductor materials, such as silicon, silicon germanium, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of non-conductive materials, such as glass, plastic, or sapphire wafers.

[0075] In the disclosed embodiments, the term "layer" refers to a material portion including an area with a thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range that is smaller than the range of a lower or upper structure. In addition, a layer may be a region of a homogeneous or inhomogeneous continuous structure having a thickness that is less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers. For example, an interconnect layer may include one or more conductors and contact sublayers (where interconnects and / or via contacts are formed), and one or more dielectric sublayers.

[0076] In the embodiments of the present disclosure, the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0077] The memory involved in the embodiments of the present disclosure includes but is not limited to a dynamic random access memory, and the dynamic random access memory will be taken as an example for exemplary description hereinafter.

[0078] Taking the fifth generation DDR (DDR5, 5th DDR) DRAM as an example, the CA signal can be used as both address sampling and instruction sampling and decoding. The CA signal here is a general term for various command address signals of DRAM, which may include command signals such as row address strobe (RAS), column address strobe (CAS), write command (WE, Write), activate command (ACT, Active), and may also include address signals such as A13~A0. In addition, in actual applications, the number of bits of the address signal included in the command address signal may be determined according to the specifications of the DRAM, and the embodiments of the present disclosure do not impose any limitations.

[0079] For example, Figure 1 As shown, it shows a schematic diagram of the composition structure of a signal processing circuit, which includes: a clock processing circuit 101, a first receiving circuit 102, a second receiving circuit 103, a third receiving circuit 104, a fourth sampling circuit 105, a fifth sampling circuit 106, a sixth sampling circuit 107, a seventh sampling circuit 108, an eighth sampling circuit 109, a ninth sampling circuit 110, a first AND gate 111, a second AND gate 112, a third AND gate 113 and an instruction decoding circuit 114. Among them, the fourth sampling circuit 105, the fifth sampling circuit 106, the eighth sampling circuit 109 and the ninth sampling circuit 110 can be composed of D-type flip-flops, and the sixth sampling circuit 107 and the seventh sampling circuit 108 can be composed of D-type flip-flops and inverters. In addition, for the instruction decoding circuit 114, it can be composed of logic components such as a three-input NAND gate and a two-input NOR gate, see for details. Figure 2 shown.

[0080] exist Figure 1In the embodiment, the input signal of the clock processing circuit 101 is the source clock signal CLK, and the output signal is the initial clock signal CK_t and the initial complementary clock signal CK_c; the input signal of the first receiving circuit 102 is the initial clock signal CK_t and the initial complementary clock signal CK_c, and the output signal is the first clock signal PCLK_E and the first complementary clock signal PCLK_O; the input signal of the second receiving circuit 103 is the source command address signal CA[13:0] and the reference signal VREFCA, and the output signal is the initial command address signal CA; the input signal of the third receiving circuit 104 is the source chip select signal CS_n and the reference signal VREFCA, and the output signal is the initial chip select signal CS. The chip select processing circuit includes a sixth sampling circuit 107, a seventh sampling circuit 108, an eighth sampling circuit 109, and a ninth sampling circuit 110. The chip select processing circuit receives the initial chip select signal CS, and samples the initial chip select signal CS once by using the first clock signal PCLK_E and the first complementary clock signal PCLK_O through the sixth sampling circuit 107 and the seventh sampling circuit 108, so as to obtain the first chip select even signal PCS_E and the first chip select odd signal PCS_O; samples the first chip select even signal PCS_E and the first chip select odd signal PCS_O by using the first clock signal PCLK_E and the first complementary clock signal PCLK_O through the eighth sampling circuit 109 and the ninth sampling circuit 110, so as to obtain the second chip select even signal PCS_ED and the second chip select odd signal PCS_OD; and samples the first clock signal PCLK_E and the first complementary clock signal PCLK_O respectively by using the first AND gate 111. The first chip select even signal PCS_ED is logically operated with the signal PCLK_E to obtain the third chip select even signal CS_CLK_E, and the first complementary clock signal PCLK_O is logically operated with the second chip select odd signal PCS_OD by using the second AND gate 112 to obtain the third chip select odd signal CS_CLK_O; the first clock signal PCLK_E is used to sample the initial command address signal CA through the fourth sampling circuit 105 to obtain the initial instruction even signal CA[4:0]_1T_E; the first complementary clock signal PCLK_O is used to sample the initial command address signal CA through the fifth sampling circuit 106 to obtain the initial instruction odd signal CA[4:0]_1T_O.

[0081] Then, the instruction decoding circuit 114 decodes CA[4:0]_1T_E, CA[4:0]_1T_O, PCS_ED, PCS_OD, CS_CLK_O and CS_CLK_E to obtain the instruction even signal CMD_E and the instruction odd signal CMD_O; finally, the third AND gate 113 of the logic gate circuit performs a logical operation on CMD_E and CMD_O to obtain the target instruction signal CMD. It should be noted that CA[13:0] here represents a group of signals, which are the combined collective name of CA[0], CA[1], ..., CA

[13] . Correspondingly, the second receiving circuit 103 actually includes 14 receiving circuits, as well as output lines, and even the subsequent sampling circuits are 14, which correspond one to one with CA[0], CA[1], ..., CA

[13] .

[0082] based on Figure 1 The signal processing circuit shown in FIG. 1 has a corresponding signal timing diagram as shown in FIG. Figure 3 as well as Figure 4 As shown, Figure 3 The timing diagram of each signal when the effective pulse width of the CS signal is the width of one preset clock cycle is shown. It should be noted that in the embodiment of the present disclosure, the signal processing circuit here can be applied to a command signal of a preset clock cycle (represented by 1N Mode), indicating that the target command signal CMD only includes a valid command of one preset clock cycle, Figure 3 The timing diagram in 1NMode is shown in FIG. 1 ; the signal processing circuit here can also be applied to a command signal of two preset clock cycles (expressed as 2NMode), indicating that the target command signal CMD includes a valid command of two preset clock cycles, Figure 4 The figure below is the timing diagram in 2N Mode.

[0083] exist Figure 3In the embodiment, the initial clock signal is represented by CK_t, the first clock signal is represented by PCLK_E, the first complementary clock signal is represented by PCLK_O, and the clock period of the CK_t signal is equal to the preset clock period, and the clock periods of the PCLK_E signal and the PCLK_O signal are both twice the preset clock period; the initial command address signal is represented by CA, and CA may include Cy, Cz, C0, C1, C2 and C3; the initial chip select signal is represented by CS, the first chip select even signal is represented by PCS_E, and the first chip select odd signal is represented by PCS_O After the CS signal is sampled by the rising edge of the PCLK_E signal, the first chip select even signal is represented by PCS_E, which is a high-level valid pulse signal, and the pulse width is twice the preset clock period; after the CS signal is sampled by the rising edge of the PCLK_O signal, the first chip select odd signal is represented by PCS_O, which is a low-level signal; after the CA signal is sampled by the rising edge of the PCLK_E signal, the initial instruction even signal is represented by CA[4:0]_1T_E. The PCS_ODD signal is the signal after the delayed output of the PCS_OD signal, which is used to perform a logical AND operation with the PCS_OD and the clock PCLK_O signal to obtain two valid pulses of the CS_CLK_O clock. Figure 4 The timing diagram of each signal in the 2N Mode is shown when the effective pulse width of the CS signal is the width of 2 preset clock cycles, which will not be described in detail here.

[0084] In the above embodiment, the initial clock signal CK_t and the initial complementary clock signal CK_c are divided into the first clock signal PCLK_E and the first complementary clock signal PCLK_O after the first receiving circuit 102, so as to sample the initial command address signal CA. The normal command (normal CMD) and the non-target on-die termination resistance command (NT ODT CMD, NotTarget On Die Termination Command) in DDR5 use the first cycle of its CA signal as the instruction and address, and the second cycle as the remaining address. Therefore, the DDR5 design requires two-stage D-type flip-flop sampling, and then uses them as the address information of the two cycles respectively. For instructions, the first-stage CA signal needs to be decoded by combinational logic, and then the decoded CMD signal is sampled at the second stage to align with the sampling address of the second cycle. The normal CMD here can be understood as normal read and write instructions, and the NT ODT CMD can be understood as non-target related instructions.

[0085] In the above embodiment, a pulse CMD signal is generated by applying a simple PCS_ED / PCS_OD and PCLK_E / PCLK_O combinational logic to generate a CS_CLK_O / CS_CLK_E sampling instruction, and then performing an AND logic operation with PCS_OD / PCS_ED. For normal CMD, decoding is performed when the CS signal is at a low level, and no matter it is 1N Mode or 2N Mode, the CS signal is at a low level only in the first cycle. Figure 5 It is shown that in 1N Mode, the CS signal is at a low level in two consecutive preset clock cycles under NT ODT CMD. Since the CS signal is at a low level in two consecutive cycles under NT ODT CMD, according to the signal processing circuit provided in the above embodiment, the CS signal in the second cycle under NT ODT CMD will be incorrectly decoded for instruction. Figure 6 For NT ODT CMD, the CS signal is at a low level for two consecutive cycles, which is used as a mark to distinguish the secondary signal as NT ODT CMD. However, when the CS signal is at a low level in the second cycle, it will be mistakenly decoded as a decoding signal, resulting in incorrect decoding.

[0086] Based on the above problems, a signal processing circuit is proposed in the embodiment of the present disclosure, such as Figure 7 As shown, including:

[0087] Instruction decoding circuit 114; wherein the instruction decoding circuit 114 includes:

[0088] The preprocessing circuit 115 is used to receive the first chip select signal corresponding to the previous cycle of the current chip select signal and the first instruction signal corresponding to the previous cycle of the current chip select signal, and perform a logic operation on the first chip select signal and the first instruction signal to generate a first chip select identification signal;

[0089] The operation circuit 116 is connected to the preprocessing circuit 115, and is used to receive the first chip selection identification signal and the current chip selection signal, and generate a decoding command corresponding to the current chip selection signal when the current chip selection signal is in an enabled state and the first chip selection identification signal is in a disabled state.

[0090] Here, if only the state of the current chip select signal and the first chip select signal corresponding to the previous cycle of the current cycle is used to determine whether to decode, a decoding error may also occur. Specifically, when the current chip select signal is at a low level, if the first chip select signal corresponding to the previous cycle of the current chip select signal is at a low level, the decoding command is canceled, which may also lead to a judgment error. Figure 8 A signal timing diagram in 1N Mode is shown in FIG. Figure 8The figure shows the situation of two consecutive normal CMDs. When determining whether to decode based only on the current chip select signal and the state of the first chip select signal corresponding to the previous cycle of the current cycle, the decoding command in the second cycle of the normal CMD will be cancelled, resulting in erroneous decoding.

[0091] It should be noted that the enabled state here can be a high level state, and the disabled state can be a low level state; or, the enabled state can be a low level state, and the disabled state can be a high level state. This is not limited in the embodiments of the present disclosure. The following will be exemplified by taking the enabled state as a low level state and the disabled state as a high level state as an example.

[0092] It can be understood that the CA1 signal in the CA signal can be used to distinguish between normal CMD and NT ODT CMD. Specifically, when the CA1 signal is at a high level, it is normal CMD, and when the CA1 signal is at a low level, it is NT ODT CMD. In the disclosed embodiment, the preprocessing circuit receives the first chip select signal and the first instruction signal corresponding to the previous cycle of the current chip select signal, and obtains the first chip select identification signal after logical operation. The operation circuit jointly determines whether to generate the decoding command corresponding to the current chip select signal based on the state of the first chip select identification signal and the state of the current chip select signal. That is to say, the decoding command corresponding to the current chip select signal is jointly determined based on the current chip select signal and the chip select signal and instruction signal corresponding to the previous cycle of the current chip select signal. Therefore, the problem of incorrect decoding of the second cycle of NT ODT CMD can be effectively improved.

[0093] However, in the scheme of jointly determining whether to generate a decoding instruction corresponding to the current chip select signal by using the first instruction signal corresponding to the previous cycle of the current cycle, the first chip select signal, and the chip select signal corresponding to the current cycle, if Fig. 9 In the 1N Mode shown, if a normal CMD is immediately followed by an NT ODT CMD, the current cycle may be identified as the second cycle of the NT ODT CMD, thereby canceling the decoding command corresponding to the current chip select signal, resulting in a decoding error. How to eliminate the incorrect decoding of the second cycle of the NT ODT CMD while ensuring that the normal command is decoded, and further improve the decoding success rate, has become an urgent problem to be solved.

[0094] Based on the above problems, the embodiments of the present disclosure also provide the following solutions.

[0095] In some embodiments, the preprocessing circuit 115 is specifically used to receive the first chip select signal and the second chip select signal corresponding to the previous cycle and the previous two cycles of the current chip select signal, respectively, and the first instruction signal and the second instruction signal corresponding to the previous cycle and the previous two cycles of the current chip select signal, respectively, and perform a logic operation on the first chip select signal and the first instruction signal to generate a first chip select identification signal, and perform a logic operation on the second chip select signal and the second instruction signal to generate a second chip select identification signal;

[0096] The operation circuit 116 is specifically used to receive the first chip select identification signal, the second chip select identification signal and the current chip select signal, and generate a decoding command corresponding to the current chip select signal when the current chip select signal is in an enabled state and at least one of the first chip select identification signal and the second chip select identification signal is in a disabled state.

[0097] It can be understood that in the above embodiment, by utilizing the current chip select signal, the first instruction signal and the first chip select signal corresponding to the previous cycle of the current cycle, the second instruction signal and the second chip select signal corresponding to the previous two cycles of the current cycle to jointly determine whether to generate a decoding command corresponding to the current chip select signal, while ensuring that the normal CMD is decoded, the second cycle of the NT ODT CMD is avoided from being erroneously decoded, thereby further improving the decoding success rate.

[0098] In some embodiments, Fig.10a As shown, the signal processing circuit further includes: a clock processing circuit 201; wherein,

[0099] The clock processing circuit 201 is used to receive a source clock signal and output an initial clock signal and an initial complementary clock signal; wherein the clock period of the source clock signal is the same as the preset clock period, the clock periods of the initial clock signal and the initial complementary clock signal are both equal to the clock period of the source clock signal, and the phase difference between the initial clock signal and the initial complementary clock signal is 180 degrees.

[0100] In some embodiments, Fig.10a As shown, the signal processing circuit also includes:

[0101] A first receiving circuit 202 is used to receive an initial clock signal and an initial complementary clock signal, and output a first clock signal and a first complementary clock signal, wherein the clock periods of the first clock signal and the first complementary clock signal are both twice the clock period of the source clock signal;

[0102] The second receiving circuit 203 is used to receive the source command address signal and output the initial command address signal;

[0103] The third receiving circuit 204 is used to receive the source chip selection signal and output an initial chip selection signal.

[0104] It should be noted that, in the embodiment of the present disclosure, whether it is the first receiving circuit 202, the second receiving circuit 203 or the third receiving circuit 204, they can all be receivers (represented by Receiver) or buffers (represented by Buffer).

[0105] It should be noted that the source command address signal here can be represented by CA[13:0], and the initial command address signal is represented by CA; the source chip select signal can be represented by CS_n, and the initial chip select signal is represented by CS; the initial clock signal and the initial complementary clock signal are represented by CK_t and CK_c respectively, and the first clock signal and the first complementary clock signal are represented by PCLK_E and PCLK_O respectively. Among them, the clock period of the first clock signal and the first complementary clock signal are both twice the clock period of the source clock signal, and the phase difference between the first clock signal and the first complementary clock signal is 180 degrees; the clock period of the initial clock signal and the initial complementary clock signal are both equal to the clock period of the source clock signal, and the phase difference between the initial clock signal and the initial complementary clock signal is 180 degrees.

[0106] It should also be noted that in the embodiment of the present disclosure, whether it is a source command address signal or an initial command address signal, it is not a single signal, but represents a group of command address signals, namely CA[0] to CA

[13] . Therefore, for the second receiving circuit, 14 receiving circuits may be included here for receiving 14 signals such as CA[0], CA[1], ..., CA

[13] . Figure 1 Only one receiving circuit is shown as an illustration.

[0107] In some embodiments, Fig.10a As shown, the signal processing circuit also includes:

[0108] The chip selection processing circuit 206 is connected to the first receiving circuit 202 and the third receiving circuit 204, and is used to receive an initial chip selection signal, sample the initial chip selection signal once using the first clock signal / first complementary clock signal to obtain a second chip selection signal; sample the second chip selection signal once using the first clock signal / first complementary clock signal to obtain a first chip selection signal; sample the first chip selection signal once using the first clock signal / first complementary clock signal to obtain a current chip selection signal;

[0109] The command address processing circuit 205 is connected to the first receiving circuit 202 and the second receiving circuit 203, and is used to receive the initial command address signal, sample the initial command address once using the first clock signal / first complementary clock signal to obtain the second instruction signal; sample the second instruction number once using the first clock signal / first complementary clock signal to obtain the first instruction signal; sample the first instruction signal once using the first clock signal / first complementary clock signal to obtain the current instruction signal.

[0110] It should be noted that Fig.10a The clock signals received by the command address processing circuit 205 and the chip selection processing circuit 206 are only exemplary and are not intended to limit the present disclosure.

[0111] In some embodiments, in a first mode, a period of a current chip select signal is equal to one preset clock period; in a second mode, a period of a current chip select signal is equal to two preset clock periods.

[0112] The signal processing circuit in the embodiment of the present disclosure can be used in the first mode and can also be used in the second mode. In the first mode, the target command signal CMD includes only one valid command of a preset clock cycle, and in the second mode, the target command signal CMD includes two valid commands of preset clock cycles, and the period of the current chip select signal in the second mode is twice the period of the current chip select signal in the first mode.

[0113] Here, in the first mode, the current chip select signal is represented by CS_E, the first chip select signal is represented by ODD_CS_1B, the first chip select identification signal is represented by CS_EVEN_P_B, the second chip select signal is represented by EVEN_CS_1B, and the second chip select identification signal is represented by CS_EVEN_PP_T; in the second mode, the current chip select signal is represented by CS_2T_E, the first chip select signal is represented by EVEN_CS_1B, the first chip select identification signal is represented by CS_EVEN_P_B_2N, the second chip select signal is represented by EVEN_CS_0B, and the second chip select identification signal is represented by CS_EVEN_PP_T_2N.

[0114] In some embodiments, Fig.10b As shown, the first chip select flag generating circuit 119 / the second chip select flag generating circuit 122 includes:

[0115] The third selection circuit 131 is connected to the input end of the corresponding NOR gate, and is used to output the first command address signal corresponding to the previous cycle / previous two cycles of the current chip select signal as the first instruction signal / second instruction signal when the first layout is laid out; and to output the second command address signal corresponding to the previous cycle / previous two cycles of the current chip select signal as the first instruction signal / second instruction signal when the second layout is laid out.

[0116] It can be understood that, depending on the layout, it is possible to select CA0 among the 14 signals included in the source command address signal CA[13:0] to be sampled and logically operated to output the first instruction signal / second instruction signal, or it is possible to select CA1 among the 14 signals included in the source command address signal CA[13:0] to be sampled and logically operated to output the first instruction signal / second instruction signal. When CA1 is selected as the first command address signal, in the first mode, the first instruction signal is represented by ODD_CA1_1B, and the second instruction signal is represented by EVEN_CA1_1B; in the second mode, the first instruction signal is represented by EVEN_CA1_1B, and the second instruction signal is represented by EVEN_CA1_0B. When CA0 is selected as the first command address signal, in the first mode, the first instruction signal is represented by ODD_CA0_1B, and the second instruction signal is represented by EVEN_CA0_1B; in the second mode, the first instruction signal is represented by EVEN_CA0_1B, and the second instruction signal is represented by EVEN_CA0_0B. It should be noted that the above only exemplifies CA0 or CA1 as the first command address signal, but is not limited thereto. In actual application, a specific selection can be made according to different layout designs.

[0117] In the following, CA1 is used as an example of the first command address signal to specifically describe how to use the signal processing circuit provided in the embodiment of the present disclosure to implement decoding in the first mode and the second mode respectively.

[0118] In some embodiments, Figure 7 as well as Fig.10b As shown, the pre-processing circuit 115 includes:

[0119] The first preprocessing circuit 117 is used to receive the first chip select signal and the first command signal in the first mode and the first chip select signal and the first command signal in the second mode, and generate first chip select identification signals corresponding to the first mode and the second mode respectively;

[0120] The second preprocessing circuit 118 is used to receive the second chip select signal and the second instruction signal in the first mode and the second chip select signal and the second instruction signal in the second mode, and generate second chip select identification signals corresponding to the first mode and the second mode respectively.

[0121] Here, the first preprocessing circuit 117 mainly processes the first chip select signal and the first instruction signal under the first mode and the second mode accordingly, thereby generating a first chip select identification signal, and the second preprocessing circuit 118 mainly processes the second chip select signal and the second instruction signal under the first mode and the second mode accordingly, thereby generating a second chip select identification signal.

[0122] In some embodiments, Fig.10b As shown, the second pre-processing circuit 118 includes:

[0123] The second chip select identification generating circuit 122 is used to receive the second chip select signal and the second instruction signal in the first mode and the second chip select signal and the second instruction signal in the second mode, and generate second intermediate chip select identification signals corresponding to the first mode and the second mode respectively;

[0124] The second selection circuit 123 is connected to the second chip selection identification generation circuit 122, and is used to output the second intermediate chip selection identification signal corresponding to the first mode in the first mode; and output the second intermediate chip selection identification signal corresponding to the second mode in the second mode;

[0125] The second sampling circuit 124 is connected to the second selection circuit 123, and is used for sampling the second intermediate chip select identification signal output by the second selection circuit 123 once to obtain the second chip select identification signal corresponding to the first mode, and sampling the second intermediate chip select identification signal output by the second selection circuit 123 twice to obtain the second chip select identification signal corresponding to the second mode.

[0126] Here, the corresponding second intermediate chip selection identification signal in the first mode is represented by EVEN_CHK2.

[0127] Here, the second selection circuit 123 is also connected to the first mode flag signal EN_1N and the second mode flag signal EN_2N. The first mode flag signal indicates that the signal processing circuit is in the first mode, and the second mode flag signal indicates that the signal processing circuit is in the second mode. The second selection circuit 123 outputs the second intermediate chip select identification signal corresponding to the first mode through the first mode flag signal, and the second selection circuit 123 outputs the second intermediate chip select identification signal corresponding to the second mode through the second mode flag signal.

[0128] Here, the second sampling circuit 124 may include a first trigger 138, a second trigger 139, and a first buffer 142, wherein the first trigger 138 and the second trigger 139 here both include a D-type trigger. The input end of the first trigger 138 is connected to the output end of the second selection circuit 123, receives the second intermediate chip selection identification signal output by the second selection circuit 123, and the clock end is connected to the first receiving circuit, receives the first clock signal PCLK_E signal, and generates the corresponding second chip selection identification signal CS_EVEN_PP_T in the first mode. The output end of the first trigger 138 is connected to the input end of the first buffer 142, and is used to enhance the signal driving capability. The input end of the second trigger 139 is connected to the output end of the first buffer 142, and the clock end is connected to the first receiving circuit, receives the first clock signal PCLK_E signal, and generates the corresponding second chip selection identification signal CS_EVEN_PP_T_2N in the second mode.

[0129] The following will be combined Fig.10b The composition of the second chip select flag generating circuit 122 is introduced in detail.

[0130] In some embodiments, the second chip select flag generation circuit 122 includes:

[0131] A first NOR gate 125, used for performing a NOR logic operation on the second command signal in the first mode and the second chip selection signal;

[0132] The first NOT gate 126 is used to perform a NOT logic operation on the logic operation result of the first NOR gate 125, and output a corresponding second intermediate chip selection identification signal in the first mode;

[0133] The second NOR gate 127 is used for performing a NOR logic operation on the second instruction signal in the second mode and the second chip selection signal, and outputting a corresponding second intermediate chip selection identification signal in the second mode.

[0134] In some specific examples, the first input terminal of the first NOR gate 125 is connected to the output terminal of the third selection circuit 131, the second input terminal of the first NOR gate 125 is connected to the chip select processing circuit, the output terminal of the first NOR gate 125 is connected to the input terminal of the second buffer 143, and the signal coming out of the second buffer 143 is divided into two paths, one path is connected to the first NOR gate 126, and the other path is connected to the first chip select identification generation circuit 119.

[0135] In some embodiments, Fig.10b As shown, the first pre-processing circuit 117 includes:

[0136] A first chip select identification generating circuit 119 is used to receive the first chip select signal and the first instruction signal in the first mode and the first chip select signal and the first instruction signal in the second mode, and generate first intermediate chip select identification signals corresponding to the first mode and the second mode respectively;

[0137] The first selection circuit 120 is connected to the first chip selection identification generation circuit 119, and is used to output the first intermediate chip selection identification signal corresponding to the first mode in the first mode; and output the first intermediate chip selection identification signal corresponding to the second mode in the second mode;

[0138] The first sampling circuit 121 is connected to the first selection circuit 120, and is used for sampling the first intermediate chip select identification signal output by the first selection circuit 120 once to obtain the first chip select identification signal corresponding to the first mode, and sampling the first intermediate chip select identification signal output by the first selection circuit 120 twice to obtain the first chip select identification signal corresponding to the second mode.

[0139] Here, the first intermediate chip selection identification signal corresponding to the second mode is represented by EVEN_CHK1.

[0140] Here, the first selection circuit 120 is also connected to the first mode flag signal EN_1N and the second mode flag signal EN_2N. The first selection circuit 120 outputs the first intermediate chip select identification signal corresponding to the first mode through the first mode flag signal, and the first selection circuit 120 outputs the first intermediate chip select identification signal corresponding to the second mode through the second mode flag signal.

[0141] Here, the first sampling circuit 121 may include a half latch 141, a third buffer 144, and a third trigger 140, wherein the third trigger 140 includes a D-type trigger. The input end of the half latch 141 is connected to the output end of the first selection circuit 120, receives the first intermediate chip selection identification signal output by the first selection circuit 120, and the clock end is connected to the first receiving circuit, receives the first clock signal PCLK_E signal, and generates the first chip selection identification signal CS_EVEN_P_B corresponding to the second mode. The output end of the half latch 141 is connected to the input end of the third buffer 144, and is used to enhance the signal driving capability. The input end of the third trigger 140 is connected to the output end of the third buffer 144, and the clock end is connected to the first receiving circuit, receives the first clock signal PCLK_E signal, and generates the first chip selection identification signal CS_EVEN_P_B_2N corresponding to the first mode.

[0142] In some embodiments, the second chip select signal in the first mode overlaps with the first chip select signal in the second mode; the second command signal in the first mode overlaps with the first command signal in the second mode;

[0143] The first chip select flag generating circuit 119 includes:

[0144] A third NOR gate 128, used for performing a NOR logic operation on the first command signal in the first mode and the first chip selection signal;

[0145] The second NOT gate 129 is used to perform a NOT logic operation on the logic operation result of the third NOR gate 128, and output a first intermediate chip selection identification signal corresponding to the first mode;

[0146] The third sampling circuit 130 is used to perform a sampling process on the inverse signal of the second intermediate chip select identification signal generated by the second chip select identification generation circuit 122 in the first mode to obtain the corresponding first intermediate chip select identification signal in the second mode.

[0147] In some specific examples, the third sampling circuit 130 includes a D-type flip-flop, and the third sampling circuit 130 can use the first complementary clock signal PCLK_O to sample the inverted signal of the second intermediate chip selection identification signal in the first mode.

[0148] Fig.11 A timing diagram in a first mode provided by an embodiment of the present disclosure, Fig.12 A timing diagram in a second mode provided for an embodiment of the present disclosure.

[0149] like Fig.11 As shown, in the first mode, when the current chip select signal CS (1st) is at a low level, it is sampled and output as CS_E by PCLK_E and sent to the instruction decoding circuit. Therefore, it is necessary to check the CS of the first two cycles of this cycle respectively. The previous cycle CS (1pre) of this cycle is sampled and output as ODD_CS_1B by PCLK_O, and a logic operation is performed on it and the CA1 sampling information ODD_CA1_1B of the previous cycle of this cycle. Then, a trigger is added after the signal of this logic output, which is sampled and output as CS_EVEN_P_B by PCLK_E again; similarly, the first two cycles CS (2pre) of this cycle are sampled and output as EVEN_CS_1B by PCLK_E, which is sampled and output as EVEN_CS_1B with the CA1 sampling information EVEN_CA1_1B of the previous cycle of this cycle, and a trigger is added after the output as EVEN_CHK2, which is sampled and output as CS_EVEN_PP_T by PCLK_E again. CS_EVEN_P_B and CS_EVEN_PP_T are used to cover the current cycle decoding command through logical operation, thereby avoiding incorrect decoding of the second cycle of NT ODT CMD.

[0150] like Fig.12As shown, in the second mode, when the current chip select signal CS (1st) is at a low level, it is sampled and outputted as CS_E by PCLK_E and sent to the instruction decoding circuit. Therefore, the CS of the first two cycles of the cycle needs to be checked respectively. The CS (1pre) of the previous cycle of the cycle is sampled and outputted as EVEN_CS_1B by PCLK_E, and the 1pre is logically operated with the CA1 sampling information EVEN_CA1_1B of the previous cycle of the cycle, and the output is EVEN_CHK1. Two-stage triggers are added and sampled and outputted as CS_EVEN_P_B_2N by PCLK_E; similarly, the CS (2pre) of the first two cycles of the cycle is sampled and outputted as EVEN_CS_0B by PCLK_E, and the 1pre is logically operated with the CA1 sampling information EVEN_CA1_0B of the first two cycles of the cycle, and the output is sampled and outputted as CS_EVEN_PP_T_2N by PCLK_E after adding two-stage triggers. CS_EVEN_P_B_2N and CS_EVEN_PP_T_2N are used to overwrite the current cycle decoding command through logical operation, thereby avoiding incorrect decoding of the second cycle of NT ODT CMD.

[0151] In some embodiments, Fig.10b As shown, the operation circuit includes:

[0152] The first operation circuit 132 is connected to both the first pre-processing circuit 117 and the second pre-processing circuit 118, and is used to receive the first chip selection identification signal and the second chip selection identification signal corresponding to the first mode, the first mode flag signal, the current chip selection signal and the current instruction signal, and output a decoding signal corresponding to the current chip selection signal or disable the decoding signal corresponding to the current chip selection signal, wherein the first mode flag signal indicates that the signal processing circuit is in the first mode;

[0153] The second operation circuit 133 is connected to both the first preprocessing circuit 117 and the second preprocessing circuit 118, and is used to receive the first chip select identification signal and the second chip select identification signal corresponding to the second mode, the second mode flag signal, the current chip select signal and the current instruction signal, and output a decoding signal corresponding to the current chip select signal or disable the decoding signal corresponding to the current chip select signal. The second mode flag signal indicates that the signal processing circuit is in the second mode.

[0154] In some embodiments, the first operation circuit 132 / the second operation circuit 133 includes: an OR gate 134, a first NAND gate 135, a second NAND gate 136 and a fourth NOR gate 137, wherein:

[0155] The input end of the OR gate 134 is used to receive the first chip selection identification signal and the second chip selection identification signal corresponding to the first mode / second mode, and the output end is connected to an input end of the first NAND gate 135;

[0156] Another input terminal of the first NAND gate 135 is used to receive the first mode flag signal / the second mode flag signal, and the output terminal is connected to the first input terminal of the fourth NOR gate 137;

[0157] The input end of the second NAND gate 136 is used to receive the current chip selection signal and the current command signal, and the output end is connected to the second input end of the fourth NOR gate 137;

[0158] The output terminal of the fourth NOR gate 137 is used to output a decoding signal corresponding to the current chip selection signal or to disable the decoding signal corresponding to the current chip selection signal.

[0159] It should be noted that Fig.10b The various logic gates in the instruction decoding circuit shown in FIG. 1 are only exemplary demonstrations, but are not limited to Fig.10b As shown in Fig.10b There are other combinations of logic gates in that have the same effect.

[0160] In some specific examples, the first operation circuit 132 includes two second NAND gates 136, and the second operation circuit 133 includes two second NAND gates 136. The second NAND gate 136 in the first operation circuit 132 is used to receive the current chip select signal CS_E corresponding to the first mode, and the command address signals CA0_E, CA1_E, CA2_E, CA3_E, and CA4_E corresponding to the first mode. The second NAND gate 136 in the second operation circuit 133 is used to receive the current chip select signal CS_2T_E corresponding to the second mode, and the command address signals CA0_2T_E, CA1_2T_E, CA2_2T_E, CA3_2T_E, and CA4_2T_E corresponding to the first mode.

[0161] For the period corresponding to the current chip select signal, when the chip select signal corresponding to the current period is at a high level, it indicates that a decoding signal corresponding to the chip select signal corresponding to the current period needs to be generated to disable it. When the chip select signal corresponding to the current period is at a low level, it indicates that a decoding signal corresponding to the chip select signal corresponding to the current period may need to be generated. However, whether it is necessary to generate a decoding signal corresponding to the chip select signal corresponding to the current period needs to be determined in combination with the first chip select signal and the first instruction signal of the previous period (1pre) of the current chip select signal.

[0162] When the first chip select signal is at a high level, it means that the current cycle is the first cycle of NT ODT CMD or normalCMD, and a decoding signal needs to be generated. When the first chip select signal is at a low level, and the first command signal is at a high level, it means that the previous cycle of the current chip select signal is normal CMD, and the current cycle is normal CMD or the first cycle of NT ODT CMD, and a decoding signal needs to be generated. When the first chip select signal and the first command signal are both at low levels, it is necessary to make a comprehensive judgment based on the second command signal and the second chip select signal of the previous two cycles (2pre) of the current chip select signal.

[0163] When the first chip select signal and the first command signal are both low, when the second chip select signal and the second command signal are also both low, it means that 1pre and 2pre are two cycles of NT ODT CMD. When the first chip select signal and the first command signal are both low, when the second chip select signal is high, or the second chip select signal is low and the second command signal is high, it means that the current cycle is the second cycle of NT ODT CMD, and it is necessary to generate a decoding signal corresponding to disabling the current chip select signal.

[0164] Therefore, the OR logic operation can be used to select the situation where the first chip select signal in 1pre is high or the first command signal is high, so that the result of the logic operation of the first chip select signal and the first command signal is a high level state (disabled state). Alternatively, the OR-NOT logic operation can be used to select the situation where the second chip select signal and the second command signal in 2pre are both low levels, so that the result of the logic operation of the second chip select signal and the second command signal is a high level state (disabled state).

[0165] Combine the following Fig.10b How to generate a decoding signal corresponding to the current chip select signal or disable a decoding signal corresponding to the current chip select signal in the first mode is introduced in detail.

[0166] The first instruction signal corresponding to the first mode is ODD_CA1_1B, the first chip select signal is ODD_CS_1B, and CS_EVEN_P_B is obtained after a logic operation through the third NOR gate 128 and the second NOR gate 129. When one of ODD_CA1_1B and ODD_CS_1B is high, CS_EVEN_P_B is high, otherwise CS_EVEN_P_B is low. The second instruction signal is EVEN_CA1_1B, the second chip select signal is EVEN_CS_1B, and CS_EVEN_PP_T is obtained after a logic operation through the first NOR gate 125 and the first NOR gate 126. When one of EVEN_CA1_1B and EVEN_CS_1B is high, CS_EVEN_PP_T is high, otherwise CS_EVEN_PP_T is low. CS_EVEN_PP_T and CS_EVEN_P_B are logically operated by an OR gate 134, and a high level is output when one of CS_EVEN_PP_T and CS_EVEN_P_B is at a high level. Then, a non-AND logic operation is performed with the current chip select signal CS_E, and a decoding signal is generated only when one of CS_EVEN_PP_T and CS_EVEN_P_B is at a high level and the current chip select signal CS_E is at a low level, otherwise a decoding signal corresponding to the disabled current chip select signal is generated.

[0167] It can be understood that the embodiment of the present disclosure checks the initial command address signal CA and the initial chip select signal CS of the first two cycles of the current chip select signal when the current chip select signal is in a low level state. If the CS signals of the first two cycles are both low levels, and the CA1 signal sampling information of the cycle is low level, the current CS signal is allowed to be transmitted to the instruction decoding circuit for instruction decoding output, and the fourth NOR gate 137 outputs the decoding signal corresponding to the current chip select signal; if the CS signal of the previous cycle is high level, or the CA1 signal sampling information of the cycle is high level, the current CS signal is also allowed to be transmitted to the instruction decoding circuit 114 for instruction decoding output, and the fourth NOR gate 137 outputs the decoding signal corresponding to the current chip select signal. In the first mode, the current CS signal is sampled and output to the instruction decoding circuit 114 by the PCLK_E signal, and the CS signals corresponding to the first two cycles are sampled and output by the PCLK_E signal and the PCLK_O signal respectively, and one level of sampling circuit is added for each, and then the PCLK_E signal is sampled and output as the second chip select identification signal CS_EVEN_PP_T and the first chip select identification signal CS_EVEN_P_B, which are sent to the operation circuit, and the decoding instruction is covered by logical operation; in the second mode, the current CS signal is sampled and output to the operation circuit by the PCLK_E signal, and the CS signals corresponding to the first two cycles are sampled and output by the PCLK_E signal, and two levels of sampling circuits need to be added for each, and the PCLK_E signal is sampled and output as the second chip select identification signal CS_EVEN_PP_T_2N and the first chip select identification signal CS_EVEN_P_B_2N, which are sent to the operation circuit, and the decoding instruction is covered by logical operation, and it is regarded as a decoding signal, thereby avoiding the incorrect decoding of the second cycle of NT ODT CMD.

[0168] Fig.13 is a timing diagram of the corresponding signal in the first mode, Fig.14 Schematic diagram of the timing of the corresponding signal in the second mode. In some embodiments, the second chip select identification signal CS_EVEN_PP_T of the previous two cycles of the current chip select signal CS and the first chip select identification signal CS_EVEN_P_B of the previous cycle are used to perform a logical operation when the current chip select signal CS is collected to complete the CS check of the previous two cycles of the current chip select signal CS; Fig.13 as well as Fig.14 The first chip select flag signal and the second chip select flag signal are shown by dotted lines. In the first mode, the CS CHECK flag signal of the previous cycle and the current sample CS_n are sampled by PCLK_E and PCLK_OT respectively. Since the first chip select flag signal and the second chip select flag signal are subjected to logical operation to obtain the judgment result, and then compared with the current CS_n, there is a difference of a preset clock cycle, which makes the trigger instruction sampling Margin in the instruction decoding circuit smaller.

[0169] In the present disclosure, Fig.13 as well as Fig.14 The first chip select flag signal and the second chip select identification signal shown by the solid line in the figure transmit the CS_EVEN_PP_T signal and the CS_EVEN_P_B signal to the operation circuit, and the instruction signal and the chip select signal of the first two cycles of the current chip select signal are checked at the instruction decoding input end. Since the current chip select signal and the CS_EVEN_PP_T and CS_EVEN_P_B signals are sampled and output to the instruction decoding end by PCLK_E / PCLK_O at the same time, the result of the logical operation of the first chip select identification signal and the second chip select identification signal is regarded as a decoding instruction and directly sent to the decoding circuit, so that the instruction sampling Margin of the next level trigger is increased.

[0170] The disclosed embodiment proposes a signal processing circuit, comprising: an instruction decoding circuit; wherein the instruction decoding circuit comprises: a preprocessing circuit, for receiving a first chip select signal corresponding to a previous cycle of a current chip select signal, a first instruction signal corresponding to a previous cycle of the current chip select signal, and performing a logical operation on the first chip select signal and the first instruction signal to generate a first chip select identification signal; an operation circuit, connected to the preprocessing circuit, for receiving the first chip select identification signal and the current chip select signal, and generating a decoding command corresponding to the current chip select signal when the current chip select signal is in an enabled state and the first chip select identification signal is in a disabled state. In the disclosed embodiment, a preprocessing circuit receives a first chip select signal and a first instruction signal corresponding to a previous cycle of a current chip select signal, and obtains a first chip select identification signal after a logic operation. The operation circuit jointly determines whether to generate a decoding command corresponding to the current chip select signal based on the state of the first chip select identification signal and the state of the current chip select signal. That is to say, the decoding command corresponding to the current chip select signal is at least jointly determined based on the current chip select signal and the chip select signal and instruction signal corresponding to the previous cycle of the current chip select signal. This can improve the problem of incorrect decoding of the second cycle of the non-target on-chip terminal resistance command, thereby improving the success rate of decoding.

[0171] Another aspect of the present disclosure also provides a memory, such as Fig.15 As shown, the memory 145 includes a signal processing circuit 146 as in any of the above embodiments.

[0172] In some embodiments, the memory 145 includes: a fifth generation double data rate synchronous dynamic random access memory DDR5.

[0173] It should be noted that the embodiments of the present disclosure can be applied to the control circuit of CA signal sampling and decoding in DRAM chips, but are not limited to this scope. Other circuits related to input signal sampling and instruction decoding can also adopt this design.

[0174] In the several embodiments provided in the present disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-targeted manner. The device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the components shown or discussed are coupled or directly coupled to each other.

[0175] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0176] The features disclosed in several method or device embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0177] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A signal processing circuit, characterized in that: The signal processing circuit comprises: an instruction decoding circuit; wherein, The instruction decoding circuit comprises: A preprocessing circuit, used for receiving a first chip select signal corresponding to a previous cycle of a current chip select signal and a first instruction signal corresponding to a previous cycle of the current chip select signal, and performing a logic operation on the first chip select signal and the first instruction signal to generate a first chip select identification signal; An operation circuit is connected to the preprocessing circuit, and is used to receive the first chip select identification signal and the current chip select signal, and generate a decoding command corresponding to the current chip select signal when the current chip select signal is in an enabled state and the first chip select identification signal is in a disabled state.

2. The signal processing circuit according to claim 1, characterized in that: The preprocessing circuit is specifically used to receive the first chip select signal and the second chip select signal corresponding to the previous cycle and the previous two cycles of the current chip select signal, respectively, and the first instruction signal and the second instruction signal corresponding to the previous cycle and the previous two cycles of the current chip select signal, and perform a logic operation on the first chip select signal and the first instruction signal to generate a first chip select identification signal, and perform a logic operation on the second chip select signal and the second instruction signal to generate a second chip select identification signal; The operation circuit is specifically used to receive the first chip select identification signal, the second chip select identification signal and the current chip select signal, and generate a decoding command corresponding to the current chip select signal when the current chip select signal is in an enabled state and at least one of the first chip select identification signal and the second chip select identification signal is in a disabled state.

3. The signal processing circuit according to claim 2, characterized in that: In the first mode, the period of the current chip select signal is equal to one preset clock period; in the second mode, the period of the current chip select signal is equal to two preset clock periods.

4. The signal processing circuit according to claim 3, characterized in that: The preprocessing circuit comprises: a first preprocessing circuit, configured to receive a first chip select signal and a first instruction signal in the first mode and a first chip select signal and a first instruction signal in the second mode, and generate first chip select identification signals corresponding to the first mode and the second mode respectively; The second preprocessing circuit is used to receive the second chip select signal and the second instruction signal in the first mode and the second chip select signal and the second instruction signal in the second mode, and generate second chip select identification signals corresponding to the first mode and the second mode respectively.

5. The signal processing circuit according to claim 4, characterized in that: The first preprocessing circuit comprises: A first chip select identification generating circuit is used to receive the first chip select signal and the first instruction signal in the first mode and the first chip select signal and the first instruction signal in the second mode, and generate first intermediate chip select identification signals corresponding to the first mode and the second mode respectively; a first selection circuit connected to the first chip select identification generating circuit, and configured to output a first intermediate chip select identification signal corresponding to the first mode in the first mode; and output a first intermediate chip select identification signal corresponding to the second mode in the second mode; A first sampling circuit is connected to the first selection circuit, and is used for sampling the first intermediate chip select identification signal output by the first selection circuit once to obtain the first chip select identification signal corresponding to the first mode, and sampling the first intermediate chip select identification signal output by the first selection circuit twice to obtain the first chip select identification signal corresponding to the second mode.

6. The signal processing circuit according to claim 5, characterized in that: The second preprocessing circuit comprises: A second chip select identification generating circuit is used to receive the second chip select signal and the second instruction signal in the first mode and the second chip select signal and the second instruction signal in the second mode, and generate second intermediate chip select identification signals corresponding to the first mode and the second mode respectively; a second selection circuit connected to the second chip select identification generating circuit, and configured to output a second intermediate chip select identification signal corresponding to the first mode in the first mode; and output a second intermediate chip select identification signal corresponding to the second mode in the second mode; A second sampling circuit is connected to the second selection circuit, and is used for sampling the second intermediate chip select identification signal output by the second selection circuit once to obtain the second chip select identification signal corresponding to the first mode, and sampling the second intermediate chip select identification signal output by the second selection circuit twice to obtain the second chip select identification signal corresponding to the second mode.

7. The signal processing circuit according to claim 6, characterized in that: The second chip select flag generating circuit comprises: A first NOR gate, used for performing a NOR logic operation on the second instruction signal in the first mode and the second chip selection signal; A first NOT gate, used for performing a NOT logic operation on a logic operation result of the first NOR gate, and outputting a corresponding second intermediate chip selection identification signal under a first mode; The second NOR gate is used to perform a NOR logic operation on the second instruction signal in the second mode and the second chip select signal, and output a corresponding second intermediate chip select identification signal in the second mode.

8. The signal processing circuit according to claim 6, characterized in that: The second chip select signal in the first mode overlaps with the first chip select signal in the second mode; The second command signal in the first mode overlaps with the first command signal in the second mode; The first chip select flag generating circuit comprises: a third NOR gate, used for performing a NOR logic operation on the first instruction signal in the first mode and the first chip selection signal; A second NOT gate, used for performing a NOT logic operation on the logic operation result of the third NOR gate, and outputting a first intermediate chip selection identification signal corresponding to the first mode; The third sampling circuit is used to perform a sampling process on the inverse signal of the second intermediate chip select identification signal generated by the second chip select identification generation circuit in the first mode to obtain the first intermediate chip select identification signal corresponding to the second mode.

9. The signal processing circuit according to claim 6, characterized in that: The first chip select flag generation circuit / the second chip select flag generation circuit comprises: The third selection circuit is connected to the input end of the corresponding NOR gate, and is used to output the first command address signal corresponding to the previous cycle / previous two cycles of the current chip select signal as the first instruction signal / second instruction signal when the first layout is laid out; and to output the second command address signal corresponding to the previous cycle / previous two cycles of the current chip select signal as the first instruction signal / second instruction signal when the second layout is laid out.

10. The signal processing circuit according to claim 4, characterized in that: The operation circuit comprises: a first operation circuit, connected to both the first preprocessing circuit and the second preprocessing circuit, configured to receive the first chip select identification signal and the second chip select identification signal corresponding to the first mode, the first mode flag signal, the current chip select signal and the current instruction signal, and output a decoding signal corresponding to the current chip select signal or disable the decoding signal corresponding to the current chip select signal, wherein the first mode flag signal indicates that the signal processing circuit is in the first mode; The second operation circuit is connected to both the first preprocessing circuit and the second preprocessing circuit, and is used to receive the first chip select identification signal and the second chip select identification signal corresponding to the second mode, the second mode flag signal, the current chip select signal and the current instruction signal, and output a decoding signal corresponding to the current chip select signal or disable the decoding signal corresponding to the current chip select signal, the second mode flag signal indicates that the signal processing circuit is in the second mode.

11. The signal processing circuit according to claim 10, characterized in that: The first operation circuit / the second operation circuit comprises: an OR gate, a first NAND gate, a second NAND gate and a fourth NOR gate, wherein: The input end of the OR gate is used to receive the first chip selection identification signal and the second chip selection identification signal corresponding to the first mode / second mode, and the output end is connected to an input end of the first NAND gate; Another input end of the first NAND gate is used to receive the first mode flag signal / the second mode flag signal, and an output end is connected to the first input end of the fourth NOR gate; The input end of the second NAND gate is used to receive the current chip selection signal and the current command signal, and the output end is connected to the second input end of the fourth NOR gate; The output end of the fourth NOR gate is used to output the decoding signal corresponding to the current chip select signal or to disable the decoding signal corresponding to the current chip select signal.

12. The signal processing circuit according to claim 3, characterized in that: The signal processing circuit further includes: a clock processing circuit; wherein, The clock processing circuit is used to receive a source clock signal and output an initial clock signal and an initial complementary clock signal; wherein, the clock period of the source clock signal is the same as the preset clock period, the clock periods of the initial clock signal and the initial complementary clock signal are both equal to the clock period of the source clock signal, and the phase difference between the initial clock signal and the initial complementary clock signal is 180 degrees.

13. The signal processing circuit according to claim 12, characterized in that: The signal processing circuit further includes: A first receiving circuit is used to receive the initial clock signal and the initial complementary clock signal, and output a first clock signal and a first complementary clock signal, wherein the clock periods of the first clock signal and the first complementary clock signal are both twice the clock period of the source clock signal; A second receiving circuit, used for receiving a source command address signal and outputting the initial command address signal; The third receiving circuit is used to receive the source chip selection signal and output the initial chip selection signal.

14. The signal processing circuit according to claim 13, characterized in that: The signal processing circuit further includes: a chip select processing circuit, connected to the first receiving circuit and the third receiving circuit, and configured to receive the initial chip select signal, sample the initial chip select signal once using the first clock signal / first complementary clock signal to obtain the second chip select signal; sample the second chip select signal once using the first clock signal / first complementary clock signal to obtain the first chip select signal; sample the first chip select signal once using the first clock signal / first complementary clock signal to obtain the current chip select signal; A command address processing circuit is connected to the first receiving circuit and the second receiving circuit, and is used to receive the initial command address signal, sample the initial command address once using the first clock signal / first complementary clock signal to obtain the second instruction signal; sample the second chip instruction number once using the first clock signal / first complementary clock signal to obtain the first instruction signal; and sample the first instruction signal once using the first clock signal / first complementary clock signal to obtain the current instruction signal.

15. A memory, characterized in that: The memory comprises the signal processing circuit as claimed in any one of claims 1 to 14.

16. The memory according to claim 15, characterized in that: The memory includes: a fifth-generation double-rate synchronous dynamic random access memory DDR5.

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