Forming semiconductor devices in silicon carbide

Abstract

A semiconductor device is formed in silicon carbide. A method includes providing a first layer (101) of epitaxial silicon carbide supported by a silicon carbide substrate (130); and a second layer (102) of silicon carbide providing epitaxy on the first layer (101); and forming a plurality of semiconductor devices (105, 105-1, 105-2, 105-3) in the second layer (102); and separating the substrate (130) from the second layer (102) at the first layer (101). The first layer (101) comprises a plurality of pores.

Description

Technical Field

[0001] Various examples of the invention generally relate to forming semiconductor devices in silicon carbide. Various examples of the invention specifically relate to techniques that enable reuse of silicon carbide substrates. Background Art

[0002] Power semiconductor devices have high voltage and / or high current switching capabilities. Power semiconductor devices thus find applications in various fields such as high voltage DC transmission (eg from offshore wind farms), smart grid components, railway traction, etc.

[0003] Power semiconductor devices are often formed using silicon carbide (SiC). SiC is a semiconductor material with a relatively wide bandgap. This facilitates high voltage and / or high current switching capabilities.

[0004] One disadvantage of currently available SiC power semiconductor devices is the high price (at least compared to silicon devices), which is caused, for example, by high substrate prices and / or lower production yields.Therefore, there is a need for advanced techniques for forming semiconductor devices in SiC. Summary of the invention

[0005] An embodiment of the method includes providing a first layer of SiC. The first layer is supported by a SiC substrate. The method also includes providing a second layer of epitaxial SiC on the first layer. The method also includes forming a plurality of semiconductor devices in the second layer. The method also includes separating the substrate from the second layer at the first layer. The first layer includes a plurality of voids.

[0006] An embodiment of the method includes providing a first layer of porous SiC supported by a substrate of SiC. The method also includes providing a second layer of epitaxial SiC on the first layer. The method also includes forming a plurality of semiconductor devices in the second layer. The method also includes separating the substrate from the second layer at the first layer.

[0007] An embodiment of the wafer includes a SiC substrate and a layer of SiC supported by the SiC substrate. The layer includes a plurality of pores.

[0008] An embodiment of the wafer includes a SiC substrate and a porous layer of SiC supported by the SiC substrate.

[0009] It is to be understood that the features mentioned above and those still to be explained below can be used not only in the respective combination indicated but also in other combinations or in isolation without departing from the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a flow chart of a method according to various examples.

[0011] Figure 2 Various process steps for forming a semiconductor device in SiC according to various examples are schematically illustrated.

[0012] Figure 3 Various process steps for forming a semiconductor device in SiC according to various examples are schematically illustrated.

[0013] Figure 4 is a flow chart of a method according to various examples, wherein the method includes a trench fill process.

[0014] Figure 5 An etch mask defining a trench for a trench filling process according to various examples is schematically illustrated.

[0015] Figure 6 A trench of a trench filling process is schematically illustrated, and a void defined by the trench is also schematically illustrated according to various examples.

[0016] Figure 7 The lateral overgrowth conditions of a trench filling process according to various examples are schematically illustrated.

[0017] Figure 8 The void density in multiple layers according to various examples is schematically illustrated.

[0018] Fig. 9 The growth rate of epitaxial growth according to various examples is schematically illustrated.

[0019] Fig.10 Schematically illustrates providing protective material at vertical edges of a wafer when singulating semiconductor devices according to various examples.

[0020] Fig.11 Schematically illustrates providing protective material at vertical edges of a wafer when singulating semiconductor devices according to various examples.

[0021] Fig.12 Singulated semiconductor devices according to various examples are schematically illustrated.

[0022] Fig.13 The pores of porous SiC according to various examples are schematically illustrated.

[0023] Fig.14 The pores of porous SiC according to various examples are schematically illustrated.

[0024] Fig.15 The void density in multiple layers according to various examples is schematically illustrated. DETAILED DESCRIPTION

[0025] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. It is to be understood that the following description of the embodiments is not to be understood in a limiting sense. The scope of the present invention is not intended to be limited by the embodiments described below or by the accompanying drawings, which are to be understood as merely illustrative.

[0026] The drawings are to be regarded as schematic representations, and the elements illustrated in the drawings are not necessarily shown to scale. Rather, the various elements are represented so that their function and general purpose become apparent to those skilled in the art.

[0027] Hereinafter, a technique for providing a semiconductor device in a wide bandgap semiconductor material is described. The semiconductor device is defined in a semiconductor material provided on a substrate or supported by a substrate. Hereinafter, if a semiconductor device is "defined in" a semiconductor material, this may mean that the semiconductor device includes the material and / or is based on the material.

[0028] The term "horizontal" as used in this specification is intended to describe an orientation that is generally parallel to a first or main horizontal side of a semiconductor substrate or body. This may be, for example, the surface of a wafer or die. Sometimes, the horizontal direction is also referred to as a lateral direction.

[0029] The term “vertical” as used in this specification intends to describe an orientation that is generally arranged perpendicular to the first side, ie parallel to the normal to the first side of the semiconductor substrate or body.

[0030] Semiconductor devices can be implemented as two-terminal devices (e.g., diodes). Semiconductor devices can also be three-terminal devices, such as field effect transistors (FETs), in particular, metal oxide field effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs), junction field effect transistors (JFETs), and thyristors, to name a few. Semiconductor devices can also include more than three terminals.

[0031] Below, various examples of processing wide bandgap semiconductor materials are described. The term "wide bandgap semiconductor material" as used in this specification is intended to describe a semiconductor material having a bandgap of 1 eV or more. Wide bandgap semiconductor materials such as SiC or gallium nitride (GaN) have a high breakdown field strength (e.g., at least 2.5 MV / cm) and a high critical avalanche field strength, respectively. Therefore, compared to lower bandgap semiconductor materials, a higher doping of the semiconductor region can be selected, which reduces the on-state resistance Ron (also referred to as the on-resistance Ron). In the following, examples are mainly explained with respect to SiC as a wide bandgap semiconductor material, but similar techniques can be easily applied to other kinds and types of wide bandgap semiconductor materials.

[0032] In various examples described herein, the semiconductor devices defined in SiC may be power semiconductor devices. The term "power semiconductor device" as used in this specification is intended to describe a semiconductor device on a single chip having high voltage (particularly, at least 250V or at least 600V) and / or high current switching capability. In other words, the power semiconductor device is intended for high currents, typically in the ampere range.

[0033] The semiconductor device may be formed in an epitaxial layer of SiC provided on the SiC substrate. This layer is hereinafter referred to as the device layer.

[0034] As a general rule, the device layer may include sublayers. For example, the sublayer may implement the drain region of the semiconductor device. The drain region may be highly doped. The thickness of the drain region may add sufficient structural stability to the obtained die when the device layer is separated from the substrate. For example, the thickness of the drain region may be in the range of at least 2 μm to at most 200 μm, or in the range of at least 10 μm to at most 100 μm, or in the range of at least 20 μm to at most 50 μm. Optionally, another sublayer of the device layer may implement a buffer zone. For example, for a FET as a semiconductor device, an n-doped buffer layer may be implemented by a corresponding sublayer. For a diode as a semiconductor device, an n-doped buffer layer may correspond to a contact layer. In the case of a bipolar diode, an n-doped back emitter region may be implemented by a corresponding sublayer. Another sublayer may implement a drift zone.

[0035] An epitaxial growth process may be used to provide the device layer to obtain crystalline SiC for high charge carrier mobility. Generally, the growth rate of the epitaxial growth process may vary across the thickness of the device layer (ie in the vertical direction), for example for different sub-layers.

[0036] In order to form a semiconductor device, a front side process may be implemented. Here, one or more electrical contacts may be formed to electrically contact different regions. For example, a source contact, a drain contact, and a gate contact may be formed for a FET as a semiconductor device.

[0037] To obtain semiconductor devices, in particular on a die of a certain thickness, according to a reference implementation, it may be required to remove large portions of the substrate, for example via grinding. The removed material may be discarded. Due to the relatively high price of SiC substrates, at least compared to silicon, this may result in a relatively high unit cost per semiconductor device. This cost can be significantly reduced, for example by allowing reuse of the substrate.

[0038] Hereinafter, a technique is described that facilitates multiple reuse of SiC substrates. Thus, multiple groups of semiconductor devices can be sequentially formed on a SiC substrate. Each group of semiconductor devices can include an array of laterally spaced semiconductor devices. By separating each group of semiconductor devices from the substrate, the substrate can then be reused to form another group of semiconductor devices. Thus, the unit cost per semiconductor device can be reduced by reusing the SiC substrate for multiple groups of semiconductor devices.

[0039] One limitation of SiC-based semiconductor devices is the tendency toward a significant defect density of the SiC substrate. For example, defects can diffuse and propagate through the semiconductor device during current conduction. Stacking errors are examples of such defects. Such an effect is called bipolar degradation. See, for example, Lendenmann, H. et al., "Degradation in SiC bipolar devices: sources and consequences of electrically active dislocations in SiC", Materials Science Forum Vol. 433, Trans Tech Publications, 2003. Stacking errors can result in an increased on-state resistance Ron for a transistor or an increased forward voltage for a diode. Such defects can reduce the yield in the manufacture of semiconductor devices. This again increases the unit cost per semiconductor device. Moreover, the operational reliability of the semiconductor device may be degraded.

[0040] Typically, defect density may require countermeasures to avoid failure of semiconductor devices. In one example, such defects can be suppressed by implementing a highly doped buffer between the substrate and the epitaxial layer of SiC in which the semiconductor device is formed. This buffer promotes a high recombination rate of positively charged electric carriers (holes) injected from the front side of the die. Thus, the growth of stacking errors can be suppressed. See Savkina, NS et al., "Characterization of 3C-SiC / 6H-SiCheterostructures grown by vacuum sublimation", Materials Science Forum, Vol. 433, pp. 293-296, Trans Tech Publications, 2003. Here, a porous layer of SiC is provided between the epitaxial SiC layer and the substrate. Thus, if compared to the density of defects in the substrate, the defect density in the epitaxial SiC layer can be significantly reduced.

[0041] Hereinafter, a technique is described to promote the suppression of the propagation of any crystalline defects of the substrate into the device layer. Thus, the yield in the manufacture of semiconductor devices can be increased, which in turn also helps to reduce the unit cost per semiconductor device. In addition, the probability of failure in operating semiconductor devices can be reduced.

[0042] In various examples described herein, such an effect can be achieved by interfacing the substrate and device layers with an additional layer. This layer is hereinafter referred to as an interface layer.

[0043] The interface layer is supported by the substrate. For example, the interface layer can be defined adjacent to the front side of the substrate. For example, the interface layer can be defined in the substrate, adjacent to the front side. Alternatively or additionally, the interface layer can be defined on the substrate, adjacent to the front side; that is, the interface layer can be supplied on top of the substrate using a growth process. There may be no other layers between the substrate and the interface layer. For example, in some embodiments, the interface layer may not be attached to the substrate using an adhesive or the like.

[0044] The lateral dimensions of the interface layer may correspond to the lateral dimensions of the substrate.For example, the interface layer may extend laterally across the entire front side of the substrate, or at least across 90% of the front side area of ​​the substrate.

[0045] The vertical dimension of the interface layer, i.e. the thickness of the interface layer, may be in the range of at least 1 μm, such as at least 2 μm or such as at least 5 μm, to at most 50 μm, such as at most 25 μm or such as at most 10 μm. Possibly, the thickness of the interface layer is at most 50% of the thickness of the device layer, optionally at most 20% of the thickness of the device layer, further optionally at most 5% of the thickness of the device layer.

[0046] The vertical dimension of the substrate may be in the range of 100 μm to 800 μm, for example in the range of 200 μm to 500 μm.

[0047] As a general rule, the thickness of the interface layer may be small if compared to the thickness of the substrate. For example, the thickness of the interface layer may be no more than 20% or alternatively 10% of the thickness of the substrate.

[0048] The material of the interface layer may correspond to the material of the substrate and / or the device layer. Typically, the substrate, the interface layer and the device layer are made of SiC. Hereinafter, the term "made of" is to be understood within the usual manufacturing tolerances and does not exclude the presence of impurities and / or dopants. It is possible, but not mandatory, that the interface layer is made of epitaxial SiC. In some contexts, the atomic level of SiC may vary between the substrate, the interface layer and the device layer. For example, it will be possible that the substrate, the interface layer and the device layer all comprise SiC in crystalline form, but, for example, according to different polytypes. It will also be possible that the substrate, the interface layer and the device layer all comprise SiC in crystalline form and in the same polytype.

[0049] As a general rule, in the various examples described herein, an epitaxial growth process can be used to provide crystalline SiC, for example, for device layers and optionally for interface layers. This can include the use of chemical vapor deposition (CVD) and / or sublimation epitaxy. For example, a step-controlled epitaxial growth process can be used, see, for example: Matsunami, Hiroyuki and Tsunenobu Kimoto, "Step-controlled epitaxial growth of SiC: High quality homoepitaxy", Materials Science and Engineering: R: Reports 20.3 (1997): 125-166. Such a step-controlled epitaxial growth process generally relies on the deviation orientation direction of the crystallographic plane of the substrate. For example, in the case of 4H-SiC, this crystallographic plane can be the SiC (1,1,-2,0) plane. Typically, in the case of 4H-SiC, the deviation direction encloses an angle of 4°-5° with respect to the SiC (1,1,-2,0) plane. Crystal growth is achieved on a platform or island on the surface of the material. The adsorbed species of CVD are incorporated into such terrace steps.

[0050] The interface layer can be designed to provide various functions. For example, the interface layer can be designed to inhibit the propagation of defects (such as stacking errors and / or dislocations) from the substrate into the device layer. Alternatively or additionally, the interface layer can be designed to enable separation of the substrate from the device layer to thereby facilitate reuse of the substrate in another process for forming another semiconductor device.

[0051] As such, a method includes providing an interface layer of SiC. The interface layer is supported by a SiC substrate. The method also includes providing a device layer of epitaxial SiC on the interface layer. The method also includes forming a plurality of semiconductor devices in the second layer. The method also includes separating the substrate from the second layer at the first layer.

[0052] There are various design options available for the interface layer to provide such functionality. For example, the interface layer may include a plurality of cavities. The cavities may be defined within the material of the interface layer.

[0053] In various examples described herein, different types of cavities may be relied upon. In one example, the cavity may be defined by an interface layer having porosity. Such a porous interface layer may be obtained from electrochemical etching (e.g., photoelectrochemical etching). Here, it is generally not required to use epitaxial SiC. Typically, the collection of pores of such a porous interface layer may not exhibit a preferred direction or any large-scale magnitude. More specifically, the pores of the porous layer may exhibit a statistical distribution of size and / or shape and / or orientation. It will be possible that the pores form an interconnected network. In other words, the porous layer may be a sponge-type porous layer.

[0054] In another example, the cavity can be realized by a pore. The pores are generally of a trimmed size and / or shape and / or orientation. For example, the pores can be defined in a top-down process using well-controlled process parameters. As such, although the pores may also exhibit a distribution of size and / or shape and / or orientation, the width of such a distribution may be significantly smaller than the width of the corresponding distribution of pores for the reference porous layer. Specifically, the pores can be aligned with a preferred direction and can exhibit a large-scale magnitude.

[0055] In any case, providing cavities (eg holes and / or voids) in the interface layer can help reduce the defect density in the device layer. Furthermore, separation of the substrate from the device layer is supported by the reduced structural rigidity and / or stability of the interface layer caused by the cavities.

[0056] The following examples will be described below.

[0057] Example 1. A method comprising:

[0058] - providing a first layer (101) of silicon carbide (e.g. epitaxial silicon carbide) supported by a silicon carbide substrate (130),

[0059] - providing an epitaxial second layer (102) of silicon carbide on the first layer (101),

[0060] - forming a plurality of semiconductor devices (105, 105-1, 105-2, 105-3) in the second layer (102), and

[0061] - separating the substrate (130) from the second layer (102) at the first layer (101),

[0062] The first layer (101) includes a plurality of pores (150).

[0063] Example 2. The method described in Example 1,

[0064] Wherein providing the first layer (101) includes using a trench filling process (2101) to define the plurality of pores (150).

[0065] Example 3. The method described in Example 2,

[0066] The trench filling process (2101) includes at least one of dry etching of the trench (160) defined by photolithography, damage implantation of the trench (160), and electrochemical etching of the trench (160).

[0067] Example 4. The method described in any one of the preceding examples,

[0068] The providing of the first layer (101) comprises using an epitaxial growth process.

[0069] Example 5. The method described in Example 2 or 3 and Example 4,

[0070] wherein the epitaxial growth process for providing the first layer (101) is a step-controlled epitaxial growth process using an off-orientation direction (161) with respect to a crystallographic plane of the substrate (130),

[0071] The trench (160) of the trench filling process (2101) encloses an angle (162) of at least 1°, optionally at least 5°, and further optionally at least 85° with respect to the deviation orientation direction (161).

[0072] Example 6. The method described in Example 4 or 5,

[0073] The growth rate of the step-controlled epitaxial growth process of the first layer (101) is in a lateral overgrowth condition (965) for enclosing the pores (150) of the plurality of pores (150).

[0074] Example 7. The method described in any one of the preceding examples,

[0075] wherein providing the first layer (101) comprises using a reflow process,

[0076] The temperature of the reflow process is in a lateral closed condition for enclosing the pores (150) in the plurality of pores (150).

[0077] Example 8. The method described in any one of the preceding examples,

[0078] Wherein providing the first layer (101) comprises etching ridges (152) between adjacent pores (150) in the plurality of pores (150).

[0079] Example 9. The method described in any one of the preceding examples,

[0080] wherein the first layer (101) comprises a first sublayer (101-1) having a first pore density (301), and further comprises a second sublayer (101-2) having a second pore density (302),

[0081] wherein the first sublayer (101-1) of the first layer (101) is arranged between the second sublayer (101-2) of the first layer (101) and the substrate (130),

[0082] The first pore density (301) is greater than the second pore density (302).

[0083] Example 10. The method described in any one of the preceding examples,

[0084] wherein providing the second layer (102) comprises using an epitaxial growth process,

[0085] The second layer (102) includes a first sublayer (102-1) and a second sublayer (102-2),

[0086] wherein the first sublayer (102-1) of the second layer (102) is arranged between the second sublayer (102-2) of the second layer (102) and the first layer (101),

[0087] The growth rate (312-1) of the epitaxial growth process of the first sublayer (102-1) of the second layer (102) is lower than the growth rate (312-2) of the epitaxial growth process of the second sublayer (102-2) of the second layer (102).

[0088] Example 11. The method described in any one of the preceding examples,

[0089] wherein the pores (150) in the plurality of pores (150) have an elongated shape,

[0090] Wherein the longitudinal axes (151) of the pores (150) in the plurality of pores (150) are aligned with each other.

[0091] Example 12. The method described in any one of the preceding examples,

[0092] The pores (150) of the plurality of pores (150) are arranged in a transverse pattern defined in the first layer (101).

[0093] Example 13. The method described in any one of the preceding examples,

[0094] The first layer (101) includes a dopant that defines the resistivity of the first layer (101), and the resistivity of the first layer (101) is less than the resistivity of the substrate (130).

[0095] Example 14. The method of any of the preceding examples, further comprising:

[0096] - planarizing the first layer (101) prior to providing the second layer (102).

[0097] Example 15. The method described in any one of the preceding examples,

[0098] wherein the first layer (101) comprises a light absorbing material,

[0099] The separation of the substrate (130) and the second layer (102) comprises damaging the first layer (101) using a laser (250) absorbed by a light absorbing material.

[0100] Example 16. The method described in Example 15,

[0101] The light absorbing material comprises at least one of at least one carbon layer obtained from an annealing process for providing the first layer (101) and a dopant.

[0102] Example 17. The method described in any one of the preceding examples,

[0103] wherein separating the substrate (130) from the second layer (102) comprises at least one of:

[0104] - injecting a fluid into the plurality of pores (150) and cooling the fluid to below its freezing point;

[0105] - Rapid pressure changes; and

[0106] - Micro-electro-discharge machining at the first layer (101).

[0107] Example 18. The method of any of the preceding examples, further comprising:

[0108] - Providing protective material at the vertical edges etched into the second layer (102).

[0109] Example 19. The method of any of the preceding examples, further comprising:

[0110] - vertically dicing the second layer (102) to singulate the semiconductor devices (105, 105-1, 105-2, 105-3) of the plurality of semiconductor devices (105, 105-1, 105-2, 105-3),

[0111] The second layer (102) is diced before separating the substrate (130) from the second layer (102).

[0112] Example 20. The method of any of the preceding examples, further comprising:

[0113] - depositing a backside metallization layer on the remaining part of the first layer (101) after said separation of the substrate (130) from the second layer (102).

[0114] Example 21. The method described in any one of the preceding examples,

[0115] wherein the first layer (101) is provided at a first growth rate (311-1, 311-2),

[0116] wherein the second layer (102) is provided at a second growth rate (312-1, 312-2),

[0117] The first growth rate is less than the second growth rate.

[0118] Example 22. A method comprising:

[0119] - providing a first layer (101) of porous silicon carbide;

[0120] - providing an epitaxial second layer (102) of silicon carbide on the first layer (101);

[0121] - forming a plurality of semiconductor devices (105, 105-1, 105-2, 105-3) in the second layer (102); and

[0122] - Separating the substrate (130) from the second layer (102) at the first layer (101).

[0123] Example 23. The method described in any one of the preceding examples,

[0124] wherein the thickness (102A) of the second layer (102) is at least 20 μm, optionally at least 50 μm; or

[0125] The thickness (102A) of the second layer (102) is at most 30 μm, optionally at most 20 μm.

[0126] Example 24. The method of any of the preceding examples, further comprising:

[0127] - defining drift regions of the plurality of semiconductor devices (105, 105-1, 105-2, 105-3) in the second layer (102).

[0128] - defining drain regions or backside emitter regions of the plurality of semiconductor devices (105, 105-1, 105-2, 105-3) in the second layer (102).

[0129] The thickness of the drain region or the backside emitter region may or may not be greater than the thickness of the drift region.

[0130] Example 25. The method described in any one of the preceding examples,

[0131] Wherein providing the first layer (101) comprises using an electrochemical etching process.

[0132] Example 26. A wafer comprising:

[0133] - a silicon carbide substrate (130), and

[0134] - a first layer (101) of silicon carbide supported by a silicon carbide substrate (130),

[0135] The first layer (101) includes a plurality of pores (150).

[0136] Example 27. The wafer of Example 26, further comprising:

[0137] - a second layer (102) of epitaxial silicon carbide comprising drift regions of a plurality of semiconductor devices and also comprising drain regions or backside emitter regions of the plurality of semiconductor devices.

[0138] The thickness of the drain region or the backside emitter region may or may not be greater than the thickness of the drift region.

[0139] Example 28. The wafer according to Example 26 or Example 27,

[0140] wherein the thickness (102A) of the second layer (102) is at least 20 μm, optionally at least 50 μm; or

[0141] The thickness (102A) of the second layer (102) is at most 30 μm, optionally at most 20 μm.

[0142] The examples described above can be combined with each other to derive additional examples. For example, it would be possible to apply the techniques described in conjunction with the first layer including pores for separating the second layer from the substrate to the same scenario in which the first layer includes holes. The additional techniques described with respect to the above methods can be applied to examples involving wafers. For example, such methods can be used to manufacture wafers.

[0143] Figure 1 is a flow chart of a method according to various examples. Figure 1 The method corresponds to an example process according to the technology described in this article.

[0144] At block 1001, a first layer is provided. The first layer is supported by a substrate. The first layer may be provided in or on a substrate. The substrate is provided by a wafer.

[0145] The first layer corresponds to the interface layer described above.For example, the interface layer may comprise a plurality of cavities, for example realized by holes or pores.

[0146] In the scenario where the interface layer includes a plurality of pores, an epitaxial growth process may be used to provide the interface layer. As such, the interface layer may be made of epitaxial SiC. Another option would be to define the interface layer in the substrate, also made of epitaxial SiC; in such a scenario, a dedicated epitaxial growth process may not be required to provide the interface layer.

[0147] In other scenarios where the interfacial layer includes pores, electrochemical etching can be used to provide the interfacial layer. In such an example, the electrochemical solution based on aqueous hydrofluoric acid (HF) can contain some additives, such as surfactants, ethanol, isopropanol. The concentration of HF is typically in the range of less than 50% by volume. The ratio between aqueous HF and additives can be 3:1, 2:1, 1:2, 1:1, 3:1, 1:4 (measured by weight). Depending on the voltage conditions used for the anodizing process, voltages below 100V or even lower (less than 10V) can be used, depending on whether the process is carried out under additional UV irradiation. The current density can set the pore density (sometimes also referred to as porosity) of the porous layer. For example, a typical current density is 10μA / cm 2 -100mA / cm 2 The pore density is a measure of the empty space in the material of the interface layer. Typically, it is defined as the volume fraction of empty material over the total volume, and thus can vary between 0% and 100%.

[0148] After etching, cleaning and drying may be performed. As a general rule, it will be likely that the interface layer is made of 4H-SiC polytype. In particular, in such a configuration, it will be likely that when the (0001) silicon face faces outward (if Another option would be to make the interface layer from 6H-SiC polytype.

[0149] Next, at block 1002, a second layer is provided. A second layer is provided on the interface layer. The second layer corresponds to the device layer described above.

[0150] Block 1002 may include an epitaxial growth process for depositing a drain region (e.g., an n-doped drain region), a buffer region (e.g., an n-doped buffer region), and / or a back emitter region onto the interface layer. For devices having a blocking capability below 3.5 kV, the thickness of the drain region or the back emitter region may be greater than the thickness of the drift region.

[0151] Block 1002 may include an epitaxial growth process for depositing a drift region.

[0152] Block 1002 may include a hydrogen pre-treatment to promote a defect-free growth process. See, for example, Feenstra, Randall M., and Colin EC Wood, Porous SiC and gallium nitride: epitaxy, catalysis, and biotechnology applications, John Wiley & Sons, 2008.

[0153] At block 1003, a plurality of semiconductor devices are formed in the device layer. This may include front-side processing to define body regions, source regions, emitter regions, and / or electrical contacts of the semiconductor devices.

[0154] At block 1004, the substrate is separated from the device layer at the interface layer. This may include supporting the device layer on a carrier before applying a force to trigger separation.

[0155] Block 1004 produces one or more dies or chips including the plurality of semiconductor devices. Block 1004 also produces the remainder of the substrate. For example, any residue of the interface layer on the substrate may be removed, for example, by grinding or polishing. For example, ultrafast polishing may be employed.

[0156] At optional block 1005, a backside metallization layer is deposited onto the backside of the one or more dies obtained from block 1004. In general, the backside metallization layer may be deposited onto the remaining portion of the interface layer attached to the device layer after the separation.

[0157] Block 1005 is optional. In some scenarios, instead of performing block 1005, it would be possible to: provide a dopant in the interface layer at block 1001; thereby, the resistivity of the interface layer can be less than the resistivity of the substrate. The remaining portion of the interface layer adjacent to the device layer can then exhibit a substantial conductivity that promotes an ohmic backside contact. The increased roughness of the backside provided by the remaining interface layer can contribute to the reduced contact resistance.

[0158] Figure 1 The method promotes the suppression of the propagation of defects from the substrate to the device layer. This corresponds to an improvement in the crystalline quality of the device layer if compared to the crystalline quality of the substrate; this promotes the use of substrates with reasonable defect density. Generally, SiC substrates with particularly low defect density are more expensive if compared to SiC substrates with relatively high defect density. In the technology described herein, it is possible to improve the defect density with the help of an interface layer; therefore, it may not be required to rely on a particularly high-quality substrate. The cavity in the interface layer stops or reduces the propagation of extended stacking errors and other defects.

[0159] pass Figure 1The dashed arrow in illustratively shows the possibility of reusing a substrate. Specifically, the remaining portion of the substrate obtained from performing block 1004 can be used as input for further iterations of blocks 1001-1005. Depending on the level of material wear at each iteration, a large number of iterations are supported by reusing a single substrate, potentially any number. In some examples, to compensate for material wear, it would be possible to provide an additional layer of epitaxial SiC after separating the substrate at block 1004. Thereby, the original thickness of the substrate can be preserved.

[0160] Combination Figure 2 A schematic diagram is used to describe the Figure 1 The method defines additional details of the process.

[0161] Figure 2 Various aspects related to processing SiC according to various examples are illustrated.

[0162] At process step 2001, a substrate 130 is provided. Figure 2 Illustrated in is a vertical direction z along which a thickness 133 of the substrate is defined. Also illustrated are a front side 131 and a back side 132 of the substrate 130 .

[0163] At process step 2002, an interface layer 101 is provided on substrate 130. Interface layer 101 is adjacent to front side 131. Interface layer 101 includes cavities. For example, interface layer 101 may be a porous layer or may include pores.

[0164] The interface layer 101 is provided using a growth process such as an epitaxial growth process. Typically, the thickness of the interface layer may be in the range of at least 1 μm to at most 50 μm or in the range of at least 2 μm to at most 10 μm.

[0165] After block 2002 the silicon face may face upward.

[0166] It would be possible to planarize the interface layer 101 after using the growth process and before process step 2003 .

[0167] At process step 2003, a device layer 102 is provided on the interface layer 101. Typically, the thickness 102A of the device layer 102 may be at least 10 μm, optionally at least 50 μm or at least 100 μm or at least 150 μm.

[0168] In other examples, a particularly small thickness of the device layer 102 may be provided at the process step 2003. For example, the thickness 102A of the device layer 102 may be at most 30 μm or at most 20 μm.

[0169] As a general rule, there may be a tendency to size the thickness of the device layer 102 to be as small as possible but as large as required. Various properties of the semiconductor device may depend on the thickness of the device layer 102, and in particular, trade-offs may occur. (i) A smaller thickness may provide better thermal properties, for example, heat may be more efficiently dissipated to a carrier or heat sink; (ii) A smaller thickness may provide faster and cost-effective processing; (iii) A larger thickness may increase, for example, the breakdown voltage of a transistor implemented by the semiconductor device; (iv) A larger thickness may provide increased structural stability to the resulting chip and when separating the device layer 102 from the substrate 130; (v) A larger thickness may result in a higher Ron.

[0170] An epitaxial growth process is used to provide the device layer 102. It is possible that the growth rate of the growth process used to provide the device layer 102 is greater than the growth rate of the growth process used to provide the interface layer 101. This may facilitate a large thickness 2003A of the device layer 102.

[0171] For example, a large growth rate of the growth process for providing device layer 102 can be facilitated by a high quality epitaxial growth process for providing interface layer 101. Planarization of interface layer 101 can also help support a large growth rate for providing device layer 102. Options for planarizing the surface include: chemical mechanical planarization; polishing; and damage etching. All of this facilitates the morphology of device layer 102 that supports low defect density and high yield of semiconductor device 105 formed at process step 2004.

[0172] Providing the device layer 102 may include defining a drift region for the semiconductor device 105 formed at process step 2004 .

[0173] At process step 2004, semiconductor devices 105 are formed in device layer 102. This includes forming electrical contacts and the like.

[0174] At process step 2005, the front side carrier 106 is attached to the device layer 102. Figure 2 In the example of , the front side carrier 106 remains attached to the device layer 102; in other examples ( Figure 2 In the process (not shown), the front side carrier 106 can be removed, for example at process step 2007.

[0175] At process step 2006 , the device layer 102 is separated from the substrate 130 at the interface layer 101 . Figure 2 Fracture 171 is shown in the figure.

[0176] As a general rule, there are various options available for inducing fracture 171 for separating substrate 130 .

[0177] In the first option, a backside laser process can be used, such as Figure 2 Here, laser 250 is irradiated onto the back side 132 of substrate 130, which causes damage to interface layer 101 due to light absorption and heating. This is facilitated by the transparency of SiC of substrate 130 with respect to laser 250. The damage to interface layer 101 further reduces the structural rigidity of interface layer 101, so that eventually fracture 171 is generated.

[0178] In order to further enhance such damage, it would be possible for the interface layer 101 to include a light absorbing material. Then, the substrate 130 can be separated from the device layer 102 by using a laser 250 absorbed by the light absorbing material. Dopants can be used as light absorbing materials. Similarly, one or more carbon layers (e.g., graphene) can be used as light absorbing materials. For example, such carbon atoms can be obtained from an annealing process applied to the interface layer 101 at process step 2002. If a light absorbing material is supplied in the interface layer 101, it may not be required to focus the laser 250 so that the highest intensity is observed at the interface layer 101. More precisely, the absorption at the interface layer 101 can be increased by means of the light absorbing material, rather than the spatially varying intensity of the laser 250. This reduces the complexity of process step 2006.

[0179] In a second option, in order to promote the fracture 171, i.e., to trigger the separation of the substrate 130 from the device layer 102, at least part of a cold splitting process can be used, see, for example, Swoboda, Marko et al., “Laserassisted SiC wafering using COLD SPLIT”, Materials Science Forum, Vol. 897, Trans Tech Publications, 2017. Here, a layer comprising one or more polymers can be deposited, for example, on the front side of the device layer 102. The polymer can have a different thermal expansion coefficient than the substrate 130. Then, when cooling, the length and / or volume change of the polymer induces mechanical stress, which leads to the fracture 171. Generally, due to the reduced structural rigidity of the interface layer 101, the mechanical stress induced by such a length change of the polymer layer can even be sufficient to cause separation; then, it may not be required to additionally employ a backside laser process. Therefore, the backside laser process is generally optional.

[0180] In a third option, separating the substrate 130 may alternatively or additionally include injecting a fluid into the pores of the interface layer 101. The fluid may then be cooled below its freezing point. The expansion of the fluid under transition to a solid state may also induce mechanical stresses that lead to fracture 171. For example, water in a fluid state or a gaseous state may be used.

[0181] In a fourth option, separating the substrate 130 may alternatively or additionally include a water spray process.

[0182] In a fifth option, the separation substrate 130 may alternatively or additionally include micro-electro-discharge machining (μEDM) in the interface layer 101 .

[0183] In a sixth option, separating the substrate 130 may alternatively or additionally include applying a rapid pressure change to induce stress.

[0184] At process step 2007, a backside metallization layer 107 is provided at the backside 132 on the remaining portion of the interface layer 101. Again, this is optional. Alternatively, the interface layer may be removed.

[0185] At process step 2008, vertical dicing of the device layer 102 is performed to singulate the semiconductor devices 105. A corresponding KERF structure may be used to define dicing lines 172.

[0186] exist Figure 2 In the scenario of FIG. 2 , the dicing of process step 2008 is after the separation of substrate 130 occurring at process step 2006. In other examples, it would be possible to singulate semiconductor devices 105 by performing dicing before separating substrate 130 from device layer 102, e.g., before process step 2006 and after process step 2005.

[0187] Figure 3 Various aspects related to processing SiC according to various examples are illustrated.

[0188] Figure 3 The processing generally corresponds to Figure 2 For example, process step 2011 corresponds to process step 2001. Process step 2013 corresponds to process step 2003. Process step 2014 corresponds to process step 2004. Process step 2015 corresponds to process step 2005. Process step 2016 corresponds to process step 2006. Process step 2017 corresponds to process step 2007. Process step 2018 corresponds to process step 2008.

[0189] In process step 2012, interface layer 101 - unlike process step 2002 - is not provided as an epitaxial layer on substrate 130 using a growth process, but is provided in substrate 130. For example, cavities may be defined in the top layer of substrate 130 by appropriately structuring it. Figure 4 is a flow chart of a method according to various examples. For example, Figure 4 The method can be combined Figure 1 Block 1001 is adopted to provide an interface layer 101 .

[0190] Specifically, Figure 4 Various aspects regarding defining a plurality of pores in the interface layer 101 are illustrated.

[0191] The method begins with block 1011. Block 1011 is an optional block. In block 1011, an epitaxial growth process is performed, specifically, a step-controlled epitaxial growth process. Crystalline SiC is deposited on a substrate (see Figure 2 In other implementations, the interface layer may be defined in the substrate so that no additional material need be deposited on top of the substrate (see Figure 3 Process step 2012).

[0192] Next, at block 1012, an etch mask is photolithographically defined, for example, using a resist and its exposure. The etch mask defines the shape of the trench. Figure 5 An example etch mask 165 is illustrated in FIG. A longitudinally shaped trench 160 is illustrated. Figure 5 is a top view; the lateral plane of the wafer corresponds to the plane of drawing.

[0193] Specifically, trench 160 encloses an angle 162 of deviation from orientation direction 161 of the step-controlled epitaxial growth process with respect to block 1011. For example, angle 162 may be at least 1°, optionally at least 5°, further optionally at least 85°. For example, the angle may be 90°±5°.

[0194] Refer again Figure 4 Next, at block 1013, trenches 160 are etched. Here, it is possible to use one or more of dry etching, damage implantation, and electrochemical etching to define trenches 160. Material is locally removed where the SiC is not protected by masking material 165 (e.g., photoresist and / or hard mask).

[0195] At block 1014, again, an epitaxial growth process is used to deposit SiC. Prior to depositing this material, the etch mask 165 is removed. By using the epitaxial growth process, the trenches are filled; this is why blocks 1012-1014 are sometimes referred to as trench fill process 2101. As will be appreciated, providing the interface layer 101 thus can include using the trench fill process 2101.

[0196] In some examples, it may be possible to implement multiple iterations of the trench fill process 2101, such as by Figure 4 As illustrated by the dashed arrows in . Thus, it is possible to provide the interface layer 101 with two or more sub-layers.

[0197] Using a trench fill process 2101 facilitates defining voids in the interface layer 101 . Figure 6 Details regarding aperture 150 are illustrated.

[0198] Figure 6 Aspects regarding the interface layer 101 including a plurality of pores 150 are illustrated. Figure 6 is along Figure 5 Cross-sectional view in the vertical direction z and line XX. Figure 6 Illustrated in FIG. 2 is the trench 160 defined by the trench fill process 2101 .

[0199] exist Figure 6 In FIG. 1 , the pores 150 are associated with the grooves 160. Figure 4 When depositing material at block 1014 of FIG. 1 , the pores 150 are created by overgrowth of the trenches 160. Thus, the pores 150 are provided in a top-down process and exhibit a preferred direction. For example, Figure 6 As shown in , the longitudinal axes 151 of the pores 150 are aligned with each other. This alignment is caused by the geometry and arrangement of the etching mask 165. Likewise, the etching mask 165 causes the arrangement of the pores 150 in the lateral pattern along the grooves 160. The pores 150 have an elongated shape along the z-direction. The pores 150 have a droplet shape. As such, the pores 150 are different from the pores of the porous layer, which are generally spherical.

[0200] As will be appreciated, in Figure 6 In some examples, the pores 150 do not form an interconnected network (sponge type cavities). In some examples, it may be desirable to define the pores 150 so that they form an interconnected network. For example, in the case where adjacent pores are connected to each other and / or for the case where the pores extend along the entire wafer in a direction perpendicular to the z-direction so that they reach the edge of the wafer, it is possible to inject a fluid for facilitating the separation of the substrate 130 by cooling the fluid below its freezing point. There are various options that can be used to define the pores 150 so that they form an interconnected network. According to the example options, suspend Figure 4 It would be possible to delay the growth process of the block 1014 in the embodiment of the present invention and, while postponing, etch the ridges 152 of the still-open pores 150. This etching may include oxidation of the material and subsequent hydrofluoric acid treatment of the oxidized material.

[0201] In some examples, such etching of ridges 152 may not be used to form an interconnect network; rather, it may enlarge the volume of individual pores 150 to further reduce the structural stability of interface layer 101. This further facilitates separation of device layer 102 from substrate 130 at interface layer 101.

[0202] As a general rule, various options are available for Figure 4 The formation of pores 150 is promoted when depositing material at block 1014. These options can be employed alone or in combination with each other.

[0203] A first option for promoting the formation of pores 150 includes appropriate selection of angle 162 (see Figure 5 ). Typically, sizing of angle 162 in the range of 4° to 90° can help facilitate enclosure of the pores.

[0204] A second option for promoting the formation of the pores 150 includes using a reflow process. Here, the lateral redistribution of the deposited SiC material encloses the pores 150. The growth process can be interrupted for such redistribution. The process parameters that promote redistribution include at least one of the following: high temperature, low pressure, a suitable gas atmosphere, for example with hydrogen. The temperature can be set so that it is in a lateral closed condition for enclosing the pores 150.

[0205] In a third option for promoting the formation of pores, the process parameters of the growth process can be set within the lateral overgrowth regime. Figure 7 This is illustrated graphically.

[0206] Figure 7 Various aspects of the process parameters for the epitaxial growth process of block 1014 are illustrated. The epitaxial growth process is a CVD process including reactants (in Figure 7 In the scenario, certain flow rates of hydrochloric acid or hydrogen chloride (HCl), vertical axis, and silane (SiH4), horizontal axis). Figure 7 As indicated in , the typical condition 965 for overgrowth to define the pores 150 relies on a relatively large silane flow rate and a relatively small HCl flow rate. This generally results in a small growth rate for material deposition. Generally, the growth rate of the epitaxial growth process of block 1014 can be set so that it is in the lateral overgrowth condition 965 for enclosing the pores 150. See, for example, Ji, Shiyang et al., “An empirical growth window concerning the input ratio of HCl / SiH4 gases in filling 4H-SiC trench by CVD,” Applied Physics Express 10.5 (2017): 055505.

[0207] Figure 8 Various aspects of pore density as a function of vertical position are illustrated. Figure 8 In the scenario, the interface layer 101 includes two sub-layers 101-1 and 101-2 (eg, obtained from multiple iterations of the trench filling process, see Figure 4 , dashed arrow). The sub-layer 101 - 1 is adjacent to the substrate 130 , and the sub-layer 101 - 2 is adjacent to the device layer 102 .

[0208] The pore density may generally correspond to the ratio between (i) the volume in which no SiC material is present in the interface layer (i.e., due to pores) and (ii) the total volume of the interface layer. Another metric associated with the pore density is the ratio between (i) the volume in which SiC material is present in the interface layer and (ii) the total volume of the interface layer.

[0209] For example, in various examples described herein, the ratio between (i) the volume in which SiC material is present in the interface layer and (ii) the total volume of the interface layer can be in the range of 10% to 90%, or alternatively in the range of 30% to 70%.

[0210] As illustrated, sub-layer 101 - 1 has a higher pore density 301 if compared to pore density 302 of sub-layer 101 - 2 .

[0211] On a general level, there may be a tendency to reduce the pore density 301, 302 for increasing distance in the vertical Z direction to the substrate 130. Thereby, seeding conditions for epitaxial growth of the device layer 102 may be improved. In particular, morphology may be improved.

[0212] Different pore densities 301, 302 may be achieved, for example, by changing the lateral pitch between adjacent trenches 160 and / or by changing the lateral geometric fill factor of the trenches 160. The pore densities 301, 302 may be varied by changing the growth rate of the epitaxial growth process used to fill the trenches 160. Fig. 9 Details on the growth rate are described in.

[0213] Fig. 9 Various aspects concerning growth rate as a function of vertical position are illustrated.

[0214] exist Fig. 9 In the embodiment, the interface layer 101 includes sub-layers 101-1 and 101-2. The device layer 102 includes sub-layers 102-1 and 102-2.

[0215] like Fig. 9 As shown in FIG. 1 , the growth rates 311 - 1 , 311 - 2 , 312 - 1 , 312 - 2 are increased for increasing the distance to the substrate 130 along the vertical Z direction. Fig. 9 In the scenario, increasing the growth rate is associated with sub-layers 101-1, 101-2, 102-1, and 102-2.

[0216] As a general trend, the growth rate can increase for increasing distance from the substrate 130 in the vertical Z direction, such as within the interface layer 101 and / or within the device layer 102. This helps avoid the propagation of disturbed surface morphology due to pores 150 in the interface layer 101. This promotes high quality semiconductor devices 105.

[0217] As will be appreciated, the average growth rate 312-1, 312-2 of the device layer 102 is greater than the average growth rate 311-1, 311-2 of the interface layer 101. This helps reduce processing time because typically the thickness of the device layer 102 is significantly greater than the thickness of the interface layer 101.

[0218] Fig.10 and 11 Various aspects of singulated semiconductor devices 105-1-105-3 are illustrated. Specifically, Fig.10 and 11 Various aspects related to protecting semiconductor devices 105 - 1 - 105 - 3 are illustrated.

[0219] Here, edge region 172 is etched. Then, protective material 180 (e.g. glass, epoxy or another oxide) is pressed into edge region 172 to cover the respective vertical edges of edge region 172. Then, dicing is performed along edge region 172 for singulating semiconductor devices 105-1-105-3 from each other. Edge passivation / edge protection is thereby provided.

[0220] The formation of the semiconductor devices 105, 105-1-105-3 can vary in the various examples described herein. For example, the so-called "high dynamic strength" (HDR) concept can be implemented, which improves the off strength of the device by reducing the free charge carrier density of the device in the junction termination region in the on-state of the device. Here, small cells along the laterally defined cut edges can be locally oxidized. Then, epitaxial lateral overgrowth can be applied to these locally oxidized areas. The area should be small enough to promote defect-free epitaxial lateral overgrowth on the one hand; on the other hand, the distance between adjacent areas should be small enough so that the injection of free charge carriers from the back side of the tube core is effectively suppressed.

[0221] Further possible modifications to the formation of the semiconductor device include defining cavities - such as holes and / or apertures - in the device layer 102 at 105, 105-1-105-3. Fig.12 This is illustrated graphically.

[0222] Fig.12Various aspects regarding defining cavities in the device layer 102 are schematically illustrated. For example, holes can be defined in laterally confined regions 178 of the device layer 102, such as using electrochemical etching. These regions 178 can be aligned with cuts 179 along which dicing is performed to singulate the semiconductor devices 105-1 to 105-3. For example, the vertical thickness 178A of these regions 178 can be greater than the thickness of the device layer 102 ( Fig.12 In other examples (see Fig.12 ), the vertical thickness 178A of these regions is less than the thickness 102A of the device layer 102, to thereby provide mechanical stabilization. It is optionally possible to deposit an epitaxially grown layer of SiC after defining the cavity in the region 178 (see Fig.12 , where region 178 does not extend completely to the front side of device layer 102). The cavity in region 178 facilitates singulation of semiconductor devices 105-1-105-3 along cut 179, for example by applying appropriate mechanical stress. Slicing may not be required. Edge quality may be increased.

[0223] Fig.13 Various aspects regarding the interface layer 101 comprising porous SiC are schematically illustrated. Fig.13 is a cross-sectional view of the interface layer 101 perpendicular to the z-direction, ie, in the xy plane. Fig.13 The diagram shows holes 601 at different z positions (z1 and z2), which are offset by a distance less than the average hole size 602. (It is noted that Fig.13 In the figure, for the sake of simplicity, not all holes are marked (601).

[0224] like Fig.13 As illustrated in , the pores 601 form an interconnected network (sponge-type pores). This means that on average, the number of interconnected pores 601 is significantly greater than 1, for example greater than 10 or greater than 100. Channels are formed between adjacent pores 601.

[0225] The holes 601 may, for example, have a spherical shape on average, i.e. have an average aspect ratio of 1. Some individual holes in the population of holes 601 may have an aspect ratio that deviates from 1, i.e. their length in the x-direction is different from their length in the y-direction (this aspect ratio is sometimes also called elongation or eccentricity). That means that the hole may have a longer extent in the vertical direction than in the lateral direction. The semiconductor structure between the holes may have, for example, a stalactite-like structure.

[0226] Fig.14 Various aspects regarding the interface layer 101 comprising porous SiC are schematically illustrated. Fig.14 An example of this generally corresponds to Fig.13 However, in Fig.14 In the example, if Fig.13 Compared with the scenario of Fig.13 Compared to the sample, the average pore size is 602 Fig.14 is smaller in the example.

[0227] The pore density may generally correspond to the ratio between (i) the volume in which no SiC material is present in the interface layer (i.e., due to pores) and (ii) the total volume of the interface layer. Another metric associated with the pore density is the ratio between (i) the volume in which SiC material is present in the interface layer and (ii) the total volume of the interface layer.

[0228] For example, in various examples described herein, the ratio between (i) the volume in which SiC material is present in the interface layer and (ii) the total volume of the interface layer can be in the range of 10% to 90%, or alternatively in the range of 30% to 70%.

[0229] exist Fig.14 In the embodiment, the pore density and pore size are configured such that an interconnected network of pores 601 is not formed.

[0230] It is possible to tailor such and other structural properties of pores 601 using appropriate processes for preparing porous interface layer 101. For example, the size and / or density of pores 601 can be adjusted by adjusting the current density of the electrochemical etching. In some examples, this is used to prepare multiple sub-layers of interface layer 101 with different pore densities and / or pore sizes. Fig.15 The corresponding scene is shown in the figure.

[0231] Fig.15 Various aspects regarding hole density as a function of vertical position are illustrated. Fig.15 In the scenario of FIG. 1 , the interface layer 101 includes two sub-layers 101 - 1 , 101 - 2 (eg, obtained from multiple iterations of an electrochemical etching process with adjusted process parameters). The sub-layer 101 - 1 is adjacent to the substrate 130 and the sub-layer 101 - 2 is adjacent to the device layer 102 .

[0232] As illustrated, sub-layer 101 - 1 has a higher hole density 801 if compared to the hole density 802 of sub-layer 101 - 2 .

[0233] On a general level, there may be a tendency to reduce the hole density 801, 802 for increasing the distance in the vertical Z direction to the substrate 130. Thereby, the seeding conditions for the epitaxial growth of the device layer 102 may be improved. In particular, the morphology may be improved.

[0234] Different hole densities 801, 802 may be achieved, for example, by varying the current density of the electrochemical etching.

[0235] For example, sub-layer 101 - 1 may have a hole density in the range of 40% to 70%; and sub-layer 101 - 2 may have a hole density in the range of 10% to 50%.

[0236] In some examples, sub-layer 101 - 1 may form an interconnected network of holes 601 ; whereas sub-layer 101 - 2 may not form an interconnected network of holes 601 .

[0237] For example, the thickness 101 - 1A of the sublayer 101 - 1 may be in the range of 0.5 μm to 50 μm. The thickness 101 - 2A may be in the range of 0.2 μm to 20 μm. Thus, the sublayer 101 - 2 may have a smaller vertical extension if compared to the sublayer 101 - 1 .

[0238] In summary, above, various techniques have been described that facilitate forming semiconductor devices in an epitaxial SiC device layer. The device layer is provided on an interface layer that includes cavities such as holes or pores. The interface layer is provided on a SiC substrate or defined in a SiC substrate near its front side.

[0239] These techniques facilitate the production of high-quality, high-yield power semiconductor devices. For example, the device layers (depending on the specific type of semiconductor device) may include a layer stack including a drain or emitter region and, optionally, a buffer region, a drift region, a p-doped body region and / or a source region or a front-side emitter.

[0240] The interface layer provides a function with respect to separating the substrate from the device layer; and / or a function with respect to a barrier against the propagation of defects.

[0241] In summary, the following examples have been described:

[0242] Although the invention has been shown and described with respect to certain preferred embodiments, equivalents and modifications will occur to others skilled in the art upon the reading and understanding of this specification. The present invention includes all such equivalents and modifications and is limited only by the scope of the appended claims.

[0243] For illustration, various techniques for separating the device layer from the substrate at the interface layer have been described for the scenario where the interface layer includes pores. Similar techniques can be readily applied to the scenario where the interface layer includes holes.

[0244] For further explanation, various techniques have been described with respect to methods including providing device layers and interface layers. A corresponding wafer can be obtained from such methods, wherein the wafer has structural properties characterized by such methods.

[0245] For further explanation, various techniques have been described in which a trench fill process is used to define voids in an epitaxially grown layer of SiC as a device layer. The trench fill process may also be used in conjunction with a scenario in which the device layer is defined in a substrate.

[0246] To further illustrate, various techniques have been described with respect to device layers having a relatively large thickness, such as at least 20 μm. Similar techniques may also be provided for relatively thin device layers, such as having a thickness of at most 20 μm.

[0247] To further illustrate, although various scenarios have been described with respect to SiC as the semiconductor material, similar techniques may be implemented in other kinds and types of wide bandgap semiconductor materials (eg, GaN, etc.).

Claims

1. A method comprising: - providing a first layer (101) of porous silicon carbide supported by a silicon carbide substrate (130), - providing an epitaxial second layer (102) of silicon carbide on the first layer (101), - forming a plurality of semiconductor devices (105, 105-1, 105-2, 105-3) in the second layer (102), and - Separating the substrate (130) from the second layer (102) at the first layer (101).

2. The method according to any one of the preceding claims, wherein the thickness (102A) of the second layer (102) is at least 20 μm, optionally at least 50 μm; or The thickness (102A) of the second layer (102) is at most 30 μm, optionally at most 20 μm.

3. The method according to claim 1 or 2, The porous silicon carbide of the first layer (101) forms an interconnected network of pores (601).

4. The method according to any one of the preceding claims, wherein the first layer (101) comprises a first sublayer (101-1) having a first pore density (801), and further comprises a second sublayer (101-2) having a second pore density (802), wherein the first sublayer (101-1) of the first layer (101) is arranged between the second sublayer (101-2) of the first layer (101) and the substrate (130), The first hole density (801) is greater than the second hole density (802).

5. The method according to any one of the preceding claims, The providing of the first layer (101) comprises using an epitaxial growth process.

6. The method according to any one of the preceding claims, Wherein providing the first layer (101) comprises using an electrochemical etching process.

7. The method according to any one of the preceding claims, wherein providing the second layer (102) comprises using an epitaxial growth process, The second layer (102) includes a first sub-layer (102-1) and a second sub-layer (102-2), wherein the first sublayer (102-1) of the second layer (102) is arranged between the second sublayer (102-2) of the second layer (102) and the first layer (101), The growth rate (312-1) of the epitaxial growth process of the first sublayer (102-1) of the second layer (102) is lower than the growth rate (312-2) of the epitaxial growth process of the second sublayer (102-2) of the second layer (102).

8. The method according to any one of the preceding claims, The first layer (101) includes a dopant that defines the resistivity of the first layer (101), and the resistivity of the first layer (101) is less than the resistivity of the substrate (130).

9. The method of any of the preceding claims, further comprising: - planarizing the first layer (101) prior to providing the second layer (102).

10. The method according to any one of the preceding claims, wherein the first layer (101) comprises a light absorbing material, The separation of the substrate (130) and the second layer (102) comprises damaging the first layer (101) using a laser (250) absorbed by a light absorbing material.

11. The method according to claim 10, The light absorbing material comprises at least one of at least one carbon layer obtained from an annealing process for providing the first layer (101) and a dopant.

12. The method according to any one of the preceding claims, wherein separating the substrate (130) from the second layer (102) comprises at least one of the following: - injecting a fluid into the porous silicon carbide of the first layer and cooling the fluid to below its freezing point; - Rapid pressure changes; and - Micro-electro-discharge machining at the first layer (101).

13. The method of any of the preceding claims, further comprising: - Providing protective material at the vertical edges etched into the second layer (102).

14. The method of any of the preceding claims, further comprising: - vertically dicing the second layer (102) to singulate the semiconductor devices (105, 105-1, 105-2, 105-3) of the plurality of semiconductor devices (105, 105-1, 105-2, 105-3), The second layer (102) is diced before separating the substrate (130) from the second layer (102).

15. The method of any of the preceding claims, further comprising: - depositing a backside metallization layer on the remaining part of the first layer (101) after said separation of the substrate (130) from the second layer (102).

16. The method according to any one of the preceding claims, wherein the first layer (101) is provided at a first growth rate (311-1, 311-2), wherein the second layer (102) is provided at a second growth rate (312-1, 312-2), The first growth rate is less than the second growth rate.

17. The method of any of the preceding claims, further comprising: - defining drift regions of the plurality of semiconductor devices (105, 105-1, 105-2, 105-3) in the second layer (102), and - defining drain regions or backside emitter regions of the plurality of semiconductor devices (105, 105-1, 105-2, 105-3) in the second layer (102), The thickness of the drain region or the back emitter region is greater than the thickness of the drift region.

18. A method comprising: - providing a first layer (101) of silicon carbide supported by a silicon carbide substrate (130), - providing an epitaxial second layer (102) of silicon carbide on the first layer (101), - forming a plurality of semiconductor devices (105, 105-1, 105-2, 105-3) in the second layer (102), and - separating the substrate (130) from the second layer (102) at the first layer (101), The first layer (101) includes a plurality of pores (150).

19. The method of claim 18, Wherein providing the first layer (101) includes using a trench filling process (2101) to define the plurality of pores (150).

20. The method of claim 19, The trench filling process (2101) includes at least one of dry etching of the trench (160) defined by photolithography, damage implantation of the trench (160), and electrochemical etching of the trench (160).

21. The method of any one of claims 18 to 20, The providing of the first layer (101) comprises using an epitaxial growth process.

22. The method of claim 19 or 20 and claim 21, wherein the epitaxial growth process for providing the first layer (101) is a step-controlled epitaxial growth process using an off-orientation direction (161) with respect to a crystallographic plane of the substrate (130), The trench (160) of the trench filling process (2101) encloses an angle (162) of at least 1°, optionally at least 5°, and further optionally at least 85° with respect to the deviation orientation direction (161).

23. The method of claim 21 or 22, The growth rate of the step-controlled epitaxial growth process of the first layer (101) is in a lateral overgrowth condition (165) for enclosing the pores (150) of the plurality of pores (150).

24. The method of any one of claims 18 to 23, wherein providing the first layer (101) comprises using a reflow process, The temperature of the reflow process is in a lateral closed condition for enclosing the pores (150) in the plurality of pores (150).

25. The method of any one of claims 18 to 24, Wherein providing the first layer (101) comprises etching ridges (152) between adjacent pores (150) in the plurality of pores (150).

26. The method of any one of claims 18 to 25, wherein the first layer (101) comprises a first sublayer (101-1) having a first pore density (301), and further comprises a second sublayer (101-2) having a second pore density (302), wherein the first sublayer (101-1) of the first layer (101) is arranged between the second sublayer (101-2) of the first layer (101) and the substrate (130), The first pore density (301) is greater than the second pore density (302).

27. The method of any one of claims 18 to 26, wherein providing the second layer (102) comprises using an epitaxial growth process, The second layer (102) includes a first sub-layer (102-1) and a second sub-layer (102-2), wherein the first sublayer (102-1) of the second layer (102) is arranged between the second sublayer (102-2) of the second layer (102) and the first layer (101), The growth rate (312-1) of the epitaxial growth process of the first sublayer (102-1) of the second layer (102) is lower than the growth rate (312-2) of the epitaxial growth process of the second sublayer (102-2) of the second layer (102).

28. The method of any one of claims 18 to 27, wherein the pores (150) in the plurality of pores (150) have an elongated shape, Wherein the longitudinal axes (151) of the pores (150) in the plurality of pores (150) are aligned with each other.

29. The method of any one of claims 18 to 28, The pores (150) of the plurality of pores (150) are arranged in a transverse pattern defined in the first layer (101).

30. The method of any one of claims 18 to 29, The first layer (101) includes a dopant that defines the resistivity of the first layer (101), and the resistivity of the first layer (101) is less than the resistivity of the substrate (130).

31. The method of any one of claims 18 to 30, further comprising: - planarizing the first layer (101) prior to providing the second layer (102).

32. The method of any one of claims 18 to 31, wherein the first layer (101) comprises a light absorbing material, The separation of the substrate (130) and the second layer (102) comprises damaging the first layer (101) using a laser (250) absorbed by a light absorbing material.

33. The method of claim 32, The light absorbing material comprises at least one of at least one carbon layer obtained from an annealing process for providing the first layer (101) and a dopant.

34. The method of any one of claims 18 to 33, wherein separating the substrate (130) from the second layer (102) comprises at least one of the following: - injecting a fluid into the plurality of pores (150) and cooling the fluid to below its freezing point; - Rapid pressure changes; and - Micro-electro-discharge machining at the first layer (101).

35. The method of any one of claims 18 to 34, further comprising: - Providing protective material at the vertical edges etched into the second layer (102).

36. The method of any one of claims 18 to 35, further comprising: - vertically dicing the second layer (102) to singulate the semiconductor devices (105, 105-1, 105-2, 105-3) of the plurality of semiconductor devices (105, 105-1, 105-2, 105-3), The second layer (102) is diced before separating the substrate (130) from the second layer (102).

37. The method of any one of claims 18 to 36, further comprising: - depositing a backside metallization layer on the remaining part of the first layer (101) after said separation of the substrate (130) from the second layer (102).

38. The method of any one of claims 18 to 37, wherein the first layer (101) is provided at a first growth rate (311-1, 311-2), wherein the second layer (102) is provided at a second growth rate (312-1, 312-2), The first growth rate is less than the second growth rate.

39. The method of any one of claims 18 to 38, further comprising: - defining drift regions of the plurality of semiconductor devices (105, 105-1, 105-2, 105-3) in the second layer (102), and - defining drain regions or backside emitter regions of the plurality of semiconductor devices (105, 105-1, 105-2, 105-3) in the second layer (102), The thickness of the drain region or the back emitter region is greater than the thickness of the drift region.

40. A wafer comprising: - a silicon carbide substrate (130), and - A first layer (101) of porous silicon carbide supported by a silicon carbide substrate (130).

41. A wafer comprising: - a silicon carbide substrate (130), and - a first layer (101) of silicon carbide supported by a silicon carbide substrate (130), The first layer (101) includes a plurality of pores (150).

42. The wafer of claim 41 further comprising: - a second layer (102) of epitaxial silicon carbide, comprising drift regions of a plurality of semiconductor devices, and also comprising drain regions or backside emitter regions of the plurality of semiconductor devices, The thickness of the drain region or the back emitter region is greater than the thickness of the drift region.

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