Reconfigurable auxiliary circuit for reducing power supply voltage fluctuation of multi-core CPU

Abstract

The invention discloses a reconfigurable auxiliary circuit for reducing power supply voltage fluctuation of a multi-core CPU. The reconfigurable auxiliary circuit comprises a traditional VRM control circuit, a single-phase voltage reduction auxiliary circuit, a back-to-back switch tube, a differentiator, a window comparator and a high-dynamic nonlinear closed-loop control circuit. The output end of a main core VRM controller of each phase in the traditional VRM control circuit is connected with a back-to-back switch tube, and a single-phase voltage reduction auxiliary circuit is connected with the back-to-back switch tube of each phase. The differentiator collects the output voltage of the main core VRM controller of each phase and then connects the output voltage with the high-dynamic nonlinear closed-loop control circuit through the window comparator; the high-dynamic nonlinear closed-loop control circuit is connected with the single-phase step-down auxiliary circuit; and the high-dynamic nonlinear closed-loop control circuit outputs a PWM pulse control signal for controlling the output of a power level in the main core VRM controller and outputting a transistor switch control signal. According to the invention, by dynamically adjusting the load connection, the voltage fluctuation under the multi-core condition is reduced.

Description

Technical Field

[0001] The invention belongs to the field of switching power supplies, and in particular relates to a reconfigurable auxiliary circuit for reducing voltage fluctuation of a multi-core CPU power supply. Background Art

[0002] Over the past few decades, switching power conversion technology has gradually matured and gradually promoted the development of advanced power design solutions in applications. The supply voltage of microprocessors has become lower and lower as the process size decreases, and high-performance microprocessors have brought about the development of technologies such as 5G data communication, artificial intelligence, high-performance computing and big data analysis. The application of these technologies has prompted the processor to require a large working current during operation. Therefore, the power supply chip of the microprocessor needs to have low voltage and high current capabilities. The design of the voltage regulator module (VRM) usually involves a trade-off between bandwidth capability and efficiency. On the one hand, it is expected to provide a fast response capability to load transients, which may require a switching frequency higher than the switching frequency usually required for steady-state loads. However, increasing the switching frequency will increase the switching loss and reduce the efficiency of the system. For low-voltage, high-current application scenarios, multi-phase buck converters have more advantages and are widely used in various occasions. Multi-phase buck converters can reduce input and output current ripples and have good distributed heat dissipation capabilities. More precise output voltage regulation and faster response time are also the main considerations for current VRM design.

[0003] In order to further improve the transient response of the new generation of central processing units (CPUs) without infinitely increasing the output capacitance of the circuit, a lot of research has focused on improving control methods and introducing auxiliary circuits. The currently widely used constant time (COT) control method and more advanced control methods, such as time optimal control (TOC), have approached the physical limit of dynamic response capabilities. Therefore, people have begun to pay attention to further improvements in auxiliary circuits. However, existing auxiliary circuit research has some defects and is not suitable for CPU power applications. Some studies require the CPU to provide comprehensive load step information to the auxiliary circuit, which has been difficult to achieve in recent years. Other studies usually rely on the current flowing through the output capacitor of the auxiliary circuit, but currently the output capacitor is usually composed of many ceramic capacitors in parallel, so obtaining current information through this method is difficult to achieve in today's CPU power applications. Summary of the invention

[0004] The purpose of the present invention is to provide a reconfigurable auxiliary circuit for reducing the voltage fluctuation of a multi-core CPU power supply, by dynamically adjusting its load connection, thereby minimizing the required output capacitance, effectively reducing the voltage fluctuation in a multi-core case, in order to solve the shortcomings of the background technology and fully utilize the advantages of the auxiliary circuit.

[0005] In order to solve the above technical problems, the specific technical solutions of the present invention are as follows:

[0006] A reconfigurable auxiliary circuit for reducing voltage fluctuations of a multi-core CPU power supply, comprising a conventional VRM control circuit, a single-phase step-down auxiliary circuit, a back-to-back switch tube, a differentiator, a window comparator and a high-dynamic nonlinear closed-loop control circuit;

[0007] In the traditional VRM control circuit, the output end of the main core VRM controller of each phase is connected to the back-to-back switch tube, and the single-phase buck auxiliary circuit is connected to the back-to-back switch tube of each phase; the single-phase buck auxiliary circuit consists of the upper switch tube S H and the lower switch tube S L and the inductor La as the current source; the upper switch tube S H Connected in series with the inductor La, the lower switch tube S L Connected in parallel between the two; when the load is boosted, the upper switch tube S H When the load voltage is reduced, the lower switch tube S L Switch on, absorb current from the load, suppress overshoot;

[0008] The differentiator collects the output voltage of the main core VRM controller of each phase and connects the output voltage to the high dynamic nonlinear closed-loop control circuit through the window comparator; the high dynamic nonlinear closed-loop control circuit is connected to the single-phase buck auxiliary circuit, and the high dynamic nonlinear closed-loop control circuit outputs a PWM pulse control signal for controlling the output of the power stage in the main core VRM controller and an output transistor switch control signal for controlling the upper switch tube S in the single-phase buck auxiliary circuit. H and the lower switch tube S L The control signal of each phase back-to-back switch tube is S N The PWM pulse control signal is calculated by a high dynamic nonlinear closed-loop control circuit, and a square wave signal with certain duty cycle information is generated through the PWM pulse control signal.

[0009] Furthermore, the inductance La is minimized to enhance the voltage fluctuation without affecting the steady-state efficiency of the main core VRM controller.

[0010] Furthermore, each group of back-to-back switch tubes consists of two back-to-back power MOS tubes connected in series. The purpose of using back-to-back MOS tubes is to enable the single-phase buck auxiliary circuit to switch between the connected cores, thereby reducing the need for multiple auxiliary circuits in multi-core power supplies. This operation relies on the fact that multiple cores will not undergo significant step changes at the same time.

[0011] Furthermore, the power stage circuit in the main core VRM controller is used to adjust the input voltage to a stable output voltage. The power stage circuit includes types such as Buck and Boost, and its structure is a combination of inductors and switches. In theory, the power stage circuit can combine any group of main phases with auxiliary circuits. For the convenience of explanation, the present invention takes the Buck circuit as an example. The power supply architecture adopted by the power stage circuit consists of two groups of reconfigurable buck converters, each group has six main phases and one auxiliary phase; the main phase uses a large inductor to reduce the overall circuit system loss, and the auxiliary phase uses a small inductor to improve the system dynamic performance.

[0012] Furthermore, the differentiator plays a vital role in determining when the auxiliary circuit stops absorbing or injecting more current. The output voltage V B Related to the derivative of the output voltage (dvout / dt). When the output voltage reaches the highest overshoot or the lowest undershoot, the slope of the output voltage becomes zero.

[0013] Furthermore, the differentiator is composed of a capacitor, a resistor and an operational amplifier; the window comparator is built by two operational amplifiers. The PWM pulse control signal is calculated by the nonlinear controller, and a square wave signal with a certain duty cycle information is generated through the PWM pulse control signal to control the single-phase auxiliary circuit switch tube S H and S L of on and off.

[0014] Furthermore, the control of the back-to-back switch tubes is divided into a three-cycle state machine. In the S0 cycle, the overall power architecture system circuit composed of each main core VRM controller is in a steady state, the back-to-back switch tubes are disconnected, and the system is not connected to the single-phase buck auxiliary circuit; after the load shedding signal is issued, it enters the S1 cycle. When the output voltage exceeds the negative threshold, the back-to-back switch tubes are turned on and S H Set high to provide additional high load slope current to the load through the small inductance La; when the load voltage undershoot reaches the minimum value, the system enters the S2 cycle, S H and S L The output of the differentiator is controlled with a specific duty cycle calculated by the differentiator, so that the source current decreases at a predetermined slope; once the detected current returns to zero, S H , S L The back-to-back switch tube is turned off and the system returns to the S0 cycle.

[0015] Furthermore, the slope of the current decrease is calculated by the following formula:

[0016]

[0017] Where d1 is the duty cycle of the load boost, V g is the input voltage, V OUTis the output voltage, L a is the inductance of the single-phase buck auxiliary circuit.

[0018] A reconfigurable auxiliary circuit for reducing power supply voltage fluctuation of a multi-core CPU of the present invention has the following advantages:

[0019] 1. The present invention adopts a reconfigurable auxiliary circuit for reducing the voltage fluctuation of the multi-core CPU power supply. The power stage circuit in the VRM controller uses a buck converter as a typical application. Compared with the traditional symmetrical multi-phase converter, it dynamically adjusts its load connection to minimize the required output capacitance, effectively reduces the voltage fluctuation in the multi-core case, improves the dynamic response speed and significantly reduces the voltage overshoot and undershoot.

[0020] 2. The reconfigurable auxiliary circuit used in the present invention to reduce the voltage fluctuation of the multi-core CPU power supply adopts a simple nonlinear control scheme, does not require a complex digital control method, reduces the use of devices such as ADC / DAC, and thus reduces the deployment cost. The auxiliary circuit can be connected to different cores by adding a pair of MOSFETs at its VRM connection, thereby further reducing the application cost.

[0021] 3. The present invention adopts a reconfigurable auxiliary circuit architecture for reducing the voltage fluctuation of the multi-core CPU power supply. The proposed single-phase step-down auxiliary circuit is completely independent and does not require special modification. It is applicable to most existing VRM controllers and has extremely high compatibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a schematic diagram of realizing a reconfigurable auxiliary circuit for reducing power supply voltage fluctuation of a multi-core CPU according to the present invention;

[0023] Figure 2 is a schematic diagram of a state machine for transistor switch control of a reconfigurable auxiliary circuit of the present invention;

[0024] Figure 3 It is a simplis simulation waveform diagram of the present invention in the application of reconfigurable multi-phase converter;

[0025] Figure 4 It is a hardware physical diagram of the dual-core power supply voltage controller of the present invention;

[0026] Figure 5 It is a practical hardware test diagram of the present invention in the application of the dual-core power supply voltage controller. DETAILED DESCRIPTION

[0027] In order to better understand the purpose, structure and function of the present invention, the following further describes in detail a reconfigurable auxiliary circuit for reducing power supply voltage fluctuation of a multi-core CPU according to the present invention in conjunction with the accompanying drawings.

[0028] Figure 1 The schematic diagram of the implementation of a reconfigurable auxiliary circuit to reduce the voltage fluctuation of the multi-core CPU power supply includes a traditional VRM control circuit, a single-phase buck auxiliary circuit, a back-to-back switch tube, a differentiator, a window comparator, and a high dynamic nonlinear closed-loop control circuit. In the traditional VRM control circuit, the output end of the main core VRM controller of each phase is connected to the back-to-back switch tube, and the single-phase buck auxiliary circuit is connected to the back-to-back switch tube of each phase; the differentiator collects the output voltage of the main core VRM controller of each phase and connects the output voltage to the high dynamic nonlinear closed-loop control circuit through the window comparator. Among them, the VRM controller connected to each group of CPU cores contains a 6-phase interleaved buck converter, and the auxiliary circuit is a single-phase buck converter. The single-phase buck auxiliary circuit uses a small filter inductor L small . High dynamic nonlinear closed-loop control circuit sampling auxiliary circuit inductor current I La And each core VRM controller output voltage V OUT The differentiator output voltage V B The output voltage of the window comparator is used to output the PWM pulse control signal and the upper switch tube S in the single-phase buck auxiliary circuit. H and the lower switch tube S L The switch control signal and the corresponding back-to-back switch control signal S N To drive the MOS tube on and off.

[0029] When the system is loaded, the auxiliary circuit needs to turn on the back-to-back switch tubes to provide additional high load slope current to the load. At this time, the current flows from the input end to the load; conversely, when the load is unloaded, the auxiliary circuit needs to absorb excess energy, and the current flows from the load to the input end. Therefore, the switch unit connecting the main core VRM controller and the auxiliary circuit needs to have a good current bidirectional flow function, and back-to-back switch tubes are a good choice.

[0030] In actual applications, if two sets of back-to-back switch tubes are closed at the same time, the auxiliary circuit is connected to two sets of core VRM controllers at the same time. Since the output voltage of each set of core VRM controllers is very likely to be inconsistent, surge current may be generated at this time, causing adverse effects on the entire system and load. Therefore, in order to avoid the above phenomenon, the auxiliary circuit is usually connected to only one set of core VRM controllers at the same time. In addition, in order to reduce switching loss and conduction loss, parasitic parameters such as parasitic resistance and capacitance on the coupling path can usually be reduced to further improve efficiency.

[0031] Figure 2 The schematic diagram of the state machine of the transistor switch control of the reconfigurable auxiliary circuit during load switching is shown in FIG. Figure 2 (a) is the state diagram of the back-to-back switch tubes when the output voltage overshoots and undershoots; Figure 2(b) is the state transition diagram of the back-to-back switch tube. In the present invention, the state machine is set to 3 cycles to realize the reconfigurable switch control, such as Figure 2 (b) In the S0 steady state, all reconfigurable path switches are off. During a core boost load transient, when the output voltage exceeds the negative threshold, the load and S H The back-to-back switches will be activated and the system will enter S1 state. This will provide additional high load slope current to the load through the smaller inductor La. When the undershoot reaches the minimum value, S H and S L The output of the differentiator is controlled at a specific duty cycle, so that the source current decreases at a predetermined slope, and the system enters the S2 state. Once the detected current returns to zero, S H , S L The back-to-back switch tube is turned off and the system returns to S0 state. The slope of the current decrease can be calculated by the following formula:

[0032]

[0033] Where d1 is the duty cycle of the load boost, V g is the input voltage, V OUT is the output voltage, L a is the inductance of the single-phase buck auxiliary circuit. The value of k1 should be appropriately selected to ensure that when the current in the auxiliary circuit decreases, the core VRM controller can react in time to avoid voltage undershoot.

[0034] The single-phase buck auxiliary circuit operates similarly during buck load transients.

[0035] Figure 3 This is a simplis simulation waveform diagram of the present invention in the application of reconfigurable multi-phase converter. The specifications are as follows: V IN =12V, V OUT =1V, I OUT =50-300A, load slope is ±1250A / μs, La=12nH. The simulation results of the proposed auxiliary circuit show the waveforms of output current, output voltage, auxiliary phase output current and auxiliary phase output voltage when the load is light to heavy and heavy to light. As can be seen from the figure, the auxiliary circuit effectively reduces the undershoot from 38mV to 22mV and the overshoot from 112mV to 60mV, thereby almost halving the voltage fluctuation and accelerating the transient recovery time.

[0036] Figure 4 This is a hardware diagram of the dual-core power supply voltage controller. The core VRM controller used in the single-phase buck auxiliary circuit is a six-phase interleaved buck converter. Its specifications are shown in Table 1:

[0037]

[0038] Load circuit parameters

[0039]

[0040] Table 1

[0041] Figure 5 This is a diagram of the actual hardware test of the present invention in the application of the dual-core power supply voltage controller. Figure 5 (a) is a comparison of the output voltage overshoot when the single-phase auxiliary circuit is turned on and the single-phase auxiliary circuit is turned on when the heavy load is switched to the light load, that is, when the output current suddenly decreases. Figure 5 (b) is a comparison diagram of the output voltage undershoot when the single-phase buck auxiliary circuit is not turned on and when the single-phase buck auxiliary circuit is turned on when the light load is switched to the heavy load, that is, when the output current suddenly increases. Figure 5 (a) and Figure 5 (b) shows good results for suppressing overshoot and overshoot, with overshoot reduced from 98mV to 48mV and undershoot reduced from 36mV to 27mV. When the two loads work alternately at an interval of 20us, the single-phase buck auxiliary circuit successfully improves the dynamic response of the two core voltages, such as Figure 5 (c) as shown.

[0042] It is to be understood that the present invention is described by some embodiments, and it is known to those skilled in the art that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. In addition, under the teachings of the present invention, these features and embodiments may be modified to adapt to specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the scope of protection of the present invention.

Claims

1. A reconfigurable auxiliary circuit for reducing power supply voltage fluctuation of a multi-core CPU, characterized in that: Including traditional VRM control circuit, single-phase step-down auxiliary circuit, back-to-back switch tube, differentiator, window comparator and high dynamic nonlinear closed-loop control circuit; In the traditional VRM control circuit, the output end of the main core VRM controller of each phase is connected to the back-to-back switch tube, and the single-phase buck auxiliary circuit is connected to the back-to-back switch tube of each phase; the single-phase buck auxiliary circuit consists of the upper switch tube S H and the lower switch tube S L and the inductor La as the current source; the upper switch tube S H Connected in series with the inductor La, the lower switch tube S L Connected in parallel between the two; when the load is boosted, the upper switch tube S H When the load voltage is reduced, the lower switch tube S L Switch on, absorb current from the load, suppress overshoot; The differentiator collects the output voltage of the main core VRM controller of each phase and connects the output voltage to the high dynamic nonlinear closed-loop control circuit through the window comparator; the high dynamic nonlinear closed-loop control circuit is connected to the single-phase buck auxiliary circuit, and the high dynamic nonlinear closed-loop control circuit outputs a PWM pulse control signal for controlling the output of the power stage in the main core VRM controller and an output transistor switch control signal for controlling the upper switch tube S in the single-phase buck auxiliary circuit. H and the lower switch tube S L The control signal of each phase back-to-back switch tube is S N Opening and shutting down; The PWM pulse control signal is calculated by a high dynamic nonlinear closed-loop control circuit, and a square wave signal with certain duty cycle information is generated through the PWM pulse control signal.

2. The reconfigurable auxiliary circuit for reducing power supply voltage fluctuation of a multi-core CPU according to claim 1, characterized in that: The inductance La is minimized to enhance the voltage fluctuation without affecting the steady-state efficiency of the main core VRM controller.

3. The reconfigurable auxiliary circuit for reducing power supply voltage fluctuation of a multi-core CPU according to claim 1, characterized in that: Each group of back-to-back switch tubes has two back-to-back power MOS tubes connected in series, so that the single-phase buck auxiliary circuit can switch between the connected main core VRM controllers.

4. The reconfigurable auxiliary circuit for reducing power supply voltage fluctuation of a multi-core CPU according to claim 1, characterized in that: The power stage circuit in the main core VRM controller is used to adjust the input voltage to a stable output voltage. The power architecture adopted by the power stage circuit consists of two groups of reconfigurable buck converters, each with six main phases and one auxiliary phase. The main phase uses a large inductor to reduce the overall circuit system loss, and the auxiliary phase uses a small inductor to improve the system dynamic performance.

5. The reconfigurable auxiliary circuit for reducing power supply voltage fluctuation of a multi-core CPU according to claim 1, characterized in that: The control of the back-to-back switch tubes is divided into a state machine with three cycles. In the S0 cycle, the overall power architecture system circuit composed of each main core VRM controller is in a steady state, the back-to-back switch tubes are disconnected, and the system is not connected to the single-phase buck auxiliary circuit; after the load shedding signal is issued, it enters the S1 cycle. When the output voltage exceeds the negative threshold, the back-to-back switch tubes are turned on to connect the single-phase buck auxiliary circuit and the upper switch tube S H Set high to provide additional high load slope current to the load through the small inductance La; when the load voltage undershoot reaches the minimum value, the system enters the S2 cycle, and the upper switch tube S H and the lower switch tube S L The specific duty cycle calculated by the differentiator is controlled according to the output of the differentiator, so that the source current decreases at a predetermined slope; once the detected current returns to zero, the upper switch tube S H , lower switch tube S L The back-to-back switch tube is turned off and the system returns to the S0 cycle.

6. The reconfigurable auxiliary circuit for reducing power supply voltage fluctuation of a multi-core CPU according to claim 5, characterized in that: The slope of the current decrease is calculated by the following formula: Where d1 is the duty cycle of the load boost, V g is the input voltage, V OUT is the output voltage, L a is the inductance of the single-phase buck auxiliary circuit.

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