A resonator and a method for preparing the same

Abstract

The present application provides a resonator and a preparation method thereof, relating to the field of resonator technology, the resonator includes a substrate and a first electrode layer, a first piezoelectric layer and a second electrode layer stacked sequentially on the substrate, the first electrode layer, the first piezoelectric layer and the second electrode layer forming a first overlapping region along the stacking direction, a capacitor stacking layer outside the first overlapping region is provided on the first piezoelectric layer, a passivation layer is provided above the second electrode layer, and the passivation layer extends above the capacitor stacking layer. In this way, capacitors can be integrated inside the resonator, and capacitors can be directly integrated on the chip, thereby improving the performance of the resonator and the filter. In addition, the passivation layer and the capacitor stacking layer are independent of each other. Therefore, the material thickness of the dielectric layer inside the capacitor stacking layer can be optimized according to performance or can be flexibly changed according to demand.

Description

Technical Field

[0001] This application relates to the field of resonator technology, and more specifically, to a resonator and its fabrication method. Background Technology

[0002] With the rapid development of wireless communication technology, more and more devices are transmitting and receiving information at higher frequency bands, placing increasingly stringent requirements on radio frequency front-end circuits. Consequently, the market demand for high-performance filters is growing. Bulk acoustic wave (BAW) filters, with their high quality factor, good out-of-band rejection, and high rectangularity coefficient, are gradually becoming the mainstream in the market.

[0003] Bulk acoustic wave (BAW) filters are constructed by cascading multiple resonators in a specific circuit configuration. High-performance filters require high-performance resonators, which possess a high quality factor. A high quality factor allows the filter to have lower insertion loss and a steeper roll-off characteristic, resulting in superior filtering performance. Therefore, fabricating resonators with high stability and superior performance is crucial.

[0004] Due to the limitations of the electromechanical coupling coefficient of the resonator material, the bandwidth of bulk acoustic wave (BAW) filters is relatively small. In practical applications, passive components such as capacitors or inductors are usually added as matching circuits or to increase the filter's bandwidth and adjust its filtering characteristics. Surface-mount capacitors are widely used in various electronic products such as mobile phones, computers, tablets, televisions, digital cameras, audio equipment, and automotive electronics. However, when used in filters, they need to be connected to the resonator filter circuit, requiring additional wiring. Furthermore, their size is larger than that of the resonator, which degrades the filter's performance and prevents the area from being reduced, greatly limiting the performance of thin-film BAW filters. Summary of the Invention

[0005] The purpose of this application is to provide a resonator and its fabrication method in view of the shortcomings of the prior art.

[0006] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows:

[0007] In one aspect of this application, a resonator is provided, including a substrate and a first electrode layer, a first piezoelectric layer and a second electrode layer sequentially stacked on the substrate. The first electrode layer, the first piezoelectric layer and the second electrode layer form a first overlapping region along the stacking direction. A capacitor stack layer located outside the first overlapping region is disposed on the first piezoelectric layer. A passivation layer is disposed above the second electrode layer and extends above the capacitor stack layer.

[0008] Optionally, the capacitor stack layer includes a lower electrode, a dielectric layer, and an upper electrode sequentially stacked on the first piezoelectric layer; the resonator also includes a first lead and a second lead, the first lead penetrating the passivation layer and contacting the lower electrode, the second lead penetrating the passivation layer and contacting the upper electrode, and the first lead and the second lead not overlapping in the stacking direction.

[0009] Optionally, the lower electrode and the upper electrode have a second overlapping region in the stacking direction, and both the first lead-out portion and the second lead-out portion are located outside the second overlapping region.

[0010] Optionally, the capacitor stack layer includes multiple upper electrodes and a lower electrode and a dielectric layer sequentially stacked on the first piezoelectric layer. The multiple upper electrodes are disposed on the side of the dielectric layer away from the lower electrode, and the multiple upper electrodes are spaced apart from each other. The multiple upper electrodes, together with the lower electrode, form multiple capacitors.

[0011] Optionally, the resonator further includes a third lead and a plurality of fourth leads, the third lead penetrating the passivation layer and contacting the lower electrode, and the plurality of fourth leads penetrating the passivation layer and contacting the plurality of upper electrodes one by one.

[0012] Optionally, the resonator also includes a plurality of fourth leads, which penetrate the passivation layer and contact a plurality of upper electrodes respectively.

[0013] Optionally, an insulating layer is provided between the first piezoelectric layer and the capacitor stack layer.

[0014] Optionally, a mass load layer located in the first overlapping region is provided between the first piezoelectric layer and the second electrode layer.

[0015] Optionally, a second piezoelectric layer is disposed between the substrate and the first electrode layer.

[0016] Optionally, a first cavity and a second cavity are further provided between the substrate and the first piezoelectric layer, wherein the first cavity is at least partially located within the first overlapping region, and the second cavity is located directly below the capacitor stack layer.

[0017] Optionally, an oxide layer is filled into the second cavity.

[0018] Another aspect of this application provides a method for fabricating a resonator, the method comprising:

[0019] A second piezoelectric layer, a first electrode layer, and a first piezoelectric layer are sequentially formed on a substrate;

[0020] A mass load layer is formed on the first piezoelectric layer;

[0021] A second electrode layer is formed on the mass load layer and a lower electrode is formed on the first piezoelectric layer, wherein the second electrode layer and the lower electrode are spaced apart.

[0022] A dielectric layer is formed on the lower electrode;

[0023] At least one upper electrode is formed on the dielectric layer, wherein the lower electrode, the dielectric layer and at least one upper electrode form a capacitor stack layer;

[0024] A passivation layer is formed on the second electrode layer, and the passivation layer extends above the capacitor stack layer.

[0025] The beneficial effects of this application include:

[0026] This application provides a resonator and its fabrication method. The resonator includes a substrate and a first electrode layer, a first piezoelectric layer, and a second electrode layer sequentially stacked on the substrate. The first electrode layer, the first piezoelectric layer, and the second electrode layer form a first overlapping region along the stacking direction. A capacitor stack layer located outside the first overlapping region is disposed on the first piezoelectric layer. A passivation layer is disposed above the second electrode layer, extending above the capacitor stack layer. This allows for the integration of capacitors within the resonator, achieving direct on-chip capacitor integration. Compared to external capacitors, this results in a smaller area, eliminates the need for additional lead paths, and avoids corresponding electrical parasitics, thereby improving the performance of the resonator and filter. Furthermore, the passivation layer and the capacitor stack layer are independent of each other. Therefore, the material thickness of the dielectric layer inside the capacitor stack layer is not limited by the device's passivation requirements. Thus, the material thickness of the dielectric layer inside the capacitor stack layer can be optimized based on performance or flexibly varied according to requirements. It also allows for fine-tuning of the capacitance value for the integrated capacitor, overcoming defects in process integration. Attached Figure Description

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0028] Figure 1 This is one of the schematic diagrams of a resonator fabrication method provided in an embodiment of this application;

[0029] Figure 2 This is a second schematic diagram of a resonator fabrication method provided in an embodiment of this application.

[0030] Figure 3 This is the third schematic diagram of a resonator fabrication method provided in the embodiments of this application;

[0031] Figure 4 This is the fourth schematic diagram of a resonator fabrication method provided in the embodiments of this application;

[0032] Figure 5 Fifth schematic diagram of a resonator fabrication method provided in this application embodiment;

[0033] Figure 6 This is the sixth schematic diagram of a resonator fabrication method provided in the embodiments of this application;

[0034] Figure 7 This is the seventh schematic diagram of a resonator fabrication method provided in the embodiments of this application;

[0035] Figure 8 This is one of the structural schematic diagrams of a resonator provided in an embodiment of this application;

[0036] Figure 9 This is a second schematic diagram of the structure of a resonator provided in an embodiment of this application;

[0037] Figure 10 This is the third schematic diagram of a resonator provided in the embodiments of this application;

[0038] Figure 11 This is the fourth schematic diagram of a resonator provided in the embodiments of this application;

[0039] Figure 12 Fifth schematic diagram of a resonator provided in the embodiments of this application;

[0040] Figure 13 This is the sixth schematic diagram of a resonator provided in the embodiments of this application.

[0041] Icons: 101-Substrate; 102-Sacrificial layer; 103-Second piezoelectric layer; 104-First electrode layer; 105-First piezoelectric layer; 106-Electrode lead-out hole; 107-Mass load layer; 108-First metal layer; 109-Second electrode layer; 110-Second metal layer; 111-Lower electrode; 112-Dielectric layer; 113-Upper electrode; 114-Capacitor stack layer; 115-Passivation layer; 116-First lead-out; 117-Second lead-out; 118-Sixth lead-out; 119-Fifth lead-out; 120-First cavity; 121-Insulating layer; 122-Second cavity; 123-Third lead-out; 124-Fourth lead-out. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0043] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. It should be noted that, unless otherwise specified, the various features in the embodiments of this application can be combined with each other, and the combined embodiments are still within the protection scope of this application.

[0044] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0045] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of this application is in use. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. In addition, the terms "first," "second," and "third," etc., are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0046] Furthermore, terms such as "horizontal" and "vertical" do not imply that components must be absolutely horizontal or suspended, but rather that they can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal than "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0047] In the description of this application, it should also be noted that, unless otherwise expressly specified and limited, the terms "set up," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0048] One aspect of this application provides a resonator, referring to... Figures 8 to 13Any one of the images includes a substrate 101 and a piezoelectric stacked layer disposed on the substrate 101. The piezoelectric stacked layer includes a first electrode layer 104, a first piezoelectric layer 105, and a second electrode layer 109 sequentially stacked on the substrate 101. This facilitates the conversion of electrical energy into mechanical energy via the first piezoelectric layer 105 after an electrical signal is applied to the first electrode layer 104 and the second electrode layer 109. It should be understood that the stacking direction in this application is... Figures 8 to 13 The vertical direction of any one of the images, or the thickness direction of the substrate 101.

[0049] Continue to refer to Figures 8 to 13 In any one of the images, the first electrode layer 104, the first piezoelectric layer 105, and the second electrode layer 109 form a first overlapping region along the stacking direction. Typically, the first overlapping region also serves as the effective resonant region or effective working region of the resonator.

[0050] To optimize the performance of the resonator, such as Figures 8 to 13 In any of the images, a capacitor stack layer 114 is provided on the first piezoelectric layer 105, which enables the integration of capacitors inside the resonator and realizes on-chip direct capacitor integration. Compared with external capacitors, the area is smaller and no additional lead-out path is required, thus avoiding corresponding electrical parasitics and improving the performance of the resonator and filter.

[0051] When integrating the capacitor stack layer 114, the capacitor stack layer 114 and the first overlapping region can be made as independent as possible. Therefore, the capacitor stack layer 114 can be located outside the first overlapping region. For example, there is no first electrode layer 104 directly below the capacitor stack layer 114. In other words, the capacitor stack layer 114 and the first electrode layer 104 do not intersect in the stacking direction. This ensures that the on-chip integrated capacitor stack layer 114 does not affect the first overlapping region of the resonator.

[0052] Based on this, such as Figures 8 to 13 In any of the above images, a passivation layer 115 can be provided on the entire device (on the side facing away from the substrate 101) to provide passivation protection for the other basic layers of the resonator. Specifically, the passivation layer 115 can be located above the second electrode layer 109, and the passivation layer 115 also extends above the capacitor stack layer 114 and the first piezoelectric layer 105. It should be noted that in this application, the passivation layer 115 and the capacitor stack layer 114 are independent of each other. Therefore, the material thickness of the dielectric layer 112 inside the capacitor stack layer 114 is not limited by the passivation requirements of the device. Thus, the material thickness of the dielectric layer 112 inside the capacitor stack layer 114 can be optimized according to performance or flexibly varied according to requirements.

[0053] The aforementioned capacitor stack layer 114 refers to a structure capable of possessing capacitive characteristics. Its specific structure can be reasonably selected and configured according to actual needs. Of course, for ease of understanding, this application will describe some examples in conjunction with the accompanying drawings.

[0054] Example 1

[0055] Please refer to Figure 8 The capacitor stack layer 114 is located outside the first overlapping region, specifically on the right side of the first overlapping region. The capacitor stack layer 114 includes a lower electrode 111, a dielectric layer 112, and an upper electrode 113. The lower electrode 111 is located on the upper surface of the first piezoelectric layer 105, the dielectric layer 112 is located above the lower electrode 111, and the upper electrode 113 is located above the dielectric layer 112. Thus, a single capacitor structure is formed by the lower electrode 111, the dielectric layer 112, and the upper electrode 113.

[0056] In order to successfully lead out the lower electrode 111 and the upper electrode 113 of the capacitor stack 114, continue to refer to Figure 8 The resonator also includes a first lead-out portion 116 and a second lead-out portion 117. The first lead-out portion 116 penetrates the passivation layer 115 and contacts the lower electrode 111, while the second lead-out portion 117 penetrates the passivation layer 115 and contacts the upper electrode 113. This allows the capacitor stack structure to be connected to the circuit through the first lead-out portion 116 and the second lead-out portion 117. Furthermore, the first lead-out portion 116 and the second lead-out portion 117 do not overlap in the stacking direction. In other words, the portion where the lower electrode 111 contacts the first lead-out portion 116 is misaligned with the portion where the upper electrode 113 contacts the second lead-out portion 117 in the stacking direction, thus forming a non-intersecting state. This makes it easier to bring out the upper electrode 113 and the lower electrode 111.

[0057] The lower electrode 111 and upper electrode 113 of the capacitor stack 114 form a second overlapping region in the stacking direction to meet the capacitor setting requirements. Based on this, the performance of the capacitor stack 114 can be optimized. For example, the first lead 116 and the second lead 117 are both located outside the second overlapping region. This avoids the first lead 116 from being directly opposite the upper electrode 113, and also avoids the second lead 117 from being directly opposite the lower electrode 111, thereby improving the parasitic capacitance that may be formed between the first lead 116 and the upper electrode 113. The same applies to the second lead 117 and the lower electrode 111.

[0058] Example 2

[0059] Please refer to Figure 9 or Figure 11The capacitor stack layer 114 is located outside the first overlapping region, specifically on the right side of the first overlapping region. The capacitor stack layer 114 includes a lower electrode 111, a dielectric layer 112, and multiple upper electrodes 113. The lower electrode 111 is stacked on the first piezoelectric layer 105, the dielectric layer 112 is stacked on the lower electrode 111, and the multiple upper electrodes 113 are laid flat on the surface of the dielectric layer 112 facing away from the lower electrode 111, with each pair of upper electrodes 113 spaced apart from the others. Each upper electrode 113 has a portion directly opposite the lower electrode 111, so one upper electrode 113 can cooperate with the lower electrode 111 to form a capacitor. Similarly, multiple upper electrodes 113 can cooperate with the lower electrode 111 to form multiple capacitors. Specifically, for example… Figure 9 or Figure 11 In this capacitor stack 114, there is a lower electrode 111, a dielectric layer 112, and two upper electrodes 113. The lower electrode 111 is stacked on the first piezoelectric layer 105, the dielectric layer 112 is stacked on the lower electrode 111, and the two upper electrodes 113 are laid flat on the dielectric layer 112, with the two upper electrodes 113 spaced apart from each other. The left upper electrode 113, together with the lower electrode 111 below it, forms one capacitor, and the right upper electrode 113, together with the lower electrode 111 below it, forms another capacitor.

[0060] To meet different capacitor connection requirements, the lower electrode 111 can be selectively led out or not led out. The following will explain this with reference to the attached figures:

[0061] For example, refer to Figure 9 As shown, the lower electrode 111 can be led out. Specifically, the resonator also includes a third lead-out portion 123 and multiple fourth leads-out portions 124. The third lead-out portion 123 penetrates the passivation layer 115 and contacts the lower electrode 111, while the multiple fourth leads-out portions 124 respectively penetrate the passivation layer 115 and contact multiple upper electrodes 113 one by one. In this way, the lower electrode 111 can be led out through the third lead-out portion 123, and each upper electrode 113 can be led out through one fourth lead-out portion 124. Thus, when connecting the capacitor stack layer 114 to the circuit, the lower electrode 111 and at least a portion of the upper electrodes 113 can be flexibly selected to be connected according to the requirements. For example, when one capacitor needs to be connected, the lower electrode 111 and one upper electrode 113 can be connected; when two capacitors need to be connected, the lower electrode 111 and two upper electrodes 113 can both be connected to the circuit. Furthermore, it should be understood that when the lower electrode 111 is also led out, the capacitors connected to the circuit can form various connection forms such as series or parallel.

[0062] For example, refer to Figure 11As shown, the lower electrode 111 does not need to be led out. Specifically, the resonator also includes multiple fourth leads 124, each of which penetrates the passivation layer 115 and contacts one of the upper electrodes 113. Thus, the lower electrode 111 does not need to be led out, and each upper electrode 113 can be led out through one of the fourth leads 124. Therefore, when the capacitor stack 114 is connected to the circuit, two capacitors can form a series connection through the lower electrode 111, for example... Figure 11 In the middle, the upper electrode 113 on the left and the lower electrode 111 form a capacitor, and the upper electrode 113 on the right and the lower electrode 111 form a capacitor. When connecting to the circuit, it can be connected through the two fourth leads 124 of the two capacitors, so that the two capacitors can be connected in series.

[0063] When the capacitor stack 114 can form multiple capacitors, the series or parallel connection between different capacitors can be adjusted by external leads, thereby adjusting the capacitance value to meet the capacitance accuracy requirements in the manufacturing process. For example Figure 10 As shown, two capacitors are illustrated. The capacitor on the right can be used as the main capacitor a, and the capacitor on the left can be used as the auxiliary capacitor b. In order to meet the capacitor accuracy requirements in the manufacturing process, if the accuracy of the main capacitor a does not meet the requirements in subsequent packaging and testing, the main capacitor a and the auxiliary capacitor b will be connected in series or in parallel through the connection of external leads, thereby adjusting the capacitance value.

[0064] The capacitance value of the auxiliary capacitor is 10-30% of that of the main capacitor, so that the adjustment range of the capacitance value can more easily meet the actual needs.

[0065] In some possible implementations, an insulating layer 121 is provided between the first piezoelectric layer 105 and the capacitor stack layer 114. This allows the capacitor stack layer 114 to be isolated by the insulating layer 121, thereby improving the performance of the capacitor stack layer 114. For example... Figure 12 In this configuration, an insulating layer 121 is provided between the first piezoelectric layer 105 and the capacitor stack layer 114. It should be understood that... Figures 9 to 11 In any similar or identical resonator, an insulating layer 121 can be provided between the first piezoelectric layer 105 and the capacitor stack layer 114 to optimize the performance of the resonator.

[0066] In some possible implementations, such as Figures 8 to 13As shown, a mass load layer 107 located in the first overlapping region is disposed between the first piezoelectric layer 105 and the second electrode layer 109. The frequency of the resonator can be adjusted through the mass load layer 107. Furthermore, when the mass load layer 107 is located between the first piezoelectric layer 105 and the second electrode layer 109, the material of the mass load layer 107 can be the same as the material of the second electrode layer 109, thereby simplifying the fabrication process.

[0067] In some possible implementations, such as Figures 8 to 13 As shown, a second piezoelectric layer 103 is disposed between the substrate 101 and the first electrode layer 104, and the formation quality of the subsequent first electrode layer 104 can be improved by the second piezoelectric layer 103.

[0068] In some possible implementations, such as Figures 8 to 13 As shown, a first cavity 120 is also provided between the substrate 101 and the first electrode layer 104, and the first cavity 120 is generally located within the first overlapping region. This allows the first cavity 120 to reflect sound waves within the first overlapping region, thereby improving the performance of the resonator. It should be understood that when the first cavity 120 is provided between the substrate 101 and the first electrode layer 104, the first overlapping region is formed by the cavity, the first electrode layer 104, the first piezoelectric layer 105, and the second electrode layer 109 along the stacking direction.

[0069] In some possible implementations, such as Figure 13 As shown, a second cavity 122 is also provided between the substrate 101 and the first piezoelectric layer 105. The second cavity 122 is located directly below the capacitor stack layer 114. In this way, the influence of the capacitor region formed by the substrate 101 and the capacitor stack layer 114 can be isolated by the second cavity 122, thereby improving the performance of the capacitor formed by the capacitor stack layer 114.

[0070] In some possible implementations, an oxide layer is filled in the second cavity 122. This oxide layer can fill the second cavity 122, thereby increasing the support strength under the capacitor stack layer 114. This is especially helpful for improving process stability for multi-capacitor structures.

[0071] In some possible implementations, such as Figures 8 to 13 As shown, to facilitate the lead-out of the first electrode layer 104, a fifth lead-out portion 119, composed of a first metal layer 108 and a second metal layer 110, can be provided. The fifth lead-out portion 119 passes through the passivation layer 115 and the first piezoelectric layer 105 and then contacts the first electrode layer 104. Similarly, to facilitate the lead-out of the second electrode layer 109, a sixth lead-out portion 118 formed by the second metal layer 110 can be provided. The sixth lead-out portion 118 passes through the passivation layer 115 and then contacts the second electrode layer 109.

[0072] Another aspect of this application provides a method for fabricating a resonator, the method comprising:

[0073] S10: A second piezoelectric layer 103, a first electrode layer 104, and a first piezoelectric layer 105 are sequentially formed on a substrate 101.

[0074] like Figure 1 As shown, after forming a second piezoelectric layer 103 on the substrate 101, a metal layer is deposited on the second piezoelectric layer 103, and a first electrode layer 104 is formed after the metal layer is patterned. Then, a first piezoelectric layer 105 is formed on the first electrode layer 104.

[0075] It is understood that when it is necessary to form the first cavity 120 and / or the second cavity 122, the first cavity 120 and / or the second cavity 122 can be formed on the substrate 101 by etching, and then the sacrificial layer 102 (oxide layer) can be filled in the first cavity 120 and / or the second cavity 122 to make the surface of the substrate 101 flat, which can facilitate the convenience of subsequent layers.

[0076] To facilitate the extraction of the first electrode layer 104, the first piezoelectric layer 105 can be etched to form an electrode extraction hole 106 that penetrates the first piezoelectric layer 105.

[0077] S20: A mass load layer 107 is formed on the first piezoelectric layer 105.

[0078] like Figure 2 As shown, a mass load layer 107 is formed on the first piezoelectric layer 105 by deposition and patterning, which is generally located in the first overlapping region. Correspondingly, in order to simplify the process, the mass load layer 107 can be made of metal. In this way, by depositing an entire metal layer, the spaced mass load layer 107 and the first metal layer 108 can be formed by patterning, wherein the first metal layer 108 is located in the electrode lead-out hole 106.

[0079] S30: A second electrode layer 109 is formed on the mass load layer 107 and a lower electrode 111 is formed on the first piezoelectric layer 105, wherein the second electrode layer 109 and the lower electrode 111 are spaced apart.

[0080] like Figure 3 As shown, a whole layer of metal is deposited on the mass load layer 107, thereby forming a second electrode layer 109, a lower electrode 111 on the first piezoelectric layer 105, and a second metal layer 110 on the first metal layer 108 after patterning, with the three layers spaced apart from each other.

[0081] S40: A dielectric layer 112 is formed on the lower electrode 111.

[0082] like Figure 4 As shown, a dielectric layer 112 is formed on the lower electrode 111 to facilitate the construction of the dielectric of the capacitor.

[0083] S50: At least one upper electrode 113 is formed on the dielectric layer 112, wherein the lower electrode 111, the dielectric layer 112 and the at least one upper electrode 113 form a capacitor stack layer 114.

[0084] like Figure 5 As shown, an upper electrode 113 is formed on the dielectric layer 112, wherein the lower electrode 111, the dielectric layer 112, and the upper electrode 113 form a capacitor stack layer 114. Of course, when multiple capacitors need to be constructed, multiple upper electrodes 113 can be formed.

[0085] S60: A passivation layer 115 is formed on the second electrode layer 109, and the passivation layer 115 extends above the capacitor stack layer 114.

[0086] like Figure 6 As shown, in Figure 5 A passivation layer 115 is deposited on top of the device to provide passivation protection. To facilitate the lead-out of the required electrodes, a first lead-out portion 116, a second lead-out portion 117, a third lead-out portion 123, a fourth lead-out portion 124, a fifth lead-out portion 119, and a sixth lead-out portion 118 can be provided according to the requirements of the different resonators mentioned above.

[0087] like Figure 7 As shown, a first cavity 120 and / or a second cavity 122 are ultimately formed by forming a release hole that communicates with the sacrificial layer 102.

[0088] It should be understood that the methods for fabricating resonators can be used to fabricate the aforementioned resonators.

[0089] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A resonator, characterized in that, The device includes a substrate and a first electrode layer, a first piezoelectric layer, and a second electrode layer sequentially stacked on the substrate. The first electrode layer, the first piezoelectric layer, and the second electrode layer form a first overlapping region along the stacking direction. A capacitor stack layer located outside the first overlapping region is disposed on the first piezoelectric layer. A passivation layer is disposed above the second electrode layer and extends above the capacitor stack layer. The capacitor stack layer includes a lower electrode, a dielectric layer, and an upper electrode sequentially stacked on the first piezoelectric layer. The passivation layer and the capacitor stack layer are independent of each other.

2. The resonator as described in claim 1, characterized in that, The resonator further includes a first lead-out portion and a second lead-out portion. The first lead-out portion penetrates the passivation layer and contacts the lower electrode, while the second lead-out portion penetrates the passivation layer and contacts the upper electrode. The first lead-out portion and the second lead-out portion do not overlap in the stacking direction.

3. The resonator as described in claim 2, characterized in that, The lower electrode and the upper electrode have a second overlapping region in the stacking direction, and both the first lead-out portion and the second lead-out portion are located outside the second overlapping region.

4. The resonator as described in claim 1, characterized in that, The capacitor stack layer includes a plurality of upper electrodes, which are disposed on the side of the dielectric layer away from the lower electrode and are spaced apart from each other. The plurality of upper electrodes, together with the lower electrode, form a plurality of capacitors.

5. The resonator as described in claim 4, characterized in that, The resonator further includes a third lead and a plurality of fourth leads. The third lead penetrates the passivation layer and contacts the lower electrode, and the plurality of fourth leads respectively penetrate the passivation layer and contact the plurality of upper electrodes.

6. The resonator as claimed in claim 4, characterized in that, The resonator also includes a plurality of fourth leads, which penetrate the passivation layer and contact the plurality of upper electrodes respectively.

7. The resonator according to any one of claims 1 to 6, characterized in that, An insulating layer is provided between the first piezoelectric layer and the capacitor stack layer; And / or, a mass load layer located in the first overlapping region is provided between the first piezoelectric layer and the second electrode layer; And / or, a second piezoelectric layer is disposed between the substrate and the first electrode layer.

8. The resonator according to any one of claims 1 to 6, characterized in that, A first cavity and a second cavity are also provided between the substrate and the first piezoelectric layer, wherein the first cavity is at least partially located within the first overlapping region, and the second cavity is located directly below the capacitor stack layer.

9. The resonator as claimed in claim 8, characterized in that, An oxide layer is filled inside the second cavity.

10. A method for fabricating a resonator, characterized in that, The method includes: A second piezoelectric layer, a first electrode layer, and a first piezoelectric layer are sequentially formed on a substrate; A mass load layer is formed on the first piezoelectric layer; A second electrode layer is formed on the mass load layer and a lower electrode is formed on the first piezoelectric layer, wherein the second electrode layer and the lower electrode are spaced apart. A dielectric layer is formed on the lower electrode; At least one upper electrode is formed on the dielectric layer, wherein the lower electrode, the dielectric layer, and the at least one upper electrode form a capacitor stack layer; A passivation layer is formed on the second electrode layer, and the passivation layer extends over the capacitor stack layer.

Images