A phase adjustment circuit, method and memory

Abstract

Embodiments of the present application disclose a phase adjustment circuit, a method and a memory; the phase adjustment circuit comprises a multi-phase clock signal generator, a phase error detector and a phase error eliminator, wherein: the multi-phase clock signal generator is configured to generate an initial multi-phase clock signal; the phase error detector is connected to the multi-phase clock signal generator and is configured to perform phase error detection on the initial multi-phase clock signal to obtain an error signal used to represent phase difference information between the initial multi-phase clock signals; the phase error eliminator is connected to the phase error detector and is configured to detect the error signal to obtain an error elimination code; and the multi-phase clock signal generator is further connected to the phase error eliminator and is configured to receive the error elimination code and perform phase adjustment on the initial multi-phase clock signal based on the error elimination code to obtain a target multi-phase clock signal.

Description

Technical Field

[0001] This application relates to the field of semiconductor devices, and more particularly to a phase adjustment circuit, method, and memory. Background Technology

[0002] In related technologies, circuits that operate based on multi-phase clock signals often experience phase errors during transmission, which can lead to uncertainties in the circuit's operation. Summary of the Invention

[0003] Based on this, embodiments of this application provide a phase adjustment circuit, method, and memory, which adjusts the phase of the initial multi-phase clock signal by using the error elimination code corresponding to the phase error of the initial multi-phase clock signal, so as to obtain a target multi-phase clock signal in which the phase difference between the clock signals meets the preset requirements.

[0004] To achieve the above objectives, this application provides a phase adjustment circuit, which includes: a multi-phase clock signal generator, a phase error detector, and a phase error canceller, wherein:

[0005] The multi-phase clock signal generator is configured to generate an initial multi-phase clock signal;

[0006] The phase error detector is connected to the multi-phase clock signal generator and is configured to perform phase error detection on the initial multi-phase clock signal to obtain an error signal that characterizes the phase difference information between the initial multi-phase clock signals.

[0007] The phase error canceller, connected to the phase error detector, is configured to detect the error signal and obtain an error cancellation code;

[0008] The multi-phase clock signal generator is also connected to the phase error canceller and is configured to receive the error cancellation code and perform phase adjustment on the initial multi-phase clock signal based on the error cancellation code to obtain the target multi-phase clock signal.

[0009] This application embodiment also provides a phase adjustment method, the phase adjustment method comprising:

[0010] An initial multi-phase clock signal is generated using a multi-phase clock signal generator;

[0011] A phase error detector is used to detect the phase error of the initial multi-phase clock signal to obtain an error signal that characterizes the phase difference information between the initial multi-phase clock signals.

[0012] A phase error canceller is used to detect the error signal to obtain the error cancellation code;

[0013] Using the aforementioned multi-phase clock signal generator, the initial multi-phase clock signal is phase-adjusted based on the error cancellation code to obtain the target multi-phase clock signal.

[0014] This application also provides a memory, which includes at least the phase adjustment circuit described in any of the above embodiments.

[0015] This application provides a phase adjustment circuit, method, and memory. The phase adjustment circuit includes a multi-phase clock signal generator, a phase error detector, and a phase error canceller. The multi-phase clock signal generator is configured to generate an initial multi-phase clock signal. The phase error detector, connected to the multi-phase clock signal generator, is configured to detect phase errors in the initial multi-phase clock signal to obtain an error signal characterizing the phase difference information between the initial multi-phase clock signals. The phase error canceller, connected to the phase error detector, is configured to detect the error signal to obtain an error cancellation code. The multi-phase clock signal generator is also connected to the phase error canceller and is configured to receive the error cancellation code and adjust the phase of the initial multi-phase clock signal based on the error cancellation code to obtain a target multi-phase clock signal. Thus, by using the error cancellation code corresponding to the phase error of the initial multi-phase clock signal, phase adjustment of the initial multi-phase clock signal can be performed to obtain a target multi-phase clock signal whose phase difference meets preset requirements.

[0016] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the technical solutions provided in the embodiments of this application. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort:

[0018] Figure 1 A schematic diagram of a delay phase-locked loop circuit that generates and outputs a four-phase clock signal in related technologies;

[0019] Figure 2 A schematic diagram of the composition of a phase adjustment circuit provided in an embodiment of this application;

[0020] Figure 3 A schematic diagram illustrating the composition of yet another phase adjustment circuit provided in an embodiment of this application;

[0021] Figure 4A A schematic diagram illustrating the phase adjustment circuit provided in this application for adjusting the phase of a four-phase clock signal;

[0022] Figure 4B A schematic diagram showing the transmission process of the four-phase clock signals in the phase adjustment circuit provided in this application embodiment;

[0023] Figure 5 A schematic diagram illustrating the composition of yet another phase adjustment circuit provided in an embodiment of this application;

[0024] Figure 6 A schematic diagram illustrating the composition of another phase adjustment circuit provided in an embodiment of this application;

[0025] Figure 7 A schematic diagram illustrating the composition of another phase adjustment circuit provided in an embodiment of this application;

[0026] Figure 8 A schematic diagram of the duty cycle detector and error cancellation code generator in the phase adjustment circuit provided in the embodiments of this application;

[0027] Figure 9 A schematic diagram illustrating the composition of another phase adjustment circuit provided in an embodiment of this application;

[0028] Figure 10 A schematic diagram of the process for generating a target multi-phase clock signal using the phase adjustment circuit provided in the embodiments of this application;

[0029] Figure 11 A schematic flowchart illustrating a phase adjustment method provided in an embodiment of this application;

[0030] Figure 12 A schematic diagram illustrating the composition of a memory provided in an embodiment of this application;

[0031] Explanation of reference numerals in the attached figures:

[0032] 1-Memory; 10-Phase adjustment circuit; 11-Multi-phase clock signal generator; 111-Delay unit; 12-Phase error detector; 121-First logic operation module; 122-Second logic operation module; 13-Phase error canceller; 131-Duty cycle detector; 1311-Signal converter; 1312-Voltage comparator; 132-Error cancellation code generator; 1321-Synchronous counter; 1322-D flip-flop. Detailed Implementation

[0033] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, it should be noted that, for ease of description, only the parts relevant to this application are shown in the accompanying drawings, not the entire structure. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this application.

[0034] The terms "first," "second," etc., used in this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0035] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0036] To better understand the embodiments of this application, the shortcomings of the related technologies will first be explained.

[0037] In related technologies, multi-phase clock signals (e.g., two-phase clock signals, four-phase clock signals, etc.) often generate phase errors during transmission in circuits. This can lead to uncertainties in read / write operations of the memory device containing the circuit, or read / write errors due to timing mismatches, thus requiring phase error calibration of the multi-phase clock signals. Figure 1 The diagram shows a delayed-locked loop (DLL) circuit for generating and transmitting a four-phase clock signal in related technologies. First, a pair of differential clock signals, CK_c and CK_t, are input. Here, CK_t is the actual clock signal, and CK_c is its phase-differential clock signal. Then, CK_c and CK_t are sequentially passed through a DLL circuit that includes at least: a clock buffer, a four-phase clock signal generator, a regulator for adjusting the phase of the clock signal, and an output circuit, to achieve the transmission of the four-phase clock signal. The four-phase clock signal generator typically includes a four-phase clock divider and a frequency regulator, such as... Figure 1 The phase adjustment of the four-phase clock signal shown in the transmission process mainly relies on the DLL circuit, and the four-phase clock signal usually exists as a reference clock signal (internal clock signal). If there is a phase error between the clock signals, it will cause problems such as sampling errors and timing conflicts in the data read / write operation of the relevant storage device.

[0038] To address the phase error problem in the transmission of multi-phase clock signals during DLL circuitry in related technologies, this application provides a phase adjustment circuit. It employs a phase error detector to detect the phase error of the initial multi-phase clock signal generated by a multi-phase clock signal generator, obtaining an error signal characterizing the phase difference between the initial multi-phase clock signals. A phase error canceller converts this error signal into a corresponding error cancellation code, allowing the multi-phase clock signal generator to directly adjust the phase of the initial multi-phase clock signal based on this error cancellation code, resulting in a target multi-phase clock signal whose phase difference meets preset requirements. This enables phase error calibration of the initial multi-phase clock signal, yielding a multi-phase clock signal with accurate relative phase relationships, and an internal clock signal that is precisely synchronized with the external clock signal, thereby ensuring the accuracy of the relevant storage device during data read / write operations.

[0039] Figure 2 The diagram illustrates the composition of a phase adjustment circuit 10 according to an embodiment of this application. The phase adjustment circuit 10 includes: a multi-phase clock signal generator 11, a phase error detector 12, and a phase error canceller 13, wherein:

[0040] The multi-phase clock signal generator 11 is configured to generate an initial multi-phase clock signal;

[0041] The phase error detector 12 is connected to the multi-phase clock signal generator 11 and is configured to perform phase error detection on the initial multi-phase clock signal to obtain an error signal that characterizes the phase difference information between the initial multi-phase clock signals.

[0042] The phase error canceller 13 is connected to the phase error detector 12 and is configured to detect the error signal to obtain an error cancellation code;

[0043] The multi-phase clock signal generator 11 is also connected to the phase error canceller 13 and is configured to receive the error cancellation code and perform phase adjustment on the initial multi-phase clock signal based on the error cancellation code to obtain the target multi-phase clock signal.

[0044] Here, the phase adjustment circuit 10 includes, but is not limited to, a multi-phase clock signal generator 11, a phase error detector 12, and a phase error canceller 13. Furthermore, the phase adjustment circuit 10 can be a part of a DLL circuit, or a circuit parallel to the DLL circuit. Here, the phase adjustment circuit 10 can be an adjustment circuit deployed within any memory 1 for adjusting the phase difference of a relevant clock signal or non-clock signal.

[0045] Here, the multi-phase clock signal generator 11 includes a frequency divider for dividing the input external clock signal to generate an initial multi-phase clock signal. The multi-phase clock signal generator 11 may also include an adjustment unit for adjusting the phase of the initial multi-phase clock signal based on an error cancellation code to obtain a target multi-phase clock signal. Here, the adjustment unit may be a delay unit, used to adjust the switching state of its delay unit based on the error cancellation code, thereby adjusting the corresponding delay time to adjust the phase of the initial multi-phase clock signal based on this delay time to obtain the target multi-phase clock signal.

[0046] Here, the initial multi-phase clock signal refers to multiple initial clock signals with different phases and relative phase relationships, such as two-phase clock signals, four-phase clock signals, eight-phase clock signals, etc. Based on this, a multi-phase clock signal generator can consist of a multi-phase clock divider, a frequency regulator, and a delay unit for adjusting the phase of the multi-phase clock signal.

[0047] In the following other embodiments of this application, the initial multi-phase clock signal is a four-phase clock signal as an example for illustration.

[0048] Here, the phase error detector 12 is connected to the multi-phase clock signal generator 11, which may include multiple logic operation modules for performing relevant logic operations on each clock signal in the four-phase clock signals, such as AND operation, NOT operation, NAND operation, etc., to determine the error information of the phase difference information between adjacent phase clock signals in the four-phase clock signals.

[0049] Here, the phase error canceller 13 is connected to the phase error detector 12 and the multi-phase clock signal generator 11. The phase error canceller 13 is used to detect the error signal output by the phase error detector 12 (e.g., duty cycle detection, frequency detection, etc.) to obtain an error cancellation code that the multi-phase clock signal generator 11 can recognize. This allows the multi-phase clock signal generator 11 to perform phase adjustment (phase error elimination) on the initial multi-phase clock signal based on the error cancellation code, so as to obtain a target multi-phase clock signal whose phase difference between clock signals meets the preset requirements.

[0050] It should be noted that the connections referred to in this disclosure, such as the phase error detector 12 being connected to the multi-phase clock signal generator 11, the phase error canceller 13 being connected to the phase error detector 12, and the multi-phase clock signal generator 11 being connected to the phase error canceller 13, can be direct connections or indirect connections through other structures.

[0051] The phase adjustment circuit provided in this application first uses a phase error detector 12 to detect the phase error of the initial multi-phase clock signal generated by the multi-phase clock signal generator 11, obtaining an error signal characterizing the phase difference information between the initial multi-phase clock signals. Second, a phase error canceller 13 converts the error signal into a corresponding error cancellation code, allowing the multi-phase clock signal generator 11 to directly adjust the phase of the initial multi-phase clock signal based on this error cancellation code, thereby obtaining a target multi-phase clock signal whose phase difference meets preset requirements. This enables phase error calibration of the initial multi-phase clock signal, resulting in a multi-phase clock signal with accurate relative phase relationships, and an internal clock signal that is precisely synchronized with the external clock signal. This ensures the timing accuracy of the storage device where the phase error adjustment circuit is located during data read / write operations.

[0052] In some embodiments, such as Figure 3 As shown, when the phase error detector 12 includes a first logic operation module 121 and a second logic operation module 122, firstly, the first logic operation module 121 controls the logical AND operation of each initial clock signal in the initial multi-phase clock signal through an enable signal to generate an intermediate signal, making the initial logic operation of each initial clock signal controllable and facilitating subsequent actual operation. Then, the second logic operation module 122 performs logical operations on the intermediate signals of adjacent phases in the intermediate signal output by the first logic operation module 121 to obtain an error signal characterizing the phase difference information between the initial multi-phase clock signals. In this way, based on controllable operation of each initial clock signal in the multi-phase clock signal, the error signal characterizing the phase difference information between the initial multi-phase clock signals can be obtained relatively conveniently and accurately. Figure 3 This diagram illustrates the composition of another phase adjustment circuit provided in an embodiment of this application. The phase adjustment circuit 10 includes: a multi-phase clock signal generator 11, a first logic operation module 121, a second logic operation module 122, and a phase error canceller 13, wherein:

[0053] The first logic operation module 121 is configured to perform an AND operation between the received preset enable signal and each initial clock signal in the initial multi-phase clock signal to obtain an intermediate signal of each initial clock signal.

[0054] The second logic operation module 122 is configured to perform logic operations on the intermediate signals of adjacent phases in the initial multi-phase clock signal to obtain the error signal.

[0055] Here, as Figure 4A The diagram illustrates the phase adjustment circuit provided in this embodiment of the application for phase adjustment of a four-phase clock signal. The first logic operation module 121, when the initial multi-phase clock signal is a four-phase clock signal, includes four operation sub-units. Each operation sub-unit can be composed of an AND gate (which can be composed of a NAND gate and a NOT gate). This operation sub-unit is used to perform an AND operation between a preset enable signal EN (i.e., a trigger signal) and a corresponding initial clock signal to obtain an intermediate signal for each initial clock signal.

[0056] In this embodiment, the preset enable signal EN is active high.

[0057] In one possible implementation, the initial multi-phase clock signal includes a four-phase initial clock signal; the four-phase initial clock signal sequentially includes a first initial clock signal, a second initial clock signal, a third initial clock signal, and a fourth initial clock signal. Since there is a fixed phase relationship between the multi-phase clock signals, for example, the third initial clock signal is the inverted signal of the first initial clock signal, and the fourth initial clock signal is the inverted signal of the second initial clock signal, a first error signal and a second error signal characterizing the phase difference information between the four initial clock signals can be obtained through the operation of the second logic operation module 122. This simplifies the related execution logic in the second logic operation module 122, and only half of the signals are needed to represent the phase difference information between all the initial clock signals, greatly saving circuit area and the amount of information to be processed. That is:

[0058] The second logic operation module 122 is further configured to perform a NAND operation on the intermediate signal of the first initial clock signal and the inverted signal of the intermediate signal of the second initial clock signal to obtain the first error signal, and to perform a NAND operation on the intermediate signal of the second initial clock signal and the inverted signal of the intermediate signal of the third initial clock signal to obtain the second error signal.

[0059] Here, as Figure 4AAs shown, the second logic operation module 122 includes at least two operation sub-units, each of which consists of a NOT gate and a NAND gate. Specifically, the NOT gate in each operation sub-unit can be used to obtain the inverted signal of the input related clock signal (e.g., the intermediate signal of the second initial clock signal or the intermediate signal of the third initial clock signal). Then, the NAND gate in each operation sub-unit can be used to perform a NAND operation with the intermediate signal of the previous phase of the initial clock signal to obtain a first or second error signal.

[0060] Following the description above, a second logic operation module 122 can also be used to perform a NAND operation on the intermediate signal of the third initial clock signal and the inverted signal of the intermediate signal of the fourth initial clock signal to generate a third error signal that characterizes the phase difference information between the third initial clock signal and the fourth initial clock signal. Since there is a fixed phase relationship between the multi-phase clock signals (such as the first clock signal and the third clock signal being inverted signals, and the second clock signal and the fourth clock signal being inverted signals), the first error signal and the second error signal mentioned above can already characterize the phase difference between adjacent phase signals in the four-phase clock signals. To save circuit area and power consumption, in another embodiment of this disclosure, the circuit for generating the third error signal may not be provided.

[0061] Here, as Figure 4B The diagram illustrates the transmission process of the four-phase clock signals in the phase adjustment circuit provided in this embodiment. It shows the initial four-phase clock signals sequentially in phase order: CLKI, CLKQ, CLKIB, and CLKQB. The phase difference between CLKI and CLKQ is also shown: T. I to Q Phase difference between CLKQ and CLRIB: T Q to IB .

[0062] Furthermore, since there is a fixed phase relationship between the four initial clock signals, the second logic operation module 122 can be used to perform NAND operations only on the inverted signals of the intermediate signals of CLKI and CLKQ, and on the inverted signals of the intermediate signals of CLKQ and CLKIB, to obtain the following... Figure 4B The diagram shows CLK, which represents the phase difference information between CLKI, CLKQ, CLKIB, and CLKQB. I_Q and CLK Q_IB .

[0063] In addition, such as Figure 4BAs shown, the clock signals input to the NAND gates of the second logic operation module 122 for NAND operation are: the intermediate signal of CLKI, the inverted signal of the intermediate signal of CLKQ, the intermediate signal of CLKQ, and the inverted signal of the intermediate signal of CLKIB.

[0064] In some embodiments, such as Figure 5 As shown, when the phase error canceller 13 includes a duty cycle detector 131 and an error cancellation code generator 132, the duty cycle detector 131 can be used to detect the duty cycle of the error signal representing the phase difference information between the initial multi-phase clock signals, obtaining a detection result. Then, the error cancellation code generator 132 uses this detection result to generate an error cancellation code to eliminate the phase offset of the initial multi-phase clock signal. In this way, by generating the corresponding phase error cancellation code through the duty cycle detection result corresponding to the error signal representing the phase difference information between the initial multi-phase clock signals, the overall execution logic of the phase adjustment circuit 10 is simplified, and the final target multi-phase clock signal is more in line with the preset requirements. Figure 5 This illustration shows a schematic diagram of another phase adjustment circuit provided in an embodiment of this application. The phase adjustment circuit 10 includes: a multi-phase clock signal generator 11, a first logic operation module 121, a second logic operation module 122, a duty cycle detector 131, and an error cancellation code generator 132; wherein:

[0065] The duty cycle detector 131 is connected to the phase error detector 12 and is configured to perform duty cycle detection on the error signal to obtain a detection result;

[0066] The error cancellation code generator 132, connected to the duty cycle detector 131, is configured to generate the error cancellation code that adjusts the phase of the initial multi-phase clock signal based on the detection result.

[0067] Here, the duty cycle detector 131 can be directly or indirectly connected to the phase error detector 12. Similarly, the error cancellation code generator 132 can be directly or indirectly connected to the duty cycle detector 131. Furthermore, the error cancellation code generator 131 is also connected to the multi-phase clock signal generator 11, and the connection can also be direct or indirect.

[0068] Among them, a duty cycle detector 131 can be used to detect the duty cycle of the error signal (duty cycle = high level time / period time) to obtain the detection result that can be characterized by numerical values ​​or codes.

[0069] As described above, the initial multi-phase clock signal is a four-phase clock signal. After phase error detection by phase error detector 12, the obtained error signals include a first error signal and a second error signal. Then, duty cycle detector 131 can be used to perform duty cycle detection on the first error signal and the second error signal to obtain a detection result.

[0070] Here, an error cancellation code generator 132 can be used to adjust a preset cancellation code based on the detection result to obtain an error cancellation code, or to generate an error cancellation code that matches the detection result. The preset cancellation code can be binary code stored in advance within the error cancellation code generator 132.

[0071] Here, the error elimination code can be a binary code; the number of bits can be determined according to actual needs, such as three-bit binary code, four-bit binary code, etc.

[0072] In some feasible implementation methods, such as Figure 6 As shown, when the duty cycle detector 131 includes a signal converter 1311 and a voltage comparator 1312, the signal converter 1311 can be used to convert the duty cycle information in the first error signal and the second error signal into corresponding voltage signals. Then, the voltage comparator 1312 can be used to compare the voltage signals output by the signal converter 1311 to obtain a detection result for counting operations. In this way, by sequentially converting and comparing the two error signals, a detection result suitable for counting operations is obtained, providing a basis for subsequently generating a related error cancellation code based on the detection result suitable for counting operations. (Refer to...) Figure 6 The diagram shown illustrates the composition of another phase adjustment circuit provided in this application embodiment. The phase adjustment circuit 10 includes: a multi-phase clock signal generator 11, a first logic operation module 121, a second logic operation module 122, a signal converter 1311, a voltage comparator 1312, and an error cancellation code generator 132, wherein:

[0073] The signal converter 1311 is configured to charge and discharge the first capacitor using the first error signal to convert the duty cycle information in the first error signal into the first voltage signal, and to charge and discharge the second capacitor using the second error signal to convert the duty cycle information in the second error signal into the second voltage signal.

[0074] The voltage comparator 1312 is configured to compare the first voltage signal and the second voltage signal to obtain a comparison signal, and convert the comparison signal into the detection result for performing a counting operation.

[0075] Here, the signal converter 1311 may include at least two conversion units. The devices included in the two conversion units may be the same or different. That is, any device capable of converting the duty cycle information in the relevant error signal into the relevant voltage signal is sufficient.

[0076] The signal converter 1311 can be used to convert the first error signal and the second error signal into different voltage signals based on the difference in duty cycle information; then the voltage comparator 1312 is used to compare the first voltage signal and the second voltage signal to obtain the corresponding detection result.

[0077] It should be noted that in the phase adjustment circuit 10, the signal converter 1311 is connected to the second logic operation module 122 in the phase error detector 12, and the voltage comparator 1312 is connected to the error cancellation code generator 132. Thus, when the voltage comparator 1312 outputs a detection result that can be used for counting operations, the error cancellation code generator 132 connected to it can be a counter.

[0078] Here, the counter can be a synchronous counter or an asynchronous counter, etc.

[0079] In some feasible implementation methods, such as Figure 7 As shown, when the error cancellation code generator 132 includes a synchronization counter 1321, this synchronization counter 1321 can be used to count the detection results to obtain the corresponding error cancellation code. In this way, by using only a conventional synchronization counter to convert the detection results into a multi-phase clock signal generator 11, the error cancellation code that can be recognized not only simplifies the overall execution logic of the phase adjustment circuit 10, but also makes it relatively convenient to generate error cancellation codes for phase error cancellation. (Reference) Figure 7 The diagram shown is a structural schematic of another phase adjustment circuit provided in an embodiment of this application. The phase adjustment circuit 10 includes: a multi-phase clock signal generator 11, a first logic operation module 121, a second logic operation module 122, a signal converter 1311, a voltage comparator 1312, and a synchronization counter 1321, wherein:

[0080] The synchronization counter 1321 is connected to the duty cycle detector 131 and is configured to generate an error elimination code based on the detection result.

[0081] Here, the synchronous counter 1321 can be composed of a flip-flop (FF) and a gate circuit. It is used to generate an error cancellation code by being triggered by the internal FF after receiving the detection result.

[0082] Here, as Figure 8As shown, the error cancellation code generator 132 can also be composed of a D flip-flop (DFF) 1322 and a synchronization counter 1321. The D flip-flop 1322 can be used. When the target multi-phase clock signal with the phase difference between adjacent phase signals meets the preset condition is obtained, a latch signal is received so that the output result of the voltage comparator 1312 remains unchanged. Thus, the voltage comparator 1312 will not output a new detection result to the synchronization counter 1321. It can also latch the detection result output by the voltage comparator 1312 and output it to the synchronization counter 1321 at an appropriate time.

[0083] Following the above description, when the initial multi-phase clock signal is a four-phase clock signal, the second logic operation module 122 of the phase adjustment circuit 10 outputs a first error signal and a second error signal, which can then be synchronously input to the duty cycle detector 131. Figure 8 The diagram shows a duty cycle detector and an error cancellation code generator in the phase adjustment circuit provided in this embodiment. The circuit can employ methods such as... Figure 8 The signal converter 1311 shown (including two identical circuits: signal conversion circuits composed of MOS transistors) converts the duty cycle information in the first error signal and the second error signal into a first voltage signal and a second voltage signal, respectively. Using... Figure 8 The voltage comparator 1312 shown compares the input first voltage signal and the second voltage signal to obtain a detection result. The detection result is input to the synchronization counter 1321 based on the control signal of the D flip-flop 1322 to generate an error cancellation code corresponding to the increase or decrease of signal delay.

[0084] Here, as Figure 8 As shown, the signal converter 1311 can be used to charge and discharge a first capacitor using a first error signal to convert the duty cycle information in the first error signal into a first voltage signal. It can also use a second error signal to charge and discharge a second capacitor to convert the duty cycle information in the second error signal into a second voltage signal.

[0085] It should be noted that, as Figure 8 As shown, under certain conditions (for example, the phase difference between adjacent phase signals has been obtained by using the phase adjustment circuit 10 to meet the preset conditions for the target multi-phase clock signal), the generation of the correlation error elimination code by the synchronous counter 1321 can be stopped. The stopping operation can be performed in two ways: 1. Stop the clock signal input to the synchronous counter 1321; 2. Use a latch signal to keep the output of the voltage comparator 1312 unchanged.

[0086] At the same time, such as Figure 8The voltage comparator 1312 shown can connect a first voltage signal and a second voltage signal to their corresponding "+" and "-" input terminals as needed, thereby outputting different levels based on the difference in voltage between the two input terminals. For example, when the voltage at the "+" input terminal is higher than that at the "-" input terminal, the voltage comparator 1312 outputs a high level; when the voltage at the "+" input terminal is lower than that at the "-" input terminal, the voltage comparator 1312 outputs a low level. A high level can be represented by 1, and a corresponding low level can be represented by 0.

[0087] In some feasible implementations, a synchronous counter 1321 can be used. Based on different detection results, the value of the preset cancellation code is adjusted differently to obtain an error cancellation code representing an increase or decrease in signal delay. Then, based on this error cancellation code, the phase of the initial multi-phase clock signal is delayed by increasing or decreasing the delay to obtain a target multi-phase clock signal that meets the preset requirements. In this way, using only a synchronous counter to generate error cancellation codes for increasing or decreasing signal delay based on different detection results, the overall execution logic of the phase adjustment circuit 10 is relatively simple. That is, the synchronous counter 1321 can be configured as follows:

[0088] The synchronization counter 1321 is configured to make a first adjustment to the value of the preset elimination code when the detection result is a first value, so as to obtain the error elimination code corresponding to the increase in signal delay;

[0089] The synchronization counter 1321 is further configured to, when the detection result is a second value, make a second adjustment to the value of the preset elimination code to obtain the error elimination code corresponding to the reduction of signal delay.

[0090] Here, the detection result can be represented by any numerical value. The first and second values ​​are different values. For example, the first value can be 1 or 0, and correspondingly, the second value can be 0 or 1.

[0091] Here, a synchronous counter 1321 can be used to adjust the value of the preset elimination code based on the detection results. This adjustment includes, but is not limited to, increasing, decreasing, or keeping it unchanged. The magnitude of the increase or decrease can be determined according to actual needs.

[0092] Among them, a synchronous counter 1321 can be used to increase the value of the preset elimination code when the detection result is the first value, so as to obtain the error elimination code corresponding to the increase in signal delay, or decrease the value of the preset elimination code when the detection result is the second value, so as to obtain the error elimination code corresponding to the decrease in signal delay.

[0093] Here, a synchronous counter 1321 can also be used. When the detection result is 1, the value of the preset elimination code is incremented by 1 to obtain the error elimination code corresponding to the increase in signal delay. Or, when the detection result is 0, the value of the preset elimination code is decremented by 1 to obtain the error elimination code corresponding to the decrease in signal delay.

[0094] It should be noted that the preset elimination code can be any form of code, such as three-bit binary code, four-bit binary code, etc. Furthermore, the error elimination code is a code with the same representational form as the preset elimination code.

[0095] In some embodiments, such as Figure 9 As shown, when a multi-phase clock signal generator 11 is used to adjust the phase of the initial multi-phase clock signal based on an error cancellation code to obtain the target multi-phase clock signal, the multi-phase clock signal generator 11 may also include a delay unit 111. This delay unit can be used to adjust the switching state of its delay unit based on the received error cancellation code, thereby adjusting the corresponding delay time. This delay time is then used to adjust the phase of the initial multi-phase clock signal to obtain the target multi-phase clock signal. Thus, by directly using the delay unit 111 in the multi-phase clock signal generator 11 to calibrate the phase error between the initial multi-phase clock signals generated by the multi-phase clock signal generator 11 based on the error cancellation code, a target multi-phase clock signal whose phase difference between the clock signals meets the preset requirements can be obtained more accurately. Figure 9 The diagram shows a schematic representation of another phase adjustment circuit provided in this application embodiment. The phase adjustment circuit 10 includes: a multi-phase clock signal generator 11 with a delay unit 111, a first logic operation module 121, a second logic operation module 122, a signal converter 1311, a voltage comparator 1312, and a synchronization counter 1321, wherein:

[0096] The delay unit 111 is configured to adjust the delay time based on the error cancellation code and to perform phase adjustment on the initial multi-phase clock signal based on the delay time to obtain the target multi-phase clock signal.

[0097] Here, the delay unit 111 is an electronic component that achieves the delay effect, such as a capacitor, inductor, transistor, etc. For example, when the error cancellation code is a 3-bit code, the delay unit 111 can be used to turn on the delay device and delay for a first duration when the error cancellation code is 000; when the error cancellation code is 001, the delay device delays for a second duration; when the error cancellation code is 100, the delay device delays for a third duration; and when the error cancellation code is 111, the delay unit delays for a fourth duration; wherein, the fourth duration > the third duration > the second duration > the first duration.

[0098] It should be noted that the delay unit 111 can receive an enable signal, which, when the enable signal is valid, adjusts the switching state of its adjustment unit based on the error cancellation code to obtain the delay time corresponding to the error cancellation code. Whether the enable signal is active high or low depends on the specific application.

[0099] Following the description above, the initial multi-phase clock signal includes a four-phase initial clock signal; the four-phase initial clock signal sequentially includes a first initial clock signal, a second initial clock signal, a third initial clock signal, and a fourth initial clock signal; the target multi-phase clock signal includes a four-phase target clock signal, the four-phase target clock signal sequentially including a first target clock signal, a second target clock signal, a third target clock signal, and a fourth target clock signal. Thus, by using delay unit 111, based on the error cancellation code, adjusting only the phases of the second and fourth initial clock signals, a four-phase clock signal with a 90-degree phase difference between adjacent clock signals can be conveniently obtained. That is, the delay unit 111 can also be configured as follows:

[0100] The delay unit 111 is configured to adjust the phase of the second initial clock signal and the fourth initial clock signal based on the error cancellation code, so that the phase difference between adjacent clock signals among the first target clock signal, the second target clock signal, the third target clock signal and the fourth target clock signal is 90 degrees.

[0101] Here, a delay unit 111 can be used to adjust the phases of the second and fourth initial clock signals based on the delay time matched by the error cancellation code, thereby obtaining a four-phase target clock signal with a phase difference of 90 degrees between adjacent clock signals. However, the invention is not limited to this; the phases of the first and third initial clock signals, or the phases of the second and third initial clock signals, can also be adjusted based on the delay code, and so on.

[0102] Based on the above description, such as Figure 10 The diagram shown is a schematic flowchart illustrating the generation of a target multi-phase clock signal using the phase adjustment circuit provided in this application embodiment. Compared to the prior art (see reference...), this... Figure 1The following components are added (as shown): a phase error detector 12 (which may further include a first logic operation module 121 and a second logic operation module 122), a duty cycle detector 131 (which may further include a signal converter 1311 and a voltage comparator 1312), and an error cancellation code generator 132 (which may include a synchronization counter 1321 and a D flip-flop 1322). In this embodiment, based on the DLL circuit, the newly added phase error detector 12, duty cycle detector 131, and error cancellation code generator 132 generate an error cancellation code corresponding to the phase error of the initial four-phase clock signal. Simultaneously, the delay unit 111 included in the four-phase clock signal generator 11 provided in this embodiment is used to adjust the phase of the initial four-phase clock signal based on the error cancellation code, so as to obtain a target four-phase clock signal whose phase difference between clock signals meets preset requirements (e.g., the phase difference between adjacent clock signals is 90°). In this way, the phase error of the initial multi-phase clock signal can be calibrated to obtain a multi-phase clock signal with accurate relative phase relationship, as well as an internal clock signal that is precisely synchronized with the external clock signal, thereby ensuring the accuracy of the relevant storage device in the read / write operation.

[0103] This application also provides a phase adjustment method, such as... Figure 11 The diagram illustrates a phase adjustment method according to an embodiment of this application. This phase adjustment method can be applied to any phase adjustment circuit 10 provided in the above embodiments, and includes the following steps:

[0104] Step S101: Generate an initial multi-phase clock signal using a multi-phase clock signal generator;

[0105] Step S102: Using a phase error detector, the initial multi-phase clock signal is subjected to phase error detection to obtain an error signal that characterizes the phase difference information between the initial multi-phase clock signals;

[0106] Step S103: Use a phase error canceller to detect the error signal and obtain the error cancellation code;

[0107] Step S104: Using the multi-phase clock signal generator, the initial multi-phase clock signal is phase-adjusted based on the error cancellation code to obtain the target multi-phase clock signal.

[0108] In some embodiments, the phase adjustment method can be applied to the phase adjustment circuit 10 provided in any of the above embodiments. The phase adjustment circuit 10 includes: a multi-phase clock signal generator 11; a phase error detector 12 connected to the multi-phase clock signal generator 11; and a phase error canceller 13 connected to both the phase error detector 12 and the multi-phase clock signal generator 11. For a detailed description of the multi-phase clock signal generator 11, the phase error detector 12, and the phase error canceller 13, please refer to the detailed description of the related adjustment circuit 10 described above.

[0109] Here, the initial multi-phase clock signal generated by the multi-phase clock signal generator 11 includes four-phase clock signals, which are sequentially comprised of a first initial clock signal, a second initial clock signal, a third initial clock signal, and a fourth initial clock signal. For example, firstly, the logic operation module in the phase error detector 12 performs phase error detection on the initial four-phase clock signals, obtaining a first error signal characterizing the phase difference information between the first and second initial clock signals, and a second error signal characterizing the phase difference information between the second and third initial clock signals. Then, the error canceller 13 simultaneously inputs the first and second error signals to the correlation signal converter for duty cycle detection, obtaining a detection result, and subsequently generating an error cancellation code (e.g., an n-bit binary code, where n is greater than or equal to 1) that matches the detection result. Finally, a device (e.g., a delayer) inside the multi-phase clock signal generator 11 for identifying the error cancellation code can be used to adjust the phase delay of the second initial clock signal and the fourth initial clock signal based on the error cancellation code (e.g., adjusting the switching state of the delayer and the delay time through the error cancellation code) to obtain a target four-phase clock signal with a phase difference of 90 degrees between adjacent clock signals.

[0110] For a more detailed implementation process, please refer to the detailed description of the phase adjustment circuit 10 in the above embodiments, which will not be repeated here.

[0111] The phase adjustment method provided in this application detects the phase error of an initial multi-phase clock signal to obtain an error signal characterizing the phase difference between the initial multi-phase clock signals. This error signal is then converted into a corresponding error cancellation code, and the initial multi-phase clock signal is directly phase-adjusted based on this error cancellation code to obtain a target multi-phase clock signal whose phase difference between the clock signals meets preset requirements. This enables phase error calibration of the initial multi-phase clock signal, resulting in a multi-phase clock signal with accurate relative phase relationships, and an internal clock signal that is precisely synchronized with the external clock signal. This ensures the accuracy of the relevant storage device during data read / write operations.

[0112] Furthermore, this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the phase adjustment method provided in any of the above embodiments.

[0113] This application embodiment also provides a memory 1, such as Figure 12 The diagram shows a schematic representation of a memory provided in an embodiment of this application; wherein the memory 1 includes the phase adjustment circuit 10 provided in any example of this application.

[0114] Here, the phase adjustment circuit 10 is a circuit that can detect and adjust the phase difference between multi-phase clock signals. It can be used as part of the DLL circuit in the memory 1, or it can be deployed in the memory 1 in parallel with the DLL circuit.

[0115] The phase adjustment circuit 10 is used to provide the memory 1 with an internal clock signal synchronized with the external clock signal (i.e., the target multi-phase clock signal mentioned in the above embodiment). This ensures the accuracy of the memory 1 during data read / write operations.

[0116] In practical applications, the phase adjustment circuit provided in this embodiment can be applied to various types of memory. As an example, it can be applied to, but is not limited to, Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM). Exemplarily, DRAM includes, but is not limited to, any one of various generations of Double Data Rate Memory (DDR) and various generations of Low Power Double Data Rate Synchronous Dynamic Random Access Memory (LPDDR), etc., without specific limitation.

[0117] For specific details regarding the phase adjustment circuit 10 in memory 1, please refer to the description of the above embodiments, which will not be repeated here.

[0118] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative; for example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. In addition, the various components shown or discussed are coupled to each other or directly coupled.

[0119] The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0120] The above are merely some embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A phase adjustment circuit, characterized by, The phase adjustment circuit comprises a multi-phase clock signal generator, a phase error detector and a phase error eliminator, wherein: The multi-phase clock signal generator is configured to generate an initial multi-phase clock signal; The phase error detector is connected to the multi-phase clock signal generator and is configured to perform phase error detection on the initial multi-phase clock signal to obtain an error signal for representing phase difference information between the initial multi-phase clock signal; The phase error eliminator is connected to the phase error detector and is configured to perform detection on the error signal to obtain an error elimination code; The multi-phase clock signal generator is further connected to the phase error eliminator and is configured to receive the error elimination code and perform phase adjustment on the initial multi-phase clock signal based on the error elimination code to obtain a target multi-phase clock signal; The phase error eliminator comprises a duty cycle detector and an error elimination code generator; The duty cycle detector is connected to the phase error detector and is configured to perform duty cycle detection on the error signal to obtain a detection result; The error elimination code generator is connected to the duty cycle detector and is configured to generate the error elimination code for performing phase adjustment on the initial multi-phase clock signal based on the detection result; The phase error detector comprises a first logic operation module and a second logic operation module; The first logic operation module is configured to perform AND operation on a received preset enable signal and each initial clock signal in the initial multi-phase clock signal to obtain an intermediate signal of each initial clock signal; The second logic operation module is configured to perform logic operation on intermediate signals of adjacent phases in the initial multi-phase clock signal to obtain the error signal; The initial multi-phase clock signal comprises four-phase initial clock signals; the four-phase initial clock signals comprise a first initial clock signal, a second initial clock signal, a third initial clock signal and a fourth initial clock signal in sequence; and the error signal comprises a first error signal and a second error signal; The second logic operation module is further configured to perform NAND operation on the intermediate signal of the first initial clock signal and an inverted signal of the intermediate signal of the second initial clock signal to obtain the first error signal, and perform NAND operation on the intermediate signal of the second initial clock signal and an inverted signal of the intermediate signal of the third initial clock signal to obtain the second error signal.

2. The phase adjustment circuit of claim 1, wherein The error elimination code generator comprises a synchronous counter; The synchronous counter is connected to the duty cycle detector and is configured to generate the error elimination code based on the detection result.

3. The phase adjustment circuit according to claim 2, wherein: The synchronous counter is configured to perform first adjustment on a value of a preset elimination code to obtain the error elimination code corresponding to signal delay increase when the detection result is a first numerical value. The synchronization counter is further configured to, when the detection result is a second value, perform a second adjustment on the value of the preset cancellation code to obtain the error cancellation code corresponding to signal delay reduction.

4. The phase adjustment circuit of claim 1, wherein, The duty cycle detector comprises a signal converter and a voltage comparator. The signal converter is configured to charge and discharge a first capacitor using the first error signal to convert duty cycle information in the first error signal into a first voltage signal, and charge and discharge a second capacitor using the second error signal to convert duty cycle information in the second error signal into a second voltage signal. The voltage comparator is configured to compare the first voltage signal and the second voltage signal to obtain a comparison signal, and convert the comparison signal into the detection result for counting operation.

5. The phase adjustment circuit of claim 1, wherein, The multi-phase clock signal generator comprises a delay unit. The delay unit is configured to adjust a delay time based on the error cancellation code, and adjust the phase of the initial multi-phase clock signal based on the delay time to obtain the target multi-phase clock signal.

6. The phase adjustment circuit of claim 5, wherein, The initial multi-phase clock signal comprises a four-phase initial clock signal, and the four-phase initial clock signal comprises a first initial clock signal, a second initial clock signal, a third initial clock signal and a fourth initial clock signal in sequence. The target multi-phase clock signal comprises a four-phase target clock signal, and the four-phase target clock signal comprises a first target clock signal, a second target clock signal, a third target clock signal and a fourth target clock signal in sequence. The delay unit is configured to adjust the phase of the second initial clock signal and the fourth initial clock signal based on the error cancellation code, so that the phase difference between adjacent clock signals in the first target clock signal, the second target clock signal, the third target clock signal and the fourth target clock signal is 90 degrees.

7. A phase adjustment method based on the phase adjustment circuit according to claim 1, characterized by, The phase adjustment method comprises: generating an initial multi-phase clock signal using a multi-phase clock signal generator; detecting the phase error of the initial multi-phase clock signal using a phase error detector to obtain an error signal representing phase difference value information between the initial multi-phase clock signals; detecting the error signal using a phase error canceller to obtain an error cancellation code; adjusting the phase of the initial multi-phase clock signal based on the error cancellation code using the multi-phase clock signal generator to obtain a target multi-phase clock signal.

8. A memory, comprising: The memory comprises at least the phase adjustment circuit according to any one of claims 1 to 6.

Images