Data sampling circuit and memory

Abstract

The invention relates to a data sampling circuit and a memory, and the data sampling circuit comprises an initial reference voltage generation module which is used for generating a first initial reference voltage, a second initial reference voltage, a third initial reference voltage and a fourth initial reference voltage; the data receiving module is used for comparing the data to be sampled with the first initial reference voltage to generate first data, comparing the data to be sampled with the second initial reference voltage to generate second data, comparing the data to be sampled with the third initial reference voltage to generate third data, comparing the data to be sampled with the fourth initial reference voltage to generate fourth data, in the comparison process, the side where the data to be sampled is located or the sides where the first to fourth initial reference voltages are located are compensated through the compensation current; the first selection circuit and the second selection circuit are configured to select to output sampling result data based on the first data, the second data, the third data or the fourth data.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor circuit design, and in particular to a data sampling circuit and a memory. Background Art

[0002] In the design of memory receiver circuits, the data to be sampled is usually sampled based on the effective edge of the sampling clock. The sampling of the data to be sampled is to compare the level of the data to be sampled with the reference voltage. If the level of the data to be sampled is greater than the reference voltage, the output data "1" is the sampling result of a high level. If the level of the data to be sampled is less than the reference voltage, the output data "0" is the sampling result of a low level.

[0003] In computer high-speed links, as the transmission speed of data signals becomes faster and faster, it is inevitable that significant inter-symbol interference (ISI) will occur. The influence of ISI may cause the level of the data to be sampled to be unable to rise to a level greater than the reference voltage, causing the receiver to sample incorrectly and output data "0", or cause the level of the data to be sampled to be unable to drop to a level less than the reference voltage, causing the receiver to sample incorrectly and output data "1". Summary of the invention

[0004] The embodiments of the present disclosure provide a data sampling circuit and a memory to improve the accuracy of data sampling performed by the memory.

[0005] An embodiment of the present disclosure provides a data sampling circuit, including: an initial reference voltage generating module, for receiving an original code, a first code, and a second code, and generating a first initial reference voltage based on the original code + the first code + the second code, generating a second initial reference voltage based on the original code + the first code - the second code, generating a third initial reference voltage based on the original code - the first code + the second code, and generating a fourth initial reference voltage based on the original code - the first code - the second code; a data receiving module, for receiving the first initial reference voltage, the second initial reference voltage, the third initial reference voltage, the fourth initial reference voltage, a third selection signal, and data to be sampled, and configured to compare the data to be sampled with the first initial reference voltage based on the third selection signal to generate the first data, compare the data to be sampled with the second initial reference voltage based on the third selection signal to generate the second data, compare the data to be sampled with the third initial reference voltage based on the third selection signal to generate the third data, and compare the data to be sampled with the fourth initial reference voltage based on the third selection signal to generate the fourth data; the third selection signal is configured to, based on the first initial reference voltage, the second initial reference voltage, the third initial reference voltage, the fourth initial reference voltage, the third selection signal, and data to be sampled, and to generate the fourth data. In the process of comparing the second initial reference voltage, the third initial reference voltage, the fourth initial reference voltage and the data to be sampled, a compensation current is provided to the side where the first initial reference voltage, the second initial reference voltage, the third initial reference voltage and the fourth initial reference voltage are located, or a compensation current is provided to the side where the data to be sampled is located; a first selection circuit is used to receive the first data, the second data, the third data, the fourth data and the second selection signal, and is configured to select to output the first reference data based on the first data or the second data based on the second selection signal, and to select to output the second reference data based on the third data or the fourth data based on the second selection signal; a second selection circuit is used to receive the first reference data, the second reference data and the first selection signal, and is configured to select to output the sampling result data based on the first reference data or the second reference data based on the first selection signal; wherein the second selection signal is used to consider the influence of the previous second bit data on the current data to be sampled, the first selection signal is used to consider the influence of the previous first bit data on the current data to be sampled, and the third selection signal is used to consider the influence of at least the previous third bit data of all data before the previous 2 bits on the current data to be sampled.

[0006] For the sampling circuit provided in this embodiment, based on the sampling influence of multiple data before the first 2 bits on the current data to be sampled, the side where the data to be sampled is located or the side where the first initial reference voltage to the fourth initial reference voltage are located is compensated by a compensation current, thereby offsetting the sampling influence of multiple data before the first 2 bits on the current data to be sampled; and based on the sampling influence of the previous first bit data and the previous second bit data on the current data to be sampled, an output adaptation comparison result is selected as the sampling result data of the memory, thereby offsetting the sampling influence of the previous first bit data and the previous second bit data on the current data to be sampled, thereby improving the accuracy of data sampling of the memory.

[0007] Optionally, the data receiving module includes: a first receiving circuit, which is used to receive a first initial reference voltage, a third selection signal and data to be sampled, and is configured to compare the data to be sampled and the first initial reference voltage based on the third selection signal to generate first data, and the third selection signal is used to provide a compensation current to the side where the first initial reference voltage is located, or to provide a compensation current to the side where the data to be sampled is located during the comparison between the first initial reference voltage and the data to be sampled; a second receiving circuit, which is used to receive a second initial reference voltage, a third selection signal and data to be sampled, and is configured to compare the data to be sampled and the second initial reference voltage based on the third selection signal to generate second data, and the third selection signal is used to provide a compensation current to the side where the second initial reference voltage is located, or to provide a compensation current to the side where the data to be sampled is located during the comparison between the second initial reference voltage and the data to be sampled. providing a compensation current; a third receiving circuit, for receiving a third initial reference voltage, a third selection signal and data to be sampled, and configured to compare the data to be sampled and the third initial reference voltage based on the third selection signal to generate third data, and the third selection signal is used to provide a compensation current to the side where the third initial reference voltage is located, or to provide a compensation current to the side where the data to be sampled is located during the comparison between the third initial reference voltage and the data to be sampled; a fourth receiving circuit, for receiving a fourth initial reference voltage, a third selection signal and data to be sampled, and configured to compare the data to be sampled and the fourth initial reference voltage based on the third selection signal to generate fourth data, and the third selection signal is used to provide a compensation current to the side where the fourth initial reference voltage is located, or to provide a compensation current to the side where the data to be sampled is located during the comparison between the fourth initial reference voltage and the data to be sampled.

[0008] Optionally, the first receiving circuit includes: a first N-type transistor, whose control end is used to receive a first initial reference voltage, a first terminal is used to output first data, a second terminal is connected to a first end of a first current source, and the second end of the first current source is grounded; a second N-type transistor, whose control end is used to receive data to be sampled, a first terminal is connected to control ends of a first P-type transistor and a second P-type transistor, and a second terminal is connected to a first end of the first current source; a first terminal of the first P-type transistor is used to receive a power supply signal, and a second terminal is connected to a first terminal of the first N-type transistor; a first terminal of the second P-type transistor is connected to a first terminal of the first P-type transistor, and a second terminal is connected to a first terminal of the second N-type transistor; and an adjustment unit, which is connected to the first terminal of the first N-type transistor and the first terminal of the second N-type transistor, and is configured to provide a compensation current to the first terminal of the first N-type transistor or the first terminal of the second N-type transistor based on a third selection signal.

[0009] Optionally, the regulating unit includes: a third N-type transistor, a first terminal connected to the first terminal of the first N-type transistor, and a control end for receiving a first regulating voltage, the voltage value of the first regulating voltage is adjusted based on a third code, and the voltage value of the first regulating voltage is positively correlated with the value of the third code; a fourth N-type transistor, a first terminal connected to the second terminal of the third N-type transistor, a control end for receiving a third selection signal, a second terminal connected to the first end of the second current source, and the second end of the second current source is grounded; a fifth N-type transistor, a first terminal connected to the first terminal of the second N-type transistor, and a control end for receiving the first regulating voltage; a sixth N-type transistor, a first terminal connected to the second terminal of the fifth N-type transistor, a control end for receiving an inverted signal of the third selection signal, and a second terminal connected to the first end of the second current source.

[0010] Optionally, the regulating unit includes: a third P-type transistor, a first terminal for receiving a power supply signal, a control terminal for receiving a second regulating voltage, the voltage value of the second regulating voltage is adjusted based on a third code, and the voltage value of the second regulating voltage is negatively correlated with the value of the third code; a fourth P-type transistor, a first terminal connected to the second terminal of the third P-type transistor, a control terminal for receiving a third selection signal, and a second terminal connected to the first terminal of the first N-type transistor; a fifth P-type transistor, a first terminal connected to the first terminal of the third P-type transistor, and a control terminal for receiving the second regulating voltage; a sixth P-type transistor, a first terminal connected to the second terminal of the fifth P-type transistor, a control terminal for receiving an inverted signal of the third selection signal, and a second terminal connected to the first terminal of the second N-type transistor.

[0011] Optionally, the initial reference voltage generating module is further configured to generate a first adjustment voltage based on a third code.

[0012] Optionally, the voltage value of the first initial reference voltage>the voltage value of the second initial reference voltage>the voltage value of the third initial reference voltage>the voltage value of the fourth initial reference voltage.

[0013] Optionally, the initial reference voltage generating module includes: a voltage divider circuit including N voltage output terminals, and the voltage outputted by each voltage output terminal is different, and N is an integer greater than 1; a decoding circuit, used to receive the original code, the first code and the second code, and configured to generate a first processing signal based on the original code + the first code + the second code, generate a second processing signal based on the original code + the first code - the second code, generate a third processing signal based on the original code - the first code + the second code, and generate a fourth processing signal based on the original code - the first code - the second code; the first processing circuit is connected to the voltage divider circuit and the decoding circuit , configured to select the corresponding voltage output terminal in the voltage divider circuit to output the first initial reference voltage based on the first processing signal; the second processing circuit, connected to the voltage divider circuit and the decoding circuit, configured to select the corresponding voltage output terminal in the voltage divider circuit to output the second initial reference voltage based on the second processing signal; the third processing circuit, connected to the voltage divider circuit and the decoding circuit, configured to select the corresponding voltage output terminal in the voltage divider circuit to output the third initial reference voltage based on the third processing signal; the fourth processing circuit, connected to the voltage divider circuit and the decoding circuit, configured to select the corresponding voltage output terminal in the voltage divider circuit to output the fourth initial reference voltage based on the fourth processing signal.

[0014] Optionally, the voltage divider circuit comprises: N-1 first resistors connected in series, wherein the first end of the first first resistor is used to receive the first internal voltage, the second end of the last first resistor is used to receive the second internal voltage, and the second end of each first resistor is connected to the first end of the next first resistor; the voltage value of the first internal voltage is greater than the voltage value of the second internal voltage; the two ends of each first resistor serve as output ports to form N voltage output ends; the first processing signal comprises N first sub-signals, and the N first sub-signals include only one valid signal, and the first processing circuit comprises: N first switching transistors, and the control end of each first switching transistor corresponds to receiving the corresponding first sub-signal; the first terminal of each first switching transistor is correspondingly connected to a corresponding voltage output end of the N voltage output ends, and the second terminal is connected to the output end of the first processing circuit to output a first initial reference voltage.

[0015] Another embodiment of the present disclosure further provides a memory, comprising the data sampling circuit provided by the above embodiment, so as to improve the accuracy of data sampling of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, and these exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise specified, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1 A schematic diagram of the influence of the first bit of data and the first two bits of data on the DQ of the sampled data provided by an embodiment of the present disclosure;

[0018] Figure 2 A schematic diagram showing the principle of sampling the data DQ to be sampled using different reference voltages provided in an embodiment of the present disclosure;

[0019] Figure 3 A structural schematic diagram of a data sampling circuit provided in one embodiment of the present disclosure;

[0020] Figure 4 A schematic diagram of the structure of a data receiving module provided in one embodiment of the present disclosure;

[0021] Figure 5 A schematic diagram of the structure of a first receiving circuit provided in an embodiment of the present disclosure;

[0022] Figure 6 A schematic diagram of the structure of an adjustment unit provided in one embodiment of the present disclosure;

[0023] Figure 7 A schematic diagram of the structure of another adjustment unit provided in one embodiment of the present disclosure;

[0024] Figure 8 A schematic diagram of the structure of an initial reference voltage generating module provided in one embodiment of the present disclosure;

[0025] Fig. 9 A schematic diagram of the structure of a voltage divider circuit and a first processing circuit provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] As can be seen from the background technology, in a computer high-speed link, as the transmission speed of data signals becomes faster and faster, it is inevitable that significant inter-symbol interference (ISI) will occur. The influence of ISI may cause the level of the data to be sampled to be unable to rise to a level greater than the reference voltage, causing the receiver to sample incorrectly and output data "0", or cause the level of the data to be sampled to be unable to drop to a level less than the reference voltage, causing the receiver to sample incorrectly and output data "1".

[0027] An embodiment of the present disclosure provides a data sampling circuit to improve the accuracy of data sampling of a memory.

[0028] It can be understood by those skilled in the art that in the various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be implemented. The division of the following embodiments is for the convenience of description and should not constitute any limitation on the specific implementation of the present disclosure. The various embodiments can be combined with each other and referenced to each other without contradiction.

[0029] Figure 1 A schematic diagram of the effect of the first bit of data and the first two bits of data provided in this embodiment on the DQ of the sampled data to be processed, Figure 2 A schematic diagram showing the principle of sampling the data DQ to be sampled using different reference voltages provided in this embodiment, Figure 3 A schematic diagram of the structure of the data sampling circuit provided in this embodiment, Figure 4 A schematic diagram of the structure of the data receiving module provided in this embodiment, Figure 5 A schematic diagram of the structure of a first receiving circuit provided in this embodiment, Figure 6 A schematic diagram of the structure of an adjustment unit provided in this embodiment, Figure 7 A schematic diagram of the structure of another adjustment unit provided in this embodiment, Figure 8 A schematic diagram of the structure of the initial reference voltage generating module provided in this embodiment, Fig. 9 The schematic diagram of the structure of the voltage divider circuit and the first processing circuit provided in this embodiment is as follows. The data sampling circuit provided in this embodiment is described in detail in conjunction with the accompanying drawings, as follows:

[0030] For the memory, the signal sampling of the memory is implemented based on a comparator. Specifically, the comparator compares the voltage of the data DQ to be sampled with the reference voltage based on the effective edge of the sampling signal. If the voltage of the data DQ to be sampled is greater than the reference voltage, the comparator outputs a high level, that is, data "1". If the voltage of the data DQ to be sampled is less than the reference voltage, the comparator outputs a low level, that is, data "0".

[0031] In the high-speed link of the computer, the transmission speed of the data signal is getting faster and faster, and the time interval of the effective edge of the sampling clock is getting smaller and smaller, so as to collect more data per unit time. However, this operation causes obvious inter-symbol interference (ISI) in the sampling of the memory.

[0032] For ISI, refer to Figure 1 In one example, when the data DQ to be sampled changes from "0" to "1", due to the decrease in the time interval between the effective edges of the sampling clock, when the effective edge of the sampling clock arrives, the actual level of the data DQ to be sampled does not rise to a sufficient level, which may cause the actual voltage of the data DQ to be sampled to be still less than the reference voltage at this time, and the comparator may perform erroneous sampling, thereby outputting data "0"; when the data DQ to be sampled changes from "1" to "0", due to the decrease in the time interval between the effective edges of the sampling clock, when the effective edge of the sampling clock arrives, the actual level of the data DQ to be sampled does not drop to a sufficient level, which may cause the actual voltage of the data DQ to be sampled to be still greater than the reference voltage at this time, and the comparator may perform erroneous sampling, thereby outputting data "1".

[0033] As for the influence of ISI, the commonly used solution is to set the reference voltage to a high reference voltage VCH and a low reference voltage VCL, and adjust the reference voltage used by the comparator to sample the current data DQ to be sampled based on the data of the previous bit. For example, if the current one-bit data is "0", the comparator is set to sample the current data DQ to be sampled based on the low reference voltage VCL. If the current data DQ to be sampled changes from "0" to "1", although the actual level of the data DQ to be sampled has not risen to a sufficient level, the low reference voltage VCL is used as the reference voltage, which reduces the possibility that the actual level of the data DQ to be sampled is less than the reference voltage, thereby alleviating the influence of ISI to a certain extent; similarly, if the current one-bit data is "1", the comparator is set to sample the current data DQ to be sampled based on the high reference voltage VCL. If the current data DQ to be sampled changes from "1" to "0", although the actual level of the data DQ to be sampled has not dropped to a sufficient level, the high reference voltage VCH is used as the reference voltage, which reduces the possibility that the actual level of the data DQ to be sampled is greater than the reference voltage, thereby alleviating the influence of ISI to a certain extent.

[0034] However, this solution only considers the influence of the first bit data on the current data DQ to be sampled, while the second bit data, the third bit data... also have a certain influence on the sampling of the current data DQ to be sampled; if only the influence of the first bit data on the sampling of the current data DQ to be sampled is considered, the comparator will still have the problem of incorrect sampling in practical applications.

[0035] For the influence of the first bit data and the second bit data on the sampled data DQ, please refer to Figure 1 , assuming that in an ideal situation, the high level of the data to be sampled DQ is set to 1, and the low level is set to 0; the current one-bit data is "0", and the current data to be sampled DQ is about to jump to "1". When the effective edge of the sampling clock comes, the level of the data to be sampled rises to 0.7. If the previous second bit data is also "0", when the effective edge of the sampling clock comes, the level of the data to be sampled only rises to 0.6. If the previous second bit data is "1", when the effective edge of the sampling clock comes, the level of the data to be sampled rises to 0.8; the current one-bit data is "1", when The previous data to be sampled DQ wants to jump to "0". When the effective edge of the sampling clock comes, the level of the data to be sampled drops to 0.3. If the previous second bit data is also "1", when the effective edge of the sampling clock comes, the level of the data to be sampled only drops to 0.4. If the previous second bit data is "0", when the effective edge of the sampling clock comes, the level of the data to be sampled drops to 0.2. It can be seen that after combining the influence of the previous second bit data and the previous third bit data..., the current data to be sampled DQ has a larger range of variation, and the memory still has the problem of incorrect sampling.

[0036] The impact of the third bit data, the fourth bit data, ... on the current data DQ to be sampled is similar to the impact of the first bit data on the current data DQ to be sampled and the impact of the second bit data on the current data DQ to be sampled, except that the earlier bit data has a smaller impact on the current sampled data DQ.

[0037] In order to consider the impact of the data before the to-be-sampled data DQ on the current to-be-sampled data DQ, refer to Figure 2 In this embodiment, one reference voltage V is adjusted into two reference voltages V+ and V- in combination with the influence of the first bit data on the data to be sampled DQ, and the two reference voltages V+ and V- are expanded into four reference voltages V++, V+-, V-+ and V-- in combination with the influence of the second bit data on the data to be sampled DQ. In the sampling process, the four reference voltages or the data to be sampled DQ are fine-tuned based on the influence of the third bit data and the previous data on the current data to be sampled DQ, so as to improve the accuracy of data sampling of the memory.

[0038] Specifically, refer to Figure 3 The data sampling circuit 100 provided in this embodiment includes:

[0039] The initial reference voltage generating module 103 is used to receive the original code code, the first code c1 and the second code c2, and based on the original code code <a:0>+First code c1 <a:0>+Second code c2 <a:0>Generate a first initial reference voltage Vr1 based on the original code code <a:0>+First code c1 <a:0>-Second code c2 <a:0>Generate a second initial reference voltage Vr2 based on the original code code <a:0>-First code c1 <a:0>+Second code c2 <a:0>Generate a third initial reference voltage Vr3 based on the original code code <a:0>-First code c1 <a:0>-Second code c2 <a:0>A fourth initial reference voltage Vr4 is generated.

[0040] For the initial reference voltage generating module 103, in one example, the larger the code used to generate the initial reference voltage, the larger the initial reference voltage generated; in another example, it can also be set that the larger the code used to generate the initial reference voltage, the smaller the initial reference voltage generated; in the subsequent description of this embodiment, the initial reference voltage generating module 103 is described in detail by taking the example that the larger the code used to generate the initial reference voltage, the larger the initial reference voltage generated.

[0041] Specifically, the initial reference voltage generating module 103 is based only on the original code code <a:0>The generated voltage is the reference voltage V mentioned above, that is, the original code code <a:0>The size of the reference voltage V is used to measure the size of the first code c1 <a:0>The size of the first bit data is used to measure the influence parameter of the previous first bit data on the current data to be sampled DQ. The initial reference voltage generation module 103 is based on the original code code <a:0>+First code c1 <a:0>The generated voltage is the reference voltage V+△V1, namely the V+ mentioned above; the initial reference voltage generation module 103 is based on the original code code <a:0>-First code c1 <a:0>The generated voltage is the reference voltage V-△V1, namely V- mentioned above; the second code c2 <a:0>The size of the second bit data is used to measure the influence parameter of the previous second bit data on the current data to be sampled DQ. The initial reference voltage generation module 103 is based on the original code code <a:0>+First code c1 <a:0>+Second code c2 <a:0>The generated voltage is the reference voltage V+△V1+△V2, that is, the first initial reference voltage Vr1, that is, the V++ mentioned above; the initial reference voltage generation module 103 is based on the original code code <a:0>+First code c1 <a:0>-Second code c2 <a:0>The generated voltage is a reference voltage V+△V1-△V2, that is, the second initial reference voltage Vr2, that is, the V+- mentioned above; the initial reference voltage generation module 103 is based on the original code code <a:0>-First code c1 <a:0>+Second code c2 <a:0>The generated voltage is the reference voltage V-△V1+△V2, that is, the third initial reference voltage Vr3, that is, the V-+ mentioned above; the initial reference voltage generation module 103 is based on the original code code <a:0>-First code c1 <a:0>-Second code c2 <a:0>The generated voltage is the reference voltage V-ΔV1-ΔV2, ie, the fourth initial reference voltage Vr4, ie, the V-- mentioned above.

[0042] As can be seen from the foregoing, under this setting, the voltage value of the first initial reference voltage Vr1 > the voltage value of the second initial reference voltage Vr2 > the voltage value of the third initial reference voltage Vr3 > the voltage value of the fourth initial reference voltage Vr4 .

[0043] Since the original code <a:0>The size of the reference voltage V is used to measure the size of the first code c1 <a:0>The size of c2 is used to measure the influence parameter of the previous first bit data on the current data to be sampled DQ. <a:0>The size of is used to measure the influence parameter of the previous second bit data on the current data to be sampled DQ, and the influence of the previous first bit data on the current data to be sampled DQ is greater than the influence of the previous second bit data on the current data to be sampled DQ, that is, the original code code <a:0>The value of > first code c1 <a:0>The value of > second code c2 <a:0>The value of .

[0044] Continue to refer Figure 3 The data sampling circuit 100 further includes: a data receiving module 104, which is used to receive a first initial reference voltage Vr1, a second initial reference voltage Vr2, a third initial reference voltage Vr3, a fourth initial reference voltage Vr4, a third selection signal sel3 and data DQ to be sampled. The data receiving module 104 is configured to compare the data DQ to be sampled with the first initial reference voltage Vr1 based on the third selection signal sel3 to generate the first data SJ1; compare the data DQ to be sampled with the second initial reference voltage Vr2 based on the third selection signal sel3 to generate the second data SJ2; compare the data DQ to be sampled with the third initial reference voltage Vr3 based on the third selection signal sel3 to generate the third data SJ3; compare the data DQ to be sampled with the fourth initial reference voltage Vr4 based on the third selection signal sel3 to generate the fourth data SJ4; wherein the third selection signal sel3 is configured to, in the process of comparing the first initial reference voltage Vr1, the second initial reference voltage Vr2, the third initial reference voltage Vr3, the fourth initial reference voltage Vr4 and the data DQ to be sampled, provide a compensation current to the side where the first initial reference voltage Vr1, the second initial reference voltage Vr2, the third initial reference voltage Vr3 and the fourth initial reference voltage Vr4 are located, or provide a compensation current to the side where the data DQ to be sampled is located. The third selection signal sel3 is used to consider the influence of at least the third bit of all data before the first 2 bits on the current data to be sampled DQ.

[0045] In some embodiments, the third selection signal sel3 is used to consider the influence of multiple data before the first 2 bits on the current data to be sampled DQ. At this time, the value of the third selection signal sel3 is the weighted sum of each bit of data within the considered data range, and the sum of the weights is 1. The closer the data is to the current data to be sampled DQ, the greater the weight. In an example, assuming that the third selection signal sel3 is used to consider the influence of the previous third bit data, the fourth bit data and the fifth bit data on the current data to be sampled DQ, at this time, the weight distribution of the previous third bit data is 0.6, the weight distribution of the previous fourth bit data is 0.25, and the weight distribution of the previous fifth bit data is 0.15, that is, the third selection signal sel3 = the value of the previous third bit data * 0.6 + the value of the previous fourth bit data * 0.25 + the value of the previous fifth bit data * 0.15.

[0046] In some embodiments, the third selection signal sel3 is only used to consider the impact of the previous third bit data on the current data to be sampled DQ. In some embodiments, the value of the third selection signal sel3 can be set directly based on the previous third bit data to directly feedback the compensation object of the compensation current based on the value of the previous third bit data.

[0047] Specifically, when the influence of the multiple data before the current 2 bits on the current data DQ to be sampled is equivalent to the influence of the previous third bit data being "0" on the current data DQ to be sampled, the third selection signal sel3 is used to control the data sampling circuit 104 to load the compensation current on the side where the data DQ to be sampled is located during the comparison process. When the influence of the multiple data before the current 2 bits on the current data DQ to be sampled is equivalent to the influence of the previous third bit data being "1" on the current data DQ to be sampled, the third selection signal sel3 is used to control the data sampling circuit 104 to load the compensation current on the side where the first initial reference voltage Vr1, the second initial reference voltage Vr2, the third initial reference voltage Vr3 and the fourth initial reference voltage Vr4 are located during the comparison process to offset the sampling influence of the multiple data before the previous 2 bits on the current data DQ to be sampled.

[0048] The first selection circuit 101 is used to receive the first data SJ1, the second data SJ2, the third data SJ3, the fourth data SJ4 and the second selection signal sel2, and is configured to select to output the first reference data SJC1 based on the first data SJ1 or the second data SJ2 based on the second selection signal sel2, and to select to output the second reference data SJC2 based on the third data SJ3 or the fourth data SJ4 based on the second selection signal sel2, wherein the second selection signal sel2 is used to consider the influence of the previous second bit data on the current data to be sampled.

[0049] Specifically, when the previous second bit data is "0", the second selection signal sel2 is used to control the first selection circuit 101 to output the first reference data SJC1 with the second data SJ2, and to output the second reference data SJC2 with the fourth data SJ4, wherein the second data SJ2 is obtained by comparison based on the second initial reference voltage Vr2, and the fourth data SJ4 is obtained by comparison based on the fourth initial reference voltage Vr4, that is, the comparison result of reducing the influence of the second coding c2 is selected based on the reference voltage V to offset the sampling influence of the previous second bit data on the current data to be sampled DQ. response; when the previous second bit data is "1", the second selection signal sel2 is used to control the first selection circuit 101 to output the first reference data SJC1 with the first data SJ1, and to output the second reference data SJC2 with the third data SJ3, wherein the first data SJ1 is obtained by comparison based on the first initial reference voltage Vr1, and the third data SJ3 is obtained by comparison based on the third initial reference voltage Vr3, that is, the comparison result of the increase of the influence of the second coding c2 on the reference voltage V is selected to offset the sampling influence of the previous second bit data on the current data to be sampled DQ.

[0050] In some embodiments, the second selection signal sel2 may be set directly based on the previous second bit data to feedback control the selection result of the first selection circuit 101 directly based on the value of the previous second bit data.

[0051] The second selection circuit 102 is used to receive the first reference data SJC1, the second reference data SJC2 and the first selection signal sel1, and is configured to select, based on the first selection signal sel1, to output the sampling result data SJ based on the first reference data SJC1 or the second reference data SJC2, wherein the first selection signal sel1 is used to consider the influence of the previous first bit data on the current data to be sampled, and the sampling result data SJ is the sampling result of the data sampling circuit, that is, the sampling result of the memory.

[0052] Specifically, when the previous first bit data is "0", the first selection signal sel1 is used to control the second selection circuit 102 to output the sampling result data SJ with the second reference data SJC2, wherein the second reference data SJC2 is obtained by comparison based on the third initial reference voltage Vr3 or the fourth initial reference voltage Vr4, that is, the comparison result of reducing the influence of the first coding c1 on the basis of the reference voltage V is selected to offset the sampling influence of the previous first bit data on the current data to be sampled DQ; when the previous first bit data is "1", the first selection signal sel1 is used to control the second selection circuit 102 to output the sampling result data SJ with the first reference data SJC1, wherein the first reference data SJC1 is obtained by comparison based on the first initial reference voltage Vr1 or the second initial reference voltage Vr2, that is, the comparison result of increasing the influence of the first coding c1 on the basis of the reference voltage V is selected to offset the sampling influence of the previous first bit data on the current data to be sampled DQ.

[0053] In some embodiments, the first selection signal sel1 may be set directly based on the previous first bit data to feedback control the selection result of the second selection circuit 102 directly based on the value of the previous first bit data.

[0054] For the sampling circuit provided in this embodiment, based on the sampling influence of multiple data before the first 2 bits on the current data to be sampled DQ, the side where the data to be sampled is located or the side where the first initial reference voltage to the fourth initial reference voltage are located is compensated by the compensation current, so as to offset the sampling influence of multiple data before the first 2 bits on the current data to be sampled DQ; and based on the sampling influence of the previous first bit data and the previous second bit data on the current data to be sampled DQ, the output adaptation comparison result is selected as the sampling result data of the memory, so as to offset the sampling influence of the previous first bit data and the previous second bit data on the current data to be sampled DQ, thereby improving the accuracy of data sampling of the memory.

[0055] For the data receiving module 104, in some embodiments, refer to Figure 4 , the data receiving module 104 comprises:

[0056] The first receiving circuit 410 is used to receive the first initial reference voltage Vr1, the third selection signal sel3 and the data to be sampled DQ, and is configured to compare the data to be sampled DQ and the first initial reference voltage Vr1 based on the third selection signal sel3 to generate the first data SJ1. The third selection signal sel3 is used to provide a compensation current to the side where the first initial reference voltage Vr1 is located, or to provide a compensation current to the side where the data to be sampled DQ is located during the comparison process between the first initial reference voltage Vr1 and the data to be sampled DQ.

[0057] The second receiving circuit 420 is used to receive the second initial reference voltage Vr2, the third selection signal sel3 and the data to be sampled DQ, and is configured to compare the data to be sampled DQ and the second initial reference voltage Vr2 based on the third selection signal sel3 to generate the second data SJ2. The third selection signal sel3 is used to provide a compensation current to the side where the second initial reference voltage Vr2 is located, or to provide a compensation current to the side where the data to be sampled DQ is located during the comparison between the second initial reference voltage Vr2 and the data to be sampled DQ.

[0058] The third receiving circuit 430 is used to receive the third initial reference voltage Vr3, the third selection signal sel3 and the data to be sampled DQ, and is configured to compare the data to be sampled DQ and the third initial reference voltage Vr3 based on the third selection signal sel3 to generate the third data SJ3. The third selection signal sel3 is used to provide a compensation current to the side where the third initial reference voltage Vr3 is located, or to provide a compensation current to the side where the data to be sampled DQ is located during the comparison between the third initial reference voltage Vr3 and the data to be sampled DQ.

[0059] The fourth receiving circuit 440 is used to receive the fourth initial reference voltage Vr4, the third selection signal sel3 and the data to be sampled DQ, and is configured to compare the data to be sampled DQ and the fourth initial reference voltage Vr4 based on the third selection signal sel3 to generate fourth data SJ4. The third selection signal sel3 is used to provide a compensation current to the side where the fourth initial reference voltage Vr4 is located, or to provide a compensation current to the side where the data to be sampled DQ is located during the comparison between the fourth initial reference voltage Vr4 and the data to be sampled DQ.

[0060] In some embodiments, reference Figure 5 , the first receiving circuit 410 includes: a first N-type transistor N101, a control end for receiving a first initial reference voltage Vr1, a first terminal for outputting first data SJ1, a second terminal connected to a first end of a first current source I1, and a second end of the first current source I1 is grounded; a second N-type transistor N102, a control end for receiving data to be sampled DQ, a first terminal connected to a control end of a first P-type transistor P101 and a second P-type transistor P102, and a second terminal connected to a first end of the first current source; a first terminal of the first P-type transistor P101 is used to receive a power supply signal, and a second terminal is connected to a first terminal of the first N-type transistor N101; a first terminal of the second P-type transistor P102 is connected to a first terminal of the first P-type transistor P101, and a second terminal is connected to a first terminal of the second N-type transistor N102; an adjusting unit 450, connected to a first terminal of the first N-type transistor N101 and a first terminal of the second N-type transistor N102, and configured to provide a compensation current to a first terminal of the first N-type transistor N101 or a first terminal of the second N-type transistor N102 based on a third selection signal sel3.

[0061] Specifically, the first receiving circuit 410 realizes comparison based on the first initial reference voltage Vr1 and the data to be sampled DQ by setting a differential amplifier circuit, and during the comparison process, the object providing the compensation current is adjusted by the adjustment unit 450 to offset the sampling influence of multiple data before the first 2 bits on the current data to be sampled DQ.

[0062] refer to Figure 5 In the circuit shown, ideally, when the first initial reference voltage Vr1 is greater than the data to be sampled DQ, the output of the first data SJ1 is "0", i.e., a low level; in actual situations, when the valid edge of the sampling signal arrives, the degree of decrease of the data to be sampled DQ is not enough, which may result in a situation where the data to be sampled DQ is greater than the first initial reference voltage Vr1. At this time, the adjustment unit 450 accelerates the pull-down of the potential at the first terminal of the first N-type transistor N101, which is equivalent to the pull-down effect of the potential at the first terminal of the first N-type transistor N101 when increasing the first initial reference voltage Vr1 to increase the conduction capability of the first N-type transistor N101. The effect of the adjustment unit 450 can be regarded as increasing the voltage of the first initial reference voltage Vr1, which avoids the situation where the data to be sampled DQ is greater than the first initial reference voltage Vr1 to a certain extent, thereby offsetting the sampling influence of multiple data before the first 2 bits on the current data to be sampled DQ. Ideally, when the first initial reference voltage Vr1 is less than the data to be sampled DQ, the output of the first data SJ1 is "1", i.e., a high level; in actual situations, when the valid edge of the sampling signal arrives, the rising degree of the data to be sampled DQ is not enough. This may lead to the situation that the data to be sampled DQ is less than the first initial reference voltage Vr1. At this time, the adjustment unit 450 accelerates the pull-down of the potential at the first terminal of the second N-type transistor N102, which is equivalent to the pull-down effect of the potential at the first terminal of the second N-type transistor N102 when increasing the data to be sampled DQ to increase the conduction capability of the second N-type transistor N102. The effect of the adjustment unit 450 can be regarded as increasing the voltage of the data to be sampled DQ, which avoids the situation that the data to be sampled DQ is less than the first initial reference voltage Vr1 to a certain extent, thereby offsetting the sampling influence of multiple data before the first 2 bits on the current data to be sampled DQ.

[0063] For the adjustment unit 450, refer to Figure 6 In one example, the regulating unit 450 includes: a third N-type transistor N103, a first terminal of which is connected to the first terminal of the first N-type transistor N101, and a control terminal for receiving a first regulating voltage, the voltage value of the first regulating voltage is adjusted based on the third code c3, and the voltage value of the first regulating voltage is positively correlated with the value of the third code c3; a fourth N-type transistor N104, a first terminal of which is connected to the second terminal of the third N-type transistor N103, a control terminal for receiving a third selection signal sel3, a second terminal of which is connected to the first terminal of the second current source I2, and the second terminal of the second current source I2 is grounded; a fifth N-type transistor N105, a first terminal of which is connected to the first terminal of the second N-type transistor N102, and a control terminal for receiving the first regulating voltage; a sixth N-type transistor N106, a first terminal of which is connected to the second terminal of the fifth N-type transistor N105, a control terminal for receiving an inverted signal of the third selection signal sel3, and a second terminal of which is connected to the first terminal of the second current source I2.

[0064] for Figure 6 The circuit shown, the third code c3 <a:0>For generating a first regulating voltage, and a third code c3 <a:0>The larger the value is, the stronger the pull-down capability of the adjustment unit 450 on the first terminal of the first N-type transistor N101 or the second N-type transistor N102 is.

[0065] Specifically, when the third selection signal sel3 is "1", that is, the first three bits of data are "1", and the data to be sampled is "0", the data to be sampled DQ may not drop enough at this time, and the adjustment unit 450 accelerates the pull-down of the potential at the first terminal of the first N-type transistor N101, which is equivalent to increasing the first initial reference voltage Vr1 to increase the conduction capability of the first N-type transistor N101 and the pull-down effect of the potential at the first terminal of the first N-type transistor N101. The effect of the adjustment unit 450 can be regarded as increasing the voltage of the first initial reference voltage Vr1, which avoids the situation where the data to be sampled DQ>the first initial reference voltage Vr1 to a certain extent, thereby offsetting the sampling influence of multiple data before the first 2 bits on the current data to be sampled DQ. When the third selection signal sel3 is "0", that is, the first three bits of data are "0", and the data to be sampled is "1", the data to be sampled DQ may not rise enough at this time, and the adjustment unit 450 accelerates the pull-down of the potential at the first terminal of the second N-type transistor N102, which is equivalent to the pull-down effect of the potential at the first terminal of the second N-type transistor N102 when increasing the data to be sampled DQ to increase the conduction capability of the second N-type transistor N102. The effect of the adjustment unit 450 can be regarded as increasing the voltage of the data to be sampled DQ, and to a certain extent avoids the situation where the data to be sampled DQ is less than the first initial reference voltage Vr1, thereby offsetting the sampling influence of multiple data before the first 2 bits on the current data to be sampled DQ.

[0066] In some embodiments, the initial reference voltage generating module 103 is further configured to generate a reference voltage based on the third code c3 <a:0>A first regulated voltage is generated.

[0067] refer to Figure 7 In another example, the regulating unit 450 includes: a third P-type transistor P103, a first terminal for receiving a power supply signal, a control terminal for receiving a second regulating voltage, a voltage value of the second regulating voltage is adjusted based on a third code c3, and the voltage value of the second regulating voltage is negatively correlated with the value of the third code c3; a fourth P-type transistor P104, a first terminal connected to the second terminal of the third P-type transistor P103, a control terminal for receiving a third selection signal sel3, and a second terminal connected to the first terminal of the first N-type transistor N101; a fifth P-type transistor P105, a first terminal connected to the first terminal of the third P-type transistor P103, and a control terminal for receiving the second regulating voltage; a sixth P-type transistor P106, a first terminal connected to the second terminal of the fifth P-type transistor P105, a control terminal for receiving an inverted signal of the third selection signal sel3, and a second terminal connected to the first terminal of the second N-type transistor N102.

[0068] for Figure 7 The circuit shown, the third code c3 <a:0>For generating a second regulating voltage, and a third code c3 <a:0>The smaller the value is, the stronger the pull-up capability of the adjustment unit 450 on the first terminal of the first N-type transistor N101 or the second N-type transistor N102 is. Figure 7 The circuit principle shown is similar to Figure 6 The circuit principles shown are basically the same, and only the generation logic of the third code c3 needs to be replaced, which will not be described in detail in this embodiment.

[0069] It should be noted that the structures of the second receiving circuit 420, the third receiving circuit 430 and the fourth receiving circuit 440 are the same as those of the first receiving circuit 410, and can be referred to Figure 5 to Figure 7 The content is replaced and will not be described in detail in this embodiment.

[0070] For the initial reference voltage generating module 103, in some embodiments, the reference voltage Figure 8 , the initial reference voltage generating module 103 includes:

[0071] The voltage divider circuit 200 includes N voltage output terminals, and each voltage output terminal outputs a different voltage, where N is an integer greater than 1.

[0072] For the voltage divider circuit 200, refer to Fig. 9 In one example, the voltage divider circuit 200 includes: N-1 first resistors connected in series, the first end of the first first resistor is used to receive the first internal voltage V1, the second end of the last first resistor is used to receive the second internal voltage V2, and the second end of each first resistor is connected to the first end of the next first resistor; the voltage value of the first internal voltage V1 is greater than the voltage value of the second internal voltage V2, and the two ends of each first resistor serve as output ports to form N voltage output ends.

[0073] Specific reference Fig. 9 , N voltage output terminals are used to output voltage Q <0> ~Q <n>, since the resistors for voltage division are all first resistors, the voltage difference between two adjacent voltage output terminals is the same, that is, Q <x>=(V1-V2) / N*x, where x is any integer from 0 to N.

[0074] It should be noted that, in other embodiments, the resistance values ​​of different first resistors may be different. In this case, the voltage difference between two adjacent voltage output terminals is different, but it still meets the Q <n> ＞Q <n-1>>……>Q <1> >Q <0> .

[0075] In some embodiments, the first internal voltage V1 is implemented based on an internal power voltage VDD of the memory, and the second internal voltage V2 is implemented based on an internal ground voltage VSS of the memory.

[0076] Continue to refer Figure 8 , decoding circuit 201, for receiving the original code code <a:0>、First code c1 <a:0>and the second code c2 <a:0>The decoding circuit 201 is configured to be based on the original code code <a:0>+First code c1 <a:0>+Second code c2 <a:0>Generate a first processed signal based on the original code <a:0>+First code c1 <a:0>-Second code c2 <a:0>Generate a second processed signal based on the original code <a:0>-First code c1 <a:0>+Second code c2 <a:0>Generate a third processed signal based on the original code <a:0>-First code c1 <a:0>-Second code c2 <a:0>A fourth processed signal is generated.

[0077] In an example, assuming a=3, the original code code<3:0>="1000", the first code c1<3:0>="0010", the second code c2<3:0>="0001", then the first processed signal is "1011", the second processed signal is "1001", the third processed signal is "0111", and the fourth processed signal is "0101".

[0078] The first processing circuit 210 is connected to the voltage-dividing circuit 200 and the decoding circuit 201, and is configured to select the corresponding voltage output terminal in the voltage-dividing circuit 200 to output the first initial reference voltage Vr1 based on the first processing signal. The second processing circuit 220 is connected to the voltage-dividing circuit 200 and the decoding circuit 201, and is configured to select the corresponding voltage output terminal in the voltage-dividing circuit 200 to output the second initial reference voltage Vr2 based on the second processing signal. The third processing circuit 230 is connected to the voltage-dividing circuit 200 and the decoding circuit 201, and is configured to select the corresponding voltage output terminal in the voltage-dividing circuit 200 to output the third initial reference voltage Vr3 based on the third processing signal. The fourth processing circuit 240 is connected to the voltage-dividing circuit 200 and the decoding circuit 201, and is configured to select the corresponding voltage output terminal in the voltage-dividing circuit 200 to output the fourth initial reference voltage Vr4 based on the fourth processing signal.

[0079] For the first processing circuit 210, refer to Fig. 9 In some embodiments, the first processed signal includes N first sub-signals (X1 <0> ~X1 <n>), and the N first sub-signals include only one valid signal, the first processing circuit 210 includes: N first switch transistors, the control end of each first switch transistor corresponds to receiving the corresponding first sub-signal, the first terminal of each first switch transistor corresponds to connecting to the corresponding voltage output end of the N voltage output ends, and the second terminal is connected to the output end of the first processing circuit 210 to output the first initial reference voltage Vr1.

[0080] Specifically, based on the above example, when a=3, the first processed signal, the second processed signal, the third processed signal and the fourth processed signal are all 4-bit signals, and the 4-bit signal corresponds to 16 binary combinations. At this time, N=15, and the binary signal "0000" corresponds to the first sub-signal X1 <0> To output the corresponding Q <0> , the binary signal "0001" corresponds to the first sub-signal X1 <1> To output the corresponding Q <1> ...The binary signal "1110" corresponds to the first sub-signal X1 <14> To output the corresponding Q <14> , the binary signal "1111" corresponds to the first sub-signal X1 <15> To output the corresponding Q <15> In addition, there is only one valid signal among the N first sub-signals included in the first processed signal, that is, when X1 <0> When output "1" is valid, X1 <1> ~X1 <15> Output is "0" invalid; when X1 <d>When the output is "1" valid, X1 <0> ~X1 <d-1>and X1<d+1> ~X1 <15> An output of "0" is invalid.

[0081] It should be noted that the above example uses X1 <0> ~X1 <n>When the output is "1", it is valid. <0> ~X1 <n>The output is invalid when it is "0" for illustration only, and does not constitute a limitation of this embodiment. In other embodiments, it can also be set to X1 <0> ~X1 <n>When the output is "0", it is valid. <0> ~X1 <n>The output is invalid when it is "1".

[0082] More specifically, in this embodiment, the first processed signal "1011" corresponds to the first sub-signal X1 <11> To output the corresponding Q <11> As the first initial reference voltage Vr1.

[0083] Similarly, for the second processing circuit 220, in some embodiments, the second processed signal includes N second sub-signals (X2 <0> ~X2 <n>), and the N second sub-signals include only one valid signal, the second processing circuit 220 includes: N second switch transistors, the control end of each second switch transistor receives the corresponding second sub-signal, the first terminal of each second switch transistor is connected to the corresponding voltage output end among the N voltage output ends, and the second terminal is connected to the output end of the second processing circuit 220 to output the second initial reference voltage Vr2.

[0084] Accordingly, in this embodiment, the second processed signal "1001" corresponds to the second sub-signal X2 <9> To output the corresponding Q <9> As the second initial reference voltage Vr2.

[0085] Similarly, for the third processing circuit 230, in some embodiments, the third processed signal includes N third sub-signals (X3 <0> ~X3 <n>), and the N third sub-signals include only one valid signal, the third processing circuit 230 includes: N third switch transistors, the control end of each third switch transistor corresponds to receiving the corresponding third sub-signal, the first terminal of each third switch transistor corresponds to connecting to the corresponding voltage output end among the N voltage output ends, and the second terminal is connected to the output end of the third processing circuit 230 to output the third initial reference voltage Vr3.

[0086] Accordingly, in this embodiment, the third processed signal "0111" corresponds to the third sub-signal X3 <7> To output the corresponding Q <7> As the third initial reference voltage Vr3.

[0087] Similarly, for the fourth processing circuit 240, in some embodiments, the fourth processed signal includes N fourth sub-signals (X4 <0> ~X4 <n>), and the N fourth sub-signals include only one valid signal, the fourth processing circuit 240 includes: N fourth switch transistors, the control end of each fourth switch transistor corresponds to receiving the corresponding fourth sub-signal, the first terminal of each fourth switch transistor is correspondingly connected to the corresponding voltage output end among the N voltage output ends, and the second terminal is connected to the output end of the fourth processing circuit 240 to output a fourth initial reference voltage Vr4.

[0088] Accordingly, in this embodiment, the fourth processed signal "0101" corresponds to the fourth sub-signal X4 <5> To output the corresponding Q <5> As the fourth initial reference voltage Vr4.

[0089] It should be noted that the relationship between the second processing circuit 220, the third processing circuit 230, the fourth processing circuit 240, the decoding circuit 201 and the voltage divider circuit 200 is the same as that of the first processing circuit 210. Fig. 9 The example is directly replaced.

[0090] For the sampling circuit provided in this embodiment, based on the sampling influence of multiple data before the first 2 bits on the current data to be sampled DQ, the side where the data to be sampled is located or the side where the first initial reference voltage to the fourth initial reference voltage are located is compensated by the compensation current, so as to offset the sampling influence of multiple data before the first 2 bits on the current data to be sampled DQ; and based on the sampling influence of the previous first bit data and the previous second bit data on the current data to be sampled DQ, the output adaptation comparison result is selected as the sampling result data of the memory, so as to offset the sampling influence of the previous first bit data and the previous second bit data on the current data to be sampled DQ, thereby improving the accuracy of data sampling of the memory.

[0091] It should be noted that the features disclosed in the data sampling circuits provided in the above embodiments can be arbitrarily combined without conflict to obtain new data sampling circuit embodiments.

[0092] Another embodiment of the present disclosure provides a memory, comprising the data sampling circuit provided by the above embodiment, so as to improve the accuracy of data sampling of the memory.

[0093] Specifically, refer to Figure 3 When the influence of the multiple data before the current 2 bits on the current data DQ to be sampled is equivalent to the influence of the previous third bit data being "0" on the current data DQ to be sampled, the third selection signal sel3 is used to control the data sampling circuit 104 to load the compensation current on the side where the data DQ to be sampled is located during the comparison process; when the influence of the multiple data before the current 2 bits on the current data DQ to be sampled is equivalent to the influence of the previous third bit data being "1" on the current data DQ to be sampled, the third selection signal sel3 is used to control the data sampling circuit 104 to load the compensation current on the side where the first initial reference voltage Vr1, the second initial reference voltage Vr2, the third initial reference voltage Vr3 and the fourth initial reference voltage Vr4 are located during the comparison process to offset the sampling influence of the multiple data before the previous 2 bits on the current data DQ to be sampled.

[0094] When the previous second bit data is "0", the second selection signal sel2 is used to control the first selection circuit 101 to output the first reference data SJC1 with the second data SJ2, and to output the second reference data SJC2 with the fourth data SJ4, wherein the second data SJ2 is obtained by comparison based on the second initial reference voltage Vr2, and the fourth data SJ4 is obtained by comparison based on the fourth initial reference voltage Vr4, that is, the comparison result of reducing the influence of the second coding c2 on the reference voltage V is selected to offset the sampling influence of the previous second bit data on the current data to be sampled DQ; When the previous second bit data is "1", the second selection signal sel2 is used to control the first selection circuit 101 to output the first reference data SJC1 with the first data SJ1, and to output the second reference data SJC2 with the third data SJ3, wherein the first data SJ1 is obtained based on the first initial reference voltage Vr1, and the third data SJ3 is obtained based on the third initial reference voltage Vr3, that is, the comparison result with the increase of the influence of the second coding c2 on the reference voltage V is selected to offset the sampling influence of the previous second bit data on the current data to be sampled DQ.

[0095] When the previous first bit data is "0", the first selection signal sel1 is used to control the second selection circuit 102 to output the sampling result data SJ with the second reference data SJC2, wherein the second reference data SJC2 is obtained by comparison based on the third initial reference voltage Vr3 or the fourth initial reference voltage Vr4, that is, the comparison result of reducing the influence of the first coding c1 on the basis of the reference voltage V is selected to offset the sampling influence of the previous first bit data on the current data to be sampled DQ; when the previous first bit data is "1", the first selection signal sel1 is used to control the second selection circuit 102 to output the sampling result data SJ with the first reference data SJC1, wherein the first reference data SJC1 is obtained by comparison based on the first initial reference voltage Vr1 or the second initial reference voltage Vr2, that is, the comparison result of increasing the influence of the first coding c1 on the basis of the reference voltage V is selected to offset the sampling influence of the previous first bit data on the current data to be sampled DQ.

[0096] For the sampling circuit provided in this embodiment, based on the sampling influence of multiple data before the first 2 bits on the current data to be sampled, the side where the data to be sampled is located or the side where the first initial reference voltage to the fourth initial reference voltage are located is compensated by a compensation current, thereby offsetting the sampling influence of multiple data before the first 2 bits on the current data to be sampled; and based on the sampling influence of the previous first bit data and the previous second bit data on the current data to be sampled, an output adaptation comparison result is selected as the sampling result data of the memory, thereby offsetting the sampling influence of the previous first bit data and the previous second bit data on the current data to be sampled, thereby improving the accuracy of data sampling of the memory.

[0097] It should be noted that the memory may be a storage unit or device based on a semiconductor device or component. For example, the memory device may be a volatile memory, such as a dynamic random access memory DRAM, a synchronous dynamic random access memory SDRAM, a double data rate synchronous dynamic random access memory DDR SDRAM, a low power double data rate synchronous dynamic random access memory LPDDR SDRAM, a graphic double data rate synchronous dynamic random access memory GDDR SDRAM, a double data rate type dual synchronous dynamic random access memory DDR2 SDRAM, a double data rate type triple synchronous dynamic random access memory DDR3 SDRAM, a double data rate fourth generation synchronous dynamic random access memory DDR4 SDRAM, a thyristor random access memory TRAM, etc.; or may be a non-volatile memory, such as a phase change random access memory PRAM, a magnetic random access memory MRAM, a resistive random access memory RRAM, etc.

[0098] Those skilled in the art will appreciate that the above embodiments are specific embodiments for implementing the present disclosure, and that in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present disclosure.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / d> < / n> < / n> < / x> < / n>

Claims

1. A data sampling circuit, characterized in that: include: an initial reference voltage generating module, configured to receive an original code, a first code, and a second code, and generate a first initial reference voltage based on the original code + the first code + the second code, generate a second initial reference voltage based on the original code + the first code - the second code, generate a third initial reference voltage based on the original code - the first code + the second code, and generate a fourth initial reference voltage based on the original code - the first code - the second code; a data receiving module, for receiving the first initial reference voltage, the second initial reference voltage, the third initial reference voltage, the fourth initial reference voltage, a third selection signal and data to be sampled, and configured to compare the data to be sampled with the first initial reference voltage based on the third selection signal to generate first data, and compare the data to be sampled with the second initial reference voltage based on the third selection signal to generate second data, and compare the data to be sampled with the third initial reference voltage based on the third selection signal to generate third data, and compare the data to be sampled with the fourth initial reference voltage based on the third selection signal to generate fourth data; The third selection signal is configured to provide a compensation current to a side where the first initial reference voltage, the second initial reference voltage, the third initial reference voltage, and the fourth initial reference voltage are located, or to provide the compensation current to a side where the data to be sampled is located, in a process of comparing the first initial reference voltage, the second initial reference voltage, the third initial reference voltage, the fourth initial reference voltage, and the data to be sampled; a first selection circuit, for receiving the first data, the second data, the third data, the fourth data and a second selection signal, and configured to select, based on the second selection signal, to output first reference data based on the first data or the second data, and to select, based on the second selection signal, to output second reference data based on the third data or the fourth data; A second selection circuit, for receiving the first reference data, the second reference data and a first selection signal, and configured to select, based on the first selection signal, to output sampling result data based on the first reference data or the second reference data; Among them, the second selection signal is used to consider the influence of the previous second bit data on the current data to be sampled, the first selection signal is used to consider the influence of the previous first bit data on the current data to be sampled, and the third selection signal is used to consider the influence of at least the previous third bit data among all the data before the first 2 bits on the current data to be sampled.

2. The data sampling circuit according to claim 1, characterized in that: The data receiving module comprises: a first receiving circuit, for receiving the first initial reference voltage, the third selection signal and data to be sampled, and configured to compare the data to be sampled and the first initial reference voltage based on the third selection signal to generate first data, wherein the third selection signal is used to provide the compensation current to a side where the first initial reference voltage is located, or to provide the compensation current to a side where the data to be sampled is located, during the comparison between the first initial reference voltage and the data to be sampled; a second receiving circuit, for receiving the second initial reference voltage, the third selection signal and the data to be sampled, and configured to compare the data to be sampled and the second initial reference voltage based on the third selection signal to generate second data, wherein the third selection signal is used to provide the compensation current to the side where the second initial reference voltage is located, or to provide the compensation current to the side where the data to be sampled is located, during the comparison between the second initial reference voltage and the data to be sampled; a third receiving circuit, for receiving the third initial reference voltage, the third selection signal and the data to be sampled, and configured to compare the data to be sampled with the third initial reference voltage based on the third selection signal to generate third data, wherein the third selection signal is used to provide the compensation current to the side where the third initial reference voltage is located, or to provide the compensation current to the side where the data to be sampled is located, during the comparison between the third initial reference voltage and the data to be sampled; A fourth receiving circuit is used to receive the fourth initial reference voltage, the third selection signal and the data to be sampled, and is configured to compare the data to be sampled and the fourth initial reference voltage based on the third selection signal to generate fourth data, and the third selection signal is used to provide the compensation current to the side where the fourth initial reference voltage is located, or to provide the compensation current to the side where the data to be sampled is located during the comparison between the fourth initial reference voltage and the data to be sampled.

3. The data sampling circuit according to claim 2, characterized in that: The first receiving circuit comprises: A first N-type transistor, a control terminal for receiving the first initial reference voltage, a first terminal for outputting first data, a second terminal connected to a first terminal of a first current source, and a second terminal of the first current source being grounded; A second N-type transistor, a control end of which is used to receive the data to be sampled, a first terminal of which is connected to the control ends of the first P-type transistor and the second P-type transistor, and a second terminal of which is connected to the first end of the first current source; The first terminal of the first P-type transistor is used to receive a power signal, and the second terminal is connected to the first terminal of the first N-type transistor; A first terminal of the second P-type transistor is connected to the first terminal of the first P-type transistor, and a second terminal is connected to the first terminal of the second N-type transistor; The regulating unit is connected to the first terminal of the first N-type transistor and the first terminal of the second N-type transistor, and is configured to provide the compensation current to the first terminal of the first N-type transistor or the first terminal of the second N-type transistor based on the third selection signal.

4. The data sampling circuit according to claim 3, characterized in that: The regulating unit comprises: a third N-type transistor, wherein the first terminal is connected to the first terminal of the first N-type transistor, and the control terminal is used to receive a first regulating voltage, wherein the voltage value of the first regulating voltage is regulated based on a third code, and the voltage value of the first regulating voltage is positively correlated with the value of the third code; a fourth N-type transistor, having a first terminal connected to the second terminal of the third N-type transistor, a control terminal used to receive the third selection signal, a second terminal connected to the first terminal of the second current source, and a second terminal of the second current source being grounded; a fifth N-type transistor, a first terminal connected to the first terminal of the second N-type transistor, and a control terminal for receiving the first regulating voltage; A sixth N-type transistor, having a first terminal connected to the second terminal of the fifth N-type transistor, a control terminal used to receive an inverted signal of the third selection signal, and a second terminal connected to the first terminal of the second current source.

5. The data sampling circuit according to claim 3, characterized in that: The regulating unit comprises: a third P-type transistor, wherein the first terminal is used to receive a power signal, and the control terminal is used to receive a second regulated voltage, wherein the voltage value of the second regulated voltage is regulated based on a third code, and the voltage value of the second regulated voltage is negatively correlated with the value of the third code; a fourth P-type transistor, having a first terminal connected to the second terminal of the third P-type transistor, a control terminal used to receive an inverted signal of the third selection signal, and a second terminal connected to the first terminal of the first N-type transistor; a fifth P-type transistor, a first terminal of which is connected to the first terminal of the third P-type transistor, and a control terminal of which is used to receive the second regulating voltage; A sixth P-type transistor, having a first terminal connected to the second terminal of the fifth P-type transistor, a control terminal for receiving the third selection signal, and a second terminal connected to the first terminal of the second N-type transistor.

6. The data sampling circuit according to claim 4, characterized in that: The initial reference voltage generating module is further configured to generate the first regulating voltage based on the third code.

7. The data sampling circuit according to claim 1, characterized in that: The voltage value of the first initial reference voltage>the voltage value of the second initial reference voltage>the voltage value of the third initial reference voltage>the voltage value of the fourth initial reference voltage.

8. The data sampling circuit according to claim 1, characterized in that: The initial reference voltage generating module comprises: The voltage divider circuit comprises N voltage output terminals, each of which outputs a different voltage, and N is an integer greater than 1; A decoding circuit, for receiving the original code, the first code and the second code, configured to generate a first processing signal based on the original code + the first code + the second code, generate a second processing signal based on the original code + the first code - the second code, generate a third processing signal based on the original code - the first code + the second code, and generate a fourth processing signal based on the original code - the first code - the second code; a first processing circuit, connected to the voltage divider circuit and the decoding circuit, and configured to select the corresponding voltage output terminal in the voltage divider circuit to output the first initial reference voltage based on the first processing signal; a second processing circuit, connected to the voltage divider circuit and the decoding circuit, and configured to select the corresponding voltage output terminal in the voltage divider circuit to output the second initial reference voltage based on the second processing signal; a third processing circuit, connected to the voltage divider circuit and the decoding circuit, and configured to select the corresponding voltage output terminal in the voltage divider circuit to output the third initial reference voltage based on the third processing signal; The fourth processing circuit is connected to the voltage divider circuit and the decoding circuit, and is configured to select the corresponding voltage output terminal in the voltage divider circuit to output the fourth initial reference voltage based on the fourth processing signal.

9. The data sampling circuit according to claim 8, characterized in that: include: The voltage divider circuit comprises: N-1 first resistors connected in series, wherein a first end of a first first resistor is used to receive a first internal voltage, a second end of a last first resistor is used to receive a second internal voltage, and a second end of each first resistor is connected to a first end of a next first resistor; A voltage value of the first internal voltage is greater than a voltage value of the second internal voltage; Two ends of each of the first resistors serve as output ports to form the N voltage output ends; The first processed signal includes N first sub-signals, and the N first sub-signals include only one valid signal. The first processing circuit includes: N first switch transistors, each of which has a control terminal that receives the corresponding first sub-signal; The first terminal of each first switch transistor is connected to a corresponding one of the N voltage output terminals, and the second terminal is connected to the output terminal of the first processing circuit to output the first initial reference voltage.

10. A memory, characterized in that: The invention comprises the data sampling circuit as claimed in any one of claims 1 to 9.

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