General photoelectric control device for digital T / R assembly test system

Abstract

The invention provides a general photoelectric control device for a digital T / R assembly test system, which is provided for a digital T / R assembly automatic test system using photoelectric transmission equipment which is developed in a customized manner or does not have synchronous output photoelectric timing or does not have single-frame timing output. By opening a timing configuration interface, timing is flexibly configured by test software according to component models, and universal application of various types of components is met; through synchronous single-frame or continuous output of optical timing and electric timing, triggering synchronization of the assembly and the instrument and accurate acquisition of downlink data are realized, and the test efficiency of the digital T / R assembly test system is improved.

Description

Technical Field

[0001] The invention belongs to the field of automation technology, and in particular relates to a universal photoelectric control device for a digital T / R component testing system. Background Art

[0002] In the field of automated testing technology, automated testing systems for digital T / R components usually use test software to schedule optoelectronic control equipment and test instruments to implement performance testing of digital T / R components, including setting instrument startup, working mode of digital T / R components, and collecting instrument data. Some optoelectronic control devices are customized designs and can only be applied to certain types of components. They cannot take into account the application testing of other types of components, and their application is very limited. Some optoelectronic control devices do not have the ability to synchronously output optical timing and electrical timing, and cannot achieve timing synchronization between components and test instruments, resulting in low efficiency. Some optoelectronic control devices do not have the ability to output single-frame timing outputs, resulting in lengthy downlink data and low analysis efficiency. For batch production testing of digital T / R components, the automated testing system requires an efficient and universal optoelectronic control method that can cover multiple types of components, synchronize optoelectronic timing, and output single-frame timing. Summary of the invention

[0003] To this end, the present invention proposes a universal photoelectric control device for a digital T / R component test system, which is provided for a digital T / R component automated test system that uses customized development or photoelectric transmission equipment that does not have synchronous output photoelectric timing or single-frame timing output. The method enables the timing to be flexibly configured by the test software according to the component model through an open timing configuration interface, thereby meeting the universal application of multiple types of components; through optical timing, electrical timing synchronization of single frame or continuous output, the trigger synchronization of components and instruments and the accurate collection of downlink data are achieved, thereby improving the test efficiency of the digital T / R component test system.

[0004] The test software configures the timing according to the timing requirements of the component model under test, and sends the system configuration table and the control timing combination table to the FPGA of the optoelectronic control device through the UDP network packet. The FPGA parses the UDP network packet, generates the corresponding timing, and sends the optical data and optical timing to the digital T / R component through the optical fiber. Synchronously, the electrical timing is sent to the external trigger port of the test instrument through the level port, realizing the synchronous control and universal application of the digital T / R components and test instruments in the automatic test system.

[0005] The universal photoelectric control device consists of a network packet receiving module, a data parsing module, a control table cache module, a timing generation module, an optical fiber transmission module, and a level transmission module. The network packet receiving module is generated by an embedded operating system built inside the FPGA. The module receives external network packet data through a receiving thread, and stores the control timing combination table that meets the frame judgment conditions into the valid data pool; the data parsing module parses the valid data pool through a data processing thread, and sends it serially according to the number of test tasks parsed. The parsed timing parameters are sent to the timing generation module, and the control table is sent to the control table cache module; the control table cache module transfers the control table into the FIFO, and transmits the FIFO data to the optical fiber transmission module under a specific timing sequence; the timing generation module parses the timing parameters, and transmits the timing signal to the optical fiber transmission module and the level transmission module under a specific timing sequence; the optical fiber transmission module packs the FIFO data and the optical timing signal into the optical fiber according to a specific timing sequence and sends it to the digital T / R component; the level transmission module sends the electrical timing signal to the instrument external trigger interface through the level port according to a specific timing sequence,

[0006] Furthermore, the general configuration includes timing resolution, timing cycle, independent switching of each timing channel, independent polarity of each timing channel, optical timing front and rear edge configuration, and electrical timing front and rear edge configuration functions.

[0007] Furthermore, the general configuration includes a timed single-frame / continuous switching function. The timed single-frame mode generates a timing sequence of a frame period after receiving a network packet, and the timing of each channel is in a closed state in subsequent periods; the timed continuous mode generates a continuous timing sequence after receiving a network packet, and each frame timing sequence is repeated.

[0008] Furthermore, the general configuration includes a single-task or multi-task configuration function, and the optoelectronic control device sends multiple frames of control signals in serial order at a frame cycle frequency at one time according to the test task sequence.

[0009] Furthermore, the components and instruments are synchronously controlled through photoelectric timing, where the instruments are controlled by external triggering. The synchronization control cycle can be shortened to milliseconds, which can greatly reduce the interaction time between the test software and the instrument.

[0010] Furthermore, the specific timing sequence period is consistent with the timing resolution and timing period of the timing configuration, and maintains a certain relative position with the output timing for internal scheduling and operation of the system.

[0011] Furthermore, all modules are implemented on a digital board based on FPGA and corresponding peripheral circuits, and the peripheral circuits need to include but not be limited to Ethernet modules, clock modules, optical transmission modules, level IO ports, and power modules.

[0012] The innovation of the present invention is that: based on FPGA implementation, through the open universal configuration interface, the timing is flexibly configured by the test software according to the component model, so as to realize the universal application of multiple types of components; through the synchronous output of optical timing and electrical timing, the synchronous control of components and instruments is realized; the characteristics of the universal configuration interface are: the control timing combination table is composed of a variable-length control table of the tested component and a fixed-length timing configuration table, which can adapt to the control table format of components of different models; the fixed-length timing configuration table can configure the timing resolution, timing cycle, independent switches of each timing, independent polarity of each timing, optical timing front and back edge parameters, and electrical timing front and back edge parameters, which can adapt to the timing generation requirements of components of different models. The characteristics of the synchronous output of optical timing and electrical timing are: the optical timing and electrical timing signals are generated by the counter of the same frequency, and share the same timing resolution, timing cycle, and parameter update conditions. Through the timing single-frame output mode, accurate collection of downlink data is realized; through the multi-task test mode, fast sending of multi-frame test tasks is realized. The characteristics of the timing single-frame output mode are: the timing configuration table can configure the timing single-frame mode, and in the single-frame mode, only one frame of timing is effective, and the remaining frames are in the timing invalid state. The characteristics of the multi-task test mode are: the timing configuration table can configure the number of test tasks, the multi-task test mode needs to be run in single-frame mode, and the timing control frame number of the component under test corresponds to the downlink data frame number one by one.

[0013] The beneficial effects of the present invention are

[0014] 1. By opening the general configuration interface, the test software can be flexibly configured according to the component model to meet the universal application of multiple types of components, making the photoelectric control equipment instrumented. In batch production testing, the photoelectric control equipment can be flexibly allocated between component test systems of different models, which can improve the utilization rate of the photoelectric control equipment and reduce the development cost, maintenance cost and operation risk of the automatic test system.

[0015] 2. Through optical timing and electrical timing synchronous output, the instrument is controlled by external triggering, which can reduce the interaction time between the test software and the instrument. The test cycle of a single test task can be shortened to milliseconds, which can improve the test efficiency of the digital T / R component test system.

[0016] 3. Through the timing single-frame mode, the amount of downlink data of the digital T / R component can be accurately controlled, the analysis time of redundant data can be reduced, and the test efficiency of the digital T / R component test system can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is a system block diagram of a general photoelectric control method.

[0018] Figure 2 This is a schematic diagram of the synchronous single-frame timing sequence.

[0019] Figure 3 Schematic diagram of synchronous continuous timing sequence.

[0020] Figure 4 This is a schematic diagram of the synchronous multi-tasking sequence. DETAILED DESCRIPTION

[0021] The technical solutions in the embodiments of the present invention are described clearly and completely below. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0022] A universal photoelectric control device for a digital T / R component test system of the present invention realizes the functions of custom configuration timing, photoelectric timing synchronous output, and timing single-frame output. It can meet the universal application of various types of components, synchronously control components and test instruments, and accurately collect downlink data. It has the advantages of a wide range of applications and high test efficiency.

[0023] like Figure 1 As shown, the universal photoelectric control device consists of a network packet receiving module, a data parsing module, a control table cache module, a timing generation module, an optical fiber transmission module, and a level transmission module, and all modules are implemented in FPGA.

[0024] The test software completes the configuration of the system configuration table and the control timing combination table according to the timing requirements of the component model and the control table requirements. First, configure the size of the component control table in the system configuration table, then fill in the component control table and timing table contents in the control timing combination table to complete the timing setting, and finally send the system configuration table and control timing combination table to the general photoelectric control module through UDP network packets in turn.

[0025] The network packet receiving module uses threads to receive external network packet data, determines the size of the component control table through the system configuration table, and then indexes the timing parameter content of the timing table according to the size of the component control table. Finally, the control table and timing table that meet the conditions are disassembled and stored in the valid data pool.

[0026] The data analysis module uses threads to analyze the effective data pool and analyze the timing resolution, timing cycle, timing switch, timing polarity, optical timing front and back edge configuration, electrical timing front and back edge configuration, timing single frame switch (single frame timing such as Figure 2 As shown, continuous timing is Figure 3 ), task quantity and other parameters, and send them serially according to the test task sequence, such as Figure 4 As shown, the timing parameters are sent to the timing generation module, and the control table is sent to the control table cache module until the number in the task sequence is empty.

[0027] The control table buffer module transfers the control table into the FIFO, and transmits the FIFO data to the optical fiber transmission module in a specific timing sequence, and the specific timing sequence position is a period of time before the output timing.

[0028] The timing generation module analyzes the timing parameters and transmits the timing signal to the optical fiber transmission module and the level transmission module in a specific timing sequence, and the specific timing sequence position is a period of time before the output timing.

[0029] The optical fiber transmission module packages the FIFO data and the optical timing signal into the optical fiber and sends the digital T / R component according to a specific timing sequence, and the specific timing sequence position is a period of time before the output timing.

[0030] The level transmission module sends the electrical timing signal to the instrument external trigger interface through the level port according to a specific timing sequence. This completes the entire process from network packet input into the photoelectric control module to the generation of control signals to the tested components and test instruments.

[0031] The present invention is not limited to the above specific implementations, and the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made to the above implementations based on the technical essence of the present invention shall be included in the protection scope of the present invention.

Claims

1. A universal photoelectric control device for a digital T / R component test system, characterized in that: It includes a network packet receiving module, a data parsing module, a control table cache module, a timing generation module, an optical fiber transmission module, and a level transmission module; The network packet receiving module receives external network packet data through a receiving thread, and stores the control timing combination table that meets the frame determination condition into a valid data pool; The data parsing module parses the valid data pool through the data processing thread, sends the parsed test tasks in serial, sends the parsed timing parameters to the timing generation module, and sends the control table to the control table cache module; The control table cache module transfers the control table into the FIFO and transmits the FIFO data to the optical fiber transmission module under a specific timing sequence; The timing generation module analyzes the timing parameters and transmits the timing signals to the optical fiber transmission module and the level transmission module under a specific timing sequence; The optical fiber transmission module packages the FIFO data and the optical timing signal into the optical fiber according to a specific timing sequence and sends the digital T / R component; The level transmission module sends the electrical timing signal to the instrument external trigger interface through the level port according to a specific timing sequence.

2. A universal photoelectric control device for a digital T / R component test system according to claim 1, characterized in that: The universal photoelectric control device realizes functions including timing resolution, timing cycle, independent switching of each timing channel, independent polarity of each timing channel, configuration of optical timing leading and trailing edges, and configuration of electrical timing leading and trailing edges.

3. A universal photoelectric control device for a digital T / R component test system according to claim 2, characterized in that: The universal photoelectric control device has a timing single-needle mode and a timing continuous mode. The timing single-frame mode generates a timing sequence of a frame period after receiving a network packet, and the timing of each channel in the subsequent period is in a closed state; the timing continuous mode generates a continuous timing sequence after receiving a network packet, and each frame timing sequence is repeated.

4. A universal photoelectric control device for a digital T / R component test system according to claim 3, characterized in that: The universal photoelectric control device has single-task and multi-task configuration functions. The photoelectric control device sends multiple frame control signals in serial order at a frame cycle frequency at one time according to the test task sequence.

5. A universal photoelectric control device for a digital T / R component test system according to claim 4, characterized in that: The timing sequence period is consistent with the timing resolution and timing period of the timing configuration, and maintains a certain relative position with the output timing, which is used for internal scheduling and operation of the system.

6. A universal photoelectric control device for a digital T / R component test system according to any one of claims 1 to 5, characterized in that: All modules are implemented on a digital board based on FPGA and corresponding peripheral circuits, including but not limited to Ethernet modules, clock modules, optical transmission modules, level IO ports, and power modules.

Images