A general-purpose optoelectronic control device for a digital T / R component testing system

Abstract

This invention proposes a universal optoelectronic control device for digital T / R component testing systems, providing an automated testing system for digital T / R components that uses custom-developed devices or lacks synchronous output optoelectronic timing or single-frame timing output. By providing an open timing configuration interface, the timing can be flexibly configured by the testing software according to the component model, meeting the needs of universal applications for multiple component types. Through synchronous single-frame or continuous output of optical and electrical timing, the system achieves trigger synchronization of components and instruments and accurate acquisition of downlink data, improving the testing efficiency of digital T / R component testing systems.

Description

Technical Field

[0001] This invention belongs to the field of automation technology, specifically relating to a general photoelectric control device for a digital T / R component testing system. Background Technology

[0002] In the field of automated testing technology, automated testing systems for digital T / R components typically use test software to schedule optoelectronic control devices and test instruments to perform performance testing on digital T / R components. This includes setting instrument startup, configuring the operating mode of the digital T / R component, and acquiring instrument data. Some optoelectronic control devices are custom-designed and can only be used for specific component models, limiting their application scope. Others lack the ability to synchronously output optical and electrical timing, failing to achieve timing synchronization between the component and the test instrument, resulting in low efficiency. Still others lack single-frame output capability, leading to lengthy downlink data and inefficient analysis. For mass production testing of digital T / R components, automated testing systems require a highly efficient and universal optoelectronic control method that can cover multiple component types, achieve synchronous optoelectronic timing, and output single-frame timing data. Summary of the Invention

[0003] To address this, this invention proposes a universal optoelectronic control device for digital T / R component testing systems. This device is designed for automated testing systems of digital T / R components that utilize custom-developed optoelectronic transmission equipment or lack synchronous output optoelectronic timing or single-frame timing output. The method utilizes an open timing configuration interface, allowing timing to be flexibly configured by the testing software based on the component model, thus meeting the general application requirements for multiple component types. Through synchronous single-frame or continuous output of optical and electrical timing, it achieves synchronized triggering of components and instruments, as well as accurate acquisition of downlink data, thereby improving the testing efficiency of digital T / R component testing systems.

[0004] The test software configures the timing according to the timing requirements of the component under test model. It sends the system configuration table and control timing combination table to the FPGA of the optoelectronic control equipment via UDP network packets. The FPGA parses the UDP network packets, generates the corresponding timing, and sends the optical data and optical timing to the digital T / R component through optical fiber. Simultaneously, it sends the electrical timing to the external trigger port of the test instrument through the level port, realizing the synchronous control and general application of the digital T / R component and the test instrument in the automatic test system.

[0005] The general-purpose optoelectronic control device consists of a network packet receiving module, a data parsing module, a control table buffer module, a timing generation module, an optical fiber transmission module, and a level transmission module. The network packet receiving module is generated by an embedded operating system built within the FPGA. This module receives external network packet data through a receiving thread and stores the control timing combination table that meets the frame determination conditions into the valid data pool. The data parsing module parses the valid data pool through a data processing thread, serially sending the parsed test tasks according to the number of tasks. The parsed timing parameters are sent to the timing generation module, and the control table is sent to the control table buffer module. The control table buffer module transmits the control table into a FIFO and transmits the FIFO data to the optical fiber transmission module under a specific timing sequence. The timing generation module parses the timing parameters and transmits the timing signals to the optical fiber transmission module and the level transmission module under a specific timing sequence. The optical fiber transmission module packages the FIFO data and optical timing signals into an optical fiber according to a specific timing sequence and transmits them to the digital T / R component. The level transmission module sends the electrical timing signals to the external trigger interface of the instrument through a level port according to a specific timing sequence.

[0006] Furthermore, the general configuration includes timing resolution, timing period, independent switching for each timing channel, independent polarity for each timing channel, optical timing leading and trailing edge configuration, and electrical timing leading and trailing edge configuration functions.

[0007] Furthermore, the general configuration includes a single-frame / continuous timing switching function. In single-frame timing mode, a timing sequence of one frame period is generated after receiving a network packet, and the timing of each channel is turned off in subsequent periods. In continuous timing mode, a continuous timing sequence is generated after receiving a network packet, and the timing sequence of each frame repeats continuously.

[0008] Furthermore, the general configuration includes single-task or multi-task configuration functions, in which the photoelectric control device sequentially sends multiple frames of control signals in sequence at a frame period frequency according to the test task sequence.

[0009] Furthermore, the components and instruments are controlled synchronously via photoelectric timing, with the instruments controlled by external triggering. The synchronization control cycle can be shortened to the millisecond level, which can greatly reduce the interaction time between the test software and the instruments.

[0010] Furthermore, the specific timing sequence period is consistent with the timing resolution and timing period configured in the timing configuration, and maintains a certain relative position with the output timing, for internal system scheduling and operation.

[0011] Furthermore, all modules are implemented on a digital board based on FPGA and corresponding peripheral circuits. The peripheral circuits must include, but are not limited to, Ethernet modules, clock modules, optical transmission modules, level I / O ports, and power supply modules.

[0012] The innovations of this invention are as follows: Based on FPGA implementation, it utilizes an open universal configuration interface, allowing timing to be flexibly configured by the test software according to the component model, achieving universal application for multiple component types; synchronous output of optical and electrical timing enables synchronized control of components and instruments; the universal configuration interface features include: a control timing combination table composed of a variable-length control table for the component under test and a fixed-length timing configuration table, adaptable to control table formats of different component models; the fixed-length timing configuration table can configure timing resolution, timing period, independent switches for each timing channel, independent polarity for each timing channel, optical timing leading and trailing edge parameters, and electrical timing leading and trailing edge parameters, adapting to the timing generation requirements of different component models. The synchronous output of optical and electrical timing features include: optical and electrical timing signals generated by a counter of the same frequency, sharing the same timing resolution, timing period, and parameter update conditions. Accurate acquisition of downlink data is achieved through a single-frame timing output mode; rapid transmission of multi-frame test tasks is achieved through a multi-task test mode. The single-frame timing output mode features: the timing configuration table can be configured for single-frame timing mode, where only one frame of timing is active, and the remaining frames are in an inactive state. The features of the multi-task test mode are: the timing configuration table can configure the number of test tasks, the multi-task test mode must be run in single-frame mode, and the timing control frames of the component under test correspond one-to-one with the downlink data frames.

[0013] The beneficial effects of this invention are as follows:

[0014] 1. By opening a universal configuration interface, the test software can be flexibly configured according to the component model at regular intervals, which can meet the universal application of multiple types of components, and instrument the optoelectronic control equipment. In batch production testing, optoelectronic control equipment can be flexibly allocated between test systems of different component models, which can improve the utilization rate of optoelectronic control equipment and reduce development costs, maintenance costs and operational risks of automatic test systems.

[0015] 2. By using optical timing and electrical timing to output synchronously, with the instrument controlled by an external trigger, the interaction time between the test software and the instrument can be reduced, and the test cycle of a single test task can be shortened to the millisecond level, which can improve the test efficiency of the digital T / R component test system.

[0016] 3. By using the timed single-frame mode, the amount of downlink data from the digital T / R component can be precisely controlled, reducing the analysis time of redundant data and improving the testing efficiency of the digital T / R component testing system. Attached Figure Description

[0017] Figure 1 This is a system block diagram of a general photoelectric control method.

[0018] Figure 2 This is a schematic diagram of a synchronous single-frame timing sequence.

[0019] Figure 3 This is a schematic diagram of a synchronous continuous timing sequence.

[0020] Figure 4 A schematic diagram for synchronizing multiple tasks and sequencing them. Detailed Implementation

[0021] The technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] The present invention provides a general photoelectric control device for a digital T / R component testing system, which realizes the functions of custom configuration timing, photoelectric timing synchronous output, and timing single-frame output. It can meet the general application of multiple types of components, synchronous control of components and test instruments, and accurate acquisition of downlink data. It has the advantages of wide application range and high testing efficiency.

[0023] like Figure 1 As shown, the general-purpose optoelectronic control device consists of a network packet receiving module, a data parsing module, a control table buffer module, a timing generation module, an optical fiber transmission module, and a level transmission module. All modules are implemented within an FPGA.

[0024] The testing software configures two tables—the system configuration table and the control timing combination table—based on the timing requirements of the component model and the control table requirements. First, it configures the size of the component control table in the system configuration table. Then, it fills in the contents of the component control table and the timing table in the control timing combination table to complete the timing settings. Finally, it sends both the system configuration table and the control timing combination table sequentially to the general-purpose optoelectronic control module via UDP network packets.

[0025] The network packet receiving module uses threads to receive external network packet data. It determines the size of the component control table through the system configuration table, then indexes the timing parameters of the timing table according to the size of the component control table, and finally disassembles the control table and timing table that meet the conditions and stores them into the valid data pool.

[0026] The data parsing module uses threads to parse the valid data pool, extracting timing resolution, timing period, timing switch, timing polarity, optical timing leading and trailing edge configuration, electrical timing leading and trailing edge configuration, and single-frame timing switch (single-frame timing such as...). Figure 2 As shown, continuous timing is as follows Figure 3 (As shown), parameters such as the number of tasks, and send them serially according to the test task sequence, such as... Figure 4 As shown, the timing parameters are sent to the timing generation module, and the control table is sent to the control table cache module until the number of tasks in the sequence is empty.

[0027] The control table buffer module transmits the control table into the FIFO and transmits the FIFO data to the fiber optic transmission module under a specific timing sequence, which is located some time before the output timing.

[0028] The timing generation module parses the timing parameters and transmits the timing signal to the fiber optic transmission module and the level transmission module under a specific timing sequence, which is located some time before the output timing.

[0029] The fiber optic transmission module packages FIFO data and optical timing signals into the optical fiber according to a specific timing sequence and sends them to the digital T / R component. This specific timing sequence is located some time before the output timing.

[0030] The level transmission module sends the electrical timing signal to the external trigger interface of the instrument through the level port according to a specific timing sequence. This completes the entire process from the network packet input into the photoelectric control module to the generation of control signals to the component under test and the test instrument.

[0031] This invention is not limited to the specific embodiments described above, and various modifications and variations are possible. Any modifications, equivalent substitutions, or improvements made to the above embodiments based on the technical essence of this invention should be included within the scope of protection of this invention.

Claims

1. A universal photoelectric control device for a digital T / R component testing system, characterized in that: It includes a network packet receiving module, a data parsing module, a control table caching module, a timing generation module, a fiber optic transmission module, and a level transmission module; The network packet receiving module receives external network packet data through a receiving thread and stores the control timing combination table that meets the frame determination conditions into the valid data pool. The data parsing module parses the valid data pool through the data processing thread, sends the parsed test task sequence serially, sends the parsed timing parameters to the timing generation module, and sends the control table to the control table cache module. The control table cache module transmits the control table into the FIFO and transmits the FIFO data to the fiber optic transmission module under a specific timing sequence. The timing generation module parses the timing parameters and transmits the optical timing signal to the optical fiber transmission module and the electrical timing signal to the level transmission module under a specific timing sequence. The optical fiber transmission module packages FIFO data and optical timing signals into an optical fiber according to a specific timing sequence and transmits them to the digital T / R component. The level transmission module sends the electrical timing signal to the external trigger interface of the instrument through the level port according to a specific timing sequence.

2. The universal photoelectric control device for a digital T / R component testing system according to claim 1, characterized in that: The general-purpose optoelectronic control device realizes functions including timing resolution, timing period, independent switching of each timing channel, independent polarity of each timing channel, optical timing leading and trailing edge configuration, and electrical timing leading and trailing edge configuration.

3. The universal photoelectric control device for a digital T / R component testing system according to claim 2, characterized in that: The general-purpose optoelectronic control device has a single-frame timing mode and a continuous timing mode. In the single-frame timing mode, a timing sequence of one frame period is generated after receiving a network packet, and the timing of each channel in subsequent periods is in the off state. In the continuous timing mode, a continuous timing sequence is generated after receiving a network packet, and each frame timing sequence is repeated continuously.

4. The universal photoelectric control device for a digital T / R component testing system according to claim 3, characterized in that: The general-purpose optoelectronic control device has single-task and multi-task configuration functions. The optoelectronic control device sends multiple frames of control signals sequentially at a frame period frequency according to the test task sequence.

5. A universal photoelectric control device for a digital T / R component testing system according to any one of claims 1-4, characterized in that: All modules are implemented on a digital board based on an FPGA and corresponding peripheral circuits.

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