RapidIO dual-port link configuration synchronous data transmitting and receiving method, device, medium and system

Abstract

The invention discloses a RapidIO dual-port link configuration synchronous data receiving and transmitting method, device, medium and system, and belongs to the field of spaceflight measurement and control, and the method comprises the steps: firstly, a main management node, a standby management node, a communication node 1 to a communication node N and an FPGA node are accessed to a RapidIO switching network through a RapidIO bus; and secondly, the FPGA node is composed of two RapidIO ports, namely, an RIO1 port and an RIO2 port. When any RapidIO port is reconfigured, the configuration information is automatically synchronized to the other RapidIO port, so that the system does not need to reconfigure the RapidIO port of the FPGA node when the system is in a fault state. According to the scheme, the hardware cost is low, the fault reconstruction time is short, the coupling between the driver and the user logic is reduced, and the overall working efficiency of the system can be improved.

Description

Technical Field

[0001] The present invention relates to the field of aerospace measurement and control, and more specifically, to a RapidIO dual-port link configuration synchronous data transceiver method, device, medium and system. Background Art

[0002] In recent years, FPGA chips are increasingly used in aerospace measurement and control systems due to their programmability, high flexibility, short development cycle, and strong parallel processing capabilities. The data collected at the previous stage is preprocessed in the FPGA chip, and the preprocessed data is sent to the DSP or PPC processor for algorithm processing and data analysis.

[0003] In the above FPGA+DSP+PPC heterogeneous platform, the traditional parallel bus can no longer meet the requirements. The high-speed serial RapidIO bus based on the packet switching architecture provides a good solution for the high-speed interconnection between multiple heterogeneous chips in the aerospace measurement and control system with its high bandwidth, low latency, and high reliability.

[0004] Generally, the working environment of aerospace measurement and control systems is complex, especially when working for a long time in extremely harsh environments such as noisy electromagnetic environments, high and low temperatures, etc. Any single point failure in the system, such as processing components and switching chips, may cause the entire system to stop working.

[0005] Therefore, it is difficult to ensure the safety of the system by simply relying on the design of a high-reliability interconnection bus. In the existing relevant materials, the common practice is to use the active-standby redundant backup method for management nodes and the backup method for ordinary nodes using multiple hardware boards.

[0006] For a simple small system, the number of functional hardware boards is limited. By adding hardware boards, when a single node fails, the function can be migrated to other hardware boards. However, for a complex large system, it is difficult to cover all nodes by adding hardware boards. At the same time, a large number of backup boards will also increase the cost of the system, and will have an adverse effect on the overall weight, volume, heat dissipation and other aspects of the system.

[0007] In the above backup method, the software needs to store the user program version in the Flash of the backup board. When a failure occurs, the function program is loaded from the Flash of the backup board, and then the management node deletes the links of the relevant nodes again and re-establishes the communication link to work normally. In the above method, since the link needs to be deleted and re-established, this will increase the system failure reconstruction time and reduce the overall system work efficiency. Summary of the invention

[0008] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a RapidIO dual-port link configuration synchronous data receiving and sending method, device, medium and system, which solves the problems of high hardware cost, long fault reconstruction time and reduced overall system working efficiency caused by the use of hardware board backup in the existing aerospace measurement and control system without substantially increasing the hardware cost.

[0009] The object of the present invention is achieved through the following solutions:

[0010] A RapidIO dual-port link configuration synchronous data transceiver system is based on a main management node, a standby management node, communication nodes 1 to communication nodes N, a RapidIO switching network and an FPGA node. The main management node, the standby management node, the communication nodes 1 to communication nodes N and the FPGA node are all connected to the RapidIO switching network through a RapidIO bus; the FPGA node includes two RapidIO ports, RIO1 and RIO2; the main management node and the standby management node both have access management configuration authority to the two RapidIO ports of the FPGA node connected to the switching network; when working normally, the control authority of RapidIO is exclusively owned by the main management node, and when the main management node fails, the control authority is obtained from the management node.

[0011] Further, the primary management node is a PPC type primary management node, and the backup management node is a PPC type backup management node.

[0012] Furthermore, the chip in the RapidIO switching network adopts a CPS1848 device or a corresponding domestically produced switching device.

[0013] A RapidIO dual-port link configuration synchronous data receiving and sending method, based on the RapidIO dual-port link configuration synchronous data receiving and sending system as described above, further includes executing the following steps:

[0014] Step S1, after power-on, the main management node initializes and configures the link information of the RIO1 port or the RIO2 port of the FPGA node; during the working process, according to the external information input, the link information of the RIO1 port or the RIO2 port of the FPGA node is dynamically configured; when any RapidIO port of the RIO1 port or the RIO2 port receives the link configuration information, the link configuration information is synchronously updated to the other RapidIO port;

[0015] Step S2, the data transmission and reception of the RIO1 port and the RIO2 port of the FPGA node are both in the data FIFO and length FIFO mode; when receiving data, the RIO1 port and the RIO2 port separate the input RIO_IP_in data according to the data RIO_sync_recv_info output by the configuration information synchronization module, and after being processed by the data receiving and merging module, the data is stored in the receiving data FIFO, and the data packet length is stored in the receiving length FIFO; when sending data, the data sending distribution module writes the data to be sent into the RIO1 sending data FIFO corresponding to the RIO1 port or the RIO2 sending data FIFO corresponding to the RIO2 port according to the RIO_sync_send_sel information output by the configuration information synchronization module, writes the length of the data packet to be sent into the RIO1 sending length FIFO corresponding to the RIO1 port or the RIO2 sending length FIFO corresponding to the RIO2 port, and sends it to the RapidIO switching network through the RapidIO IP core corresponding to the RIO1 port or the RIO2 port.

[0016] A RapidIO dual-port link configuration synchronous data receiving and sending method, based on the RapidIO dual-port link configuration synchronous data receiving and sending system as described above, comprises executing the following steps:

[0017] First, the FPGA node RIO1 port receives the configuration information sent from the main management node and the backup management node, writes the RIO1 port configuration flag RIO1_cfg_flag into the configuration flag FIFO; writes the configuration information RIO1_cfg_info into the configuration information synchronization module;

[0018] Then, the FPGA node RIO2 port receives the configuration information sent from the main management node and the backup management node, writes the RIO2 port configuration flag RIO2_cfg_flag into the configuration flag FIFO; writes the configuration information RIO2_cfg_info into the configuration information synchronization module;

[0019] Next, when the configuration flag FIFO is not empty, the configuration information synchronization module reads the configuration flag FIFO value RIO_cfg_flag, and synchronizes RIO1_cfg_info and RIO2_cfg_info according to the value of RIO_cfg_flag;

[0020] Finally, the configuration information synchronization module outputs the receiving configuration information RIO_sync_recv_info, the sending configuration information RIO_sync_send_info and the data sending distribution selection signal RIO_sync_send_sel; sends the receiving configuration information RIO_sync_recv_info to the RIO1 receiving processing module and the RIO2 receiving processing module; sends the sending configuration information RIO_sync_send_info to the RIO1 sending processing module and the RIO2 sending processing module; sends the data sending distribution selection signal RIO_sync_send_sel to the data sending distribution module.

[0021] Further, the value of the RIO1 port configuration flag RIO1_cfg_flag is 2'b01, and the value of the RIO2 port configuration flag RIO2_cfg_flag is 2'b10;

[0022] When the configuration flag FIFO is not empty, the configuration information synchronization module reads the configuration flag FIFO value RIO_cfg_flag, and synchronizes RIO1_cfg_info and RIO2_cfg_info according to the value of RIO_cfg_flag, specifically including the sub-steps:

[0023] When the value of RIO_cfg_flag is 2'b01, the output transmission configuration information RIO_sync_send_info and reception configuration information RIO_sync_recv_info use the corresponding values ​​in RIO1_cfg_info, and set the data transmission distribution selection signal RIO_sync_send_sel to 2'b01;

[0024] When the value of RIO_cfg_flag is 2'b10, the output transmission configuration information RIO_sync_send_info and reception configuration information RIO_sync_recv_info use the corresponding values ​​in RIO2_cfg_info, and set the data transmission distribution selection signal RIO_sync_send_sel to 2'b10.

[0025] A RapidIO dual-port link configuration synchronous data receiving and sending method, based on the RapidIO dual-port link configuration synchronous data receiving and sending system as described above, comprises executing the following steps:

[0026] First, the FPGA node RIO1 port receives data from communication node 1 to communication node N, identifies the received RIO1_IP_in according to the receiving configuration information RIO_sync_recv_info output by the configuration information synchronization module, writes the correctly identified received data RIO1_recv_data_in into the RIO1 receive data FIFO, and writes the received data packet length RIO1_recv_len_in into the RIO1 receive length FIFO;

[0027] Then, the FPGA node RIO2 port receives data from communication node 1 to communication node N, identifies the received RIO2_IP_in according to the receiving configuration information RIO_sync_recv_info output by the configuration information synchronization module, writes the correctly identified received data RIO2_recv_data_in into the RIO2 receiving data FIFO, and writes the received data packet length RIO2_recv_len_in into the RIO2 receiving length FIFO;

[0028] Then, the receiving data merging module monitors whether the RIO1 receiving length FIFO and the RIO2 receiving length FIFO are not empty; when the RIO1 receiving length FIFO is not empty, the RIO1 receiving length FIFO value is read, and according to the receiving length FIFO value read by RIO1, data of corresponding length is read from the RIO1 receiving data FIFO, and written into the receiving data FIFO, and after the reading of the RIO1 receiving data FIFO is completed, the receiving length FIFO value read by RIO1 is written into the receiving length FIFO; when the RIO2 receiving length FIFO is not empty, the RIO2 receiving length FIFO value is read, and according to the receiving length FIFO value read by RIO2, data of corresponding length is read from the RIO2 receiving data FIFO, and written into the receiving data FIFO, and after the reading of the RIO2 receiving data FIFO is completed, the receiving length FIFO value read by RIO2 is written into the receiving length FIFO;

[0029] Finally, the data User_recv_data output by the receive data FIFO is the user receive data, and the data User_recv_len output by the receive length FIFO is the length of the user receive data packet; when the receive length FIFO is not empty, data of corresponding length is read from the receive data FIFO according to the value of User_recv_len.

[0030] A RapidIO dual-port link configuration synchronous data receiving and sending method, based on the RapidIO dual-port link configuration synchronous data receiving and sending system as described above, comprises executing the following steps:

[0031] First, the user writes the data to be sent User_send_data into the send data FIFO, and writes the length of the send data packet User_send_len into the send length FIFO;

[0032] Then, the data transmission distribution module monitors whether the transmission length FIFO is empty. When the transmission length FIFO is not empty, the data in the transmission data FIFO is read according to the value of the data transmission distribution selection signal RIO_sync_send_sel output by the configuration information synchronization module, and written into the RIO1 transmission data FIFO or the RIO2 transmission data FIFO; when the value of RIO_sync_send_sel is 2'b01, the value operation of reading the transmission length FIFO is executed, and then the corresponding length is read from the transmission data FIFO according to the value of the read transmission length FIFO. Data is written into the RIO1 transmit data FIFO, and after the transmit data FIFO is read, the currently read transmit length FIFO value is written into the RIO1 transmit length FIFO; when the RIO_sync_send_sel value is 2'b10, the value operation of reading the transmit length FIFO is executed, and according to the value of the read transmit length FIFO, data of corresponding length is read from the transmit data FIFO and written into the RIO2 transmit data FIFO, and after the transmit data FIFO is read, the currently read transmit length FIFO value is written into the RIO2 transmit length FIFO;

[0033] Finally, the RIO1 send processing module monitors whether the RIO1 send length FIFO is not empty. When the RIO1 send length FIFO is not empty, it reads the value of the RIO1 send length FIFO, and reads the data of the corresponding length from the RIO1 send data FIFO according to the read value of the RIO1 send length FIFO, and sends the data to be sent Send_data_RIO1 to the RapidIO switching network through the RapidIOIP core;

[0034] The RIO2 send processing module monitors whether the RIO2 send length FIFO is not empty. When the RIO2 send length FIFO is not empty, it reads the value of the RIO2 send length FIFO, and reads data of corresponding length from the RIO2 send data FIFO according to the read value of the RIO2 send length FIFO, and sends the data to be sent Send_data_RIO1 to the RapidIO switching network through the RapidIO IPcore.

[0035] A RapidIO dual-port link configuration synchronous data receiving and sending method, based on the RapidIO dual-port link configuration synchronous data receiving and sending system as described above, comprises executing the following steps:

[0036] Step 1: The FPGA node RapidIO dual-port link configuration synchronization process enters the initial state after the power-on reset is completed, and monitors whether the RIO1_IP_in output from the RapidIO IP core of the RIO1 port is the configuration information and whether the RIO2_IP_in output from the RapidIO IP core of the RIO2 port is the configuration information;

[0037] Among them, it is monitored whether RIO1_IP_in output from the RapidIO IP core of the RIO1 port is in the configuration information process. If yes, it is transferred to writing the RIO configuration identifier into the write configuration identifier FIFO, the configuration information is written into the information synchronization module state, and then transferred to the configuration identifier FIFO whether it is empty process determination; in the configuration identifier FIFO whether it is empty process, otherwise it is transferred to the update configuration information synchronization module state, and after the update configuration information synchronization module is completed, it returns to the initial state;

[0038] Among them, it is monitored whether RIO2_IP_in output from the RapidIO IP core of the RIO2 port is in the configuration information process. If it is, it is transferred to writing the RIO configuration identifier into the write configuration identifier FIFO, the configuration information is written into the information synchronization module state, and then transferred to the configuration identifier FIFO whether it is empty process judgment; in the configuration identifier FIFO whether it is empty process, otherwise it is transferred to the update configuration information synchronization module state, and after the update configuration information synchronization module is completed, it returns to the initial state.

[0039] A RapidIO dual-port link configuration synchronous data receiving and sending method, based on the RapidIO dual-port link configuration synchronous data receiving and sending system as described above, comprises executing the following steps:

[0040] The data receiving process of the RIO1 port of the FPGA node enters the initial state after the power-on reset is completed; monitor whether the RIO1_IP_in output from the RapidIO IP core of the RIO1 port is valid data, if so, enter the state of writing the RIO1 data into the RIO1 receiving data FIFO, and then enter the process of determining whether the current RIO data packet has been written; in the process of determining whether the current RIO data packet has been written, if yes, return to the initial state;

[0041] The monitoring is as follows: whether RIO1_IP_in outputted from the RapidIO IP core of the RIO1 port is valid data, otherwise, it is transferred to the flow of determining whether RIO1_IP_in is a data length packet; in the flow of determining whether RIO1_IP_in is a data length packet, if yes, it is transferred to the flow of writing the RIO data length into the RIO1 receiving length FIFO state, and then it is transferred to the flow of determining whether the RIO1 receiving length FIFO is empty; in the flow of determining whether the RIO1 receiving length FIFO is empty, otherwise, it is transferred to the state of reading the value of the RIO1 receiving length FIFO, and then it is transferred to the state of reading the RIO1 receiving data FIFO, and writing the receiving data FIFO state, and then it is transferred to the flow of determining whether the RIO1 receiving data FIFO is read; in the flow of determining whether the RIO1 receiving data FIFO is read, if yes, it is transferred to the state of writing the value of the RIO1 receiving length FIFO into the receiving length FIFO state, and then it returns to the initial state;

[0042] as well as,

[0043] The data receiving process of the RIO2 port of the FPGA node enters the initial state after the power-on reset is completed; monitor whether the RIO2_IP_in output from the RapidIO IP core of the RIO2 port is valid data. If so, it will enter the state of writing the RIO data into the RIO2 receiving data FIFO, and then enter the process of determining whether the current RIO data packet has been written. In the process of determining whether the current RIO data packet has been written, if yes, it will return to the initial state;

[0044] The monitoring is as follows: whether RIO2_IP_in output from the RapidIO IP core of the RIO2 port is valid data, otherwise, it enters the process of determining whether RIO2_IP_in is a data length packet; in the process of determining whether RIO2_IP_in is a data length packet, if yes, it enters the process of writing the RIO data length into the RIO2 receiving length FIFO state, and then enters the process of determining whether the RIO2 receiving length FIFO is empty; in the process of determining whether the RIO2 receiving length FIFO is empty, otherwise, it enters the state of reading the RIO2 receiving length FIFO value, and then enters the state of reading the RIO2 receiving data FIFO and writing the receiving data FIFO state, and then enters the process of determining whether the RIO2 receiving data FIFO is read; in the process of determining whether the RIO2 receiving data FIFO is read, if yes, it enters the process of writing the RIO2 receiving length FIFO value into the receiving length FIFO state, and then returns to the initial state.

[0045] A RapidIO dual-port link configuration synchronous data receiving and sending method, based on the RapidIO dual-port link configuration synchronous data receiving and sending system as described above, comprises executing the following steps:

[0046] The data transmission process between the RIO1 port and the RIO2 port of the FPGA node enters the initial state after the power-on reset is completed; monitors whether the transmission length is empty, and returns to the initial state if it is; otherwise, it enters the process of determining whether the value of RIO_sync_send_sel is 2'b01 or 2'b10;

[0047] In the process determination state of whether the value of RIO_sync_send_sel is 2'b01 or 2'b10, if the value of RIO_sync_send_sel is 2'b01, then enter the state of writing RIO_send_data into RIO1 transmit data FIFO, and then enter the process of determining whether the writing of RIO1 transmit data FIFO is completed; in the process of determining whether the writing of RIO1 transmit data FIFO is completed, if yes, enter the state of writing RIO_send_len into RIO1 transmit length FIFO, and then enter the process of determining whether RIO1 length FIFO is empty; in the process of determining whether RIO1 length FIFO is empty, otherwise enter the state of reading RIO1 transmit length FIFO value, then enter the state of reading RIO1 transmit data FIFO, and then enter the process of determining whether the reading of RIO1 transmit data FIFO is completed; in the process of determining whether the reading of RIO1 transmit data FIFO is completed, if yes, return to the initial state;

[0048] In the process determination state of whether the value of RIO_sync_send_sel is 2'b01 or 2'b10, if the value of RIO_sync_send_sel is 2'b10, it will enter the state of writing RIO_send_data into RIO2 transmit data FIFO, and then enter the process of determining whether the writing of RIO2 transmit data FIFO is completed; in the process of determining whether the writing of RIO2 transmit data FIFO is completed, if yes, it will enter the state of writing RIO_send_len into RIO2 transmit length FIFO, and then enter the process of determining whether RIO2 length FIFO is empty; in the process of determining whether RIO2 length FIFO is empty, otherwise, it will enter the state of reading RIO2 transmit length FIFO value, and then enter the state of reading RIO2 transmit data FIFO, and then enter the process of determining whether the reading of RIO2 transmit data FIFO is completed. In the process of determining whether the reading of RIO2 transmit data FIFO is completed, if yes, it will return to the initial state.

[0049] A RapidIO dual-port link configuration synchronous data transceiver comprises a processor and a memory, wherein the memory stores a computer program, and when the computer program is loaded by the processor, the method described in any one of the above items is executed.

[0050] A computer-readable storage medium stores a computer program, wherein the computer program is loaded by a processor and executes any of the above methods.

[0051] The beneficial effects of the present invention include:

[0052] (1) The solution of the present invention can reduce the number of hardware boards, reduce system cost, volume and weight. Through the RapidIO dual-port method, the redundant backup of the RapidIO port is realized. In a single board, by adding a RapidIO port, the traditional method of relying on adding hardware boards to achieve redundant backup capabilities is solved.

[0053] (2) The solution of the present invention can reduce the time required for system recovery in a faulty state. Through the RapidIO dual-port link configuration synchronization method, when the link of any one of the RapidIO dual-ports is reconfigured, the link configuration information is automatically synchronized to the other RapidIO port. On the one hand, when the main management node fails, the backup management node obtains control. Since the RapidIO port works normally, there is no need for the backup management node to resend the link configuration information. On the other hand, when one of the two working RapidIO ports fails, since the information of the two RapidIO ports has been synchronized at the time of link configuration, there is no need for the main management node or the backup management node to resend the link configuration information to the other RapidIO port. Therefore, when the information of any one of the RapidIO ports is reconfigured, the configuration information will be automatically synchronized to the other RapidIO port, so that when the FPGA node fails, there is no need to reconfigure the RapidIO port of the FPGA node, thereby reducing the recovery time in a faulty state of the system.

[0054] (3) The solution of the present invention adopts a dual RapidIO port hot backup mode to improve the reliability of the system. Through the RapidIO dual-port mode, the two RapidIO ports are in hot backup mode, and the link configuration information of the two RapidIO ports is automatically synchronized. Whether the main management node fails or any one of the two RapidIO ports in the FPGA node fails, the system can quickly recover from the fault state to the normal working state, solving the problem of low reliability of the traditional cold backup mode.

[0055] (4) The software implementation of the solution of the present invention is simple, and the coupling between the data transceiver driver and the user logic is reduced. The RapidIO dual-port data transceiver adopts the data FIFO + length FIFO implementation mode. On the one hand, the input RapidIO dual-port data is received, and after merging and processing, the received data and the data packet length are output to the user logic; on the other hand, the data to be sent by the user logic is distributed to the corresponding RapidIO port after the data distribution processing. The RapidIO dual-port underlying driver is shielded, so that the user logic only focuses on data transceiver processing, and function development becomes simpler and more efficient. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0057] Figure 1 A schematic diagram of a method for synchronously transmitting and receiving data in a RapidIO dual-port link configuration according to an embodiment of the present invention;

[0058] Figure 2 for Figure 1 RapidIO dual-port link configuration synchronization implementation schematic diagram;

[0059] Figure 3 for Figure 1 RapidIO dual-port link configuration synchronous data reception implementation schematic diagram;

[0060] Figure 4 for Figure 1 RapidIO dual-port link configuration synchronous data transmission implementation flow chart;

[0061] Figure 5 for Figure 2 RapidIO dual-port link configuration synchronization process flow chart;

[0062] Figure 6 for Figure 3 RIO1 port data receiving process flow chart;

[0063] Figure 7 for Figure 3 RIO2 port data receiving process flow chart;

[0064] Figure 8 for Figure 4 RapidIO dual-port link configuration synchronous data transmission process flow chart. DETAILED DESCRIPTION

[0065] All features disclosed in all embodiments in this specification, or steps in all methods or processes implicitly disclosed, except for mutually exclusive features and / or steps, can be combined and / or expanded or replaced in any manner.

[0066] The specific implementation process of the present invention is as follows:

[0067] like Figure 1 As shown, the present invention provides a RapidIO dual-port link configuration synchronous data transceiving method, including: main management node (PPC type) + standby management node (PPC type) + communication node 1 to communication node N (FPGA / DSP / PPC any type) + RapidIO switching network + FPGA node. The main management node, standby management node, communication node 1 to communication node N and FPGA node are all connected to the RapidIO switching network through the RapidIO bus; the FPGA node includes two RapidIO ports, RIO1 port and RIO2 port; the chip in the RapidIO switching network adopts CPS1848 or corresponding domestic switching devices.

[0068] like Figure 2 As shown in the figure, the FPGA node is implemented using the RapidIO IP core (RIO1_IP) + RIO1 receiving configuration module + RIO1 receiving processing module + RIO1 sending processing module + configuration identification FIFO + configuration information synchronization module + data sending distribution module + RapidIO IP core (RIO2_IP) + RIO2 receiving configuration module + RIO2 receiving processing module + RIO2 sending processing module software architecture.

[0069] Figure 2In the process, first, the RIO1 port of the FPGA node receives the configuration information sent from the main management node and the backup management node, writes the RIO1 port configuration flag RIO1_cfg_flag (value is 2'b01) into the configuration flag FIFO, and writes the configuration information RIO1_cfg_info into the configuration information synchronization module. Secondly, the RIO2 port of the FPGA node receives the configuration information sent from the main management node and the backup management node, writes the RIO2 port configuration flag RIO2_cfg_flag (value is 2'b10) into the configuration flag FIFO, and writes the configuration information RIO2_cfg_info into the configuration information synchronization module. Furthermore, when the configuration flag FIFO is not empty, the configuration information synchronization module reads the configuration flag FIFO value RIO_cfg_flag, and synchronizes RIO1_cfg_info with RIO2_cfg_info according to the value of RIO_cfg_flag. On the one hand, when the value of RIO_cfg_flag is 2'b01, the output transmission configuration information RIO_sync_send_info and the reception configuration information RIO_sync_recv_info use the corresponding values ​​in RIO1_cfg_info, and set the data transmission distribution selection signal RIO_sync_send_sel to 2'b01; on the other hand, when the value of RIO_cfg_flag is 2'b10, the output transmission configuration information RIO_sync_send_info and the reception configuration information RIO_sync_recv_info use the corresponding values ​​in RIO2_cfg_info, and set the data transmission distribution selection signal RIO_sync_send_sel to 2'b10.

[0070] Figure 2 In the configuration information synchronization module, the receiving configuration information RIO_sync_recv_info, the sending configuration information RIO_sync_send_info and the data sending distribution selection signal RIO_sync_send_sel are output. The receiving configuration information RIO_sync_recv_info is sent to the RIO1 receiving processing module and the RIO2 receiving processing module; the sending configuration information RIO_sync_send_info is sent to the RIO1 sending processing module and the RIO2 sending processing module; the data sending distribution selection signal RIO_sync_send_sel is sent to the data sending distribution module.

[0071] like Figure 3As shown, FPGA node data reception is implemented using the RapidIO IP core (RIO1_IP) + RIO1 receive processing module + RIO1 receive data FIFO + RIO1 receive length FIFO + RapidIO IP core (RIO2_IP) + RIO2 receive processing module + RIO2 receive data FIFO + RIO2 receive length FIFO + configuration information synchronization module + data receive merging module + receive data FIFO + receive length FIFO software architecture.

[0072] Figure 3 In the process, first, the RIO1 port of the FPGA node receives data from the communication nodes 1 to the communication nodes N, identifies the received RIO1_IP_in according to the receiving configuration information RIO_sync_recv_info output by the configuration information synchronization module, writes the correctly identified received data RIO1_recv_data_in into the RIO1 receiving data FIFO, and writes the received data packet length RIO1_recv_len_in into the RIO1 receiving length FIFO. Secondly, the RIO2 port of the FPGA node receives data from the communication nodes 1 to the communication nodes N, identifies the received RIO2_IP_in according to the receiving configuration information RIO_sync_recv_info output by the configuration information synchronization module, writes the correctly identified received data RIO2_recv_data_in into the RIO2 receiving data FIFO, and writes the received data packet length RIO2_recv_len_in into the RIO2 receiving length FIFO. Furthermore, the receiving data merging module monitors whether the RIO1 receiving length FIFO and the RIO2 receiving length FIFO are not empty. On the one hand, when the RIO1 receive length FIFO is not empty, the RIO1 receive length FIFO value is read, and according to the receive length FIFO value read by RIO1, data of corresponding length is read from the RIO1 receive data FIFO and written into the receive data FIFO, and after the reading of the RIO1 receive data FIFO is completed, the receive length FIFO value read by RIO1 is written into the receive length FIFO; on the other hand, when the RIO2 receive length FIFO is not empty, the RIO2 receive length FIFO value is read, and according to the receive length FIFO value read by RIO2, data of corresponding length is read from the RIO2 receive data FIFO and written into the receive data FIFO, and after the reading of the RIO2 receive data FIFO is completed, the receive length FIFO value read by RIO2 is written into the receive length FIFO.

[0073] Figure 3In the example, the User_recv_data output by the receive data FIFO is the user received data, and the User_recv_len output by the receive length FIFO is the length of the user received data packet. When the receive length FIFO is not empty, data of corresponding length can be read from the receive data FIFO according to the value of User_recv_len.

[0074] like Figure 4 As shown, FPGA node data transmission is implemented using the RapidIO IP core (RIO1_IP) + RIO1 transmission processing module + RIO1 transmission data FIFO + RIO1 transmission length FIFO + RapidIO IP core (RIO2_IP) + RIO2 transmission processing module + RIO2 transmission data FIFO + RIO2 transmission length FIFO + configuration information synchronization module + data transmission distribution module + transmission data FIFO + transmission length FIFO software architecture.

[0075] Figure 4 In the process, first, the user writes the data to be sent User_send_data into the send data FIFO, and writes the length of the send data packet User_send_len into the send length FIFO. Secondly, the data transmission distribution module monitors whether the send length FIFO is empty. When the send length FIFO is not empty, the data in the send data FIFO is read according to the value of the data transmission distribution selection signal RIO_sync_send_sel output by the configuration information synchronization module, and written into the RIO1 send data FIFO or the RIO2 send data FIFO. On the one hand, when the value of RIO_sync_send_sel is 2'b01, the numerical operation of reading the send length FIFO is performed, and then according to the value of the read send length FIFO, data of the corresponding length is read from the send data FIFO and written into the RIO1 send data FIFO, and after the send data FIFO is read, the currently read send length FIFO value is written into the RIO1 send length FIFO; on the other hand, when the value of RIO_sync_send_sel is 2'b10, the numerical operation of reading the send length FIFO is performed, and according to the value of the read send length FIFO, data of the corresponding length is read from the send data FIFO and written into the RIO2 send data FIFO, and after the send data FIFO is read, the currently read send length FIFO value is written into the RIO2 send length FIFO.

[0076] Figure 4In the RIO1 send processing module, the RIO1 send length FIFO is monitored to see if it is not empty. When the RIO1 send length FIFO is not empty, the value of the RIO1 send length FIFO is read, and data of corresponding length is read from the RIO1 send data FIFO according to the read value of the RIO1 send length FIFO, and the data to be sent Send_data_RIO1 is sent to the RapidIO switching network through the RapidIO IP core (RIO1_IP).

[0077] Figure 4 In the RIO2 send processing module, the RIO2 send length FIFO is monitored to see if it is not empty. When the RIO2 send length FIFO is not empty, the value of the RIO2 send length FIFO is read, and data of corresponding length is read from the RIO2 send data FIFO according to the read value of the RIO2 send length FIFO, and the data to be sent Send_data_RIO1 is sent to the RapidIO switching network through the RapidIO IP core (RIO1_IP).

[0078] Figure 4 In the above, User_send_data is the data sent by the user, User_send_len is the length of the data packet sent by the user, User_send_data is written into the send data FIFO, and User_send_len is written into the send length FIFO.

[0079] like Figure 5 As shown in the figure, the FPGA node RapidIO dual-port link configuration synchronization process enters the initial state after the power-on reset is completed. At the same time, it monitors whether the RIO1_IP_in output from the RapidIO IP core of the RIO1 port is the configuration information and whether the RIO2_IP_in output from the RapidIO IP core of the RIO2 port is the configuration information.

[0080] Figure 5 In the process, monitor whether RIO1_IP_in output from the RapidIO IP core of the RIO1 port is in the configuration information process. If yes, enter the process of writing the RIO configuration identifier into the write configuration identifier FIFO, the configuration information is written into the information synchronization module state, and then enter the process of determining whether the configuration identifier FIFO is empty. In the process of whether the configuration identifier FIFO is empty, otherwise enter the state of the update configuration information synchronization module, and after the update configuration information synchronization module is completed, return to the initial state.

[0081] Figure 5In the process, monitor whether RIO2_IP_in output from the RapidIO IP core of the RIO2 port is in the configuration information process. If yes, enter the process of writing the RIO configuration identifier into the write configuration identifier FIFO, the configuration information is written into the information synchronization module state, and then enter the process of determining whether the configuration identifier FIFO is empty. In the process of whether the configuration identifier FIFO is empty, otherwise enter the state of the update configuration information synchronization module, and after the update configuration information synchronization module is completed, return to the initial state.

[0082] like Figure 6 As shown in the figure, the data receiving process of the RIO1 port of the FPGA node enters the initial state after the power-on reset is completed. Monitor whether the RIO1_IP_in output from the RapidIO IP core of the RIO1 port is valid data. If so, it will enter the state of writing the RIO data into the RIO1 receiving data FIFO, and then enter the process of determining whether the current RIO data packet has been written. In the process of whether the current RIO data packet has been written, if yes, it will return to the initial state.

[0083] Figure 6 In the process, monitor whether RIO1_IP_in output from the RapidIO IP core of the RIO1 port is valid data, otherwise, enter the process of determining whether RIO1_IP_in is a data length packet. In the process of determining whether RIO1_IP_in is a data length packet, if yes, enter the process of writing the RIO data length into the RIO1 receive length FIFO state, and then enter the process of determining whether the RIO1 receive length FIFO is empty. In the process of whether the RIO1 receive length FIFO is empty, otherwise, enter the state of reading the RIO1 receive length FIFO value, and then enter the state of reading the RIO1 receive data FIFO and writing the receive data FIFO, and then enter the process of determining whether the RIO1 receive data FIFO is read. In the process of whether the RIO1 receive data FIFO is read, if yes, enter the state of writing the RIO1 receive length FIFO value into the receive length FIFO state, and then return to the initial state.

[0084] like Figure 7 As shown in the figure, the data receiving process of the RIO2 port of the FPGA node enters the initial state after the power-on reset is completed. Monitor whether the RIO2_IP_in output from the RapidIO IP core of the RIO2 port is valid data. If so, enter the state of writing the RIO data into the RIO2 receiving data FIFO, and then enter the process of determining whether the current RIO data packet has been written. In the process of determining whether the current RIO data packet has been written, if yes, return to the initial state.

[0085] Figure 7In the process, monitor whether RIO2_IP_in output from the RIO2 port RapidIO IP core is valid data, otherwise, enter the process of determining whether RIO2_IP_in is a data length packet. In the process of determining whether RIO2_IP_in is a data length packet, if yes, enter the state of writing the RIO data length into the RIO2 receive length FIFO, and then enter the process of determining whether the RIO2 receive length FIFO is empty. In the process of whether the RIO2 receive length FIFO is empty, otherwise, enter the state of reading the RIO2 receive length FIFO value, and then enter the state of reading the RIO2 receive data FIFO and writing the receive data FIFO, and then enter the process of determining whether the RIO2 receive data FIFO is read. In the process of whether the RIO2 receive data FIFO is read, if yes, enter the state of writing the RIO2 receive length FIFO value into the receive length FIFO, and then return to the initial state.

[0086] like Figure 8 As shown in the figure, the data transmission process between the RIO1 port and the RIO2 port of the FPGA node enters the initial state after the power-on reset is completed. It monitors whether the transmission length is empty, and returns to the initial state if it is; otherwise, it goes to the process of judging whether the value of RIO_sync_send_sel is 2'b01 or 2'b10.

[0087] Figure 8 In the process of determining whether the value of RIO_sync_send_sel is 2'b01 or 2'b10, if the value of RIO_sync_send_sel is 2'b01, the state of writing RIO_send_data into the RIO1 transmit data FIFO is entered, and then the process of determining whether the writing of the RIO1 transmit data FIFO is completed is entered. In the process of determining whether the writing of the RIO1 transmit data FIFO is completed, if yes, the state of writing RIO_send_len into the RIO1 transmit length FIFO is entered, and then the process of determining whether the RIO1 length FIFO is empty is entered. In the process of determining whether the RIO1 length FIFO is empty, otherwise, the state of reading the value of the RIO1 transmit length FIFO is entered, and then the state of reading the RIO1 transmit data FIFO is entered, and then the process of determining whether the reading of the RIO1 transmit data FIFO is completed is entered. In the process of determining whether the reading of the RIO1 transmit data FIFO is completed, if yes, the process returns to the initial state.

[0088] Figure 8In the process of determining whether the value of RIO_sync_send_sel is 2'b01 or 2'b10, if the value of RIO_sync_send_sel is 2'b10, the state of writing RIO_send_data into the RIO2 transmit data FIFO is entered, and then the process of determining whether the writing of the RIO2 transmit data FIFO is completed is entered. In the process of determining whether the writing of the RIO2 transmit data FIFO is completed, if yes, the state of writing RIO_send_len into the RIO2 transmit length FIFO is entered, and then the process of determining whether the RIO2 length FIFO is empty is entered. In the process of determining whether the RIO2 length FIFO is empty, otherwise, the state of reading the value of the RIO2 transmit length FIFO is entered, and then the state of reading the RIO2 transmit data FIFO is entered, and then the process of determining whether the reading of the RIO2 transmit data FIFO is completed is entered. In the process of determining whether the reading of the RIO2 transmit data FIFO is completed, if yes, the process returns to the initial state.

[0089] It should be noted that within the scope of protection defined in the claims of the present invention, the following embodiments can be combined and / or expanded or replaced in any logical way from the above specific implementation methods, such as disclosed technical principles, disclosed technical features or implicitly disclosed technical features.

[0090] Example 1

[0091] A RapidIO dual-port link configuration synchronous data transceiver system is based on a main management node, a standby management node, communication nodes 1 to communication nodes N, a RapidIO switching network and an FPGA node. The main management node, the standby management node, the communication nodes 1 to communication nodes N and the FPGA node are all connected to the RapidIO switching network through a RapidIO bus; the FPGA node includes two RapidIO ports, RIO1 and RIO2; the main management node and the standby management node both have access management configuration authority to the two RapidIO ports of the FPGA node connected to the switching network; when working normally, the control authority of RapidIO is exclusively owned by the main management node, and when the main management node fails, the control authority is obtained from the management node.

[0092] Example 2

[0093] On the basis of Example 1, the primary management node is a PPC type primary management node, and the backup management node is a PPC type backup management node.

[0094] Example 3

[0095] Based on the embodiment 1, the chip in the RapidIO switching network adopts CPS1848 device or corresponding domestically produced switching device.

[0096] Example 4

[0097] A RapidIO dual-port link configuration synchronous data receiving and sending method, based on the RapidIO dual-port link configuration synchronous data receiving and sending system described in Example 1, further comprising executing the following steps:

[0098] Step S1, after power-on, the main management node initializes and configures the link information of the RIO1 port or the RIO2 port of the FPGA node; during the working process, according to the external information input, the link information of the RIO1 port or the RIO2 port of the FPGA node is dynamically configured; when any RapidIO port of the RIO1 port or the RIO2 port receives the link configuration information, the link configuration information is synchronously updated to the other RapidIO port;

[0099] Step S2, the data transmission and reception of the RIO1 port and the RIO2 port of the FPGA node are both in the data FIFO and length FIFO mode; when receiving data, the RIO1 port and the RIO2 port separate the input RIO_IP_in data according to the data RIO_sync_recv_info output by the configuration information synchronization module, and after being processed by the data receiving and merging module, the data is stored in the receiving data FIFO, and the data packet length is stored in the receiving length FIFO; when sending data, the data sending distribution module writes the data to be sent into the RIO1 sending data FIFO corresponding to the RIO1 port or the RIO2 sending data FIFO corresponding to the RIO2 port according to the RIO_sync_send_sel information output by the configuration information synchronization module, writes the length of the data packet to be sent into the RIO1 sending length FIFO corresponding to the RIO1 port or the RIO2 sending length FIFO corresponding to the RIO2 port, and sends it to the RapidIO switching network through the RapidIO IP core corresponding to the RIO1 port or the RIO2 port.

[0100] Example 5

[0101] A RapidIO dual-port link configuration synchronous data receiving and sending method, based on the RapidIO dual-port link configuration synchronous data receiving and sending system described in Example 1, comprises executing the following steps:

[0102] First, the FPGA node RIO1 port receives the configuration information sent from the main management node and the backup management node, writes the RIO1 port configuration flag RIO1_cfg_flag into the configuration flag FIFO; writes the configuration information RIO1_cfg_info into the configuration information synchronization module;

[0103] Then, the FPGA node RIO2 port receives the configuration information sent from the main management node and the backup management node, writes the RIO2 port configuration flag RIO2_cfg_flag into the configuration flag FIFO; writes the configuration information RIO2_cfg_info into the configuration information synchronization module;

[0104] Next, when the configuration flag FIFO is not empty, the configuration information synchronization module reads the configuration flag FIFO value RIO_cfg_flag, and synchronizes RIO1_cfg_info and RIO2_cfg_info according to the value of RIO_cfg_flag;

[0105] Finally, the configuration information synchronization module outputs the receiving configuration information RIO_sync_recv_info, the sending configuration information RIO_sync_send_info and the data sending distribution selection signal RIO_sync_send_sel; sends the receiving configuration information RIO_sync_recv_info to the RIO1 receiving processing module and the RIO2 receiving processing module; sends the sending configuration information RIO_sync_send_info to the RIO1 sending processing module and the RIO2 sending processing module; sends the data sending distribution selection signal RIO_sync_send_sel to the data sending distribution module.

[0106] Example 6

[0107] Based on Example 5, the value of the RIO1 port configuration flag RIO1_cfg_flag is 2'b01, and the value of the RIO2 port configuration flag RIO2_cfg_flag is 2'b10;

[0108] When the configuration flag FIFO is not empty, the configuration information synchronization module reads the configuration flag FIFO value RIO_cfg_flag, and synchronizes RIO1_cfg_info and RIO2_cfg_info according to the value of RIO_cfg_flag, specifically including the sub-steps:

[0109] When the value of RIO_cfg_flag is 2'b01, the output transmission configuration information RIO_sync_send_info and reception configuration information RIO_sync_recv_info use the corresponding values ​​in RIO1_cfg_info, and set the data transmission distribution selection signal RIO_sync_send_sel to 2'b01;

[0110] When the value of RIO_cfg_flag is 2'b10, the output transmission configuration information RIO_sync_send_info and reception configuration information RIO_sync_recv_info use the corresponding values ​​in RIO2_cfg_info, and set the data transmission distribution selection signal RIO_sync_send_sel to 2'b10.

[0111] Example 7

[0112] A RapidIO dual-port link configuration synchronous data receiving and sending method, based on the RapidIO dual-port link configuration synchronous data receiving and sending system described in Example 1, comprises executing the following steps:

[0113] First, the FPGA node RIO1 port receives data from communication node 1 to communication node N, identifies the received RIO1_IP_in according to the receiving configuration information RIO_sync_recv_info output by the configuration information synchronization module, writes the correctly identified received data RIO1_recv_data_in into the RIO1 receive data FIFO, and writes the received data packet length RIO1_recv_len_in into the RIO1 receive length FIFO;

[0114] Then, the FPGA node RIO2 port receives data from communication node 1 to communication node N, identifies the received RIO2_IP_in according to the receiving configuration information RIO_sync_recv_info output by the configuration information synchronization module, writes the correctly identified received data RIO2_recv_data_in into the RIO2 receiving data FIFO, and writes the received data packet length RIO2_recv_len_in into the RIO2 receiving length FIFO;

[0115] Then, the receiving data merging module monitors whether the RIO1 receiving length FIFO and the RIO2 receiving length FIFO are not empty; when the RIO1 receiving length FIFO is not empty, the RIO1 receiving length FIFO value is read, and according to the receiving length FIFO value read by RIO1, data of corresponding length is read from the RIO1 receiving data FIFO, and written into the receiving data FIFO, and after the reading of the RIO1 receiving data FIFO is completed, the receiving length FIFO value read by RIO1 is written into the receiving length FIFO; when the RIO2 receiving length FIFO is not empty, the RIO2 receiving length FIFO value is read, and according to the receiving length FIFO value read by RIO2, data of corresponding length is read from the RIO2 receiving data FIFO, and written into the receiving data FIFO, and after the reading of the RIO2 receiving data FIFO is completed, the receiving length FIFO value read by RIO2 is written into the receiving length FIFO;

[0116] Finally, the data User_recv_data output by the receive data FIFO is the user receive data, and the data User_recv_len output by the receive length FIFO is the length of the user receive data packet; when the receive length FIFO is not empty, data of corresponding length is read from the receive data FIFO according to the value of User_recv_len.

[0117] Example 8

[0118] A RapidIO dual-port link configuration synchronous data receiving and sending method, based on the RapidIO dual-port link configuration synchronous data receiving and sending system described in Example 1, comprises executing the following steps:

[0119] First, the user writes the data to be sent User_send_data into the send data FIFO, and writes the length of the send data packet User_send_len into the send length FIFO;

[0120] Then, the data transmission distribution module monitors whether the transmission length FIFO is empty. When the transmission length FIFO is not empty, the data in the transmission data FIFO is read according to the value of the data transmission distribution selection signal RIO_sync_send_sel output by the configuration information synchronization module, and written into the RIO1 transmission data FIFO or the RIO2 transmission data FIFO; when the value of RIO_sync_send_sel is 2'b01, the value operation of reading the transmission length FIFO is executed, and then the corresponding length is read from the transmission data FIFO according to the value of the read transmission length FIFO. Data is written into the RIO1 transmit data FIFO, and after the transmit data FIFO is read, the currently read transmit length FIFO value is written into the RIO1 transmit length FIFO; when the RIO_sync_send_sel value is 2'b10, the value operation of reading the transmit length FIFO is executed, and according to the value of the read transmit length FIFO, data of corresponding length is read from the transmit data FIFO and written into the RIO2 transmit data FIFO, and after the transmit data FIFO is read, the currently read transmit length FIFO value is written into the RIO2 transmit length FIFO;

[0121] Finally, the RIO1 send processing module monitors whether the RIO1 send length FIFO is not empty. When the RIO1 send length FIFO is not empty, it reads the value of the RIO1 send length FIFO, and reads the data of the corresponding length from the RIO1 send data FIFO according to the read value of the RIO1 send length FIFO, and sends the data to be sent Send_data_RIO1 to the RapidIO switching network through the RapidIOIP core;

[0122] The RIO2 send processing module monitors whether the RIO2 send length FIFO is not empty. When the RIO2 send length FIFO is not empty, it reads the value of the RIO2 send length FIFO, and reads data of corresponding length from the RIO2 send data FIFO according to the read value of the RIO2 send length FIFO, and sends the data to be sent Send_data_RIO1 to the RapidIO switching network through the RapidIO IPcore.

[0123] Example 9

[0124] A RapidIO dual-port link configuration synchronous data receiving and sending method, based on the RapidIO dual-port link configuration synchronous data receiving and sending system described in Example 1, comprises executing the following steps:

[0125] Step 1: The FPGA node RapidIO dual-port link configuration synchronization process enters the initial state after the power-on reset is completed, and monitors whether the RIO1_IP_in output from the RapidIO IP core of the RIO1 port is the configuration information and whether the RIO2_IP_in output from the RapidIO IP core of the RIO2 port is the configuration information;

[0126] Among them, it is monitored whether RIO1_IP_in output from the RapidIO IP core of the RIO1 port is in the configuration information process. If yes, it is transferred to writing the RIO configuration identifier into the write configuration identifier FIFO, the configuration information is written into the information synchronization module state, and then transferred to the configuration identifier FIFO whether it is empty process determination; in the configuration identifier FIFO whether it is empty process, otherwise it is transferred to the update configuration information synchronization module state, and after the update configuration information synchronization module is completed, it returns to the initial state;

[0127] Among them, it is monitored whether RIO2_IP_in output from the RapidIO IP core of the RIO2 port is in the configuration information process. If it is, it is transferred to writing the RIO configuration identifier into the write configuration identifier FIFO, the configuration information is written into the information synchronization module state, and then transferred to the configuration identifier FIFO whether it is empty process judgment; in the configuration identifier FIFO whether it is empty process, otherwise it is transferred to the update configuration information synchronization module state, and after the update configuration information synchronization module is completed, it returns to the initial state.

[0128] Example 10

[0129] A RapidIO dual-port link configuration synchronous data receiving and sending method, based on the RapidIO dual-port link configuration synchronous data receiving and sending system described in Example 1, comprises executing the following steps:

[0130] The data receiving process of the RIO1 port of the FPGA node enters the initial state after the power-on reset is completed; monitor whether the RIO1_IP_in output from the RapidIO IP core of the RIO1 port is valid data, if so, enter the state of writing the RIO1 data into the RIO1 receiving data FIFO, and then enter the process of determining whether the current RIO data packet has been written; in the process of determining whether the current RIO data packet has been written, if yes, return to the initial state;

[0131] The monitoring is as follows: whether RIO1_IP_in outputted from the RapidIO IP core of the RIO1 port is valid data, otherwise, it is transferred to the flow of determining whether RIO1_IP_in is a data length packet; in the flow of determining whether RIO1_IP_in is a data length packet, if yes, it is transferred to the flow of writing the RIO data length into the RIO1 receiving length FIFO state, and then it is transferred to the flow of determining whether the RIO1 receiving length FIFO is empty; in the flow of determining whether the RIO1 receiving length FIFO is empty, otherwise, it is transferred to the state of reading the value of the RIO1 receiving length FIFO, and then it is transferred to the state of reading the RIO1 receiving data FIFO, and writing the receiving data FIFO state, and then it is transferred to the flow of determining whether the RIO1 receiving data FIFO is read; in the flow of determining whether the RIO1 receiving data FIFO is read, if yes, it is transferred to the state of writing the value of the RIO1 receiving length FIFO into the receiving length FIFO state, and then it returns to the initial state;

[0132] as well as,

[0133] The data receiving process of the RIO2 port of the FPGA node enters the initial state after the power-on reset is completed; monitor whether the RIO2_IP_in output from the RapidIO IP core of the RIO2 port is valid data. If so, it will enter the state of writing the RIO data into the RIO2 receiving data FIFO, and then enter the process of determining whether the current RIO data packet has been written. In the process of determining whether the current RIO data packet has been written, if yes, it will return to the initial state;

[0134] The monitoring is as follows: whether RIO2_IP_in output from the RapidIO IP core of the RIO2 port is valid data, otherwise, it enters the process of determining whether RIO2_IP_in is a data length packet; in the process of determining whether RIO2_IP_in is a data length packet, if yes, it enters the process of writing the RIO data length into the RIO2 receiving length FIFO state, and then enters the process of determining whether the RIO2 receiving length FIFO is empty; in the process of determining whether the RIO2 receiving length FIFO is empty, otherwise, it enters the state of reading the RIO2 receiving length FIFO value, and then enters the state of reading the RIO2 receiving data FIFO and writing the receiving data FIFO state, and then enters the process of determining whether the RIO2 receiving data FIFO is read; in the process of determining whether the RIO2 receiving data FIFO is read, if yes, it enters the process of writing the RIO2 receiving length FIFO value into the receiving length FIFO state, and then returns to the initial state.

[0135] Embodiment 11

[0136] A RapidIO dual-port link configuration synchronous data receiving and sending method, based on the RapidIO dual-port link configuration synchronous data receiving and sending system described in Example 1, comprises executing the following steps:

[0137] The data transmission process between the RIO1 port and the RIO2 port of the FPGA node enters the initial state after the power-on reset is completed; monitors whether the transmission length is empty, and returns to the initial state if it is; otherwise, it enters the process of determining whether the value of RIO_sync_send_sel is 2'b01 or 2'b10;

[0138] In the process determination state of whether the value of RIO_sync_send_sel is 2'b01 or 2'b10, if the value of RIO_sync_send_sel is 2'b01, then enter the state of writing RIO_send_data into RIO1 transmit data FIFO, and then enter the process of determining whether the writing of RIO1 transmit data FIFO is completed; in the process of determining whether the writing of RIO1 transmit data FIFO is completed, if yes, enter the state of writing RIO_send_len into RIO1 transmit length FIFO, and then enter the process of determining whether RIO1 length FIFO is empty; in the process of determining whether RIO1 length FIFO is empty, otherwise enter the state of reading RIO1 transmit length FIFO value, then enter the state of reading RIO1 transmit data FIFO, and then enter the process of determining whether the reading of RIO1 transmit data FIFO is completed; in the process of determining whether the reading of RIO1 transmit data FIFO is completed, if yes, return to the initial state;

[0139] In the process determination state of whether the value of RIO_sync_send_sel is 2'b01 or 2'b10, if the value of RIO_sync_send_sel is 2'b10, it will enter the state of writing RIO_send_data into RIO2 transmit data FIFO, and then enter the process of determining whether the writing of RIO2 transmit data FIFO is completed; in the process of determining whether the writing of RIO2 transmit data FIFO is completed, if yes, it will enter the state of writing RIO_send_len into RIO2 transmit length FIFO, and then enter the process of determining whether RIO2 length FIFO is empty; in the process of determining whether RIO2 length FIFO is empty, otherwise, it will enter the state of reading RIO2 transmit length FIFO value, and then enter the state of reading RIO2 transmit data FIFO, and then enter the process of determining whether the reading of RIO2 transmit data FIFO is completed. In the process of determining whether the reading of RIO2 transmit data FIFO is completed, if yes, it will return to the initial state.

[0140] Example 12

[0141] A RapidIO dual-port link configuration synchronous data transceiver comprises a processor and a memory, wherein the memory stores a computer program, and when the computer program is loaded by the processor, the method described in any one of Embodiments 4 to 11 is executed.

[0142] Example 13

[0143] A computer-readable storage medium stores a computer program in the readable storage medium, wherein the computer program is loaded by a processor and executes the method described in any one of Embodiments 4 to 11.

[0144] The units involved in the embodiments of the present invention may be implemented by software or hardware, and the units described may also be arranged in a processor. The names of these units do not, in some cases, limit the units themselves.

[0145] According to one aspect of an embodiment of the present invention, a computer program product or a computer program is provided, the computer program product or the computer program includes a computer instruction, and the computer instruction is stored in a computer-readable storage medium. A processor of a computer device reads the computer instruction from the computer-readable storage medium, and the processor executes the computer instruction, so that the computer device executes the method provided in the above various optional implementations.

[0146] As another aspect, an embodiment of the present invention further provides a computer-readable medium, which may be included in the electronic device described in the above embodiment; or may exist independently without being assembled into the electronic device. The above computer-readable medium carries one or more programs, and when the above one or more programs are executed by an electronic device, the electronic device implements the method described in the above embodiment.

Claims

1. A RapidIO dual-port link configuration synchronous data transceiver system, characterized in that: Based on the main management node, the standby management node, the communication node 1 to the communication node N, the RapidIO switching network and the FPGA node, the main management node, the standby management node, the communication node 1 to the communication node N and the FPGA node are all connected to the RapidIO switching network through the RapidIO bus; the FPGA node includes two RapidIO ports, RIO1 and RIO2; the main management node and the standby management node have access management configuration authority to the two RapidIO ports of the FPGA node connected to the switching network; when working normally, the control authority of RapidIO is exclusively owned by the main management node, and when the main management node fails, the control authority is obtained from the management node.

2. The RapidIO dual-port link configuration synchronous data transceiver system according to claim 1, characterized in that: The primary management node is a PPC type primary management node, and the backup management node is a PPC type backup management node.

3. The RapidIO dual-port link configuration synchronous data transceiver system according to claim 1, characterized in that: The chip in the RapidIO switching network adopts CPS1848 device or corresponding domestic switching device.

4. A RapidIO dual-port link configuration synchronous data transmission and reception method, characterized in that: The RapidIO dual-port link configuration synchronous data transceiver system according to claim 1 further comprises executing the following steps: Step S1, after power-on, the main management node initializes and configures the link information of the RIO1 port or the RIO2 port of the FPGA node; during the working process, according to the external information input, the link information of the RIO1 port or the RIO2 port of the FPGA node is dynamically configured; when any RapidIO port of the RIO1 port or the RIO2 port receives the link configuration information, the link configuration information is synchronously updated to the other RapidIO port; Step S2, the data transmission and reception of the RIO1 port and the RIO2 port of the FPGA node are both in the data FIFO and length FIFO mode; when receiving data, the RIO1 port and the RIO2 port separate the input RIO_IP_in data according to the data RIO_sync_recv_info output by the configuration information synchronization module, and after being processed by the data receiving and merging module, the data is stored in the receiving data FIFO, and the data packet length is stored in the receiving length FIFO; when sending data, the data sending distribution module writes the data to be sent into the RIO1 sending data FIFO corresponding to the RIO1 port or the RIO2 sending data FIFO corresponding to the RIO2 port according to the RIO_sync_send_sel information output by the configuration information synchronization module, writes the length of the data packet to be sent into the RIO1 sending length FIFO corresponding to the RIO1 port or the RIO2 sending length FIFO corresponding to the RIO2 port, and sends it to the RapidIO switching network through the RapidIO IP core corresponding to the RIO1 port or the RIO2 port.

5. A RapidIO dual-port link configuration synchronous data transmission and reception method, characterized in that: The RapidIO dual-port link configuration synchronous data transceiver system according to claim 1 comprises the following steps: First, the FPGA node RIO1 port receives the configuration information sent from the main management node and the backup management node, writes the RIO1 port configuration flag RIO1_cfg_flag into the configuration flag FIFO; writes the configuration information RIO1_cfg_info into the configuration information synchronization module; Then, the FPGA node RIO2 port receives the configuration information sent from the main management node and the backup management node, writes the RIO2 port configuration flag RIO2_cfg_flag into the configuration flag FIFO; writes the configuration information RIO2_cfg_info into the configuration information synchronization module; Next, when the configuration flag FIFO is not empty, the configuration information synchronization module reads the configuration flag FIFO value RIO_cfg_flag, and synchronizes RIO1_cfg_info and RIO2_cfg_info according to the value of RIO_cfg_flag; Finally, the configuration information synchronization module outputs the receiving configuration information RIO_sync_recv_info, the sending configuration information RIO_sync_send_info and the data sending distribution selection signal RIO_sync_send_sel; sends the receiving configuration information RIO_sync_recv_info to the RIO1 receiving processing module and the RIO2 receiving processing module; sends the sending configuration information RIO_sync_send_info to the RIO1 sending processing module and the RIO2 sending processing module; sends the data sending distribution selection signal RIO_sync_send_sel to the data sending distribution module.

6. The RapidIO dual-port link configuration synchronous data receiving and sending method according to claim 5, characterized in that: The value of the RIO1 port configuration flag RIO1_cfg_flag is 2'b01, and the value of the RIO2 port configuration flag RIO2_cfg_flag is 2'b10; When the configuration flag FIFO is not empty, the configuration information synchronization module reads the configuration flag FIFO value RIO_cfg_flag, and synchronizes RIO1_cfg_info and RIO2_cfg_info according to the value of RIO_cfg_flag, specifically including the sub-steps: When the value of RIO_cfg_flag is 2'b01, the output transmission configuration information RIO_sync_send_info and reception configuration information RIO_sync_recv_info use the corresponding values ​​in RIO1_cfg_info, and set the data transmission distribution selection signal RIO_sync_send_sel to 2'b01; When the value of RIO_cfg_flag is 2'b10, the output transmission configuration information RIO_sync_send_info and reception configuration information RIO_sync_recv_info use the corresponding values ​​in RIO2_cfg_info, and set the data transmission distribution selection signal RIO_sync_send_sel to 2'b10.

7. A RapidIO dual-port link configuration synchronous data transmission and reception method, characterized in that: The RapidIO dual-port link configuration synchronous data transceiver system according to claim 1 comprises the following steps: First, the FPGA node RIO1 port receives data from communication node 1 to communication node N, identifies the received RIO1_IP_in according to the receiving configuration information RIO_sync_recv_info output by the configuration information synchronization module, writes the correctly identified received data RIO1_recv_data_in into the RIO1 receive data FIFO, and writes the received data packet length RIO1_recv_len_in into the RIO1 receive length FIFO; Then, the FPGA node RIO2 port receives data from communication node 1 to communication node N, identifies the received RIO2_IP_in according to the receiving configuration information RIO_sync_recv_info output by the configuration information synchronization module, writes the correctly identified received data RIO2_recv_data_in into the RIO2 receiving data FIFO, and writes the received data packet length RIO2_recv_len_in into the RIO2 receiving length FIFO; Then, the receiving data merging module monitors whether the RIO1 receiving length FIFO and the RIO2 receiving length FIFO are not empty; when the RIO1 receiving length FIFO is not empty, the RIO1 receiving length FIFO value is read, and according to the receiving length FIFO value read by RIO1, data of corresponding length is read from the RIO1 receiving data FIFO, and written into the receiving data FIFO, and after the reading of the RIO1 receiving data FIFO is completed, the receiving length FIFO value read by RIO1 is written into the receiving length FIFO; when the RIO2 receiving length FIFO is not empty, the RIO2 receiving length FIFO value is read, and according to the receiving length FIFO value read by RIO2, data of corresponding length is read from the RIO2 receiving data FIFO, and written into the receiving data FIFO, and after the reading of the RIO2 receiving data FIFO is completed, the receiving length FIFO value read by RIO2 is written into the receiving length FIFO; Finally, the data User_recv_data output by the receive data FIFO is the user receive data, and the data User_recv_len output by the receive length FIFO is the length of the user receive data packet; when the receive length FIFO is not empty, data of corresponding length is read from the receive data FIFO according to the value of User_recv_len.

8. A RapidIO dual-port link configuration synchronous data transmission and reception method, characterized in that: The RapidIO dual-port link configuration synchronous data transceiver system according to claim 1 comprises the following steps: First, the user writes the data to be sent User_send_data into the send data FIFO, and writes the length of the send data packet User_send_len into the send length FIFO; Then, the data transmission distribution module monitors whether the transmission length FIFO is empty. When the transmission length FIFO is not empty, the data in the transmission data FIFO is read according to the value of the data transmission distribution selection signal RIO_sync_send_sel output by the configuration information synchronization module, and written into the RIO1 transmission data FIFO or the RIO2 transmission data FIFO; when the value of RIO_sync_send_sel is 2'b01, the value operation of reading the transmission length FIFO is executed, and then the corresponding length is read from the transmission data FIFO according to the value of the read transmission length FIFO. Data is written into the RIO1 transmit data FIFO, and after the transmit data FIFO is read, the currently read transmit length FIFO value is written into the RIO1 transmit length FIFO; when the RIO_sync_send_sel value is 2'b10, the value operation of reading the transmit length FIFO is executed, and according to the value of the read transmit length FIFO, data of corresponding length is read from the transmit data FIFO and written into the RIO2 transmit data FIFO, and after the transmit data FIFO is read, the currently read transmit length FIFO value is written into the RIO2 transmit length FIFO; Finally, the RIO1 send processing module monitors whether the RIO1 send length FIFO is not empty. When the RIO1 send length FIFO is not empty, it reads the value of the RIO1 send length FIFO, and reads data of corresponding length from the RIO1 send data FIFO according to the read value of the RIO1 send length FIFO, and sends the data to be sent Send_data_RIO1 to the RapidIO switching network through the RapidIO IPcore; The RIO2 send processing module monitors whether the RIO2 send length FIFO is not empty. When the RIO2 send length FIFO is not empty, it reads the value of the RIO2 send length FIFO, and reads data of corresponding length from the RIO2 send data FIFO according to the read value of the RIO2 send length FIFO, and sends the data to be sent Send_data_RIO1 to the RapidIO switching network through the RapidIO IP core.

9. A RapidIO dual-port link configuration synchronous data transmission and reception method, characterized in that: The RapidIO dual-port link configuration synchronous data transceiver system according to claim 1 comprises the following steps: Step 1: The FPGA node RapidIO dual-port link configuration synchronization process enters the initial state after the power-on reset is completed, and monitors whether the RIO1_IP_in output from the RapidIO IP core of the RIO1 port is the configuration information and whether the RIO2_IP_in output from the RapidIO IP core of the RIO2 port is the configuration information; Among them, it is monitored whether RIO1_IP_in output from the RapidIO IP core of the RIO1 port is in the configuration information process. If yes, it is transferred to writing the RIO configuration identifier into the write configuration identifier FIFO, the configuration information is written into the information synchronization module state, and then transferred to the configuration identifier FIFO whether it is empty process determination; in the configuration identifier FIFO whether it is empty process, otherwise it is transferred to the update configuration information synchronization module state, and after the update configuration information synchronization module is completed, it returns to the initial state; Among them, it is monitored whether RIO2_IP_in output from the RapidIO IP core of the RIO2 port is in the configuration information process. If it is, it is transferred to writing the RIO configuration identifier into the write configuration identifier FIFO, the configuration information is written into the information synchronization module state, and then transferred to the configuration identifier FIFO whether it is empty process judgment; in the configuration identifier FIFO whether it is empty process, otherwise it is transferred to the update configuration information synchronization module state, and after the update configuration information synchronization module is completed, it returns to the initial state.

10. A RapidIO dual-port link configuration synchronous data transceiver method, characterized in that: The RapidIO dual-port link configuration synchronous data transceiver system according to claim 1 comprises the following steps: The data receiving process of the RIO1 port of the FPGA node enters the initial state after the power-on reset is completed; monitor whether the RIO1_IP_in output from the RapidIO IP core of the RIO1 port is valid data, if so, enter the state of writing the RIO1 data into the RIO1 receiving data FIFO, and then enter the process of determining whether the current RIO data packet has been written; in the process of determining whether the current RIO data packet has been written, if yes, return to the initial state; The monitoring is to determine whether RIO1_IP_in output from the RapidIO IP core of the RIO1 port is valid data, otherwise, it is transferred to the process of determining whether RIO1_IP_in is a data length packet; in the process of determining whether RIO1_IP_in is a data length packet, if yes, it is transferred to the state of writing the RIO data length into the RIO1 receiving length FIFO, and then transferred to the process of determining whether the RIO1 receiving length FIFO is empty; In the process of whether the RIO1 receive length FIFO is empty, if not, it will go into the state of reading the RIO1 receive length FIFO value, and then go into the state of reading the RIO1 receive data FIFO, and write the receive data FIFO state, and then go into the process of judging whether the RIO1 receive data FIFO is read; In the process of whether the RIO1 receive data FIFO is read and completed, if yes, it will enter the state of writing the RIO1 receive length FIFO value into the receive length FIFO state, and then return to the initial state; as well as, The data receiving process of the RIO2 port of the FPGA node enters the initial state after the power-on reset is completed; monitor whether the RIO2_IP_in output from the RapidIO IP core of the RIO2 port is valid data. If so, it will enter the state of writing the RIO data into the RIO2 receiving data FIFO, and then enter the process of determining whether the current RIO data packet has been written. In the process of determining whether the current RIO data packet has been written, if yes, it will return to the initial state; The monitoring is to determine whether RIO2_IP_in output from the RapidIO IP core of the RIO2 port is valid data, otherwise, it is transferred to the process of determining whether RIO2_IP_in is a data length packet; in the process of determining whether RIO2_IP_in is a data length packet, if yes, it is transferred to the state of writing the RIO data length into the RIO2 receiving length FIFO, and then transferred to the process of determining whether the RIO2 receiving length FIFO is empty; In the process of whether the RIO2 receive length FIFO is empty, if not, it will go into the state of reading the RIO2 receive length FIFO value, and then go into the state of reading the RIO2 receive data FIFO, and write the receive data FIFO state, and then go into the process of judging whether the RIO2 receive data FIFO is read; In the process of whether the RIO2 receive data FIFO is read and completed, if yes, it will enter the state of writing the RIO2 receive length FIFO value into the receive length FIFO state, and then return to the initial state.

11. A RapidIO dual-port link configuration synchronous data receiving and sending method, characterized in that: The RapidIO dual-port link configuration synchronous data transceiver system according to claim 1 comprises the following steps: The data transmission process between the RIO1 port and the RIO2 port of the FPGA node enters the initial state after the power-on reset is completed; monitors whether the transmission length is empty, and returns to the initial state if it is; otherwise, it enters the process of determining whether the value of RIO_sync_send_sel is 2'b01 or 2'b10; In the process determination state of whether the value of RIO_sync_send_sel is 2'b01 or 2'b10, if the value of RIO_sync_send_sel is 2'b01, then enter the state of writing RIO_send_data into RIO1 transmit data FIFO, and then enter the process of determining whether the writing of RIO1 transmit data FIFO is completed; in the process of determining whether the writing of RIO1 transmit data FIFO is completed, if yes, enter the state of writing RIO_send_len into RIO1 transmit length FIFO, and then enter the process of determining whether RIO1 length FIFO is empty; in the process of determining whether RIO1 length FIFO is empty, otherwise enter the state of reading RIO1 transmit length FIFO value, then enter the state of reading RIO1 transmit data FIFO, and then enter the process of determining whether the reading of RIO1 transmit data FIFO is completed; in the process of determining whether the reading of RIO1 transmit data FIFO is completed, if yes, return to the initial state; In the process determination state of whether the value of RIO_sync_send_sel is 2'b01 or 2'b10, if the value of RIO_sync_send_sel is 2'b10, it will enter the state of writing RIO_send_data into RIO2 transmit data FIFO, and then enter the process of determining whether the writing of RIO2 transmit data FIFO is completed; in the process of determining whether the writing of RIO2 transmit data FIFO is completed, if yes, it will enter the state of writing RIO_send_len into RIO2 transmit length FIFO, and then enter the process of determining whether RIO2 length FIFO is empty; in the process of determining whether RIO2 length FIFO is empty, otherwise, it will enter the state of reading RIO2 transmit length FIFO value, and then enter the state of reading RIO2 transmit data FIFO, and then enter the process of determining whether the reading of RIO2 transmit data FIFO is completed. In the process of determining whether the reading of RIO2 transmit data FIFO is completed, if yes, it will return to the initial state.

12. A RapidIO dual-port link configuration synchronous data transceiver device, characterized in that: The method comprises a processor and a memory, wherein a computer program is stored in the memory, and when the computer program is loaded by the processor, the method according to any one of claims 4 to 11 is executed.

13. A computer-readable storage medium, characterized in that: A computer program is stored in the readable storage medium, and the computer program is loaded by a processor to execute the method according to any one of claims 4 to 11.

Images