UVM verification platform of UCIe adaptation layer

Abstract

The invention provides a UVM verification platform of a UCIe adaptation layer. The platform comprises an FDI assembly, the UCIe adaptation layer to be verified, an error injection delay module and an RDI assembly. The FDI component is used for constructing a first data signal from a protocol layer and sending the first data signal to the UCIe adaptation layer to be verified; the UCIe adaptation layer to be verified is used for processing the first data signal to obtain a second data signal; and the error injection delay module is used for performing error injection and delay operation on the second data signal to obtain a third data signal and sending the third data signal to the RDI component, and can perform link delay simulation and error injection scene construction on the UCIe adaptation layer to assist in performing UCIe adaptation layer function verification.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit testing, and in particular to a UVM verification platform for a UCIe adaptation layer. Background Art

[0002] UCIe (Universal Chiplet Interconnect express) is the fastest solution in the field of high-speed interconnection. It is a layered protocol with three layers: Protocol Layer, which is implemented through a protocol based on a flow control unit (FLIT) to ensure maximum efficiency and reduce latency. D2D AdapterLayer, which is used to provide functions such as link state management and parameter negotiation, supports ARB (arbitration) / MUX (multi-way selection) functions, CRC (Cyclic Redundancy Check) and data error correction mechanism. PhysicalLayer, which is responsible for electrical signals, clocks, link training, etc.

[0003] The functional quality of the adaptation layer determines the transmission efficiency of the protocol layer and the physical layer. Therefore, how to effectively verify the retransmission error correction and other functions and transmission efficiency of the adaptation layer is the key to UCIe design. However, the UCIe adaptation layer currently does not have a suitable VIP (Verification Intellectual Property core, verification IP) to assist in functional verification. Summary of the invention

[0004] The present application provides a UVM verification platform for a UCIe adaptation layer to simulate link delay and construct an injection error scenario for the UCIe adaptation layer, thereby assisting in functional verification of the UCIe adaptation layer.

[0005] The present application provides a UVM verification platform for a UCIe adaptation layer, the platform comprising: FDI component, UCIe adaptation layer to be verified, error injection delay module and RDI component; The FDI component is used to construct a first data signal from the protocol layer and send it to the UCIe adaptation layer to be verified; The UCIe adaptation layer to be verified is used to process the first data signal to obtain a second data signal; The error injection and delay module is used to perform error injection and delay operations on the second data signal to obtain a third data signal and send it to the RDI component.

[0006] According to a UVM verification platform for a UCIe adaptation layer provided by the present application, the RDI component is also used to construct a fourth data signal from the physical layer; Correspondingly, the error injection delay module is further used to perform error injection and delay operations on the fourth data signal to obtain a fifth data signal and send it to the UCIe adaptation layer to be verified; The UCIe adaptation layer to be verified is further used to process the fifth data signal to obtain a sixth data signal and send the sixth data signal to the FDI component.

[0007] According to a UVM verification platform for a UCIe adaptation layer provided by the present application, the FDI component and the RDI component are both components of the uvm_component type designed based on UVM.

[0008] According to a UVM verification platform for a UCIe adaptation layer provided by the present application, the error injection delay module includes a link error injection submodule and a link delay submodule connected to each other; The link error injection submodule is used to perform an error injection operation on the input signal; The link delay submodule is used to perform a delay operation on the input signal after the error injection operation is performed.

[0009] According to a UVM verification platform for a UCIe adaptation layer provided by the present application, the link error injection submodule includes a link signal input port, an error injection signal input port and a signal output port; The link signal input port is used to input a data signal from a UCIe adaptation layer or an RDI component to be verified; The error injection signal input port is used to input an error injection signal, and the signal output port is used to output a data signal after the error injection operation.

[0010] According to a UVM verification platform for a UCIe adaptation layer provided by the present application, the error injection signal includes error injection enable indication information, error injection type indication information and error injection value indication information.

[0011] According to a UVM verification platform of a UCIe adaptation layer provided by the present application, the error injection types include interval error injection and continuous error injection.

[0012] According to a UVM verification platform for a UCIe adaptation layer provided by the present application, the link delay submodule includes a link signal input port, a reference clock input port, a delay control signal input port and a signal output port; The link signal input port is used to input the data signal after the error injection operation; The reference clock input port is used to input a delayed reference clock signal; The delay control signal input port is used to input a delay control signal; The signal output port is used to output the data signal after the delay operation.

[0013] According to a UVM verification platform of a UCIe adaptation layer provided by the present application, the link delay submodule includes a plurality of cascaded delay models and a multiplexer connected to each delay model signal; Each delay model is used to determine a respective delay amount based on the period of the delay reference clock signal, and to perform a delay operation on the data signal after the error injection operation based on the respective delay amount; The multiplexer is used to control the target delay model to output a data signal after the delay operation based on the delay control signal.

[0014] According to a UVM verification platform of a UCIe adaptation layer provided by the present application, the delay control signal includes a delay value control variable, the delay value control variable is used to indicate the delay value corresponding to the delay operation, and the delay value control variable is defined by a random variable macro.

[0015] The UVM verification platform of the UCIe adaptation layer provided in the present application includes: an FDI component, a UCIe adaptation layer to be verified, an error injection delay module and an RDI component; the FDI component is used to construct a first data signal from a protocol layer and send it to the UCIe adaptation layer to be verified; the UCIe adaptation layer to be verified is used to process the first data signal to obtain a second data signal; the error injection delay module is used to perform error injection and delay operations on the second data signal to obtain a third data signal and send it to the RDI component, which can simulate the link delay of the UCIe adaptation layer and construct an error injection scenario, and assist in the functional verification of the UCIe adaptation layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the present application or the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0017] Figure 1 It is a schematic diagram of the structure of the UVM verification platform of the UCIe adaptation layer provided by this application; Figure 2 It is a schematic diagram of input and output signals of the link error injection submodule provided by the present application; Figure 3 It is a specific structural diagram of the link delay submodule provided in this application. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be clearly and completely described below in conjunction with the drawings in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0019] Figure 1 It is a schematic diagram of the structure of the UVM verification platform of the UCIe adaptation layer provided by this application, such as Figure 1 As shown, the circuit comprises: The platform includes: FDI (Flit-aware D2D Interface) component, UCIe adaptation layer to be verified, error injection delay module and RDI (Raw D2D Interface) component; The FDI component is used to construct a first data signal from the protocol layer and send it to the UCIe adaptation layer to be verified; The UCIe adaptation layer to be verified is used to process the first data signal to obtain a second data signal; The error injection and delay module is used to perform error injection and delay operations on the second data signal to obtain a third data signal and send it to the RDI component.

[0020] Specifically, considering that the main functions of the UCIe adaptation layer are CRC and data error correction, and that the transmission of the physical layer has a delay, this application designs a UVM verification platform for the UCIe adaptation layer, which can effectively ensure the RTL (Register Transfer Level) design quality of the UCIe adaptation layer. More specifically, since the UCIe adaptation layer contains input and output paths in two directions, TX (sending data, i.e., the UCIe adaptation layer as the data transmitter) and RX (receiving data, i.e., the UCIe adaptation layer as the data receiver), its data flow with the FDI end and the RDI end is bidirectional. Based on this, the UVM verification platform of the embodiment of the present application constructs the first data signal from the protocol layer through the FDI component and sends it to the UCIe adaptation layer to be verified. The UCIe adaptation layer to be verified processes the first data signal to obtain the second data signal, and then performs error injection and delay operations on the second data signal through the error injection delay module to obtain the third data signal (which can effectively simulate the data jump error caused by electromagnetic interference and other problems in the physical layer and effectively simulate the transmission delay of the physical layer) and send it to the RDI component. Based on this, by monitoring the first data signal, the second data signal and the third data signal, the functional verification of the UCIe adaptation layer as the data sending end can be realized.

[0021] Similarly, the RDI component is also used to construct a fourth data signal from the physical layer; Correspondingly, the error injection delay module is further used to perform error injection and delay operations on the fourth data signal to obtain a fifth data signal and send it to the UCIe adaptation layer to be verified; The UCIe adaptation layer to be verified is further used to process the fifth data signal to obtain a sixth data signal and send the sixth data signal to the FDI component.

[0022] The UVM verification platform of the embodiment of the present application constructs the fourth data signal from the physical layer through the RDI component and performs error injection and delay operations on the fourth data signal through the error injection delay module to obtain the fifth data signal (which can effectively simulate the data jump error caused by electromagnetic interference and other problems in the physical layer and effectively simulate the transmission delay of the physical layer) and sends it to the UCIe adaptation layer to be verified. The UCIe adaptation layer to be verified processes the fifth data signal to obtain the sixth data signal and sends it to the FDI component. Based on this, by monitoring the fourth data signal, the fifth data signal and the sixth data signal, the functional verification of the UCIe adaptation layer as a data receiving end can be realized.

[0023] It can be understood that the FDI component and the RDI component are both components of the uvm_component type designed based on UVM.

[0024] Further, the error injection delay module includes a link error injection submodule and a link delay submodule connected to each other; The link error injection submodule is used to perform an error injection operation on the input signal; The link delay submodule is used to perform a delay operation on the input signal after the error injection operation is performed.

[0025] It can be understood that, when the UCIe adaptation layer acts as a data sending end, the input signal is the second data signal; when the UCIe adaptation layer acts as a data receiving end, the input signal is the fourth data signal.

[0026] The link error injection submodule includes a link signal input port, an error injection signal input port and a signal output port; The link signal input port is used to input a data signal (i.e., the aforementioned second data signal or fourth data signal) from the UCIe adaptation layer or RDI component to be verified; The error injection signal input port is used to input an error injection signal, and the signal output port is used to output a data signal after the error injection operation.

[0027] Figure 2This is a schematic diagram of the input and output signals of the link error injection submodule (i.e., error_inject) provided by this application, wherein input refers to the data signal from the UCIe adaptation layer or RDI component to be verified, and output refers to the data signal after the error injection operation. Figure 2 It is worth noting that the injection error signal includes injection error enable indication information (i.e. Figure 2 Injection error enable), injection error type indication information (i.e. Figure 2 The error type) and the error value indication information (i.e. Figure 2 The error injection value is an incorrect value). The error injection enable indication signal is used to enable the error injection operation. The error injection type indication information is used to indicate the error injection type, and the error injection type includes interval error injection and continuous error injection. For the situation where there are fewer error options, continuous error injection can be used. For the situation where there are many error options and they cannot be traversed, interval error injection can be used. Based on this, the efficiency and comprehensiveness of the simulation can be guaranteed. The error injection value indication information is used to indicate the value of the error injection. It can be understood that the error injection signals of the embodiments of the present application are all issued by components of the uvm_component type based on the UVM design. Based on this, by adjusting the error injection signal, the embodiments of the present application can arbitrarily adjust the error injection simulation use case.

[0028] Further, the link delay submodule includes a link signal input port, a reference clock input port, a delay control signal input port and a signal output port; The link signal input port is used to input the data signal after the error injection operation; The reference clock input port is used to input a delayed reference clock signal; The delay control signal input port is used to input a delay control signal; The signal output port is used to output the data signal after the delay operation.

[0029] Figure 3 is a schematic diagram of the specific structure of the link delay submodule provided in this application, such as Figure 3 As shown, the link delay submodule includes multiple cascaded delay models (i.e. Figure 3 delay0 to delayN) and a multiplexer connected to each delay model signal (i.e. Figure 3 middle mux); Each delay model is used to determine the delay reference clock signal (i.e. Figure 3 The cycle of cclk in the byte determines the delay amount, and based on the delay amount, the data signal after the injection error operation (i.e. Figure 3 Input data in) to perform delay operation; The multiplexer is used to control the delay signal (i.e. Figure 3The target delay model outputs the data signal after the delay operation (i.e. Figure 3 Output data in ).

[0030] It is understandable that the number of delay models (ie, N) can be determined according to actual needs, and the present application embodiment does not specifically limit this. The delay model can be constructed in advance through a generate statement, and the delay amount of the delay model is preferably an integer multiple of the delay reference clock signal period.

[0031] The delay control signal includes a delay value control variable, and the delay value control variable is used to indicate the delay value corresponding to the delay operation. Based on this, the multiplexer can determine the delay value corresponding to the delay operation based on the delay control signal, and then control the target delay model to output the data signal after the delay operation. It is worth noting that the delay value control variable is defined by a random variable macro. Specifically, by defining a valid variable in the package scope, making a random change to the valid variable, and then associating define with the valid variable, the random variable macro definition of the delay value control variable can be implemented, thereby achieving random changes in the delay value corresponding to the delay operation. Based on this, the coverage of the delay simulation can be guaranteed, thereby ensuring the comprehensiveness and accuracy of the UCIe adaptation layer function verification results.

[0032] The UVM verification platform of the UCIe adaptation layer provided in the embodiment of the present application includes: an FDI component, a UCIe adaptation layer to be verified, an error injection delay module and an RDI component; the FDI component is used to construct a first data signal from a protocol layer and send it to the UCIe adaptation layer to be verified; the UCIe adaptation layer to be verified is used to process the first data signal to obtain a second data signal; the error injection delay module is used to perform error injection and delay operations on the second data signal to obtain a third data signal and send it to the RDI component, which can simulate the link delay of the UCIe adaptation layer and construct an error injection scenario, and assist in the functional verification of the UCIe adaptation layer.

[0033] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0034] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, by hardware. Based on this understanding, the above technical solution can be essentially or in other words, the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as a ROM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0035] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A UVM verification platform for a UCIe adaptation layer, characterized in that: The platform includes: FDI component, UCIe adaptation layer to be verified, error injection delay module and RDI component; The FDI component is used to construct a first data signal from the protocol layer and send it to the UCIe adaptation layer to be verified; The UCIe adaptation layer to be verified is used to process the first data signal to obtain a second data signal; The error injection and delay module is used to perform error injection and delay operations on the second data signal to obtain a third data signal and send it to the RDI component.

2. The UVM verification platform of the UCIe adaptation layer according to claim 1, characterized in that, The RDI component is also used to construct a fourth data signal from the physical layer; Correspondingly, the error injection delay module is further used to perform error injection and delay operations on the fourth data signal to obtain a fifth data signal and send it to the UCIe adaptation layer to be verified; The UCIe adaptation layer to be verified is further used to process the fifth data signal to obtain a sixth data signal and send the sixth data signal to the FDI component.

3. The UVM verification platform of the UCIe adaptation layer according to claim 2, characterized in that, The FDI component and the RDI component are both components of the uvm_component type designed based on UVM.

4. The UVM verification platform of the UCIe adaptation layer according to claim 3, characterized in that, The error injection delay module comprises a link error injection submodule and a link delay submodule connected to each other; The link error injection submodule is used to perform an error injection operation on the input signal; The link delay submodule is used to perform a delay operation on the input signal after the error injection operation is performed.

5. The UVM verification platform of the UCIe adaptation layer according to claim 4, characterized in that, The link error injection submodule includes a link signal input port, an error injection signal input port and a signal output port; The link signal input port is used to input a data signal from a UCIe adaptation layer or an RDI component to be verified; The error injection signal input port is used to input an error injection signal, and the signal output port is used to output a data signal after the error injection operation.

6. The UVM verification platform of the UCIe adaptation layer according to claim 5, characterized in that: The error injection signal includes error injection enable indication information, error injection type indication information and error injection value indication information.

7. The UVM verification platform of the UCIe adaptation layer according to claim 6, characterized in that: The injection errors include interval injection errors and continuous injection errors.

8. The UVM verification platform of the UCIe adaptation layer according to claim 7, characterized in that: The link delay submodule includes a link signal input port, a reference clock input port, a delay control signal input port and a signal output port; The link signal input port is used to input the data signal after the error injection operation; The reference clock input port is used to input a delayed reference clock signal; The delay control signal input port is used to input a delay control signal; The signal output port is used to output the data signal after the delay operation.

9. The UVM verification platform of the UCIe adaptation layer according to claim 8, characterized in that: The link delay submodule includes a plurality of cascaded delay models and a multiplexer connected to the delay model signals; Each delay model is used to determine a respective delay amount based on the period of the delay reference clock signal, and to perform a delay operation on the data signal after the error injection operation based on the respective delay amount; The multiplexer is used to control the target delay model to output a data signal after the delay operation based on the delay control signal.

10. The UVM verification platform of the UCIe adaptation layer according to claim 9, characterized in that: The delay control signal includes a delay value control variable, and the delay value control variable is used to indicate a delay value corresponding to a delay operation, and the delay value control variable is defined by a random variable macro.

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