A training simulation method based on optical fiber with superimposed moving targets

Abstract

The present invention relates to the field of image processing and simulation technology, and discloses a training simulation method for superimposed moving targets based on optical fibers, wherein the training simulator comprises a first memory, a main processor, an editable logic gate array, a second memory, an optical switch, and optical fibers A, B, and C, wherein the first memory and the editable logic gate array are all connected to the main processor, the second memory and optical fibers A, B, and C are all connected to the editable logic gate array, the editable logic gate array is also connected to one side of the optical switch, and the other side of the optical switch is provided with a P1 port, a P1' port, a P2 port, a P2' port, a P3 port, and a P3' port, wherein the P1 port and the P1' port are connected to an image processing system, the P2 port and the P2' port are connected to a real detector, and the P3 port and the P3' port are connected to the editable logic gate array. The present invention realizes the ability of seamless switching between the simulator and the real detector, supporting multi-channel video output, and dynamically embedding a controllable moving target in a simulated video through a simulation method for superimposed moving targets.

Description

Technical Field

[0001] The invention relates to the technical field of image processing and simulation, and in particular to an optical fiber-based training simulation method capable of superimposing moving targets. Background Art

[0002] In the development and debugging of image processing systems, performance verification of installed detectors and functional testing of back-end equipment are key links to ensure the overall performance of the system. In view of the limited lifespan and long-term operating loss of high-end sensor components such as refrigerated infrared detectors, continuous testing using directly installed detectors is not only costly, but also not conducive to the long-term maintenance strategy of the equipment. Therefore, the development of an image signal simulator that combines high-fidelity simulation with flexible configuration is of far-reaching significance for optimizing the test process, reducing test costs, and improving test efficiency.

[0003] A Zynq-based image frame rate controllable simulator and method with announcement number CN116456093B achieves flexible frame rate adjustment by leveraging the powerful processing capabilities of Zynq devices. However, most of these simulators are pure software or hardware simulation environments, and the switching of installed detectors requires complex hardware circuit operations, which is not only cumbersome to operate, but also increases the difficulty of system integration and maintenance, limiting the rapid switching and flexible deployment of the test environment. In addition, this type of simulator usually only supports a single video stream output and lacks the ability to dynamically embed controllable moving targets in simulated videos, making it difficult to fully meet the performance evaluation requirements of advanced algorithms such as back-end tracking and recognition.

[0004] In addition, a dual-channel infrared scene simulator device with announcement number CN110376732A focuses on generating targets and backgrounds with complex infrared radiation characteristics and thermal images based on theoretical models. It can simulate infrared scenes under different meteorological conditions and radiation backgrounds, and effectively evaluate the imaging performance of infrared detection and sensing equipment. However, the core purpose of this solution is to detect and evaluate the imaging capabilities of front-end detection equipment, rather than functional verification and performance verification of back-end processing systems. Therefore, its design does not consider the need to bypass the actual detector and directly provide analog signals to the back-end equipment, so it cannot be directly used for comprehensive testing and verification of advanced algorithms such as back-end tracking and recognition.

[0005] In summary, the existing technology still has obvious deficiencies in achieving seamless switching between simulators and real detectors, supporting multi-channel video output, and generating controllable moving targets, and it is difficult to meet the needs of comprehensive and efficient testing of image processing systems. Therefore, it is particularly important to develop a new training simulator that can overcome these deficiencies. Summary of the invention

[0006] In view of this, the present invention aims to address the deficiencies in the prior art, and its main purpose is to provide an optical fiber-based training simulation method for superimposed moving targets, which solves the technical problems in the prior art of difficulty in seamless switching between simulators and actual detectors, lack of support for multi-channel video output, and lack of ability to dynamically embed controllable moving targets in simulated videos.

[0007] To achieve the above purpose, the present invention adopts the following technical solutions:

[0008] The present invention discloses a training simulation method for a superimposable moving target based on optical fiber, which is used for a training simulator for a superimposable moving target based on optical fiber. The training simulator comprises a first memory, a main processor, an editable logic gate array, a second memory, an optical switch and optical fibers A, B and C. The first memory and the editable logic gate array are all connected to the main processor, the second memory and the optical fibers A, B and C are all connected to the editable logic gate array, the editable logic gate array is also connected to one side of the optical switch through an input and output interface, the other side of the optical switch is provided with a P1 port, a P1' port, a P2 port, a P2' port, a P3 port and a P3' port, the P1 port and the P1' port are output ports of the optical switch and are connected to an image processing system, the P2 port and the P2' port are connected to a mounted detector, the P3 port is connected to the editable logic gate array through an optical fiber A, the P3' port is connected to the editable logic gate array through an optical fiber B, and the optical fiber C is also connected to a control terminal;

[0009] The training simulation method comprises the following steps:

[0010] S01, a step of presetting a target model in the main processor;

[0011] S02, a step of recording a simulated image and storing it in the first memory;

[0012] S03, the step of the control terminal issuing a control command;

[0013] S04, the editable logic gate array receives the control command and determines whether it is in simulation mode, if not, proceeding to step S05, otherwise, proceeding to step S06;

[0014] S05, switching the optical switch to communicate with the installed detector, and the installed detector records the installed video and transmits it to the image processing system through the optical switch;

[0015] S06, the editable logic gate array transmits the control command to the main processor, the main processor receives and parses the control command, reads and adjusts the simulation image from the first memory, and sends the adjusted simulation image to the editable logic gate array;

[0016] S07, the main processor determines whether to superimpose the target, if not, then go to step S08, otherwise, then go to step S09;

[0017] S08, returning to step S04;

[0018] S09, the main processor further parses the control command, obtains target type information, target size information and target motion mode, extracts the preset target model that matches the target type information and target size information, and based on the target motion mode, calculates the position of the target model in each frame of the simulated image, and then performs superposition of the target model, generates a superposition image set, and sends the superposition image set to the editable logic gate array;

[0019] S10, the editable logic gate array transmits the superimposed image set to the second memory, the second memory caches and reads the superimposed image set, and adjusts the timing of the read superimposed image set based on the timing of the installed detector to generate a simulated video;

[0020] S11, the editable logic gate array reads and packages the analog video in the second memory, and transmits the analog video to the image processing system.

[0021] As a preferred solution, the first memory is a non-volatile memory, the installed detector is also used to record the simulated image, the main processor stores the simulated image recorded by the installed detector in the first memory through an embedded multimedia card interface, and the second memory is a double-rate synchronous dynamic random access memory, which is used for caching and timing adjustment of the superimposed image set.

[0022] As a preferred solution, the first memory is EMMC, the second memory is DDR, the editable logic gate array is FPGA, the main processor is SOC, and the optical switch is a dual-way two-choice switch.

[0023] As a preferred solution, the editable logic gate array receives the control command through the optical fiber C, and transmits the control command to the main processor through a serial port.

[0024] As a preferred solution, the main processor transmits any one of the analog image and the superimposed image set to the editable logic gate array through an interconnection bus.

[0025] As a preferred solution, the interconnection bus is any one of MIPI and PCIe.

[0026] As a preferred solution, the editable logic gate array controls the optical switch to switch the video source through the input and output interface, and the input and output interface includes a high level state and a low level state;

[0027] When the input / output interface is in the high level state, the P1 port and the P1' port are connected to the P2 port and the P2' port respectively, and the installed video is output;

[0028] When the input-output interface is in the low level state, the P1 port and the P1' port are respectively connected to the P3 port and the P3' port to output the analog video.

[0029] As a preferred solution, the image processing system is used to receive and process the installed video and the analog video, and the editable logic gate array sends the analog video to the optical switch through the optical fiber A and the optical fiber B.

[0030] As a preferred solution, the image processing system is provided with a fiber optic transmission protocol, and the editable logic gate array is provided with a GTX resource inside. The editable logic gate array packets the analog video based on the fiber optic transmission protocol, and converts the parallel video data of the analog video into high-speed differential data through the GTX resource and sends it to the optical switch. The editable logic gate array also receives and parses the control command through the GTX resource to determine the analog state.

[0031] As a preferred solution, based on step S06, the following steps are included:

[0032] S601, the editable logic gate array transmits the control command to the main processor;

[0033] S602, the main processor receives and analyzes the control command to obtain image frame information and image frame rate information required to be presented;

[0034] S603, the main processor reads the simulated image from the first memory, adjusts the image based on the image frame information and the image frame rate information, and feeds back the adjusted image to the editable logic gate array.

[0035] Compared with the prior art, the present invention has obvious advantages and beneficial effects. Specifically, it can be seen from the above technical solution that it mainly improves the seamless switching capability between the training simulator and the actual detector by adopting an optical fiber-based signal transmission method and a simulation method that can superimpose moving targets, and combines a high-performance processing unit, thereby reducing the complexity of system integration and the difficulty of maintenance. At the same time, by utilizing multi-channel video output technology, parallel testing of multiple back-end devices in the same test environment is realized, which significantly improves the test efficiency. In addition, by integrating a dynamic motion target generation module, controllable moving targets can be embedded in the simulated video in real time, thereby meeting the testing requirements of complex scenes and dynamic targets for advanced algorithms such as back-end tracking and recognition. It not only overcomes the shortcomings of the prior art in seamless switching, multi-channel video output and dynamic motion target generation, but also significantly improves the comprehensiveness and efficiency of image processing system testing.

[0036] In order to more clearly illustrate the structural features and effects of the present invention, the present invention is described in detail below in conjunction with the accompanying drawings and specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 It is a flow chart of a training simulation method for superimposed moving targets based on optical fiber according to an embodiment of the present application;

[0038] Figure 2 This is a workflow diagram of a training simulator based on optical fiber and capable of superimposing moving targets according to an embodiment of the present application;

[0039] Figure 3 It is a structural block diagram of a training simulator based on optical fiber and capable of superimposing moving targets according to an embodiment of the present application;

[0040] Figure 4 It is a diagram of the optical path relationship of the optical switch of the embodiment of the present application. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and implementation examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0042] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

[0043] See also Figures 1 to 4The embodiment of the present invention provides a training simulation method for a superimposable moving target based on optical fiber, which is used for a training simulator for a superimposable moving target based on optical fiber. The training simulator includes a first memory, a main processor, an editable logic gate array, a second memory, an optical switch and optical fibers A, B, and C. The first memory and the editable logic gate array are all connected to the main processor, the second memory and the optical fibers A, B, and C are all connected to the editable logic gate array, the editable logic gate array is also connected to one side of the optical switch through an input and output interface, and the other side of the optical switch is provided with a P1 port, a P1' port, a P2 port, a P2' port, a P3 port, and a P3' port. The P1 port and the P1' port are output ports of the optical switch and are connected to an image processing system, the P2 port and the P2' port are connected to a mounted detector, the P3 port is connected to the editable logic gate array through an optical fiber A, the P3' port is connected to the editable logic gate array through an optical fiber B, and the optical fiber C is also connected to a control terminal.

[0044] The training simulation method includes the following steps:

[0045] S01, a step of presetting a target model in a main processor.

[0046] It is convenient to superimpose the target model according to the control command later, so as to enhance the realism of the simulation video and the test effect.

[0047] S02, a step of recording a simulated image and storing it in a first memory.

[0048] Provide basic image data for the subsequent generation of simulation videos to ensure the diversity and flexibility of simulation videos.

[0049] S03, the step of the control terminal issuing a control command.

[0050] The control commands are used to control the running status of the training simulator and the generation of simulation videos, thus realizing the automation and intelligence of the test process.

[0051] S04, the editable logic gate array receives the control command and determines whether it is in the simulation state. If not, it proceeds to step S05, otherwise, it proceeds to step S06.

[0052] Realize seamless switching between training simulators and actual detectors to improve test efficiency and flexibility.

[0053] S05, switching the optical switch to connect with the installed detector, the installed detector records the installed video and transmits it to the image processing system through the optical switch.

[0054] Used to verify the processing power and performance of backend devices.

[0055] S06, the editable logic gate array transmits the control command to the main processor, the main processor receives and parses the control command, reads and adjusts the simulation image from the first memory, and sends the adjusted simulation image to the editable logic gate array.

[0056] Realize dynamic adjustment and real-time update of simulation images.

[0057] S07, the main processor determines whether to superimpose the target, if not, it goes to step S08, otherwise, it goes to step S09.

[0058] Flexibly choose whether to superimpose targets based on test requirements to improve the pertinence and accuracy of the test.

[0059] S08, return to step S04, continue to receive control commands and determine the state of the training simulator to achieve continuity and stability of the test process.

[0060] S09, the main processor further parses the control command, obtains the target type information, target size information and target motion mode, extracts the preset target model that matches the target type information and target size information, and solves the position of the target model in each frame of the simulated image based on the target motion mode, and then performs the superposition of the target model, generates a superimposed image set, and sends the superimposed image set to the editable logic gate array. The function of dynamically embedding a controllable moving target in the simulated video is realized, and the comprehensiveness and fidelity of the test are improved.

[0061] S10, the editable logic gate array transmits the superimposed image set to the second memory, the second memory caches and reads the superimposed image set, and adjusts the timing of the read superimposed image set based on the timing of the installed detector to generate a simulated video. Ensure that the timing of the simulated video is consistent with the installed detector, improve the accuracy and reliability of the test, facilitate the switching between the installed detector and the training simulator, and improve the real-time performance.

[0062] S11, the editable logic gate array reads and packages the analog video in the second memory and transmits it to the image processing system. It is used for performance verification and functional testing of back-end equipment to realize automation and intelligence of the test process.

[0063] In this embodiment, the first memory is a non-volatile memory. The non-volatile memory has the characteristic of persistent data storage, which can ensure that the recorded image will not be lost even in the event of a power outage. The installed detector is also used to record simulated images to provide actual image data as a reference or comparison for the simulation. The main processor efficiently and stably stores the simulated image recorded by the installed detector in the first memory through an embedded multimedia card interface, namely, an EMMC interface, to achieve fast data writing and long-term storage. The second memory is a double-rate synchronous dynamic random access memory, which, with its high-speed data reading and writing capabilities and large-capacity storage space, is used for caching and timing adjustment of superimposed image sets, to ensure that the simulated video can undergo necessary processing and optimization before being transmitted to the image processing system, thereby improving the real-time and accuracy of the test.

[0064] Specifically, the first memory is EMMC, which has high integration and low power consumption, and is suitable for storing a large amount of image data. The second memory is DDR, and its high-speed data transmission rate and low latency characteristics can meet the needs of real-time processing of simulated video. The editable logic gate array is FPGA, which can efficiently receive, process and transmit control commands and image data with its flexible logic programming ability and powerful parallel processing ability, and realize complex simulated video generation and dynamic target overlay functions. The main processor is SOC, which integrates multiple functional units such as CPU and GPU, and can efficiently process image data and control commands to realize the intelligent and automatic operation of the simulator. The optical switch is a dual-channel two-choice switch, which can quickly switch the input / output port as needed, realize seamless switching between the simulator and the installed detector, and improve the flexibility and efficiency of the test.

[0065] The editable logic gate array receives control commands at high speed and stability through optical fiber C, and transmits the control commands to the main processor through the serial port, a standard communication interface, to achieve reliable transmission and timely processing of control commands.

[0066] The main processor transmits any one of the analog image and superimposed image set to the editable logic gate array through the interconnection bus, which is an efficient data transmission channel, to achieve rapid processing and transmission of image data.

[0067] The interconnect bus is either MIPI or PCIe. Both bus standards have the characteristics of high bandwidth and low latency, which can meet the high requirements of analog video data transmission and ensure the real-time and accuracy of the test.

[0068] Furthermore, the editable logic gate array accurately controls the optical switch to switch the video source through the input and output interface. The input and output interface includes a high level state and a low level state. These two states correspond to different video output paths, respectively, thereby realizing flexible selection and switching of the video source. The input and output interface is GPIO.

[0069] When the input and output interface is in a high level state, the P1 port and the P1' port are connected to the P2 port and the P2' port respectively, and the installed video is output to the image processing system for actual performance testing and verification of the back-end equipment.

[0070] When the input and output interface is in a low level state, the P1 port and the P1' port are connected to the P3 port and the P3' port respectively, and the analog video is output to the image processing system to simulate the test scene and verify the processing performance of the back-end equipment.

[0071] The image processing system has powerful video processing capabilities, which is used to receive and efficiently process the installed video and simulated video from the optical switch to ensure the accuracy and reliability of the test results. In addition, in order to achieve high-speed and stable transmission of analog video, the editable logic gate array sends the packaged analog video to the optical switch through optical fiber A and optical fiber B.

[0072] Furthermore, the image processing system is equipped with a fiber transmission protocol to ensure lossless transmission and efficient processing of video data. The editable logic gate array is equipped with GTX resources. The editable logic gate array packages the analog video based on the fiber transmission protocol, and converts the video data of the parallel analog video into high-speed differential data and sends it to the optical switch through the GTX resources to meet the high requirements of fiber transmission. This conversion process ensures the integrity and accuracy of the analog video data and improves the stability and efficiency of video transmission. The editable logic gate array also receives and parses the control commands through the GTX resources to quickly determine whether the training simulator is in the simulation state.

[0073] In addition, based on step S06, the following steps are included:

[0074] S601, the step of the editable logic gate array transmitting the control command to the main processor.

[0075] This step ensures the timely delivery of control information and provides key instructions for subsequent processing.

[0076] S602, the main processor receives and parses the control command to obtain image frame information and image frame rate information required to be presented.

[0077] Image size information and image frame rate information are crucial to the generation of simulated videos. They determine the size and playback smoothness of the simulated videos, thereby ensuring the authenticity and accuracy of the test scenes.

[0078] S603, the main processor reads the analog image from the first memory, adjusts the image based on the image size information and the image frame rate information, and feeds back to the editable logic gate array.

[0079] In this step, image adjustments include size scaling, frame rate matching, etc. to ensure that the simulated video meets the test requirements, and the feedback to the editable logic gate array is prepared for subsequent image overlay and output. The implementation of this step not only improves the flexibility of the simulated video, but also ensures the reliability and accuracy of the test results.

[0080] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A training simulation method for a superimposable moving target based on optical fiber, used for a training simulator for a superimposable moving target based on optical fiber, characterized in that: The training simulator includes a first memory, a main processor, an editable logic gate array, a second memory, an optical switch and optical fibers A, B and C. The first memory and the editable logic gate array are connected to the main processor, the second memory and optical fibers A, B and C are connected to the editable logic gate array, the editable logic gate array is also connected to one side of the optical switch through an input and output interface, the other side of the optical switch is provided with a P1 port, a P1' port, a P2 port, a P2' port, a P3 port and a P3' port, the P1 port and the P1' port are output ports of the optical switch and are connected to an image processing system, the P2 port and the P2' port are connected to a mounted detector, the P3 port is connected to the editable logic gate array through an optical fiber A, the P3' port is connected to the editable logic gate array through an optical fiber B, and the optical fiber C is also connected to a control terminal; The training simulation method comprises the following steps: S01, a step of presetting a target model in the main processor; S02, a step of recording a simulated image and storing it in the first memory; S03, the step of the control terminal issuing a control command; S04, the editable logic gate array receives the control command and determines whether it is in simulation mode, if not, proceeding to step S05, otherwise, proceeding to step S06; S05, switching the optical switch to communicate with the mounting detector, and the mounting detector generates and records the mounting video and transmits it to the image processing system through the optical switch; S06, the editable logic gate array transmits the control command to the main processor, the main processor receives and parses the control command, reads and adjusts the simulation image from the first memory, and sends the adjusted simulation image to the editable logic gate array; S07, the main processor determines whether to superimpose the target, if not, then go to step S08, otherwise, then go to step S09; S08, returning to step S04; S09, the main processor further parses the control command, obtains target type information, target size information and target motion mode, extracts the preset target model that matches the target type information and target size information, and based on the target motion mode, calculates the position of the target model in each frame of the simulated image, and then performs superposition of the target model, generates a superposition image set, and sends the superposition image set to the editable logic gate array; S10, the editable logic gate array transmits the superimposed image set to the second memory, the second memory caches and reads the superimposed image set, and adjusts the timing of the read superimposed image set based on the timing of the installed detector to generate a simulated video; S11, the editable logic gate array reads and packages the analog video in the second memory, and transmits the analog video to the image processing system.

2. The optical fiber-based superimposed moving target training simulation method according to claim 1, characterized in that: The first memory is a non-volatile memory, the installed detector is also used to record the simulated image, the main processor stores the simulated image recorded by the installed detector in the first memory through the embedded multimedia card interface, and the second memory is a double-rate synchronous dynamic random access memory, which is used for caching and timing adjustment of the superimposed image set.

3. The optical fiber-based superimposed moving target training simulation method according to claim 1, characterized in that: The first memory is EMMC, the second memory is DDR, the editable logic gate array is FPGA, the main processor is SOC, and the optical switch is a dual-way two-choice switch.

4. The optical fiber-based superimposable moving target training simulation method according to claim 1, characterized in that: The editable logic gate array receives the control command through the optical fiber C, and transmits the control command to the main processor through the serial port.

5. The optical fiber-based superimposed moving target training simulation method according to claim 1, characterized in that: The main processor transmits any one of the analog image and the superimposed image set to the editable logic gate array through an interconnection bus.

6. The optical fiber-based superimposed moving target training simulation method according to claim 5, characterized in that: The interconnect bus is any one of MIPI and PCIe.

7. The optical fiber-based superimposed moving target training simulation method according to claim 1, characterized in that: The editable logic gate array controls the optical switch to switch the video source through the input and output interface, and the input and output interface includes a high level state and a low level state; When the input / output interface is in the high level state, the P1 port and the P1' port are connected to the P2 port and the P2' port respectively, and the installed video is output; When the input-output interface is in the low level state, the P1 port and the P1' port are respectively connected to the P3 port and the P3' port to output the analog video.

8. The optical fiber-based superimposed moving target training simulation method according to claim 1, characterized in that: The image processing system is used to receive and process the installed video and the analog video, and the editable logic gate array sends the analog video to the optical switch through the optical fiber A and the optical fiber B.

9. The optical fiber-based superimposed moving target training simulation method according to claim 1, characterized in that: The image processing system is provided with a fiber optic transmission protocol, and the editable logic gate array is provided with a GTX resource inside. The editable logic gate array packets the analog video based on the fiber optic transmission protocol, and converts the parallel video data of the analog video into high-speed differential data through the GTX resource and sends it to the optical switch. The editable logic gate array also receives and parses the control command through the GTX resource to determine the analog state.

10. The optical fiber-based superimposed moving target training simulation method according to claim 1, based on step S06, is characterized in that: The following steps are involved: S601, the editable logic gate array transmits the control command to the main processor; S602, the main processor receives and analyzes the control command to obtain image frame information and image frame rate information required to be presented; S603, the main processor reads the simulated image from the first memory, adjusts the image based on the image frame information and the image frame rate information, and feeds back the adjusted image to the editable logic gate array.

Images