Semiconductor structure and preparation method thereof

Abstract

The invention provides a semiconductor structure and a preparation method thereof, and relates to the field of semiconductors. The semiconductor structure comprises a substrate and isolation structures, the substrate is provided with a plurality of active regions which are arranged at intervals in an array mode, and the isolation structures are located between the adjacent active regions; the defect concentration of at least part of one side of the isolation structure close to the top surface of the substrate is smaller than that of at least part of one side of the isolation structure away from the top surface of the substrate. According to the invention, the possibility of electric leakage of the semiconductor structure is reduced, and the storage performance of the memory is ensured.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory that can write and read data randomly at high speed and is widely used in data storage devices or apparatuses.

[0003] The substrate of a DRAM includes a plurality of active regions spaced apart from each other, and a shallow trench isolation (STI) structure for isolating adjacent active regions.

[0004] However, the above shallow trench isolation structure has a hot electron induced punch through (HEIP) effect, which is prone to leakage, thereby affecting the storage performance of the memory. Summary of the invention

[0005] The present invention provides a semiconductor structure and a preparation method thereof, which are used to solve the problem that a shallow trench isolation structure has a hot carrier penetration effect, is prone to leakage, and causes damage to electronic devices such as memory.

[0006] In a first aspect, the present disclosure provides a semiconductor structure, comprising a substrate and an isolation structure, wherein the substrate has a plurality of active regions spaced apart and arranged in an array, and the isolation structure is located between adjacent active regions;

[0007] The defect concentration of at least a portion of the isolation structure on a side close to the substrate top surface is smaller than the defect concentration of at least a portion of the isolation structure on a side away from the substrate top surface.

[0008] In the above semiconductor structure, optionally, the substrate is provided with a trench, and the isolation layer includes a first isolation layer, a second isolation layer and a third isolation layer which are stacked;

[0009] Part of the first isolation layer covers the bottom of the trench, and the remaining part of the first isolation layer covers the sidewall of the trench;

[0010] The second isolation layer comprises a first isolation portion and a second isolation portion connected to each other, the first isolation portion and the second isolation portion both cover a portion of the first isolation layer located on the sidewall of the trench, and the second isolation portion is located at an end of the first isolation portion away from the bottom of the trench, and the defect concentration of the second isolation portion is lower than the defect concentration of the first isolation portion;

[0011] One end of the third isolation layer facing the bottom of the trench covers the first isolation layer, and the third isolation layer covers a surface of the second isolation layer facing away from the first isolation layer.

[0012] In the above semiconductor structure, optionally, the material of the first isolation portion and the material of the second isolation portion are both set to nitride, and the second isolation portion is obtained by high-pressure annealing in a deuterium gas environment and post-annealing.

[0013] In the above semiconductor structure, optionally, along the thickness direction of the substrate, a ratio of the length of the first isolation portion to the depth of the trench is greater than or equal to 0.1 and less than or equal to 0.5.

[0014] In the above semiconductor structure, optionally, the first isolation layer and the third isolation layer are made of the same material, which is oxide.

[0015] In a second aspect, the present disclosure provides a method for preparing a semiconductor structure, comprising:

[0016] Providing a substrate, the substrate comprising a plurality of active regions arranged in an interval array;

[0017] forming an isolation structure, wherein the isolation structure is located in the substrate and between adjacent active regions;

[0018] The defect concentration of at least a portion of the isolation structure on a side close to the substrate top surface is smaller than the defect concentration of at least a portion of the isolation structure on a side away from the substrate top surface.

[0019] In the above-mentioned method for preparing a semiconductor structure, optionally, the isolation structure includes a first isolation layer, a second isolation layer and a third isolation layer which are stacked; forming the isolation structure includes:

[0020] forming a trench in the substrate, wherein the trench is located between adjacent active regions;

[0021] forming the first isolation layer, wherein a portion of the first isolation layer covers the bottom of the trench, and the remaining portion of the first isolation layer covers the sidewall of the trench;

[0022] The second isolation layer is formed, wherein the second isolation layer includes a first isolation portion and a second isolation portion connected to each other, wherein the first isolation portion and the second isolation portion both cover a portion of the first isolation layer located on the side wall of the trench, and the second isolation portion is located at an end of the first isolation portion away from the bottom of the trench, and the defect concentration of the second isolation portion is lower than the defect concentration of the first isolation portion; the third isolation layer is formed, wherein the end of the third isolation layer facing the bottom of the trench covers the first isolation layer, and the third isolation layer covers a surface of the second isolation layer away from the first isolation layer.

[0023] In the above-mentioned method for preparing a semiconductor structure, optionally, forming the second isolation layer includes:

[0024] forming a second isolation material layer, wherein the second isolation material layer covers a surface of the first isolation layer facing away from the substrate;

[0025] The second isolation material layer on the surface of the first isolation layer at the bottom of the trench is removed, and the second isolation material layer on the surface of the first isolation layer at the sidewall of the trench is retained.

[0026] In the above method for preparing a semiconductor structure, optionally, forming the second isolation layer and the third isolation layer includes:

[0027] forming a third isolation material layer, wherein the third isolation material layer fills the groove formed by the second isolation material layer and a portion of the first isolation layer; a portion of the third isolation material layer close to the bottom of the groove abuts against the first isolation layer;

[0028] Etching back a portion of the thickness of the third isolation material layer to expose a portion of the second isolation material layer located on the sidewall of the trench, the remaining portion of the third isolation material layer forming a first portion of the third isolation layer, and the second isolation material layer covered by the first portion forming a first isolation portion;

[0029] processing the second isolation material layer exposed by the first portion to form the second isolation portion;

[0030] A fourth isolation material layer is formed, the fourth isolation material layer fills the groove surrounded by the top surface of the first portion and the side surface of the second isolation material layer, and the fourth isolation material layer forms the second portion of the third isolation layer.

[0031] In the above method for preparing a semiconductor structure, optionally, processing the second isolation material layer exposed by the first portion includes:

[0032] The second isolation material layer is nitride, and is subjected to high pressure annealing in a deuterium gas environment, and then subjected to post-annealing treatment on the second isolation material layer;

[0033] And / or, the third isolation material layer and the fourth isolation material layer are made of the same material, which is oxide.

[0034] The present disclosure provides a semiconductor structure and a method for preparing the same, wherein a plurality of active regions arranged in an array of intervals and an isolation structure located between adjacent active regions are provided in the semiconductor structure, so that different active regions are isolated by the isolation structure to avoid electrical interference between the active regions. The defect concentration of at least a portion of the isolation structure close to the top surface of the substrate is less than the defect concentration of at least a portion of the isolation structure away from the top surface of the substrate.

[0035] In this way, the possibility of hot carriers being captured at the bottom of the isolation structure can be made greater than the possibility of hot carriers being captured at the top of the isolation structure, thereby reducing the possibility of hot carriers in the substrate being captured by the top of the isolation structure to form an electron accumulation region, preventing the formation of a hole accumulation region corresponding to the electron accumulation region in the active region, and reducing the possibility of hot carriers in the substrate accumulating at the top of the isolation structure, reducing the possibility of the HEIP effect occurring in the semiconductor structure, and reducing the possibility of leakage in the semiconductor structure, thereby improving the yield of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0037] Figure 1 is a schematic diagram of the structure of a silicon nitride layer and a source / drain region;

[0038] Figure 2 A schematic structural diagram of a semiconductor structure including a gate layer and a gate dielectric layer provided in an embodiment of the present disclosure;

[0039] Figure 3 A schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure;

[0040] Figure 4 A schematic flow chart of a method for preparing a semiconductor junction is provided for an embodiment of the present disclosure;

[0041] Figure 5 A schematic structural diagram of a substrate with grooves provided in an embodiment of the present disclosure;

[0042] Figure 6 A schematic diagram of a structure for forming a first isolation layer provided in an embodiment of the present disclosure;

[0043] Figure 7A schematic diagram of a structure for forming a second isolation material layer provided in an embodiment of the present disclosure;

[0044] Figure 8 A schematic diagram of a structure in which a portion of the second isolation material layer located on the sidewall of the trench is retained according to an embodiment of the present disclosure;

[0045] Fig. 9 A schematic diagram of a structure for forming a third isolation material layer provided in an embodiment of the present disclosure;

[0046] Fig.10 A schematic diagram of the structure of the third isolation material layer with a portion of the third isolation material layer etched back provided in an embodiment of the present disclosure;

[0047] Fig.11 A schematic diagram of a structure for forming a first isolation portion and a second isolation portion provided in an embodiment of the present disclosure;

[0048] Fig.12 A schematic diagram of defect concentration of nitride materials provided by an embodiment of the present disclosure;

[0049] Fig.13 A schematic diagram of the structure for forming a third isolation layer provided in an embodiment of the present disclosure.

[0050] Description of reference numerals:

[0051] 1. Silicon nitride layer; 2. Source / drain region;

[0052] 100, substrate;

[0053] 110, active region; 111, first active region; 112, second active region; 113, gate layer; 114, gate dielectric layer; 120, trench;

[0054] 200. Isolation structure;

[0055] 210, first isolation layer; 220, second isolation layer; 221, first isolation portion; 222, second isolation portion; 223, second isolation material layer; 230, third isolation layer; 231, first portion; 232, second portion; 233, third isolation material layer.

[0056] The above drawings show clear embodiments of the present disclosure, which will be described in more detail below. These drawings and text descriptions are not intended to limit the scope of the present disclosure in any way, but to illustrate the concepts of the present disclosure to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0057] In the substrate of the DRAM device, a plurality of source / drain regions are arranged at intervals, an isolation region is provided between adjacent source / drain regions, and an isolation structure is provided in the isolation region to block adjacent source / drain regions and avoid electrical interference between adjacent source / drain regions. The isolation structure of the source / drain region is often prepared by a shallow trench isolation process (STI for short). The isolation structure includes a plurality of isolation layers stacked in layers, and the isolation layers include a silicon nitride layer.

[0058] The source / drain region 2 and the silicon nitride layer 1 of the isolation structure are spaced apart, and an isolation layer may be disposed between the two (the isolation layer between the source / drain region 2 and the isolation structure is not shown in the figure). Figure 1 The hot carriers in the source / drain region 2 will be captured by the silicon nitride layer 1 located at the side wall position of the source / drain region 2, so that an electron accumulation region is formed in the silicon nitride layer 1, and a hole accumulation region corresponding to the electron accumulation region is formed at the side wall position of the source / drain region 2. For example, in a P-channel metal oxide semiconductor structure (PMOS) in which holes are the main carriers, when the semiconductor structure is in a working state, hot carriers will continue to accumulate on the top of the isolation structure, thereby making the semiconductor structure prone to HEIP effect, which reduces the channel length of the semiconductor structure and increases the leakage current, resulting in leakage problems, leading to poor DRAM devices.

[0059] During the research process, it was found that increasing the amount of hot carriers captured at the bottom of the isolation structure can effectively alleviate the above-mentioned HEIP effect; increasing the amount of hot carriers captured at the bottom of the isolation structure can reduce the possibility of electron accumulation areas and hole accumulation areas formed between the top of the isolation structure and the source / drain region 2, and reduce the possibility of hot carriers accumulating at the top of the isolation structure. In this way, the HEIP effect can be alleviated, leakage problems can be avoided or alleviated, and the yield of DRAM devices can be improved.

[0060] In view of this, the present disclosure provides a semiconductor structure and a method for preparing the same, wherein a plurality of active regions arranged in an array of intervals and an isolation structure located between adjacent active regions are provided in a substrate of the semiconductor structure, so that different active regions are isolated by the isolation structure to avoid electrical interference between the active regions. The defect concentration of at least a portion of the isolation structure close to the top surface of the substrate is less than the defect concentration of at least a portion of the isolation structure away from the top surface of the substrate.

[0061] In this way, the possibility of hot carriers being captured at the bottom of the isolation structure can be made greater than the possibility of hot carriers being captured at the top of the isolation structure, thereby reducing the possibility of hot carriers in the substrate being captured by the top of the isolation structure to form an electron accumulation region, preventing the formation of a hole accumulation region corresponding to the electron accumulation region in the active region, reducing the possibility of breakdown between the two, reducing the possibility of HEIP effect in semiconductor devices, and reducing the possibility of leakage in the semiconductor structure, thereby improving the yield of the semiconductor structure.

[0062] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0063] The technical solution of the present invention and how the technical solution of the present invention solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present invention will be described below in conjunction with the accompanying drawings.

[0064] Reference Figure 2 and Figure 3 As shown, in the first aspect, an embodiment of the present disclosure provides a semiconductor structure, including a substrate 100 and an isolation structure 200, wherein the substrate 100 includes a plurality of active areas 110 arranged in an interval array, and the isolation structure 200 is located in the substrate 100 and between adjacent active areas 110, so as to isolate different active areas 110 through the isolation structure 200, thereby reducing the possibility of electrical interference between the active areas 110.

[0065] The defect concentration of at least a portion of the isolation structure 200 on a side close to the top surface of the substrate 100 is lower than the defect concentration of at least a portion of the isolation structure 200 on a side away from the top surface of the substrate 100. The possibility of at least a portion of the isolation structure 200 on a side away from the top surface of the substrate 100 capturing hot carriers is greater than the possibility of at least a portion of the isolation structure 200 on a side close to the top surface of the substrate 100 capturing hot carriers.

[0066] The substrate 100 can provide a support base for the structural layer disposed on the substrate 100. The material of the substrate 100 can be single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium compound or silicon-on-insulator (SOI), etc., or other materials known to those skilled in the art.

[0067] The substrate 100 includes an active region 110 . The active region 110 may be formed by ion doping. The active region 110 may be a source region and / or a drain region. The present embodiment does not limit the type of the active region 110 .

[0068] There may be multiple active regions 110, and the multiple active regions 110 may be arranged in an array in the substrate 100. A trench 120 may be provided in the substrate 100 on one side of the active region 110, and the trench 120 may serve as a structural basis for the subsequent formation of an isolation structure 200. Alternatively, the trench 120 may also be located between two adjacent active regions 110, so that the isolation structure 200 located in the trench 120 may be used to electrically isolate the two adjacent active regions 110, thereby reducing the possibility of electrical interference between the two adjacent active regions 110.

[0069] Reference Figure 3 As shown, as a feasible implementation, the isolation structure 200 is stacked with a first isolation layer 210, a second isolation layer 220 and a third isolation layer 230; wherein, part of the first isolation layer 210 covers the bottom of the groove 120, and the remaining part of the first isolation layer 210 covers the side wall of the groove 120; the second isolation layer 220 covers the first isolation layer 210 located on the side wall of the groove 120; the third isolation layer 230 covers the first isolation layer 210 at one end toward the bottom of the groove 120, and the third isolation layer 230 covers the surface of the second isolation layer 220 away from the first isolation layer 210.

[0070] Exemplarily, the second isolation layer 220 includes a first isolation portion 221 and a second isolation portion 222 that are connected to each other, the first isolation portion 221 and the second isolation portion 222 both cover a portion of the first isolation layer 210 located on the side wall of the trench 120, and the second isolation portion 222 is located at an end of the first isolation portion 221 that is away from the bottom of the trench 120, and the defect concentration of the second isolation portion 222 is lower than the defect concentration of the first isolation portion 221, so that the possibility of the first isolation portion 221 capturing hot carriers is greater than the possibility of the second isolation portion 222 capturing hot carriers.

[0071] One end of the first isolation portion 221 facing the bottom of the groove 120 contacts the portion of the first isolation layer 210 covering the bottom of the groove 120, and the first isolation portion 221 covers the portion of the first isolation layer 210 located on the side wall of the groove 120. The end of the first isolation portion 221 facing away from the bottom of the groove 120 is connected to the second isolation portion 222. At least a portion of the second isolation portion 222 can be arranged on the outside of the groove 120 so that the second isolation portion 222 is completely covered by the first isolation layer 210.

[0072] Along the thickness direction of the substrate 100, the ratio of the length of the first isolation portion 221 to the depth of the trench 120 is greater than or equal to 0.1 and less than or equal to 0.5. For example, the ratio of the length of the first isolation portion 221 to the depth of the trench 120 can be set to one of 0.1, 0.2, 0.3, 0.4 and 0.5; or, the ratio of the length of the first isolation portion 221 to the length of the second isolation portion 222 can also be set to be greater than or equal to 0.1 and less than or equal to 1. For example, the ratio of the length of the first isolation portion 221 to the length of the second isolation portion 222 can be set to one of 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9 and 1, so that the first isolation portion 221 captures hot carriers at the bottom of the trench 120, thereby reducing the possibility of hot carriers being located at the top of the trench 120.

[0073] It should be noted that, in the semiconductor structure, a large number of hot carriers generally migrate closer to the notch side of the trench 120 than to the bottom side of the trench 120, so the electron gathering area is generally formed in the second isolation layer 220 located at the top sidewall. Accordingly, a hole gathering area is formed in the active area 110 corresponding to the top sidewall of the trench 120, so that the position where the electrical breakdown occurs is correspondingly closer to the notch side of the trench 120.

[0074] Reference Figure 3 As shown, the second isolation layer 220 is configured to include a first isolation portion 221 and a second isolation portion 222. The first isolation portion 221 is disposed at one end of the second isolation portion 222 close to the bottom of the trench 120. The defect concentration of the first isolation portion 221 is higher than the defect concentration of the second isolation portion 222, so that the possibility of the first isolation portion 221 capturing hot carriers is greater than the possibility of the second isolation portion 222 capturing hot carriers, thereby reducing the possibility of forming an electron accumulation region in the second isolation layer 220 located on the top side wall.

[0075] The material of the first isolation layer 210 is the same as the material of the third isolation layer 230, and is different from the material of the second isolation layer 220. Exemplarily, the material of the first isolation layer 210 and the material of the third isolation layer 230 are both set to oxides, for example, the material of the first isolation layer 210 and the material of the third isolation layer 230 can be set to silicon oxide, and the material of the second isolation layer 220 is set to nitride, for example, the material of the second isolation layer 220 can be set to silicon nitride, so that the adsorption capacity of the second isolation layer 220 for hot carriers is higher than the adsorption capacity of the first isolation layer 210 and the third isolation layer 230 for hot carriers, so that the hot carriers are easily captured by the second isolation layer 220.

[0076] As a feasible implementation, the material of the second isolation layer 220 is set to nitride. In the second isolation layer 220, the second isolation portion 222 can be obtained by high pressure annealing (HPA) and post annealing (Post Anneal) in a deuterium gas (ie D2) environment.

[0077] Exemplarily, a second isolation material layer 223 can be formed on the surface of the first isolation layer 210 facing away from the groove 120, so that the second isolation material layer 223 covers the first isolation layer 210 located on the side wall of the groove 120, and then high-pressure annealing is performed in a deuterium gas environment, and then a portion of the second isolation material layer 223 near the top of the groove 120 is annealed at a later stage, so that the portion of the second isolation material layer 223 near the top of the groove 120 forms the second isolation portion 222, and the portion of the second isolation material layer 223 that has not been annealed under high pressure in the deuterium gas environment forms the first isolation portion 221, thereby realizing the formation process of the first isolation portion 221 and the second isolation portion 222.

[0078] As a feasible implementation, in the manufacturing process of the semiconductor structure, at least part of the first isolation layer 210 is located outside the trench 120, and the part of the first isolation layer 210 located outside the trench 120 is located on the top surface of the substrate 100; at least part of the second isolation portion 222 is located outside the trench 120, and the part of the second isolation portion 222 located outside the trench 120 covers the top surface of the first isolation layer 210; at least part of the third isolation layer 230 is located outside the trench 120, and the part of the third isolation layer 230 located outside the trench 120 covers the top surface of the second isolation portion 222, or the third isolation layer 230 is arranged flush with the top surface of the second isolation portion 222.

[0079] The top surface of the second portion outside the groove 120 is flush with the top surface of the third isolation layer 230. In semiconductor preparation, the first isolation layer 210 outside the groove 120, the second isolation portion 222 covering the top surface of the first isolation layer 210, and the third isolation layer 230 outside the groove 120 can be polished along the top surface of the substrate 100 by a chemical mechanical polishing process (CMP), so that the top surfaces of the first isolation layer 210, the second isolation portion 222, and the third isolation layer 230 are all flush with the top surface of the substrate 100. The formed structure can be referred to Figure 3 shown.

[0080] Reference Figure 2As shown, as an achievable implementation, the plurality of active regions 110 include a first active region 111 and a second active region 112 that are spaced apart, and the trench 120 is located between the first active region 111 and the second active region 112. PMOS transistors are disposed in both the first active region 111 and the second active region 112.

[0081] It should be noted that, in this embodiment, the first active region 111 and the second active region 112 are respectively disposed on opposite sides of the isolation structure 200, and the isolation structure 200 can electrically isolate the first active region 111 and the second active region 112. Wherein, transistor structures can be formed in both the first active region 111 and the second active region 112, and only the gate layer 113 and the gate dielectric layer 114 of the transistor in the first active region 111 are shown in the figure, and the gate dielectric layer 114 is disposed between the gate layer 113 and the substrate 100, and a channel region is disposed at a position corresponding to the gate dielectric layer 114 in the substrate 100.

[0082] Based on, PMOS transistors are disposed in the first active area 111 and the second active area 112, and the first active area 111 and the second active area 112 near the first trench 120 are both P-type semiconductors. Of course, in some embodiments, NMOS transistors may be disposed in the first active area 111 and the second active area 112, and the first active area 111 and the second active area 112 near the trench 120 are both N-type semiconductors.

[0083] In summary, by providing a plurality of active regions 110 arranged in an interval array in the semiconductor structure and an isolation structure 200 located between adjacent active regions 110, different active regions 110 are isolated by the isolation structure 200, thereby avoiding electrical interference between the active regions 110. The defect concentration of at least a portion of the isolation structure 200 close to the top surface of the substrate 100 is smaller than the defect concentration of at least a portion of the isolation structure 200 away from the top surface of the substrate 100.

[0084] In this way, the possibility of hot carriers being captured at the bottom of the isolation structure 200 can be made greater than the possibility of hot carriers being captured at the top of the isolation structure 200, thereby reducing the possibility of hot carriers in the substrate 100 being captured by the top of the isolation structure 200 to form an electron accumulation region, preventing the formation of a hole accumulation region corresponding to the electron accumulation region in the active area 110, reducing the possibility of breakdown between the two, and reducing the possibility of leakage in the isolation structure 200, thereby improving the yield of the semiconductor structure.

[0085] Reference Figure 4-Figure 13 As shown, in a second aspect, an embodiment of the present disclosure provides a method for preparing a semiconductor structure, comprising:

[0086] S100, providing a substrate 100, wherein the substrate 100 includes a plurality of active regions 110 arranged in an interval array;

[0087] The material of the substrate 100 may be single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium compound, silicon on insulator, etc., or other materials known to those skilled in the art. In addition, the active region 110 may be formed by ion doping, and the active region 110 may be a source region and / or a drain region. The present embodiment does not limit the type of the active region 110.

[0088] S200 , forming an isolation structure 200 , wherein the isolation structure 200 is located in the substrate 100 and between adjacent active regions 110 ;

[0089] The defect concentration of at least a portion of the isolation structure 200 close to the top surface of the substrate 100 is less than the defect concentration of at least a portion of the isolation structure 200 away from the top surface of the substrate 100. Exemplarily, the isolation layer may include a first isolation layer 210, a second isolation layer 220, and a third isolation layer 230 that are stacked; wherein the first isolation layer 210 is disposed on the inner wall of the trench 120, the second isolation layer 220 is disposed on the surface of the first isolation layer 210 away from the inner wall of the trench 120, and the third isolation layer 230 is disposed on the surface of the second isolation layer 220 away from the first isolation layer 210.

[0090] The material of the first isolation layer 210 is the same as the material of the third isolation layer 230, and is different from the material of the second isolation layer 220. Exemplarily, the material of the first isolation layer 210 and the material of the third isolation layer 230 can both be set to oxide, for example, the material of the first isolation layer 210 and the material of the third isolation layer 230 are both set to silicon oxide, and the material of the second isolation layer 220 is set to nitride, for example, the material of the second isolation layer 220 is set to silicon nitride.

[0091] Specifically, forming the isolation structure 200 includes:

[0092] A trench 120 is formed in the substrate 100 , wherein the trench 120 is located between adjacent active regions 110 ;

[0093] Reference Figure 5 As shown, the trench 120 can be formed by mask plate and photolithography, that is, a hard mask plate and photoresist are sequentially formed on the substrate 100, and the mask pattern is transferred to the hard mask plate by high selectivity etching, and then transferred to the substrate 100, so as to form the trench 120.

[0094] Forming a first isolation layer 210 in the trench 120, wherein a portion of the first isolation layer 210 covers the bottom of the trench 120, and the remaining portion of the first isolation layer 210 covers the sidewall of the trench 120;

[0095] Reference Figure 5 and Figure 6 As shown, the first isolation layer 210 is prepared and formed in the groove 120 by an atomic layer deposition process or a chemical vapor deposition process, and the thickness of the first isolation layer 210 is uniformly set at various locations. Part of the first isolation layer 210 covers the bottom of the groove 120, and the remaining part of the first isolation layer 210 covers the sidewall of the groove 120;

[0096] Alternatively, part of the first isolation layer 210 can also be formed outside the trench 120, and the part of the first isolation layer 210 located outside the trench 120 is located on the top surface of the substrate 100, so that the first isolation layer 210 located in the trench 120 completely covers the bottom and side walls of the trench 120.

[0097] A second isolation layer 220 is formed, wherein the second isolation layer 220 includes a first isolation portion 221 and a second isolation portion 222 connected to each other, wherein the first isolation portion 221 and the second isolation portion 222 both cover a portion of the first isolation layer 210 located on the sidewall of the trench 120, and the second isolation portion 222 is located at an end of the first isolation portion 221 away from the bottom of the trench 120, and the defect concentration of the second isolation portion 222 is lower than the defect concentration of the first isolation portion 221; a third isolation layer 230 is formed, wherein an end of the third isolation layer 230 facing the bottom of the trench 120 covers the first isolation layer 210, and the third isolation layer 230 covers a surface of the second isolation layer 220 away from the first isolation layer 210;

[0098] Reference Figure 6-Figure 13 As shown, as an achievable implementation, forming the second isolation layer 220 and the third isolation layer 230 includes:

[0099] forming a second isolation material layer 223, wherein the second isolation material layer 223 covers a surface of the first isolation layer 210 facing away from the substrate 100;

[0100] Reference Figure 6 and Figure 7 As shown, the second isolation material layer 223 can be formed on the surface of the first isolation layer 210 away from the substrate 100 by chemical vapor deposition (CVD) and other methods, and in the groove 120, part of the second isolation material layer 223 covers the first isolation layer 210 located at the bottom of the groove 120, and the remaining part of the second isolation material layer 223 covers the first isolation layer 210 located on the side wall of the groove 120; and part of the second isolation material layer 223 can also be formed on the outside of the groove 120, and the part of the second isolation material layer 223 formed on the outside of the groove 120 covers the top surface of the first isolation layer 210.

[0101] The second isolation material layer 223 on the surface of the first isolation layer 210 at the bottom of the trench 120 is removed, and the second isolation material layer 223 on the surface of the first isolation layer 210 on the sidewall of the trench 120 is retained;

[0102] Reference Figure 7 and Figure 8 As shown, illustratively, a portion of the second isolation material layer 223 on the surface of the first isolation layer 210 located at the bottom of the groove 120 can be removed by etching or the like to expose the first isolation layer 210 located at the bottom of the groove 120, and the second isolation material layer 223 on the surface of the first isolation layer 210 located on the side wall of the groove 120 is retained, and the remaining portion of the second isolation material layer 223 and a portion of the first isolation layer 210 form a groove, so that the second isolation material layer 223 on the surface of the first isolation layer 210 located on the side wall of the groove 120 is used to form the second isolation layer 220.

[0103] Reference Figure 8 and Fig. 9 As shown, after removing a portion of the second isolation material layer 223 on the surface of the first isolation layer 210 at the bottom of the trench 120, a third isolation material layer 233 is formed, the third isolation material layer 233 fills the groove surrounded by the second isolation material layer 223 and a portion of the first isolation layer 210, and a portion of the third isolation material layer 233 near the bottom of the trench 120 abuts against the first isolation layer 210;

[0104] The third isolation material layer 233 can also be formed by deposition to fill the groove surrounded by the second isolation material layer 223 and part of the first isolation layer 210. The end of the third isolation material layer 233 facing away from the first isolation layer 210 can be flush with the top surface of the first isolation layer 210 and the second isolation material layer 223; or, along the thickness direction of the substrate 100, the length of the third isolation material layer 233 can also be less than the depth of the groove.

[0105] Reference Fig. 9 and Fig.10 As shown, a portion of the thickness of the third isolation material layer 233 is etched back to expose a portion of the second isolation material layer 223 located on the sidewall of the trench 120, and the remaining portion of the third isolation material layer 233 forms a first portion 231 of the third isolation layer 230, and the second isolation material layer 223 covered by the first portion 231 forms a first isolation portion 221;

[0106] Exemplarily, a portion of the thickness of the third isolation material layer 233 is etched back so that the remaining portion of the third isolation material layer 233 covers the first isolation layer 210 toward one end of the first isolation layer 210 , and the remaining portion of the third isolation material layer 233 forms the first portion 231 of the third isolation layer 230 ;

[0107] The remaining portion of the third isolation material layer 233 fills the second isolation material layer 223 near the bottom of the trench 120, thereby exposing a portion of the second isolation material layer 223 located on the side wall of the trench 120, and the second isolation material layer 223 covered by the first portion 231 of the third isolation layer 230 forms a first isolation portion 221.

[0108] Along the thickness direction of the substrate 100, the length of the remaining portion of the third isolation material layer 233 is equal to the length of the first isolation portion 221, and the ratio of the length of the remaining portion of the third isolation material layer 233 to the depth of the trench 120 is greater than or equal to 0.1 and less than or equal to 0.5. For example, the ratio of the length of the remaining portion of the third isolation material layer 233 to the depth of the trench 120 can be set to one of 0.1, 0.2, 0.3, 0.4 and 0.5;

[0109] Alternatively, the ratio of the length of the remaining portion of the third isolation material layer 233 to the length of the second isolation material layer 223 exposed by the first portion 231 of the third isolation layer 230 can also be set to be greater than or equal to 0.1 and less than or equal to 1. For example, the ratio of the length of the remaining portion of the third isolation material layer 233 to the length of the second isolation material layer 223 exposed by the first portion 231 of the third isolation layer 230 can be set to one of 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9 and 1, so that the first isolation portion 221 captures hot carriers at the bottom of the trench 120, reducing the possibility of hot carriers being located at the top of the trench 120.

[0110] Processing the second isolation material layer 223 exposed by the first portion 231 to form a second isolation portion 222;

[0111] Reference Fig.10 and Fig.11 As shown, a high-pressure annealing treatment is performed in a deuterium gas environment, and a post-annealing treatment is performed on the second isolation material layer 223 exposed by the first portion 231 of the third isolation layer 230, so that the defect concentration of the second isolation material layer 223 exposed by the first portion 231 of the third isolation layer 230 is reduced, thereby forming a second isolation portion 222 in the second isolation material layer 223 exposed by the first portion 231 of the third isolation layer 230.

[0112] It should be noted that during the high-pressure annealing treatment of the second isolation material layer 223 in the deuterium gas environment, the concentration of deuterium gas in the environment of the second isolation material layer 223 is set to 6%, and the concentration of nitrogen gas is set to 94%; the pressure can be set to 10 atm (i.e., 10 times the standard atmospheric pressure), the temperature can be set to 450 degrees Celsius, and the annealing treatment time can be set to 1 hour;

[0113] During the later annealing of the second isolation material layer 223, the nitrogen concentration in the environment of the second isolation material layer 223 is set to 100%, the temperature can be set to 600 degrees Celsius, and the annealing time can be set to 1 hour, so that the second isolation material layer 223 exposed by the first part 231 of the third isolation layer 230 forms a second isolation portion 222.

[0114] Reference Fig.12 As shown, the first curve (i.e., the As-dep curve in the figure) represents the defect concentration curve of the unannealed nitride material, the second curve (i.e., the D2 HPA curve in the figure) represents the defect concentration curve of the nitride material that has only been subjected to high pressure annealing in a deuterium environment, and the third curve (i.e., the D2HPA+Post anneal curve in the figure) represents the defect concentration curve of the nitride material that has been subjected to high pressure annealing in a deuterium environment and post-annealing. Fig.12 In FIG. 5 , the abscissa represents the trap energy level of the nitride material (ie, Trap energy level), and the ordinate represents the defect concentration of the nitride material (ie, Trap density).

[0115] Reference Fig.12 As shown, the defect concentration of the nitride material of the third curve is lower than the defect concentration of the nitride material of the second curve, and the defect concentration of the nitride material of the second curve is lower than the defect concentration of the nitride material of the first curve; when the first isolation portion 221 has not been subjected to high-pressure annealing and post-annealing in a deuterium gas environment, and the second isolation portion 222 has been subjected to high-pressure annealing and post-annealing in a deuterium gas environment, the defect concentration of the second isolation portion 222 is lower than the defect concentration of the first isolation portion 221, so that the possibility of the first isolation portion 221 capturing hot carriers is greater than the possibility of the second isolation portion 222 capturing hot carriers.

[0116] forming a fourth isolation material layer, the fourth isolation material layer filling the groove formed by the top surface of the first portion 231 and the side surface of the second isolation material layer 223 , and the fourth isolation material layer forming the second portion 232 of the third isolation layer 230 ;

[0117] Reference Fig.11 and Fig.13 As shown, illustratively, the fourth isolation material layer can also be formed by deposition to fill the groove surrounded by the first part 231 of the third isolation layer 230 and the second isolation material layer 223, and the end of the fourth isolation material layer facing away from the first isolation layer 210 can be flush with the top surface of the first isolation layer 210 and the second isolation material layer 223.

[0118] The fourth isolation material layer forms the second part 232 of the third isolation layer 230, and the material of the fourth isolation material layer and the material of the third isolation material layer 233 can both be set to oxide, and the material of the fourth isolation material layer can be different from the material of the third isolation material layer 233; or, the material of the fourth isolation material layer can also be set the same as the material of the third isolation material layer 233, for example, the material of the fourth isolation material layer and the material of the third isolation material layer 233 are both set to silicon oxide, so that the material of the third isolation layer 230 is set to silicon oxide.

[0119] It should be noted that after the third isolation layer 230 is formed, the tops of the first isolation layer 210, the second isolation layer 220 and the third isolation layer 230 can be polished by a CMP process so that the top surfaces of the three are flush with the top surface of the substrate 100, so that the first isolation layer 210, the second isolation layer 220 and the third isolation layer 230 form an isolation layer, thereby realizing the formation process of the isolation structure 200.

[0120] In a third aspect, an embodiment of the present disclosure provides a memory, which may include the above-mentioned semiconductor structure. The memory may include, for example, a dynamic random access memory (DRAM), a static random access memory (SRAM), a flash memory, an electrically erasable programmable read-only memory (EEPROM), a phase change random access memory (PRAM), or a magnetoresistive random access memory (MRAM). The non-storage device may be a logic device (such as a microprocessor, a digital signal processor, or a microcontroller) or a device similar thereto.

[0121] The semiconductor structure in the memory in this embodiment is the same as that in the above-mentioned embodiment, and can achieve the same technical effects as those thereof, which will not be described in detail here.

[0122] In the description of the embodiments of the present disclosure, it should be understood that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, or it can be indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to the specific circumstances. The orientation or position relationship indicated by the terms "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc. is based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure. In the description of the present disclosure, the meaning of "multiple" is two or more, unless otherwise precisely and specifically specified.

[0123] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present disclosure described herein can, for example, be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0124] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A semiconductor structure, characterized in that: The invention comprises a substrate and an isolation structure, wherein the substrate has a plurality of active regions which are spaced apart and arranged in an array, and the isolation structure is located between adjacent active regions; The defect concentration of at least a portion of the isolation structure on a side close to the substrate top surface is smaller than the defect concentration of at least a portion of the isolation structure on a side away from the substrate top surface.

2. The semiconductor structure according to claim 1, characterized in that: The substrate is provided with a groove, and the isolation layer includes a first isolation layer, a second isolation layer and a third isolation layer which are stacked; Part of the first isolation layer covers the bottom of the trench, and the remaining part of the first isolation layer covers the sidewall of the trench; The second isolation layer comprises a first isolation portion and a second isolation portion connected to each other, the first isolation portion and the second isolation portion both cover a portion of the first isolation layer located on the sidewall of the trench, and the second isolation portion is located at an end of the first isolation portion away from the bottom of the trench, and the defect concentration of the second isolation portion is lower than the defect concentration of the first isolation portion; One end of the third isolation layer facing the bottom of the trench covers the first isolation layer, and the third isolation layer covers a surface of the second isolation layer facing away from the first isolation layer.

3. The semiconductor structure according to claim 2, characterized in that: The material of the first isolation part and the material of the second isolation part are both set to nitride, and the second isolation part is obtained by high-pressure annealing in a deuterium gas environment and post-annealing.

4. The semiconductor structure according to claim 2, characterized in that: Along the thickness direction of the substrate, a ratio of the length of the first isolation portion to the depth of the trench is greater than or equal to 0.1 and less than or equal to 0.

5.

5. The semiconductor structure according to claim 3, characterized in that: The first isolation layer and the third isolation layer are made of the same material, which is oxide.

6. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a plurality of active regions arranged in an interval array; forming an isolation structure, wherein the isolation structure is located in the substrate and between adjacent active regions; The defect concentration of at least a portion of the isolation structure on a side close to the substrate top surface is smaller than the defect concentration of at least a portion of the isolation structure on a side away from the substrate top surface.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that: The isolation structure comprises a first isolation layer, a second isolation layer and a third isolation layer which are stacked; Forming the isolation structure includes: forming a trench in the substrate, wherein the trench is located between adjacent active regions; forming the first isolation layer, wherein a portion of the first isolation layer covers the bottom of the trench, and the remaining portion of the first isolation layer covers the sidewall of the trench; The second isolation layer is formed, wherein the second isolation layer includes a first isolation portion and a second isolation portion connected to each other, wherein the first isolation portion and the second isolation portion both cover a portion of the first isolation layer located on the side wall of the trench, and the second isolation portion is located at an end of the first isolation portion away from the bottom of the trench, and the defect concentration of the second isolation portion is lower than the defect concentration of the first isolation portion; the third isolation layer is formed, wherein the end of the third isolation layer facing the bottom of the trench covers the first isolation layer, and the third isolation layer covers a surface of the second isolation layer away from the first isolation layer.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that: Forming the second isolation layer includes: forming a second isolation material layer, wherein the second isolation material layer covers a surface of the first isolation layer facing away from the substrate; The second isolation material layer on the surface of the first isolation layer at the bottom of the trench is removed, and the second isolation material layer on the surface of the first isolation layer at the sidewall of the trench is retained.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that: The second isolation layer and the third isolation layer are formed, comprising: forming a third isolation material layer, wherein the third isolation material layer fills the groove formed by the second isolation material layer and a portion of the first isolation layer; a portion of the third isolation material layer close to the bottom of the groove abuts against the first isolation layer; Etching back a portion of the thickness of the third isolation material layer to expose a portion of the second isolation material layer located on the sidewall of the trench, the remaining portion of the third isolation material layer forming a first portion of the third isolation layer, and the second isolation material layer covered by the first portion forming a first isolation portion; processing the second isolation material layer exposed by the first portion to form the second isolation portion; A fourth isolation material layer is formed, the fourth isolation material layer fills the groove surrounded by the top surface of the first portion and the side surface of the second isolation material layer, and the fourth isolation material layer forms the second portion of the third isolation layer.

10. The method for preparing a semiconductor structure according to claim 9, characterized in that: Processing the second isolation material layer exposed by the first portion, comprising: The second isolation material layer is nitride, and is subjected to high pressure annealing in a deuterium gas environment, and then subjected to post-annealing treatment on the second isolation material layer; And / or, the third isolation material layer and the fourth isolation material layer are made of the same material, which is oxide.

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