Novel 3D-structured memory and its fabrication method

Abstract

This invention provides a novel 3D memory structure and its fabrication method. By directly forming memory cells on the active region after the gate structure formation process, this invention reduces the impact of the memory cell-related process thermal budget on front-end devices and reduces the influence of the front layer on the memory cell outline. The lower electrode of the memory cell is directly connected to the active region, and the upper electrode is led out through a lead-out structure with a larger size, improving the connection reliability between the upper / lower electrodes of the memory cell and the corresponding components. The lead-out structure and the active region / gate structure without memory cells are led out through corresponding contact / connection structures, reducing the need for dielectric layers and photomask processes. The 3D structure of the memory cells, continuously distributed on the inner wall of the trench, increases the effective area for phase transition.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a novel 3D memory and its fabrication method. Background Technology

[0002] Novel memory technologies such as phase-change RAM (PRAM) or ferroelectric RAM (FeRAM) are devices that integrate memory cells in back-to-the-line (BEOL) processes. The memory cells are inserted between metal layers, and their storage performance is directly proportional to the effective area of ​​the memory and electrode layers. Using a three-dimensional (3D) structure for the memory cells can effectively increase storage density or achieve better cell performance / reliability within the same cell area.

[0003] Traditional 3D structure technology is integrated into the front-end-of-line (FEOL) device and contact structure after the 3D structure process is completed. The thermal budget (the heat energy required for silicon exposure in the process) of this 3D structure process may affect the front-end process device. At the same time, the profile of the 3D structure memory cell is greatly affected by the previous layer. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a novel 3D memory and its fabrication method, which can reduce the impact of the thermal budget of the memory cell process on the front-end process device, reduce the impact of the front layer on the memory cell outline, increase the effective area of ​​phase change, improve memory performance, and save photomask process and reduce production cost while ensuring that the connection performance of the contact structure remains unchanged.

[0005] To address the aforementioned problems, this invention provides a method for fabricating a novel 3D-structured memory. The method includes the following steps: forming a semiconductor substrate, the semiconductor substrate including a substrate, and defining an active region within the substrate; forming a first dielectric layer covering the surface of the substrate, the first dielectric layer containing trenches that penetrate the first dielectric layer perpendicular to the substrate surface and expose a portion of the active region; forming 3D-structured memory cells and lead-out structures, the memory cells being continuously distributed along the inner walls of the trenches, the memory cells including a first electrode layer, a memory layer, and a second electrode layer arranged sequentially. A second dielectric layer is formed at the bottom of the trench, where the first electrode layer contacts the active region, and the lead-out structure covers the second electrode layer and fills the trench; a second dielectric layer is formed, which covers the first dielectric layer, all the memory cells, and all the lead-out structures, and a contact hole is formed in the second dielectric layer that penetrates the second dielectric layer along a direction perpendicular to the substrate surface and exposes part of the lead-out structure; a contact structure and a metal structure are formed, where the contact structure fills the contact hole and contacts the lead-out structure, and the metal structure is located on the surface of the second dielectric layer and contacts the contact structure.

[0006] To address the aforementioned problems, the present invention also provides a novel 3D structure memory, comprising: a substrate, wherein an active region is defined within the substrate; a first dielectric layer covering the surface of the substrate, wherein a trench is formed within the first dielectric layer penetrating the first dielectric layer in a direction perpendicular to the surface of the substrate and exposing a portion of the active region; memory cells continuously distributed on the inner wall of the trench, wherein each memory cell includes a first electrode layer, a memory layer, and a second electrode layer arranged in sequence, wherein the first electrode layer is in contact with the active region at the bottom of the trench; a lead-out structure covering the second electrode layer and filling the trench; a second dielectric layer covering the first dielectric layer, all the memory cells, and all the lead-out structures, wherein a contact hole is formed within the second dielectric layer penetrating the second dielectric layer in a direction perpendicular to the surface of the substrate and exposing a portion of the lead-out structures; a contact structure filling the contact hole and contacting the lead-out structures; and a metal structure located on the surface of the second dielectric layer and in contact with the contact structure.

[0007] The above technical solution reduces the impact of the thermal budget of the memory cell process on the front-end device and the influence of the front layer on the memory cell outline by directly forming the memory cell on the active region after the gate structure formation process. The lower electrode (first electrode layer) of the memory cell is directly connected to the active region, and the upper electrode (second electrode layer) of the memory cell is led out through a lead-out structure with a larger size, which improves the connection reliability between the upper / lower electrodes of the memory cell and the corresponding components. The lead-out structure and the active region / gate structure without memory cells are led out through corresponding contact structures / connection structures, reducing the dielectric layer and photomask processes. The 3D structure of the memory cell continuously distributed on the inner wall of the trench increases the effective phase transition area. This invention can increase the effective phase transition area of ​​the memory cell, maintain the connection performance of the contact structure, reduce the impact of the thermal budget of the memory cell process on the front-end device, reduce the influence of the front layer on the memory cell outline, and reduce the dielectric layer and photomask processes, thereby improving memory performance, optimizing and improving device operating efficiency and reliability, and reducing production costs.

[0008] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Techniques, methods, and apparatus known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and apparatus should be considered part of the specification. Attached Figure Description

[0009] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a schematic diagram of the device structure of a 3D memory in the prior art;

[0011] Figure 2 A schematic diagram of the contour defects of a 3D structure memory in the prior art;

[0012] Figure 3 This is a schematic diagram illustrating the steps of a novel 3D memory fabrication method according to an embodiment of the present invention;

[0013] Figure 4 This is a schematic diagram of a device structure of a semiconductor substrate provided in an embodiment of the present invention;

[0014] Figures 5A-5B This is a schematic diagram of a device structure forming a first dielectric layer according to an embodiment of the present invention;

[0015] Figures 6A to 6C This is a schematic diagram of a device structure forming a memory cell according to an embodiment of the present invention;

[0016] Figures 7A-7B This is a schematic diagram of a device structure for forming a second dielectric layer according to an embodiment of the present invention;

[0017] Figure 8 This is a schematic diagram of a device structure forming a contact structure and a metal structure according to an embodiment of the present invention. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] Please see Figure 1 This is a schematic diagram of the device structure of a 3D memory in the prior art. For example... Figure 1 As shown, a conventional 3D memory structure includes: a substrate 10; a first dielectric layer 111 formed on the substrate 10; a first connection structure 121 formed within the first dielectric layer 111; a second dielectric layer 112 formed on the first dielectric layer 111; a memory cell 14 formed within the second dielectric layer 112 and in contact with the first connection structure 121; a second connection structure 122 in contact with the memory cell 14; a third dielectric layer 113 covering the second dielectric layer 112 and covering the memory cell 14 and the second connection structure 122; a third connection structure 123 formed within the third dielectric layer 113 and in contact with the memory cell 14; and a metal structure 13 formed on the surface of the third dielectric layer 113 and in contact with the third connection structure 123. The memory cell 14 consists of a lower electrode layer 141, an intermediate memory layer 142, and an upper electrode layer 143. A first barrier layer 191 is formed between the first dielectric layer 111 and the second dielectric layer 112, and a second barrier layer 192 is formed between the second dielectric layer 112 and the third dielectric layer 113.

[0020] The use of a three-dimensional (3D) structure in the memory cell 14 can effectively improve storage density or achieve better cell performance / reliability within the same cell area. However, the fabrication process of this memory cell is integrated after the front-end process (FEOL) device and contact structure are completed, and the thermal budget of the process affects the front-end device. The profile of this memory cell is significantly influenced by the preceding layers, such as... Figure 2 As shown in the dashed box. Figure 2The image shows a single-layer color block representing a storage unit. The outline of the storage unit within the dashed frame is deformed due to the presence of protruding contact structures. Furthermore, the fabrication of this memory requires the deposition of multiple dielectric layers, and the fabrication of the first connection structure 121, the second connection structure 122, and the third connection structure 123 requires three photomask processes, increasing production costs.

[0021] To address the issues of thermal budget impacting front-end device fabrication in existing memory cell fabrication processes, significant influence of the memory cell contour on the preceding layers, and increased production costs due to the need for multi-layer dielectric deposition and multiple photomask processes, this invention provides a novel 3D memory structure and its fabrication method. This method increases the effective phase-change area of ​​the memory cell while maintaining the connection performance of the contact structure, reduces the impact of thermal budget on front-end device fabrication, minimizes the influence of the preceding layers on the memory cell contour, and reduces the number of dielectric layers and photomask processes. This improves memory performance, optimizes device operating efficiency and reliability, and reduces production costs.

[0022] One embodiment of the present invention provides a method for fabricating a novel 3D memory structure.

[0023] Please refer to the following: Figures 3-8 ,in, Figure 3 This is a schematic diagram illustrating the steps of a novel 3D memory fabrication method according to an embodiment of the present invention; Figure 4 This is a schematic diagram of a device structure of a semiconductor substrate provided in an embodiment of the present invention; Figures 5A-5B This is a schematic diagram of a device structure forming a first dielectric layer according to an embodiment of the present invention; Figures 6A to 6C This is a schematic diagram of a device structure forming a memory cell according to an embodiment of the present invention;

[0024] Figures 7A-7B This is a schematic diagram of a device structure for forming a second dielectric layer according to an embodiment of the present invention; Figure 8 This is a schematic diagram of a device structure forming a contact structure and a metal structure according to an embodiment of the present invention.

[0025] like Figure 3As shown, the fabrication method of the novel 3D structure memory described in this embodiment includes the following steps: S1, forming a semiconductor substrate, the semiconductor substrate including a substrate, and defining an active region within the substrate; S2, forming a first dielectric layer, the first dielectric layer covering the surface of the substrate, and forming trenches in the first dielectric layer that penetrate the first dielectric layer along a direction perpendicular to the surface of the substrate and expose a portion of the active region; S3, forming 3D structure memory cells and lead-out structures, the memory cells being continuously distributed on the inner wall of the trenches, the memory cells including a first electrode layer, a memory layer, and a second electrode layer arranged in sequence. The bottom of the trench, the first electrode layer, and the active region are in contact. The lead-out structure covers the second electrode layer and fills the trench. S4: A second dielectric layer is formed, which covers the first dielectric layer, all the memory cells, and all the lead-out structures. A contact hole is formed in the second dielectric layer, penetrating the second dielectric layer in a direction perpendicular to the substrate surface and exposing part of the lead-out structure. S5: A contact structure and a metal structure are formed. The contact structure fills the contact hole and is in contact with the lead-out structure. The metal structure is located on the surface of the second dielectric layer and is in contact with the contact structure.

[0026] Please refer to step S1 and Figure 4 A semiconductor substrate is formed, the semiconductor substrate including a substrate 40, and an active region 401 is defined in the substrate 40.

[0027] The substrate 40 is used to support the device structure above it, and the device structure can also be formed in the substrate 40. In this embodiment, the substrate 40 may include a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanide (SiGe) substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate, etc.; the substrate 40 may also be a stacked structure, such as a silicon / germanium silicon stack, etc.

[0028] In this embodiment, a gate structure 49 is further formed on the surface of the substrate 40, and an active region 401 is defined within the substrate 40 between two adjacent gate structures 49. Before the step (S2) of forming the first dielectric layer, the method further includes: forming a contact layer 41, which covers the surface of the substrate 40 and exposes the gate structure 49, such as... Figure 4As shown. The source / drain electrodes on both sides of the gate structure 49 can be led out through the contact layer 41. Specifically, the material of the contact layer 41 is metal silicide. The gate structure 49 includes a polysilicon gate 491, a gate oxide layer 492 located below the polysilicon gate 491, and a spacer 493 located on the sidewall of the polysilicon gate 491.

[0029] Please refer to step S2 and Figure 5B A first dielectric layer 51 is formed, which covers the surface of the substrate 40. A trench 510 is formed in the first dielectric layer 51, which penetrates the first dielectric layer 51 in a direction perpendicular to the surface of the substrate 40 and exposes part of the active region 401.

[0030] In this embodiment, the step of forming the first dielectric layer 51 specifically includes: (1) forming a first etch barrier layer 58 covering the surface of the substrate 40, forming the first dielectric layer 51 covering the first etch barrier layer 58, and forming a first protective layer 59 covering the first dielectric layer 51, such as Figure 5A As shown. (2) Using the first etching barrier layer 58 as the etching stop layer, the first protective layer 59 and the first dielectric layer 51 are etched to form the trench 510, as shown. Figure 5B As shown. The material of the first dielectric layer 51 can be an oxide (OX) material, such as silicon oxide (SiO). The material of the first etch stop layer 58 can be silicon nitride (SiN). The material of the first protective layer 59 can be silicon oxynitride (SiON). The first etch stop layer 58 serves as an etch stop layer for etching to form the trench 510, and the first protective layer 59 is used to protect the first dielectric layer 51 during trench etching.

[0031] When the substrate 40 also has a gate structure 49 and a contact layer 41, the first etch barrier layer 58 covers the gate structure 49 and the contact layer 41, and the first dielectric layer 51 fills the area between two adjacent gate structures 49.

[0032] Please refer to step S3 and Figure 6C The storage unit 60 and the lead-out structure 64 form a 3D structure. The storage unit 60 is continuously distributed on the inner wall of the trench 510. The storage unit 60 includes a first electrode layer 61, a storage layer 62 and a second electrode layer 63 arranged in sequence. At the bottom of the trench 510, the first electrode layer 61 is in contact with the active region 401. The lead-out structure 64 covers the second electrode layer 63 and fills the trench 510.

[0033] Specifically, when the substrate 40 surface is covered with the contact layer 41, the first electrode layer 61 is in contact with the active region 401 through the contact layer 41.

[0034] In this embodiment, the storage cell 60 and lead-out structure 64 forming a 3D structure further include: (1) sequentially depositing a first electrode material layer 610, a storage material layer 620, and a second electrode material layer 630 on the inner wall of the trench 510 and the surface of the first dielectric layer 51, such as... Figure 6A As shown. (2) A lead-out material layer 640 is deposited to cover the second electrode material layer 630 and fill the trench 510, as shown. Figure 6B As shown. (3) Pattern the first electrode material layer 610, the storage material layer 620, the second electrode material layer 630, and the lead-out material layer 640 to form the first electrode layer 61, the storage layer 62, and the second electrode layer 63, which are continuously distributed on the inner wall of the trench 510 and arranged in sequence, and to form the lead-out structure 64 that covers the second electrode layer 63 and fills the trench 510, as shown. Figure 6C As shown.

[0035] In some embodiments, the first electrode material layer 610, the storage material layer 620, and the second electrode material layer 630 can be deposited and grown using maskless atomic layer deposition (ALD). The lead-out material layer 640 can also be deposited and grown using maskless atomic layer deposition (ALD). The patterning can be achieved by etching the first electrode material layer 610, the storage material layer 620, the second electrode material layer 630, and the lead-out material layer 640 using a predetermined mask.

[0036] In some embodiments, the first electrode layer 61 and the second electrode layer 63 are both made of titanium nitride, the storage layer 62 is made of ferroelectric material or phase change material, and the lead-out structure 64 is made of tungsten metal.

[0037] In this embodiment, the storage unit 60 has a 3D structure. Specifically, the first electrode layer 61, the storage layer 62, and the second electrode layer 63 have the same shape.

[0038] In this embodiment, the storage cells 60 are continuously distributed on the inner wall of the trench 510 and on a portion of the surface of the first dielectric layer 51 adjacent to the trench 510, such as... Figure 6C As shown.

[0039] In this embodiment, a second protective layer 69 is also formed on the surface of the lead-out structure 64. The material of the second protective layer 69 can be silicon oxynitride (SiON). The second protective layer 69 can be formed before the above-described patterning process to protect the lead-out material layer 640 during the patterning process and remain on the surface of the lead-out structure 64 after the patterning process is completed.

[0040] This embodiment directly forms the memory cell after the gate structure (and further, the contact layer) process, reducing the impact of the thermal budget of the memory cell process on the front-end device and reducing the impact of the front layer on the memory cell outline. The lower electrode (first electrode layer) of the memory cell is directly connected to the active region, and the upper electrode (second electrode layer) of the subsequent memory cell is led out through a lead-out structure with a larger size, which improves the connection reliability between the upper / lower electrodes of the memory cell and the corresponding components, and reduces the dielectric layer and photomask process. Furthermore, the 3D structure of the memory cell 60, which is continuously distributed on the inner wall of the trench 510, increases the effective area of ​​the phase transition.

[0041] Please refer to step S4 and Figure 7B A second dielectric layer 71 is formed, which covers the first dielectric layer 51, all the memory cells 60 and all the lead-out structures 64. A contact hole 701 is formed in the second dielectric layer 71, which penetrates the second dielectric layer 71 in a direction perpendicular to the surface of the substrate 40 and exposes part of the lead-out structure 64.

[0042] In this embodiment, the step of forming the second dielectric layer 71 specifically includes: (1) forming a second etch barrier layer 78 covering the first dielectric layer 51, all the memory cells 60, and all the lead-out structures 64; forming the second dielectric layer 71 covering the second etch barrier layer 78; and forming an etch protection layer 79 covering the second dielectric layer 71, such as... Figure 7A As shown. (2) Using the second etch stop layer 78 as the etch stop layer, etch the etch protection layer 79 and the second dielectric layer 71 to form the contact hole 701, as shown. Figure 7B As shown. The material of the second dielectric layer 71 can be an oxide (OX) material, such as silicon oxide (SiO). The material of the second etch stop layer 78 can be silicon nitride (SiN). The material of the etch protection layer 79 can be silicon oxynitride (SiON). The second etch stop layer 78 serves as an etch stop layer for etching to form the contact hole 701, and the etch protection layer 79 is used to protect the second dielectric layer 71 during the etching of the contact hole.

[0043] In this embodiment, a connection hole 702 is formed simultaneously with the contact hole 701. The connection hole 702 penetrates the second dielectric layer 71 and the first dielectric layer 51 along a direction perpendicular to the surface of the substrate 40, and is spaced apart from the contact hole 701. Specifically, after the contact hole 701 is formed by etching with the second etch stop layer 78 as the etch stop layer, the first protective layer 59 and the first dielectric layer 51 are etched with the first etch stop layer 58 as the etch stop layer to form the connection hole 702. Specifically, part of the connection hole 702 exposes the substrate 40 (specifically, the contact layer 41 above another active region 401 without memory cells within the substrate 40), and part of the connection hole 702 exposes the top of the gate structure 49 (not shown).

[0044] Please refer to step S5 and Figure 8 A contact structure 81 and a metal structure 89 are formed. The contact structure 81 fills the contact hole 701 and is in contact with the lead-out structure 64. The metal structure 89 is located on the surface of the second dielectric layer 71 and is in contact with the contact structure 81.

[0045] In some embodiments, the steps of forming the contact structure 81 and the metal structure 89 specifically include: (1) depositing a metal material and planarizing it to form the contact structure 81 within the contact hole 701; and (2) depositing a metal material on the surface of the second dielectric layer 71 and patterning it to form the metal structure 89. The planarization can be achieved using a chemical mechanical polishing (CMP) process. The patterning can refer to existing metal patterning processes, which will not be elaborated here.

[0046] In this embodiment, the top surface of the contact structure 81 is flush with the top surface of the second dielectric layer 71. The material of the contact structure 81 can be tungsten.

[0047] In this embodiment, a connection structure 82 is formed concurrently with the contact structure 81. The connection structure 82 penetrates the second dielectric layer 71 and the first dielectric layer 51 along a direction perpendicular to the surface of the substrate 40, and the connection structure 82 is spaced apart from the contact structure 81. A portion of the connection structure 82 is used to contact the substrate 40 (specifically, to contact the contact layer 41 above another active region 401 without memory cells within the substrate 40), and a portion of the connection structure 82 is used to contact the gate structure 49. Through the contact structure 81 and the connection structure 82, the lead-out structure on the upper electrode (second electrode layer) of the memory cell and the active region / gate structure without memory cells are led out.

[0048] In this embodiment, the metal structure 89 is also in one-to-one contact with the connecting structure 82. The metal structure 89 serves as a solder pad. The material of the metal structure 89 is selected from aluminum, copper, or an aluminum-copper alloy, preferably an aluminum-copper alloy.

[0049] Based on the same inventive concept, the present invention also provides a novel 3D memory structure prepared using the method described above.

[0050] Please see Figures 4-8 The novel 3D memory structure described in this embodiment includes: a substrate 40, an active region 401, a first dielectric layer 51, a memory cell 60, a lead-out structure 64, a second dielectric layer 71, a contact structure 81, and a metal structure 89.

[0051] Specifically, the active region 401 is defined within the substrate 40. In this embodiment, a gate structure 49 is formed on the surface of the substrate 40, and the active region 401 is defined within the substrate 40 between two adjacent gate structures 49. The novel 3D memory structure further includes a contact layer 41, which covers the surface of the substrate 40 and exposes the gate structure 49. Specifically, the material of the contact layer 41 is silicide. The gate structure 49 includes a polysilicon gate 491, a gate oxide layer 492 located below the polysilicon gate 491, and a spacer 493 located on the sidewall of the polysilicon gate 491.

[0052] Specifically, the first dielectric layer 51 covers the surface of the substrate 40, and a trench 510 is formed within the first dielectric layer 51 that penetrates the first dielectric layer 51 along a direction perpendicular to the surface of the substrate 40 and exposes a portion of the active region 401 (e.g., Figure 5B (As shown).

[0053] Specifically, the storage cells 60 are continuously distributed on the inner wall of the trench 510. Each storage cell 60 includes a first electrode layer 61, a storage layer 62, and a second electrode layer 63 arranged in sequence. At the bottom of the trench 510, the first electrode layer 61 is in contact with the active region 401. The lead-out structure 64 covers the second electrode layer 63 and fills the trench 510.

[0054] Specifically, the second dielectric layer 71 covers the first dielectric layer 51, all the memory cells 60, and all the lead-out structures 64. A contact hole 701 is formed within the second dielectric layer 71, penetrating the second dielectric layer 71 along a direction perpendicular to the surface of the substrate 40 and exposing a portion of the lead-out structures 64. Figure 7B (As shown).

[0055] Specifically, the contact structure 81 fills the contact hole 701 and contacts the lead-out structure 64. The metal structure 89 is located on the surface of the second dielectric layer 71 and contacts the contact structure 81.

[0056] In this embodiment, the first electrode layer 61 and the second electrode layer 63 are both made of titanium nitride, the storage layer 62 is made of ferroelectric material or phase change material, the first dielectric layer 51 and the second dielectric layer 71 are made of oxide (e.g., silicon oxide), the contact structure 81 is made of tungsten metal, and the metal structure 89 is made of aluminum, copper, or an aluminum-copper alloy.

[0057] In this embodiment, the top surface of the contact structure 81 is flush with the top surface of the second dielectric layer 71.

[0058] In this embodiment, the novel 3D memory structure further includes a connection structure 82, formed using the same process as the contact structure 81. The connection structure 82 penetrates the second dielectric layer 71 and the first dielectric layer 51 along a direction perpendicular to the surface of the substrate 40, and the connection structure 82 is spaced apart from the contact structure 81. A portion of the connection structure 82 is used to contact the substrate 40 (specifically, to contact the contact layer 41 above another active region 401 without memory cells within the substrate 40), and a portion of the connection structure 82 is used to contact the gate structure 49. Through the contact structure 81 and the connection structure 82, the lead-out structure on the upper electrode (second electrode layer) of the memory cell and the active region / gate structure without memory cells are led out. The metal structure 89 also makes one-to-one contact with the connection structure 82. The metal structure 89 serves as a bonding pad.

[0059] In this embodiment, the storage cells 60 are continuously distributed on the inner wall of the trench 510 and on a portion of the surface of the first dielectric layer 51 adjacent to the trench 510. Specifically, the first electrode layer 61, the storage layer 62, and the second electrode layer 63 have the same shape.

[0060] This embodiment directly forms memory cells on the active region after the gate structure (and further, the contact layer) is formed, reducing the impact of the thermal budget of the memory cell process on the front-end devices and reducing the impact of the front layer on the memory cell outline. The lower electrode (first electrode layer) of the memory cell is directly connected to the active region, and the upper electrode (second electrode layer) of the memory cell is led out through a lead-out structure with a larger size, improving the connection reliability between the upper / lower electrodes of the memory cell and the corresponding components. The lead-out structure and the active region / gate structure without memory cells are led out through corresponding contact structures / connection structures, reducing the dielectric layer and photomask processes. Furthermore, the 3D structure of the memory cell, which is continuously distributed on the inner wall of the trench, increases the effective area of ​​the phase transition.

[0061] In the above description, descriptions of well-known components and technologies have been omitted to avoid unnecessarily obscuring the concept of the present invention. In the various embodiments described above, each embodiment focuses on its differences from other embodiments; similar or identical parts between embodiments can be referred to mutually.

[0062] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising a…" does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element. Additionally, embodiments and features thereof in this invention can be combined with each other without conflict.

[0063] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for fabricating a novel 3D memory structure, characterized in that, The method includes the following steps: forming a semiconductor substrate, the semiconductor substrate including a substrate, a gate structure formed on the surface of the substrate, and an active region defined in the substrate between two adjacent gate structures; forming a contact layer, the contact layer covering the surface of the substrate and exposing the gate structure; A first dielectric layer is formed, which covers the surface of the substrate. A trench is formed in the first dielectric layer, penetrating the first dielectric layer in a direction perpendicular to the surface of the substrate and exposing a portion of the active region. A 3D memory cell and an outgoing structure are formed. The memory cells are continuously distributed on the inner wall of the trench. The memory cell includes a first electrode layer, a memory layer, and a second electrode layer arranged in sequence. At the bottom of the trench, the first electrode layer contacts the active region through the contact layer. The outgoing structure covers the second electrode layer and fills the trench. A second dielectric layer is formed, which covers the first dielectric layer, all the memory cells and all the lead-out structures. A contact hole is formed in the second dielectric layer that penetrates the second dielectric layer in a direction perpendicular to the substrate surface and exposes part of the lead-out structures. The system forms a contact structure and a metal structure, wherein the contact structure fills the contact hole and is in contact with the lead-out structure, and the metal structure is located on the surface of the second dielectric layer and is in contact with the contact structure.

2. The method according to claim 1, characterized in that, The storage cells are continuously distributed on the inner wall of the trench and on a portion of the surface of the first dielectric layer adjacent to the trench.

3. The method according to claim 1, characterized in that, The step of forming the first dielectric layer specifically includes: forming a first etch stop layer covering the surface of the substrate, forming a first dielectric layer covering the first etch stop layer, and forming a first protective layer covering the first dielectric layer; using the first etch stop layer as an etch stop layer, etching the first protective layer and the first dielectric layer to form the trench.

4. The method according to claim 1, characterized in that, The steps for forming the 3D structure of the storage cell and the lead-out structure specifically include: sequentially depositing a first electrode material layer, a storage material layer, and a second electrode material layer on the inner wall of the trench and the surface of the first dielectric layer; depositing a lead-out material layer that covers the second electrode material layer and fills the trench; patterning the first electrode material layer, the storage material layer, the second electrode material layer, and the lead-out material layer to form a first electrode layer, the storage layer, and the second electrode layer that are continuously distributed on the inner wall of the trench and sequentially stacked, and forming the lead-out structure that covers the second electrode layer and fills the trench.

5. The method according to claim 1, characterized in that, The step of forming the second dielectric layer specifically includes: forming a second etch stop layer covering the first dielectric layer, all the memory cells and all the lead-out structures, forming a second dielectric layer covering the second etch stop layer, and forming an etch protection layer covering the second dielectric layer; using the second etch stop layer as an etch stop layer, etching the etch protection layer and the second dielectric layer to form the contact hole.

6. The method according to claim 1, characterized in that, The steps for forming the contact structure and the metal structure specifically include: depositing a metal material and planarizing it to form the contact structure within the contact hole, wherein the top surface of the contact structure is flush with the top surface of the second dielectric layer; depositing a metal material on the surface of the second dielectric layer and patterning it to form the metal structure.

7. The method according to claim 1, characterized in that, A connection structure is formed simultaneously with the contact structure. The connection structure penetrates the second dielectric layer and the first dielectric layer along a direction perpendicular to the substrate surface, and the connection structure is spaced apart from the contact structure.

8. The method according to claim 1, characterized in that, The first electrode layer and the second electrode layer are both made of titanium nitride, the storage layer is made of ferroelectric material or phase change material, the first dielectric layer and the second dielectric layer are made of oxide, the contact structure is made of tungsten metal, and the metal structure is made of aluminum, copper, or aluminum-copper alloy.

9. A novel 3D-structured memory, characterized in that, Includes: a substrate, wherein an active region is defined within the substrate; A gate structure is formed on the surface of the substrate, and an active region is defined in the substrate between two adjacent gate structures. A contact layer covers the surface of the substrate and exposes the gate structure; A first dielectric layer covers the surface of the substrate, and a trench is formed in the first dielectric layer that penetrates the first dielectric layer in a direction perpendicular to the surface of the substrate and exposes a portion of the active region. Storage cells are continuously distributed on the inner wall of the trench. Each storage cell includes a first electrode layer, a storage layer, and a second electrode layer arranged in sequence. At the bottom of the trench, the first electrode layer is in contact with the active region through the contact layer. An outgoing structure covers the second electrode layer and fills the trench. A second dielectric layer covers the first dielectric layer, all the memory cells and all the lead-out structures, and a contact hole is formed in the second dielectric layer that penetrates the second dielectric layer in a direction perpendicular to the substrate surface and exposes part of the lead-out structures. The contact structure fills the contact hole and contacts the lead-out structure; And a metal structure, located on the surface of the second dielectric layer and in contact with the contact structure.

10. The novel 3D structure memory according to claim 9, characterized in that, The storage cells are continuously distributed on the inner wall of the trench and on a portion of the surface of the first dielectric layer adjacent to the trench.

11. The novel 3D structure memory according to claim 9, characterized in that, The first electrode layer and the second electrode layer are both made of titanium nitride, the storage layer is made of ferroelectric material or phase change material, the first dielectric layer and the second dielectric layer are both made of oxide, the contact structure is made of tungsten metal, and the metal structure is made of aluminum, copper, or aluminum-copper alloy.

12. The novel 3D structure memory according to claim 9, characterized in that, The contact layer is made of metal silicide.

13. The novel 3D structure memory according to claim 9, characterized in that, The substrate surface is covered with a first etch barrier layer, the first dielectric layer surface is covered with a first protective layer, the lead-out structure surface away from the first dielectric layer is covered with a second protective layer, and the surfaces of the first and second protective layers are covered with a second etch barrier layer.

14. The novel 3D structure memory according to claim 13, characterized in that, The first etch barrier layer and the second etch barrier layer are both made of silicon nitride, and the first protective layer and the second protective layer are both made of silicon oxynitride.

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