Transistor preparation method and electronic equipment
During the preparation process of vertical gate fully surround transistors, anisotropic etching technology is used to remove the epitaxial silicon sidewalls and remaining gate materials in the silicon substrate, which solves the short circuit problem caused by metal contamination and improves the transistor Preparation accuracy and reliability.
Patent Information
- Application Number
- CN202310827205.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-07-06
- Publication Date
- 2025-01-10
AI Technical Summary
During the deposition of the metal gate of the vertical gate fully surrounds the transistor, the source/drain is prone to metal contamination, resulting in a short circuit that is difficult to avoid.
By sequentially stacking the first silicon layer, the silicon germanium layer and the second silicon layer on the silicon substrate and etching to form a plurality of silicon columns, then depositing the gate material on these silicon columns and etching by anisotropic etching The epitaxial silicon sidewalls of the second silicon layer and the remaining gate material inside are removed to avoid short circuits.
It effectively prevents short circuit between the source/drain and gate, and improves the accuracy and reliability of the transistor preparation process.
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Figure CN119300381A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a method for manufacturing a transistor and an electronic device. Background Art
[0002] The vertical gate-all-around (VGAA) transistor is a new type of semiconductor device. Compared with the planar GAA transistor, the vertical GAA transistor (VGAA) has a small projected area and an unlimited channel length.
[0003] In the related art, during the process of depositing the metal gate of the VGAA transistor, the exposed source / drain is easily contaminated with metal and is difficult to remove, which may cause a short circuit between the source / drain and the metal gate. Summary of the invention
[0004] The embodiment of the present application provides a method for manufacturing a transistor and an electronic device, which effectively prevents the source / drain of the transistor from being contaminated by metal. The technical solution is as follows:
[0005] In one aspect, a method for preparing a transistor is provided, the method comprising:
[0006] A first silicon layer 301, a silicon germanium layer 302 and a second silicon layer 303 are sequentially stacked on a silicon substrate 300, wherein the first silicon layer 301 is in contact with the silicon substrate 300;
[0007] By etching the first silicon layer 301, the silicon germanium layer 302 and the second silicon layer 303, a plurality of first silicon pillars 304 are formed along a first direction;
[0008] A plurality of columns of second masks 305 are formed on the plurality of first silicon pillars 304 along a second direction, wherein the second masks (305) include sidewalls (305-1); the first silicon layer 301, the silicon germanium layer 302 and the second silicon layer 303 are etched according to the plurality of columns of second masks 305; on the basis of the grooves obtained by etching, the silicon germanium layer 302 is further etched to form lateral grooves; epitaxial silicon is laterally grown on the first silicon layer 301, the lateral grooves and the second silicon layer 303; a gate material is deposited on the first silicon layer 301; anisotropic etching of the gate material is performed according to the plurality of sidewalls 305-1 to remove the gate material outside the epitaxial silicon sidewalls of the second silicon layer 303; and the gate material in the plurality of sidewalls 305-1 and the second silicon layer 303 is removed to form a plurality of second silicon pillars 306, wherein the plurality of second silicon pillars 306 are distributed in an array along the first direction and the second direction;
[0009] Based on the plurality of second silicon pillars 306 , a vertical all-around gate transistor is formed.
[0010] On the other hand, an electronic device is provided, wherein the electronic device includes a logic device, and the logic device is manufactured by the above transistor manufacturing method. The electronic device includes a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device or a smart mobile terminal.
[0011] The beneficial effects brought by the technical solution provided in the embodiments of the present application include at least:
[0012] By performing anisotropic etching on the gate material of the second silicon layer 303, the gate material deposited outside the epitaxial silicon sidewall of the second silicon layer 303 is removed, and then the remaining gate material in the second silicon layer 303 is removed again, thereby avoiding a short circuit between the source / drain and the gate. BRIEF DESCRIPTION OF THE DRAWINGS
[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0014] Figure 1 is a schematic diagram of a VGAA transistor provided by one or more exemplary embodiments of the present application;
[0015] Figure 2 is a flow chart of a method for preparing a transistor provided by one or more exemplary embodiments of the present application;
[0016] Figure 3 is a schematic diagram of relevant steps of a method for preparing a transistor provided by one or more exemplary embodiments of the present application;
[0017] Figure 4 is a schematic diagram of relevant steps of a method for preparing a transistor provided by one or more exemplary embodiments of the present application;
[0018] Figure 5 is a schematic diagram of relevant steps of a method for preparing a transistor provided by one or more exemplary embodiments of the present application;
[0019] Figure 6 is a schematic diagram of relevant steps of a method for preparing a transistor provided by one or more exemplary embodiments of the present application;
[0020] Figure 7 is a schematic diagram of relevant steps of a method for preparing a transistor provided by one or more exemplary embodiments of the present application;
[0021] Figure 8is a schematic diagram of relevant steps of a method for preparing a transistor provided by one or more exemplary embodiments of the present application;
[0022] Fig. 9 is a schematic diagram of relevant steps of a method for preparing a transistor provided by one or more exemplary embodiments of the present application;
[0023] Fig.10 is a flow chart of a method for preparing a transistor provided by one or more exemplary embodiments of the present application;
[0024] Fig.11 is a schematic diagram of relevant steps of a method for preparing a transistor provided by one or more exemplary embodiments of the present application;
[0025] Fig.12 is a schematic diagram of relevant steps of a method for preparing a transistor provided by one or more exemplary embodiments of the present application;
[0026] Fig.13 is a schematic diagram of relevant steps of a method for preparing a transistor provided by one or more exemplary embodiments of the present application;
[0027] Fig.14 is a schematic diagram of relevant steps of a method for preparing a transistor provided by one or more exemplary embodiments of the present application;
[0028] Fig.15 is a schematic diagram of relevant steps of a method for preparing a transistor provided by one or more exemplary embodiments of the present application;
[0029] Fig.16 is a schematic diagram of relevant steps of a method for preparing a transistor provided by one or more exemplary embodiments of the present application;
[0030] Fig.17 is a schematic diagram of a stacking structure provided by one or more exemplary embodiments of the present application;
[0031] Fig.18 is a schematic diagram of a stacking structure provided by one or more exemplary embodiments of the present application;
[0032] Fig.19 is a schematic diagram of a process for forming a stacked structure provided by one or more exemplary embodiments of the present application;
[0033] Fig. 20 is a schematic diagram of a formation process of a stacking structure provided by one or more exemplary embodiments of the present application;
[0034] Fig.21 is a schematic diagram of a formation process of a stacking structure provided by one or more exemplary embodiments of the present application;
[0035] Fig. 22 It is a schematic diagram of a formation process of a stacking structure provided by one or more other exemplary embodiments of the present application. DETAILED DESCRIPTION
[0036] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.
[0037] In an embodiment of the present application, a method for preparing a transistor is provided. Optionally, the method for preparing the transistor is mainly applied in a process for preparing a VGAA transistor.
[0038] First, the structure of the VGAA transistor is introduced. Figure 1 As shown, the transistor array 100 includes a plurality of transistor cells 110. Each transistor cell 110 includes a bit line (BL) 111, a word line (WL) 112, a source / drain 113, and a gate 114.
[0039] Among them, multiple transistor units 110 in the same column of the transistor array 100 are connected by coupling with the extended bit line 111; multiple transistor units 110 in the same row of the transistor array 100 are connected by coupling with the extended word line 112.
[0040] The word line 112 is connected to the gate 114 and serves as a gate line to turn on the transistor unit 110 . The bit line 111 is connected to the source / drain 113 and serves as a data signal writing line. The word line 112 surrounds the gate 114 .
[0041] Figure 2 A flowchart of a method for preparing a transistor provided by an exemplary embodiment of the present application is shown, the method comprising:
[0042] Step 201, stacking a first silicon layer, a silicon germanium layer, and a second silicon layer in sequence on a silicon substrate;
[0043] Combined with reference Figure 3 , Figure 3 It is shown that a first silicon layer 301 , a silicon germanium layer 302 and a second silicon layer 303 are sequentially stacked on a silicon substrate 300 ; wherein the first silicon layer 301 is in contact with the silicon substrate 300 .
[0044] Step 202, forming a plurality of first silicon pillars along a first direction by etching the first silicon layer, the silicon germanium layer and the second silicon layer;
[0045] In one embodiment, a plurality of columns of first masks are formed on the second silicon layer along a first direction; the first silicon layer, the silicon germanium layer and the second silicon layer are etched according to the plurality of columns of first masks to form a plurality of first silicon pillars along the first direction.
[0046] A plurality of columns of first masks are formed along a first direction on the second silicon layer 303. Optionally, the first direction is the direction of the bit line of the transistor finally generated. Optionally, the mask material includes a photoresist material, a photoresist, an anti-reflection material, and some hard mask materials. The plurality of columns of first masks extend along the first direction.
[0047] Combined with reference Figure 4 , Figure 4 The three-dimensional structure obtained by etching the silicon substrate 300, the first silicon layer 301, the silicon germanium layer 302 and the second silicon layer 303 according to multiple columns of the first mask is shown. Figure 4 A plurality of first silicon pillars 304 along a first direction are shown. In one embodiment, a SADP (Self-Aligned Double Patterning) process is used to etch the silicon substrate 300, the first silicon layer 301, the silicon germanium layer 302, and the second silicon layer 303. In one embodiment, SADP is used for etching according to the array period size or the critical size. In one embodiment, SAQP (Self-aligned Quadruple Patterning) is used for etching according to the array period size or the critical size. In one embodiment, LELE (Litho-Etch-Lith-Etch) is used for etching according to the array period size or the critical size. In one embodiment, a dry process is used for etching.
[0048] Step 203, forming a plurality of columns of second masks along a second direction on the plurality of first silicon pillars, wherein the second masks include sidewalls;
[0049] Combined with reference Figure 5 , Figure 5 A plurality of columns of second masks 305 are shown. The plurality of columns of second masks 305 extend along a second direction. Optionally, the second direction is the direction of a word line of a transistor finally generated.
[0050] Step 204, etching the first silicon layer, the silicon germanium layer and the second silicon layer according to the second mask of multiple columns; based on the grooves obtained by etching, continuing to etch the silicon germanium layer to form lateral grooves; and laterally epitaxially growing silicon on the first silicon layer, the lateral grooves and the second silicon layer;
[0051] Combined with reference Figure 6 , Figure 6 Part (A) shows the three-dimensional structure formed after performing a lateral epitaxial silicon operation. Figure 6Part (B) shows a two-dimensional plan view of the corresponding three-dimensional structure observed along the second direction.
[0052] Step 205, depositing a gate material on the first silicon layer; performing anisotropic etching of the gate material according to the plurality of sidewalls to remove the gate material outside the epitaxial silicon sidewalls of the second silicon layer; and then removing the plurality of sidewalls and the gate material in the second silicon layer to form a plurality of second silicon pillars;
[0053] Optionally, the gate material includes at least one of a gate oxide layer, a high-K material and a gate metal layer.
[0054] Optionally, the gate material includes dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, zirconium oxide, and other dielectric materials, and conductive materials such as polysilicon, tantalum, aluminum, and tungsten.
[0055] Combined with reference Figure 7 , Figure 7 Part (A) shows a three-dimensional structure obtained by depositing gate materials in gaps among the silicon germanium layer 302 , the second silicon layer 303 , and the plurality of spacers 305 - 1 . Figure 7 Part (B) shows a two-dimensional schematic diagram of the corresponding three-dimensional structure observed along the second direction. That is, Figure 7 The three-dimensional structure obtained by filling the gate material above the first silicon layer 301 is shown.
[0056] Combined with reference Figure 8 , Figure 8 Part (A) shows a three-dimensional structure obtained by anisotropically etching the gate material according to the plurality of sidewall spacers 305 - 1 in the plurality of columns of the second mask 305 . Figure 8 Part (B) shows a two-dimensional schematic diagram of the corresponding three-dimensional structure observed along the second direction. In one embodiment, after performing anisotropic etching of the gate material, metal residues on the sidewalls of the plurality of sidewalls 305-1 and the epitaxial silicon sidewalls of the second silicon layer 303 are also removed. In one embodiment, after performing anisotropic etching of the gate material, the sidewalls of the silicon germanium layer 302 are also aligned with the sidewalls of the plurality of sidewalls 305-1.
[0057] Combined with reference Fig. 9 , Fig. 9 Part (A) shows a three-dimensional structural diagram of a plurality of second silicon pillars 306 formed by further removing a plurality of sidewalls 305 - 1 and gate materials in the second silicon layer 303 . Fig. 9 Part (B) shows a two-dimensional schematic diagram of the corresponding three-dimensional structure observed along the second direction. Fig. 9 The plurality of second silicon pillars 306 are shown to be distributed in an array along the first direction and the second direction.
[0058] Step 206 , forming a vertical all-around gate transistor based on the plurality of second silicon pillars.
[0059] In one embodiment, a vertical all-around gate transistor is formed based on the plurality of second silicon pillars 306 by adding contact pins.
[0060] In summary, by performing anisotropic etching on the gate material of the second silicon layer 303, the gate material deposited outside the epitaxial silicon sidewall of the second silicon layer 303 is removed, and then the remaining gate material in the second silicon layer 303 is removed again, thereby avoiding a short circuit between the source / drain and the gate.
[0061] Fig.10 A flowchart of a method for preparing a transistor provided by an exemplary embodiment of the present application is shown, the method comprising:
[0062] Step 1001, stacking a first silicon layer, a silicon germanium layer, and a second silicon layer in sequence on a silicon substrate;
[0063] Combined with reference Fig.11 , Fig.11 Part (A) of FIG. 3 shows that a first silicon layer 301 , a silicon germanium layer 302 , and a second silicon layer 303 are sequentially stacked on a silicon substrate 300 , wherein the first silicon layer 301 is in contact with the silicon substrate 300 .
[0064] Step 1002 , forming a plurality of first silicon pillars along a first direction by etching the first silicon layer, the silicon germanium layer, and the second silicon layer.
[0065] In one embodiment, a plurality of columns of first masks are formed on the second silicon layer along a first direction; the first silicon layer, the silicon germanium layer and the second silicon layer are etched according to the plurality of columns of first masks to form a plurality of first silicon pillars along the first direction.
[0066] A plurality of columns of first masks are formed along a first direction on the second silicon layer 301. Optionally, the first direction is the direction of the bit line of the transistor finally formed. The mask material includes a photoresist material, a photoresist, an anti-reflection material, and some hard mask materials. Optionally, the first mask extends along the first direction.
[0067] Combined with reference Fig.11 , Fig.11 Part (B) shows that the first silicon layer 301, the silicon germanium layer 302, and the second silicon layer 303 are etched according to multiple columns of the first mask to form a three-dimensional structure of multiple first silicon pillars 304 along the first direction. In one embodiment, the partial volume of the first silicon layer 301, the silicon germanium layer 302, and the second silicon layer 303 that is not within the coverage of the first mask is etched away. In one embodiment, the etching is performed using a dry process.
[0068] In one embodiment, SADP is used for etching according to the array period size or the critical size. In one embodiment, SAQP (Self-aligned Quadruple Patterning) is used for etching according to the array period size or the critical size. In one embodiment, LELE (Litho-Etch-Lith-Etch) is used for etching according to the array period size or the critical size.
[0069] Step 1003, filling oxide between the plurality of first silicon pillars;
[0070] Combined with reference Fig.11 , Fig.11 Part (C) shows the three-dimensional structure obtained by oxide between the plurality of first silicon pillars 304. Optionally, the oxide is silicon dioxide.
[0071] Step 1004, forming a plurality of columns of second masks along a second direction on the plurality of first silicon pillars, the second masks comprising sidewalls;
[0072] Combined with reference Fig.12 , Fig.12 Part (A) of FIG. 3 shows a three-dimensional structure obtained by forming a plurality of columns of second masks 305 along the second direction on the plurality of first silicon pillars 304. The second masks 305 extend along the second direction.
[0073] Step 1005, etching the first silicon layer, the silicon germanium layer and the second silicon layer according to a plurality of columns of second masks to form a plurality of first grooves;
[0074] Combined with reference Fig.12 , Fig.12 Part (B) shows a three-dimensional structure obtained by etching the first silicon layer 301, the silicon germanium layer 302, and the second silicon layer 303 according to the multiple columns of second masks 305 to form multiple first grooves 307. In one embodiment, the partial volume of the first silicon layer 301, the silicon germanium layer 302, and the second silicon layer 303 that is not covered by the multiple columns of second masks 305 is etched away. Fig.12 Part (B) of FIG. 3 also shows any one of the plurality of second masks 305, including a three-layer structure of a spacer 305-1, a mandrel 305-2 and a spacer 305-1. In one embodiment, a dry process is used for etching.
[0075] Step 1006, performing a first lateral etching on the silicon germanium layer;
[0076] Combined with reference Fig.12 , Fig.12 Part (C1) shows a three-dimensional structure obtained by performing the first lateral etching on the silicon germanium layer 302.
[0077] Fig.12 Part (C2) shows a two-dimensional plane view obtained by observing the corresponding three-dimensional structure in the second direction. In one embodiment, the second direction is the word line direction. The second direction is the direction of the word line of the transistor finally generated.
[0078] In one embodiment, the first lateral etching is performed using an ALE (Atomic Layer Etch) process.
[0079] Step 1007, performing a first lateral epitaxial silicon growth on the first silicon layer, the silicon germanium layer and the second silicon layer to form a first lateral groove; filling the first lateral groove with oxide and grinding it flat; filling the first groove with oxide and grinding it flat;
[0080] Combined with reference Fig.13 , Fig.13 Part (A1) shows a three-dimensional structure obtained by performing a first lateral epitaxial silicon growth on the first silicon layer 301 , the silicon germanium layer 302 , and the second silicon layer 303 to form a first lateral groove 308 . Fig.13 Part (A2) shows a two-dimensional plan view of the corresponding three-dimensional structure observed along the second direction.
[0081] Fig.13 Part (B1) shows a three-dimensional structure obtained by filling the first lateral groove 308 and the first groove 307 with oxide and then grinding them flat. Fig.13 Part (B2) shows a two-dimensional plane view of the corresponding three-dimensional structure observed along the second direction. In one embodiment, the flattening operation is performed by CMP (Chemical Mechanical Polishing).
[0082] Step 1008, etching the first silicon layer, the silicon germanium layer, and the second silicon layer according to the plurality of mandrels in the plurality of columns of the second mask to form a plurality of second grooves;
[0083] Combined with reference Fig.13 , Fig.13 Part (C1) shows a three-dimensional structure in which a plurality of second grooves 309 are formed by etching the first silicon layer 301 , the silicon germanium layer 302 , and the second silicon layer 303 according to a plurality of mandrels 305 - 2 in a plurality of columns of the second mask 305 . Fig.13 Part (C2) shows a two-dimensional plan view of the corresponding three-dimensional structure observed along the second direction.
[0084] In one embodiment, the first silicon layer 301, the silicon germanium layer 302 and the second silicon layer 303 are partially covered by the plurality of mandrels 305-2 and etched away. In one embodiment, the first silicon layer 301, the silicon germanium layer 302 and the second silicon layer 303 are partially covered by the plurality of spacers 305-1 and etched away.
[0085] In one embodiment, a wet process or an ALE (Atomic Layer Etch) process is used to etch the first silicon layer 301 , the silicon germanium layer 302 , and the second silicon layer 303 to form a plurality of second grooves 309 .
[0086] Step 1009, performing a second lateral etching on the silicon germanium layer;
[0087] Combined with reference Fig.14 , Fig.14 Part (A1) shows a three-dimensional structure obtained by performing a second lateral etching on the silicon germanium layer 302 . Fig.14 Part (A2) shows a two-dimensional plan view of the corresponding three-dimensional structure observed along the second direction. Combined with the first lateral etching of the silicon germanium layer 302 in step 1007, the two lateral etchings enable the silicon germanium material of the silicon germanium layer 302 to be completely removed.
[0088] Step 1010, performing a second lateral epitaxial silicon growth on the first silicon layer, the silicon germanium layer and the second silicon layer to form a second lateral groove, filling the second lateral groove with oxide and grinding it flat; filling the second groove with oxide and grinding it flat;
[0089] Combined with reference Fig.14 , Fig.14 Part (B1) shows that a second lateral epitaxial silicon growth is performed on the first silicon layer 301 , the silicon germanium layer 302 , and the second silicon layer 303 to form a three-dimensional structure of a second lateral groove 310 . Fig.14 Part (B2) shows a two-dimensional plan view of the corresponding three-dimensional structure observed along the second direction.
[0090] Fig.14 Part (C1) shows the three-dimensional structure obtained by filling the second lateral groove 310 with oxide and grinding it flat, and by filling the second groove 309 with oxide and grinding it flat. Fig.14 Part (C2) shows a two-dimensional plan view of the corresponding three-dimensional structure. Optionally, the oxide is silicon dioxide.
[0091] In one embodiment, the planarizing operation is performed by CMP (Chemical Mechanical Polishing).
[0092] Step 1011, etching the oxide on the first silicon layer;
[0093] Combined with reference Fig.15 , Fig.15 Part (A1) shows the three-dimensional structure after the second silicon layer 303 and the oxide between the plurality of spacers 305 - 1 are etched. Fig.15Part (A2) of FIG. 1 shows a two-dimensional plane view of the corresponding three-dimensional structure. Fig.15 , Fig.15 Part (B1) shows the three-dimensional structure after the oxide of the silicon germanium layer 302 is further etched. Fig.15 Part (B2) shows a two-dimensional plane view of the corresponding three-dimensional structure. That is, Fig.15 Parts (A1), (A2), (B1), and (B2) show schematic diagrams after the oxide above the first silicon layer is etched.
[0094] In one embodiment, the oxide on the silicon germanium layer 302 is etched by a dry process; and then the oxide on the silicon germanium layer 302 is etched by a wet process.
[0095] Step 1012, depositing a gate material in the gaps between the silicon germanium layer, the second silicon layer, and the plurality of spacers;
[0096] Optionally, the gate material includes at least one of a gate oxide layer, a high-K material and a gate metal layer. Optionally, the gate material includes dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, zirconium oxide, and conductive materials such as polysilicon, tantalum, aluminum, and tungsten.
[0097] Combined with reference Fig.15 , Fig.15 Part (C1) shows a three-dimensional structure obtained by depositing a gate material in the gaps among the silicon germanium layer 302, the second silicon layer 303 and the plurality of spacers 305-1. Fig.15 Part (C2) shows a two-dimensional plane view of the corresponding three-dimensional structure. That is, Fig.15 Parts (C1) and (C2) show schematic diagrams of a three-dimensional structure obtained by depositing a gate material in the gap above the first silicon layer 301 .
[0098] Step 1013, performing anisotropic etching of the gate material on the layer where the multiple sidewalls are located, etching to the sidewalls of the multiple sidewalls; and performing anisotropic etching of the gate material on the second silicon layer, etching to the epitaxial silicon sidewalls of the second silicon layer; and performing anisotropic etching of the gate material on the silicon germanium layer outside the coverage of the multiple sidewalls in the multiple columns of the second mask;
[0099] Combined with reference Fig.16 , Fig.16Part (A1) shows a three-dimensional structure obtained by performing anisotropic etching of gate materials on the layer where the multiple sidewalls 305-1 are located, the second silicon layer 303 and the silicon germanium layer 302. The metal anisotropic etching of the layer where the multiple sidewalls 305-1 are located will etch to the sidewalls of the multiple sidewalls, the metal anisotropic etching of the second silicon layer 303 will etch to the epitaxial silicon sidewalls, and the metal anisotropic etching of the silicon germanium layer 302 will etch to the coverage boundary of the multiple sidewalls 305-1. Fig.16 Part (A2) shows a two-dimensional plan view of the corresponding three-dimensional structure observed along the second direction.
[0100] In one embodiment, after performing anisotropic etching of the gate material, metal residues on the sidewalls of the plurality of spacers 305-1 and the epitaxial silicon sidewalls of the second silicon layer 303 are removed. In one embodiment, after performing anisotropic etching of the gate material, the sidewalls of the silicon germanium layer 302 are aligned with the sidewalls of the plurality of spacers 305-1.
[0101] Step 1014, filling oxide in the gaps between the silicon germanium layer, the second silicon layer, and the plurality of spacers;
[0102] Combined with reference Fig.16 , Fig.16 Part (B1) shows a three-dimensional structure obtained by filling oxide in the gaps between the silicon germanium layer 302, the second silicon layer 303, and the plurality of spacers 305-1. Fig.16 Part (B2) of FIG. 1 shows a two-dimensional plane view of the corresponding three-dimensional structure observed along the second direction. That is, Fig.16 Part (B1) and part (B2) of the diagram show a three-dimensional structure obtained by filling oxide on the first silicon layer 301. Optionally, the oxide is silicon dioxide.
[0103] Step 1015, removing a plurality of side walls;
[0104] Step 1016, removing the remaining gate material in the second silicon layer to form a plurality of second silicon pillars;
[0105] Combined with reference Fig.16 , Fig.16 Part (C1) shows a three-dimensional structure obtained by removing a plurality of spacers 305 - 1 and the remaining gate material in the second silicon layer 303 . Fig.16 Part (C2) shows a two-dimensional plan view of the corresponding three-dimensional structure observed along the second direction. Fig.16 Portions (C1) and (C2) of FIG. 3 show the second silicon pillar 306 .
[0106] Step 1017 , forming a vertical all-around gate transistor based on the plurality of second silicon pillars.
[0107] In one embodiment, a vertical all-around gate transistor is formed by adding contact pins based on the plurality of second silicon pillars 306. In this embodiment, the vertical all-around gate transistor is also called a metal ring gate transistor or a metal replaceable gate transistor.
[0108] In summary, by performing anisotropic etching on the gate material of the second silicon layer 303, the gate material deposited outside the epitaxial silicon sidewall of the second silicon layer 303 is removed, and then the remaining gate material in the second silicon layer 303 is removed again, thereby avoiding a short circuit between the source / drain and the gate.
[0109] In one embodiment, step 202 or step 1002 includes: forming a plurality of first silicon pillars along a first direction by etching the silicon substrate, the first silicon layer, the silicon germanium layer, and the second silicon layer.
[0110] based on Figure 2 and Fig.10 In the method embodiment shown, when executing step 201 and step 1001 , well isolation is also formed in the stack structure.
[0111] In one embodiment, in conjunction with reference Fig.17 , Fig.17 Part (A1) shows the stack structure after well isolation is formed. Fig.17 Part (A2) shows a two-dimensional plan view of the stacked structure. Considering the stacked structure after well isolation, it includes a silicon substrate 300, a first silicon layer 301, a silicon germanium layer 302 and a second silicon layer 303. Further, the silicon substrate 300 includes an upper silicon substrate 300-1 and a lower silicon substrate 300-2. Optionally, the lower silicon substrate 300-2 is doped to N type, the upper silicon substrate 300-1 is doped to P type, and the first silicon layer 301 is doped to P type. Optionally, the lower silicon substrate 300-2 is doped to P type, the upper silicon substrate 300-1 is doped to N type, and the first silicon layer 301 is doped to N type.
[0112] It can be noted that Fig.17 Part (B1) shows the three-dimensional structure of the plurality of first silicon pillars 307 obtained after taking well isolation into consideration. Fig.17 At this time, the longitudinal etching depth of the first silicon pillar 307 only reaches the upper part of the silicon substrate 300-1, and the plurality of first silicon pillars 307 (i.e., bit lines) are isolated from each other by the PN junction structure to prevent leakage between the first silicon pillars 307.
[0113] In one embodiment, in conjunction with reference Fig.18 , Fig.18 Part (A1) shows the stack structure after well isolation is formed. Fig.18Part (A2) shows a two-dimensional plan view of the stacked structure. Considering the stacked structure after well isolation, it includes a silicon substrate 300, a first silicon layer 301, a silicon germanium layer 302, a second silicon layer 303, and a third silicon layer 304 located between the silicon substrate 300 and the first silicon layer. Optionally, the silicon substrate 300 is doped to P type, and the first silicon layer 301 and the third silicon layer 304 are doped to N type.
[0114] It can be noted that Fig.18 Part (B1) shows the three-dimensional structure of the plurality of first silicon pillars 307 obtained after taking well isolation into consideration. Fig.18 At this time, the longitudinal etching depth of the first silicon pillars 307 only reaches the third silicon layer 304, and the plurality of first silicon pillars 307 (ie, bit lines) are isolated from each other by the PN junction structure to prevent leakage between the first silicon pillars 307.
[0115] Illustratively, the following four possible implementations of step 201 and step 1001 are provided.
[0116] A first possible implementation method is to obtain a silicon substrate; dope the lower part of the silicon substrate into N-type and dope the upper part of the silicon substrate into P-type; sequentially stack a first silicon layer, a silicon germanium layer and a second silicon layer on the silicon substrate; dope the first silicon layer into P-type. Optionally, after doping the silicon substrate, annealing is performed to restore the silicon substrate lattice.
[0117] Combined with reference Fig.19 , Fig.19 Part (A) shows a silicon substrate 300; Fig.19 Part (B) of FIG. 1 shows a lower portion of the silicon substrate 300 - 1 doped with N type and an upper portion of the silicon substrate 300 - 2 doped with P type. Fig.19 Part (C) shows the stacked first silicon layer 301 , silicon germanium layer 302 , and second silicon layer 303 , wherein the first silicon layer 301 is doped to a P type.
[0118] A second possible implementation method is to obtain a silicon substrate; dope the lower part of the silicon substrate into P type, and dope the upper part of the silicon substrate into N type; sequentially stack a first silicon layer, a silicon germanium layer, and a second silicon layer on the silicon substrate; and dope the first silicon layer into N type. Optionally, after doping the silicon substrate, an annealing operation is performed to restore the silicon substrate lattice.
[0119] Combined with reference Fig. 20 , Fig. 20 Part (A) shows a silicon substrate 300; Fig. 20 Part (B) of FIG. 1 shows a lower portion of the silicon substrate 300 - 1 doped with a P type and an upper portion of the silicon substrate 300 - 2 doped with an N type. Fig. 20 Part (C) shows the stacked first silicon layer 301 , silicon germanium layer 302 , and second silicon layer 303 , and the first silicon layer 301 is doped to N type.
[0120] A third possible implementation method is to obtain a silicon substrate; dope the silicon substrate into N-type; sequentially stack a third silicon layer, a first silicon layer, a silicon germanium layer, and a second silicon layer on the silicon substrate; and dope the third silicon layer and the first silicon layer into P-type.
[0121] Combined with reference Fig.21 , Fig.21 Part (A) shows a silicon substrate 300; Fig.21 Part (B) of FIG. 1 shows a silicon substrate 300 doped to an N-type. Fig.21 Part (C) shows the stacked third silicon layer 304, the first silicon layer 301, the silicon germanium layer 302 and the second silicon layer 303. The third silicon layer 304 is doped to P type, and the first silicon layer 301 is doped to P type.
[0122] A fourth possible implementation method is to obtain a silicon substrate; dope the silicon substrate into P type; sequentially stack a third silicon layer, a first silicon layer, a silicon germanium layer, and a second silicon layer on the silicon substrate; and dope the third silicon layer and the first silicon layer into N type.
[0123] Combined with reference Fig. 22 , Fig. 22 Part (A) shows a silicon substrate 300; Fig. 22 Part (B) of FIG. 1 shows a silicon substrate 300 doped to a P type. Fig. 22 Part (C) shows the stacked third silicon layer 304, the first silicon layer 301, the silicon germanium layer 302 and the second silicon layer 303. The third silicon layer 304 is doped to N type, and the first silicon layer 301 is doped to N type.
[0124] An embodiment of the present application provides an electronic device, wherein the electronic device includes a logic device, wherein the logic device includes a 3D NAND gate circuit as provided in the above embodiment. The logic device can be applied to a logic operator and a memory, etc.
[0125] Optionally, the electronic device includes a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device or a smart mobile terminal.
[0126] In the present application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. The term "at least one" means one or more, and the term "plurality" means two or more, unless otherwise clearly defined.
[0127] The term "and / or" in this application is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.
[0128] The above description is only an exemplary embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.
Claims
1. A method for preparing a transistor, characterized in that: The method comprises: A first silicon layer (301), a silicon germanium layer (302) and a second silicon layer (303) are sequentially stacked on a silicon substrate (300), wherein the first silicon layer (301) is in contact with the silicon substrate (300); Forming a plurality of first silicon pillars (304) along a first direction by etching the first silicon layer (301), the silicon germanium layer (302) and the second silicon layer (303); Forming a plurality of columns of second masks (305) along a second direction on the plurality of first silicon pillars (304), the second masks (305) comprising sidewalls (305-1); etching the first silicon layer (301), the silicon germanium layer (302) and the second silicon layer (303) according to the plurality of columns of second masks (305); etching the silicon germanium layer (302) on the basis of the grooves obtained by etching to form lateral grooves; etching the first silicon layer (301), the lateral grooves and the second silicon layer (303) lateral epitaxial silicon; depositing gate material on the first silicon layer (301); performing anisotropic etching on the gate material according to the plurality of sidewalls (305-1) to remove the gate material outside the epitaxial silicon sidewalls of the second silicon layer (303); then removing the plurality of sidewalls (305-1) and the gate material in the second silicon layer (303) to form a plurality of second silicon pillars (306), wherein the plurality of second silicon pillars (306) are distributed in an array along the first direction and the second direction; Based on the plurality of second silicon pillars (306), a vertical all-around gate transistor is formed.
2. The method according to claim 1, characterized in that: The anisotropic etching of the gate material is performed according to the plurality of sidewalls (305-1), comprising: Anisotropic etching of the gate material is performed on the layer where the multiple sidewalls (305-1) are located, and the etching is performed to the sidewalls of the multiple sidewalls (305-1); and anisotropic etching of the gate material is performed on the second silicon layer (303), and the etching is performed to the epitaxial silicon sidewalls of the second silicon layer (303); and, outside the coverage range of the multiple sidewalls (305-1), anisotropic etching of the gate material is performed on the silicon germanium layer (302).
3. The method according to claim 1 or 2, characterized in that: The first silicon layer (301), the silicon germanium layer (302) and the second silicon layer (303) are etched according to the plurality of second masks (305); based on the grooves obtained by etching, the silicon germanium layer (302) is further etched to form lateral grooves; Laterally epitaxial silicon is grown on the first silicon layer (301), the lateral groove and the second silicon layer (303), comprising: Etching the first silicon layer (301), the silicon germanium layer (302) and the second silicon layer (303) according to the plurality of second masks (305) to form a plurality of first grooves (307); performing a first lateral etching on the silicon germanium layer (302), and then performing a first lateral epitaxial silicon growth on the first silicon layer (301), the silicon germanium layer (302) and the second silicon layer (303) to form first lateral grooves (308); The first silicon layer (301), the silicon germanium layer (302) and the second silicon layer (303) are etched according to the multiple core shafts (305-2) in the multiple columns of the second mask (305) to form a plurality of second grooves (309); a second lateral etching is performed on the silicon germanium layer (302), and then a second lateral epitaxial silicon growth is performed on the first silicon layer (301), the silicon germanium layer (302) and the second silicon layer (303) to form second lateral grooves (310), and the two lateral etchings enable the silicon germanium material of the silicon germanium layer (302) to be completely removed.
4. The method according to claim 3, characterized in that After forming the first lateral groove (308), the method further includes: filling the first lateral groove (308) with oxide and grinding it flat; filling the first groove (307) with oxide and grinding it flat; After forming the second lateral groove (310), the method further includes: filling the second lateral groove (310) with oxide and grinding it flat; and filling the second groove (309) with oxide and grinding it flat.
5. The method according to claim 4, characterized in that The step of depositing a gate material on the first silicon layer (301) comprises: Etching the oxide above the first silicon layer (301); The gate material is deposited in the gaps between the silicon germanium layer (302), the second silicon layer (303) and the plurality of spacers (305-1).
6. The method according to claim 5, characterized in that The etching of the oxide on the first silicon layer 301 includes: Etching the oxide above the silicon germanium layer (302) by a dry process; The oxide of the silicon germanium layer (302) is then etched using a wet process.
7. The method according to claim 5, characterized in that The step of removing the plurality of sidewalls (305-1) and the gate material in the second silicon layer (303) to form a plurality of second silicon pillars (306) comprises: Filling oxide in the gaps between the silicon germanium layer (302), the second silicon layer (303), and the plurality of sidewalls (305-1); Removing the plurality of side walls (305-1); The remaining gate material in the second silicon layer (303) is removed to form the plurality of second silicon pillars (306).
8. The method according to claim 1 or 2, characterized in that: Any second mask (305) in the plurality of columns of second masks (305) comprises a three-layer structure of a side wall (305-1), a core shaft (305-2) and a side wall (305-1).
9. An electronic device, characterized in that: The electronic device comprises a logic device, and the logic device comprises a transistor manufactured according to the method for manufacturing a transistor as claimed in any one of claims 1 to 8.
10. The electronic device according to claim 9, characterized in that: The electronic device includes a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device or a smart mobile terminal.