P-channel VDMOS device and preparation method thereof
Through the two source area ion implantation process, boron difluoride and boron form a continuous source area, the problem of difficult control of the consistency of gate source and drain and threshold voltage in the back gate oxygen process of P-channel VDMOS devices is solved, and the problem of difficulty in controlling the consistency of gate source and drain and threshold voltage in the rear gate oxygen process is realized. More stable device performance.
Patent Information
- Application Number
- CN202411310054.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-19
- Publication Date
- 2025-01-10
AI Technical Summary
The existing P-channel VDMOS devices have gate source and drain problems in the rear gate oxygen process, and the threshold voltage consistency is difficult to control, mainly due to the injection damage and interface state problems caused by high concentration boron injection.
The ion implantation process of the source area is adopted. The first injection uses boron difluoride to control the channel. The second injection uses boron to form a continuous and suitable source area with a width. The injection dose is reduced before the gate oxidation step and the interface state is reduced. question.
It effectively improves the gate source and drain increase problem of P-channel VDMOS devices, improves the consistency of the device threshold voltage, and avoids changes in other device parameters.
Smart Images
Figure CN119300389A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a P-channel VDMOS device and a preparation method thereof. Background Art
[0002] In the field of power semiconductors, VDMOS is widely used due to its fast switching speed and high input impedance. Among them, P-channel VDMOS plays an irreplaceable role in electronic systems because it can effectively simplify circuit structure and improve circuit performance.
[0003] Conventional VDMOS production processes use polysilicon self-aligned processes, and the formation of the gate oxide layer and the deposition of polysilicon are completed before the body and source regions are injected. The gate oxide layer will undergo high-temperature thermal processes such as well-pushing, resulting in many oxide layer defects and interface states, and poor gate oxide quality. Therefore, in areas where the reliability of the VDMOS gate oxide layer is required to be high, the last gate oxide process is usually used, that is, the gate oxidation step is arranged after the body and source regions are injected, so as to avoid the gate oxide layer from experiencing high-temperature thermal processes, reduce gate oxide layer defects and interface states, and improve the gate oxide layer quality.
[0004] At present, the post-gate oxide production process of P-channel VDMOS is generally as follows: a semiconductor epitaxial layer is formed on a semiconductor substrate, a body region and a source region are formed in sequence on the surface of the epitaxial layer by injection, a gate oxide layer and a polysilicon gate are grown, gate etching is performed, an isolation dielectric layer is grown, a contact hole passes through the isolation dielectric layer and is connected to the source region, the body region, and the polysilicon gate, and a front metal is deposited to form an ohmic contact between the source and the gate. In the prior art, the device threshold voltage is mainly ensured by adjusting the gate oxide layer thickness and the body region and source region injection dose. For P-channel VDMOS produced by the post-gate oxide process, the impurity injected into the source region is boron, which is easier to diffuse and enter the gate oxide layer. A higher source region injection dose is usually required to ensure source contact. High-concentration boron injection will introduce more injection damage and interface states, which may cause the device to have a risk of gate-source leakage in severe cases. In addition, high-concentration boron injection is easily affected by thermal processes such as gate oxidation, making it difficult to control the threshold voltage consistency of P-channel VDMOS devices produced by the post-gate oxide process.
[0005] To improve the gate-source leakage of P-channel VDMOS, the gate oxide thickness can be increased to increase the gate oxide breakdown voltage. Although this method can effectively enhance the anti-breakdown capability of the gate oxide and reduce the gate-source leakage current, it will also increase the device threshold voltage, reduce the transconductance, and cause changes in device parameters. It is also possible to repair ion implantation damage by increasing the source region post-injection annealing treatment. Although this method can repair ion implantation damage to a certain extent and reduce the gate-source leakage current, increasing the source region post-injection annealing temperature or time will cause the redistribution and lateral diffusion of the implanted impurities, and may produce secondary defects, causing changes in device parameters such as reduced threshold voltage and increased source-drain current.
[0006] In view of this, the present invention is proposed. Summary of the invention
[0007] The object of the present invention is to provide a method for preparing a P-channel VDMOS device, which improves the problem of increased gate-source leakage of the P-channel VDMOS device produced by the existing gate-last oxide process and improves the consistency of the device threshold voltage.
[0008] The present invention provides a method for preparing a P-channel VDMOS device, comprising the following steps:
[0009] Forming a semiconductor epitaxial layer on a semiconductor substrate, forming a mask layer on the surface of the semiconductor epitaxial layer, using the first mask layer as a mask, sequentially performing body region implantation and first source region implantation in the semiconductor epitaxial layer to form a body region and a first source region;
[0010] removing the first photoresist layer and the first mask layer, and sequentially forming a gate oxide layer and a polysilicon layer;
[0011] Etching the polysilicon layer to form a polysilicon gate, then coating photoresist to form a second photoresist layer, using the second photoresist layer as a mask, performing a second source region implantation on the body region and the first source region to form a second source region;
[0012] The second photoresist layer is removed, and an isolation dielectric layer and a metal layer are deposited in sequence.
[0013] As a preferred embodiment of the present technical solution, the window for the first source region injection and the window for the second source region injection partially overlap.
[0014] As a preferred embodiment of the present technical solution, during the first source region injection, the injected impurity is boron difluoride, the injection energy is 50KeV-80KeV, and preferably 60KeV-70KeV, and the injection dose is 1E14-8E14, and preferably 5E14-6E14.
[0015] As a preferred embodiment of the present technical solution, during the second source region injection, the injected impurity is boron, the injection energy is 50KeV-80KeV, and preferably 50KeV-60KeV, and the injection dose is 1E15-8E15, and preferably 4E15-5E15.
[0016] As a preferred embodiment of the present technical solution, when forming the first mask layer on the surface of the semiconductor epitaxial layer, a mask film is deposited on the surface of the semiconductor epitaxial layer, and the mask film in the body region of the mask film is etched to form the first mask layer.
[0017] As a preferred embodiment of the present technical solution, during the first source region injection, a photoresist film is coated on the body region, the photoresist in the first source region injection window area of the photoresist film is removed to form a first photoresist layer, and the first mask layer and the first photoresist layer are used as masks to perform the first source region injection on the body region to form a first source region.
[0018] As a preferred embodiment of the present technical solution, during the second source region injection, the polysilicon layer is etched to form a polysilicon gate, and then a photoresist film is coated, and the photoresist in the second source region injection window area of the photoresist film is removed to form a second photoresist layer, and the second source region injection is performed on the body region and the first source region using the second photoresist layer as a mask to form a second source region.
[0019] As a preferred embodiment of the present technical solution, the first source region and the second source region form a source region with a continuous junction and an appropriate width.
[0020] As a preferred embodiment of the present technical solution, the semiconductor substrate, the semiconductor epitaxial layer, the first source region and the second source region are all P-type doped, and the body region is N-type doped.
[0021] The present invention also provides a P-channel VDMOS device prepared by the above preparation method, which should also fall within the protection scope of the present invention.
[0022] The method for preparing a P-channel VDMOS device of the present invention has at least the following beneficial effects:
[0023] In the method of preparing a P-channel VDMOS device using a gate-last oxidation process of the present invention, the device channel is controlled by a first source region injection, the source ohmic contact is ensured by a second source region injection, and the two source region ion injection processes form a source region with a continuous junction and an appropriate width, which not only does not cause changes in other device parameters, but also can improve the consistency of the threshold voltage; in addition, the process of two source region ion injections can also reduce the first source region injection dose before the gate oxidation step, thereby reducing the interface state problem that may be introduced, and improving the phenomenon of increased gate-source leakage of the P-channel VDMOS device produced by the gate-last oxidation process. Therefore, the preparation method of the P-channel VDMOS device of the present invention effectively improves the problem of increased gate-source leakage of the P-channel VDMOS device produced by the existing gate-last oxidation process, and improves the consistency of the device threshold voltage. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0025] Figure 1 The present invention is a flow chart of a method for preparing a P-channel VDMOS device;
[0026] Figure 2-6 It is a schematic diagram of the hierarchical structure during the preparation process of the P-channel VDMOS device of the present invention.
[0027] Description of reference numerals:
[0028] 1: semiconductor substrate; 2: semiconductor epitaxial layer; 3: body region; 4: first source region; 5: first mask layer; 6: first photoresist layer; 7: gate oxide layer; 8: polysilicon layer; 9: second photoresist layer; 10: second source region; 11: isolation dielectric layer; 12: metal layer; 13: source region. DETAILED DESCRIPTION
[0029] The technical solution of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0030] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.
[0031] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise clearly and specifically defined. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0032] Example 1
[0033] This embodiment provides a method for preparing a P-channel VDMOS device. Figure 1-6 As shown, the method for preparing a P-channel VDMOS device provided in this embodiment includes the following steps:
[0034] S101, forming a semiconductor epitaxial layer 2 on a semiconductor substrate 1, forming a first mask layer 5 on the surface of the semiconductor epitaxial layer 2, and using the first mask layer 5 as a mask, sequentially performing body region 3 implantation and a first source region implantation in the semiconductor epitaxial layer 2 to form a body region 3 and a first source region 4, such as Figure 2 As shown;
[0035] Specifically, the material of the first mask layer 5 may be silicon nitride (Si3N4), and silicon oxide (SiO2) may also be used instead;
[0036] When the material of the first mask layer 5 is silicon nitride, first, silicon nitride is deposited on the surface of the semiconductor epitaxial layer 2 to form a silicon nitride film, and then, the body region of the silicon nitride film is etched and silicon nitride is implanted in the window region to form the first mask layer 5;
[0037] When the material of the first mask layer 5 is silicon oxide, first, silicon oxide is deposited on the surface of the semiconductor epitaxial layer 2 to form a silicon oxide film, and then the body region of the silicon oxide film is etched and silicon oxide is implanted into the window region to form the first mask layer 5;
[0038] Further, using the first mask layer 5 as a mask, body region implantation and well drive-in are performed in the semiconductor epitaxial layer 2, thereby forming a body region 3;
[0039] Further, a photoresist film is coated on the body region 3, and the photoresist in the first source region injection window area of the photoresist film is removed to form a first photoresist layer 6. With the first mask layer 5 and the first photoresist layer 6 as masks, a first source region injection is performed on the body region 3 to form a first source region 4. The first source region injection is mainly used to control the device channel; wherein, during the first source region injection, the injected impurity is boron difluoride, the injection energy is 50KeV-80KeV, and preferably 60KeV-70KeV, and the injection dose is 1E14-8E14, and preferably 5E14-6E14.
[0040] During the first source region injection, the impurity injected is boron difluoride. First, the mass of boron difluoride is higher than that of boron, and the distribution and concentration of the impurity can be more accurately controlled during the injection process, thereby effectively adjusting and controlling the channel characteristics of the device. At the same time, fluorine has the effect of suppressing the interface trap density. In addition, while ensuring the threshold voltage of the device, a relatively low injection dose is selected to reduce the interface damage between the epitaxial layer and the gate oxide layer, thereby reducing the risk of gate-source leakage.
[0041] S102, removing the first photoresist layer 6 and the first mask layer 5, and sequentially forming a gate oxide layer 7 and a polysilicon layer 8 on the surfaces of the semiconductor epitaxial layer 2, the body region 3 and the first source region 4, as shown in FIG. Figure 3 As shown;
[0042] In the specific implementation process of the present invention, the removal of the first photoresist layer 6 and the first mask layer 5, and the formation process of the gate oxide layer 7 and the polysilicon layer 8 can all refer to the prior art, and the present invention will not repeat them any more.
[0043] S103, etching the polysilicon layer 8 to form a polysilicon gate, then coating a photoresist film, and removing the photoresist in the second source region injection window area of the photoresist film to form a second photoresist layer 9, using the second photoresist layer 9 as a mask, performing a second source region injection on the body region 3 and the first source region 4, thereby forming a second source region 10, as shown in FIG. Figure 4 As shown;
[0044] The second source region injection is mainly used to ensure the ohmic contact of the device source, which will not only not cause changes in other device parameters, but also reduce the dose of the source region injection before the gate oxidation step, thereby making it easier to control the consistency of the threshold voltage of the device. The present invention can make the first source region 4 and the second source region 10 finally form a source region 13 with a continuous junction and an appropriate width through the process of two source region injections.
[0045] Specifically, the window for the second source region injection partially overlaps with the window for the first source region injection, and during the second source region injection, the injected impurity is boron, the injection energy is 50KeV-80KeV, and preferably 50KeV-60KeV, the injection dose is 1E15-8E15, and preferably 4E15-5E15.
[0046] During the second source region injection, the injected impurity is boron. This is because boron, as a highly active P-type impurity, can ensure that a sufficiently good ohmic contact is formed between the source region 13 and the metal layer 12 .
[0047] Therefore, the present invention uses different impurities (boron difluoride and boron) in the two source region injection processes, which can accurately control the channel characteristics, ensure the source ohmic contact, optimize the source region 13 structure, and thus improve the overall performance of the device.
[0048] In this embodiment, the semiconductor substrate 1 , the semiconductor epitaxial layer 2 , the first source region 4 and the second source region 10 are all P-type doped, and the body region 3 is N-type doped.
[0049] S104, remove the second photoresist layer 9, deposit the isolation dielectric layer 11 and perform planarization, such as Figure 5 As shown;
[0050] In this embodiment, the removal of the photoresist layer 9 and the deposition and planarization of the isolation dielectric layer 11 may refer to the prior art, and the present invention will not elaborate on them any more.
[0051] S105, etching the isolation dielectric layer 11 to form a contact hole, and depositing the metal layer 12, such as Figure 6 As shown;
[0052] Specifically, after depositing the isolation dielectric layer 11, planarization is performed and selective etching is performed to form contact holes, and then a front metal layer is deposited and selectively etched to form a source and a gate;
[0053] Further, a back metal layer is prepared on the back side of the semiconductor substrate 1 to form a drain electrode;
[0054] The method for preparing the semiconductor field effect transistor after forming the isolation dielectric layer 11 in this embodiment can refer to the prior art, and the present invention will not elaborate on it any more.
[0055] Example 2
[0056] The P-channel VDMOS device of this embodiment, such as Figure 6As shown, the P-channel VDMOS device of this embodiment includes a semiconductor substrate 1, a semiconductor epitaxial layer 2, a body region 3, a source region 13, a gate oxide layer 7, a polysilicon layer 8, an isolation dielectric layer 11 and a metal layer 12, wherein the source region 13 is prepared by a process of two source region injections, specifically prepared by the preparation method of the aforementioned method embodiment 1, wherein the materials and properties of each part may refer to embodiment 1, and will not be repeated here.
[0057] In the above description, the technical details of patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above.
[0058] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A method for preparing a P-channel VDMOS device, characterized in that: The following steps are involved: A semiconductor epitaxial layer (2) is formed on a semiconductor substrate (1), a first mask layer (5) is formed on the surface of the semiconductor epitaxial layer (2), and body region implantation and first source region implantation are sequentially performed in the semiconductor epitaxial layer (2) using the first mask layer (5) as a mask, so as to form a body region (3) and a first source region (4); removing the first photoresist layer (6) and the first mask layer (5), and sequentially forming a gate oxide layer (7) and a polysilicon layer (8); Etching the polysilicon layer (8) to form a polysilicon gate, then coating a photoresist to form a second photoresist layer (9), using the photoresist layer as a mask, performing a second source region implantation on the body region (3) and the first source region (4) to form a second source region (10); The second photoresist layer (9) is removed, and an isolation dielectric layer (11) and a metal layer (12) are deposited in sequence.
2. The preparation method according to claim 1, characterized in that: The window for the first source region injection and the window for the second source region injection partially overlap.
3. The preparation method according to claim 1, characterized in that: During the first source region injection, the injected impurity is boron difluoride, the injection energy is 50KeV-80KeV, and the injection dose is 1E14-8E14.
4. The preparation method according to claim 1, characterized in that: During the second source region implantation, the implanted impurity is boron, the implantation energy is 50KeV-80KeV, and the implantation dose is 1E15-8E15.
5. The preparation method according to claim 1, characterized in that: When forming a first mask layer (5) on the surface of the semiconductor epitaxial layer (2), a mask film is deposited on the surface of the semiconductor epitaxial layer (2), and the body region (3) of the mask film is etched to implant the mask film in the window region to form the first mask layer (5).
6. The preparation method according to claim 1, characterized in that: During the first source region injection, a photoresist film is coated on the body region (3), the photoresist in the first source region injection window area of the photoresist film is removed to form a first photoresist layer (6), and the first mask layer (5) and the first photoresist layer (6) are used as masks to perform the first source region injection on the body region (3) to form a first source region (4).
7. The preparation method according to claim 1, characterized in that: During the second source region injection, the polysilicon layer (8) is etched to form a polysilicon gate, and then a photoresist film is coated, and the photoresist in the second source region injection window area of the photoresist film is removed to form a second photoresist layer (9). The second source region injection is performed on the body region (3) and the first source region (4) using the second photoresist layer (9) as a mask to form a second source region (10).
8. The preparation method according to claim 1, characterized in that: The first source region (4) and the second source region (10) form a source region (13) with a continuous junction and an appropriate width.
9. The preparation method according to claim 1, characterized in that: The semiconductor substrate (1), the semiconductor epitaxial layer (2), the first source region (4) and the second source region (10) are all P-type doped, and the body region (3) is N-type doped.
10. A P-channel VDMOS device, characterized in that: Prepared according to the preparation method according to any one of claims 1 to 9.