Integrated structure of hybrid heterogeneous integrated circuit and preparation method thereof

Abstract

The invention provides an integrated structure of a hybrid heterogeneous integrated circuit and a preparation method thereof, and the method comprises the steps: S1, preparing a GaN HEMT device which comprises a first substrate, a buffer layer, a GaN channel, a first grid electrode, a first source electrode, a first drain electrode and a barrier layer; s2, preparing a SiC JFET device, wherein the SiC JFET device comprises a second substrate, a SiC channel, an n-EPI layer, a second source electrode and a second drain electrode; s3, the first drain electrode and the first source electrode of the GaN HEMT device are correspondingly connected with the second drain electrode and the second source electrode of the SiC JFET device in a bonding mode, and the integrated structure of the hybrid heterogeneous integrated circuit is obtained. According to the invention, the pitch is reduced, and the connection density of the integrated circuit is improved.

Description

Technical Field

[0001] The invention belongs to the field of semiconductors, and in particular relates to an integrated structure of a hybrid heterogeneous integrated circuit and a preparation method thereof. Background Art

[0002] Power semiconductor materials such as Si, GaN, and SiC all have their own advantages and disadvantages. Among them, Si is more mature, but the bandgap is relatively short, and the performance value as a power device is higher. GaN HEMT devices have excellent two-dimensional electron gas concentration and high mobility, but when the voltage level is too high, the vertical substrate voltage resistance is limited. At the same time, due to the need for epitaxial thickness matching the voltage level, the cost of epitaxial growth will also increase. SiC MOSFET devices have excellent thermal conductivity and voltage resistance, but due to the presence of many defects in their gate oxide interface, the channel mobility is low, resulting in a larger resistance. Therefore, a new power device structure that fully integrates the advantages of different materials is needed. Since horizontal devices have the natural advantage of horizontal integration, the basic devices of traditional integrated circuits are horizontal structures, such as LDMOS and CMOS in the BCD process. However, this type of integrated circuit has problems such as dispersion between components, large area, and low transmission efficiency. Therefore, traditional horizontal circuits have gradually developed into vertical or 3D circuits to achieve circuit structures with higher integration density. The traditional vertical integration method is to stack two functional materials and form vertical interconnections between them through silicon vias (TSVs). However, due to the requirement of TSV aspect ratio, the size of the connection port cannot be guaranteed, which limits the further reduction of the pitch. Summary of the invention

[0003] In view of this, the present invention provides an integrated structure of a hybrid heterogeneous integrated circuit and a preparation method thereof, wherein a GaN HEMT device and a SiC JFET device are firstly prepared separately, and then the GaN HEMT device and the SiC JFET device are bonded and connected, thereby reducing the pitch and improving the connection density of the integrated circuit.

[0004] In order to achieve the above object, the present invention adopts the following technical solutions:

[0005] First, the present invention provides a method for preparing an integrated structure of a hybrid heterogeneous integrated circuit, comprising the following steps:

[0006] S1. Prepare a GaN HEMT device, wherein the GaN HEMT device comprises a first substrate, a buffer layer, a GaN channel, a first gate, a first source, a first drain and a barrier layer, wherein the first substrate, the buffer layer, the GaN channel and the barrier layer are stacked in sequence, the first gate is located on a side of the barrier layer away from the GaN channel, one end of the first source and the first drain is located on a side of the barrier layer away from the GaN channel, and the other end is connected to the GaN channel;

[0007] S2. Prepare a SiC JFET device, wherein the SiC JFET device comprises a second substrate, a SiC channel, an n-EPI layer, a second source and a second drain, wherein the second substrate, the SiC channel and the n-EPI layer are stacked in sequence, a p-type doping region and an n-type doping region are provided on a side of the n-EPI layer away from the SiC channel, the second drain and the second source are located on a side of the n-EPI layer away from the SiC channel, the second drain is connected to the n-type doping region, and the second source is connected to the p-type doping region;

[0008] S3. The first drain and the first source of the GaN HEMT device are bonded and connected to the second drain and the second source of the SiC JFET device respectively, to obtain an integrated structure of a hybrid heterogeneous integrated circuit.

[0009] Preferably, in step S1, the other ends of the first source and the first drain of the GaN HEMT device are both located on a side of the buffer layer close to the first substrate.

[0010] Preferably, in step S3, the specific step of bonding connection is to remove the first substrate, and the first source and the first drain are located at the end of the buffer layer close to the first substrate and are bonded to the second source and the second drain of the SiC JFET device respectively.

[0011] Preferably, in step S3, the specific step of bonding connection is to rotate the GaN HEMT device until the barrier layer is close to the n-EPI layer of the SiC JFET device, and then bond the first source and the first drain to the second source and the second drain respectively.

[0012] Preferably, the bonding connection is solder bump bonding or hybrid bonding.

[0013] Preferably, the number of the first source electrodes is two, the number of the second source electrodes is two, and the two first source electrodes and the two second source electrodes are bonded in a one-to-one correspondence.

[0014] Preferably, the number of the first drain electrode is one, and two first gate electrodes are sandwiched outside the first drain electrode; the number of the second drain electrode is one, and two second gate electrodes are sandwiched outside the second drain electrode.

[0015] Preferably, the GaN HEMT device further comprises a current-carrying layer, wherein the current-carrying layer is located on a side of the barrier layer away from the GaN channel.

[0016] Preferably, the material of the first substrate includes at least one of Si or SiC.

[0017] Secondly, the present invention provides an integrated structure of a hybrid heterogeneous integrated circuit, and the integrated structure is prepared by adopting the manufacturing method.

[0018] Compared with the prior art, the present invention has the following beneficial effects:

[0019] (1) The present invention first prepares GaN HEMT devices and SiC JFET devices separately, and then bonds the GaN HEMT devices and SiC JFET devices, thereby reducing the pitch and improving the connection density of the integrated circuit.

[0020] (2) The present invention first prepares GaN HEMT devices and SiC JFET devices separately, and then bonds the GaN HEMT devices and SiC JFET devices, thereby avoiding the problem of ohmic contact temperature mismatch.

[0021] (3) The GaN HEMT device and the SiC JFET device of the present invention form a bond between metals or a hybrid bond through a dielectric-metal mixed interface, which has low contact resistance, high interconnection density and high reliability. In addition, the electrical connection distance between the GaN HEMT device and the SiC JFET device is short, the parasitics are small, and a fast switching response speed can be achieved.

[0022] (4) In the present invention, when the rear parasitics of the first source and the first drain in the GaN HEMT device are small, the GaN HEMT device is rotated to the n-EPI layer of the SiC JFET device where the barrier layer is close to the first source and the first drain, respectively, by a flip-chip process, and then the first source and the first drain are bonded to the second source and the second drain, respectively. There is no need to perform a complex TGV through-hole process, and the operation is simple and fast. At the same time, the quality of the GaN HEMT device prepared in this way is higher than that of the direct epitaxial method, and fast switching under low on-resistance can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 The preparation process of the integrated structure of the hybrid heterogeneous integrated circuit provided in Example 1 of the present invention;

[0024] Figure 2 A preparation process of the integrated structure of the hybrid heterogeneous integrated circuit provided in Embodiment 2 and Embodiment 3 of the present invention;

[0025] Figure 3 A schematic diagram of a GaN HEMT device architecture provided by an embodiment of the present invention;

[0026] Figure 4 A schematic diagram of a SiC JFET device architecture provided in one embodiment of the present invention.

[0027] Figure numerals: integrated structure 100 of hybrid heterogeneous integrated circuit, GaN HEMT device 1, first substrate 11, buffer layer 12, GaN channel 13, first gate 14, first source 15, first drain 16, barrier layer 17, current-carrying layer 18, SiC JFET device 2, second substrate 21, SiC channel 22, n-EPI layer 23, p-type doped region 231, n-type doped region 232, second source 24, second drain 25. DETAILED DESCRIPTION

[0028] The present invention is further described in detail below in conjunction with specific embodiments so that those skilled in the art can understand the present invention more clearly.

[0029] like Figure 1-4 As shown, the present invention provides a method for preparing an integrated structure 100 of a hybrid heterogeneous integrated circuit, comprising the following steps:

[0030] S1. Prepare a GaN HEMT device 1, wherein the GaN HEMT device 1 comprises a first substrate 11, a buffer layer 12, a GaN channel 13, a first gate 14, a first source 15, a first drain 16 and a barrier layer 17, wherein the first substrate 11, the buffer layer 12, the GaN channel 13 and the barrier layer 17 are stacked in sequence, the first gate 14 is located on a side of the barrier layer 17 away from the GaN channel 13, one end of the first source 15 and the first drain 16 are located on a side of the barrier layer 17 away from the GaN channel 13, and the other end is connected to the GaN channel 13;

[0031] Specifically, the GaN HEMT device 1 is also called a gallium nitride high electron mobility transistor. The first substrate 11 is usually made of sapphire, silicon (Si), silicon carbide (SiC) or gallium nitride (GaN). The selection of the first substrate 11 will affect the performance and cost of the device. The buffer layer 12 is between the first substrate 11 and the GaN channel 13 to reduce lattice mismatch and stress. This layer is usually an aluminum nitride (AlN) or gallium nitride (GaN) film. The GaN channel 13 mainly includes a two-dimensional electron gas (2DEG) layer with high electron mobility. This layer is usually a heterostructure composed of aluminum nitride (Al) and gallium nitride (GaN). A common structure is an AlGaN / GaN heterostructure, in which the aluminum content of the AlGaN layer determines the density of the electron gas. The first gate 14 is a key part for controlling the flow of current and is usually made of a metal material (such as tungsten or gold). The design and size of the first gate 14 have an important influence on the switching characteristics and frequency response of the device. The design and layout of the first source 15 and the first drain 16 are crucial to the current conduction capability and power characteristics of the device. They are also usually made of metal materials and form good contact with the active layer. The barrier layer 17 plays an important role in semiconductor materials and is used to control the flow of electrons, form a special band structure, and realize device functions. The design and manufacturing process of these structures directly affect the performance of the GaN HEMT device 1, such as switching speed, power handling capability, and thermal management capability. The specific structure of the GaN HEMT device 1 can be as follows Figure 3 shown.

[0032] S2. Prepare a SiC JFET device 2, wherein the SiC JFET device 2 comprises a second substrate 21, a SiC channel 22, an n-EPI layer 23, a second source 24 and a second drain 25. The second substrate 21, the SiC channel 22 and the n-EPI layer 23 are stacked in sequence, a p-type doping region 231 and an n-type doping region 232 are provided on a side of the n-EPI layer 23 away from the SiC channel 22, the second drain 25 and the second source 24 are located on a side of the n-EPI layer 23 away from the SiC channel 22, the second drain 25 is connected to the n-type doping region 232, and the second source 24 is connected to the p-type doping region 231;

[0033] Specifically, the SiC JFET device 2 is also called a silicon carbide junction field effect transistor, and the second substrate 21 generally uses single crystal silicon carbide, which provides the device with high thermal conductivity and high electric field tolerance. The SiC channel 22 is a flow path for electrons or holes, and is generally composed of n-type or p-type materials with a low degree of doping. The design of the SiC channel 22 directly affects the conductivity and switching speed of the device. The n-EPI layer 23 refers to an n-type doped layer formed by epitaxial growth technology, which is widely used in modern semiconductor devices and provides excellent electronic properties and performance. The gate of the SiC JFET is generally a p-type or n-type region connected to the source. The gate controls the current between the second source 24 and the second drain 25 by applying a voltage. The second source 24 and the second drain 25 are the input and output ends of the current, and are generally formed by doping on a SiC substrate. The second source 24 is generally n-type doped, while the second drain 25 can be p-type or n-type doped, depending on the design of the device. The SiC JFET device 2 is widely used in power electronics, electric vehicles, renewable energy, industrial control and other fields due to its high temperature, high power and high frequency performance.

[0034] S3, the first drain 16 and the first source 15 of the GaN HEMT device 1 are bonded and connected to the second drain 25 and the second source 24 of the SiC JFET device 2 respectively, to obtain an integrated structure 100 of a hybrid heterogeneous integrated circuit.

[0035] In the above technical scheme, the present invention first prepares GaN HEMT device 1 and SiC JFET device 2 separately, and then bonds GaN HEMT device 1 and SiC JFET device 2, thereby reducing the pitch and improving the connection density of the integrated circuit. At the same time, since the present invention first prepares GaN HEMT device 1 and SiC JFET device 2 separately, and then bonds GaN HEMT device 1 and SiC JFET device 2, the problem of ohmic contact temperature mismatch is avoided. The GaN HEMT device 1 and SiC JFET device 2 of the present invention form a bond between metals or form a hybrid bond through a dielectric-metal mixed interface, with low contact resistance, high interconnection density and high reliability.

[0036] In some embodiments, Figure 1As shown, in step S1, the other ends of the first source 15 and the first drain 16 of the GaN HEMT device 1 are both located on the side of the buffer layer 12 close to the first substrate 11. Further, in step S3, the specific step of bonding connection is to remove the first substrate 11, and the first source 15 and the first drain 16 are located at the end of the buffer layer 12 close to the first substrate 11 and are bonded to the second source 24 and the second drain 25 of the SiC JFET device 2 respectively. In this way, the electrical connection distance between the GaN HEMT device 1 and the SiC JFET device 2 is short, the parasitic is small, and a fast switching response speed can be achieved.

[0037] In some embodiments, in step S3, the specific step of bonding connection is to rotate the GaN HEMT device 1 until the barrier layer 17 is close to the n-EPI layer 23 of the SiC JFET device 2, and then bond the first source 15 and the first drain 16 to the second source 24 and the second drain 25 respectively. This method is flip-chip bonding, such as Figure 2 As shown, the GaN HEMT device 1 is first rotated 180° so that the barrier layer 17 is close to the n-EPI layer 23 of the SiC JFET device 2, and then the first source 15 and the first drain 16 are bonded to the second source 24 and the second drain 25 respectively. When the rear-end parasitics of the first source 15 and the first drain 16 in the GaN HEMT device 1 are small, the GaN HEMT device 1 is bonded to the SiC JFET device 2 by a flip-chip process. There is no need to perform a complex TGV through-hole process, and the operation is simple and fast. At the same time, the quality of the GaN HEMT device 1 prepared in this way is higher than that of the direct epitaxial method, and fast switching under low on-resistance can be achieved.

[0038] Further, the bonding connection is solder bump bonding or hybrid bonding, and the solder bump bonding is a common chip bonding technology, which is usually used to package and connect chips. In this method, a layer of solder is applied to the metal surface of the chip, and then the chip is bonded to another substrate or chip, and the bonding is achieved by heating and applying pressure. The solder melts after heating to form a reliable connection. In some embodiments, the main process steps of bump bonding include: the first step: bump bottom metallization (UBM); the second step: chip bumping; the third step: assembling the bumped wafer onto the substrate / board; the fourth step: filling the bottom pores of the chip with non-conductive material. The hybrid bonding is a modern advanced bonding technology for stacking two or more chips together in the same package to build a so-called 3D chip. The core of this technology is to align the crystal faces of different chips through a special process and achieve bonding at the atomic level, thereby achieving high-density, high-performance chip stacking. Hybrid bonding technology is widely used in processors, memory, AI and other fields to help compress chip size, improve performance and energy efficiency.

[0039] In some embodiments, the number of the first source electrodes 15 is two, the number of the second source electrodes 24 is two, and the two first source electrodes 15 and the two second source electrodes 24 are bonded one-to-one. The number of the first source electrodes 15 is two, which is equivalent to two GaN devices for one SiC device, and the actual device structure is half, and the middle TSV is shared.

[0040] Furthermore, the number of the first drain electrode 16 is one, and two first gate electrodes 14 are sandwiched outside the first drain electrode 16 ; the number of the second drain electrode 25 is one, and two second gate electrodes are sandwiched outside the second drain electrode 25 .

[0041] In some embodiments, the GaN HEMT device 1 further includes a current-carrying layer 18, wherein the current-carrying layer 18 is located on a side of the barrier layer 17 away from the GaN channel 13, and the current-carrying layer 18 is Figure 1 The carrier layer in the semiconductor material is the particle responsible for charge transport in the semiconductor material.

[0042] In some embodiments, the material of the first substrate 11 includes at least one of Si or SiC.

[0043] The present invention also provides an integrated structure 100 of a hybrid heterogeneous integrated circuit, and the integrated structure is manufactured by the manufacturing method.

[0044] Example 1

[0045] S1. Prepare a GaN HEMT device 1, wherein the GaN HEMT device 1 comprises a first substrate 11, a buffer layer 12, a GaN channel 13, a first gate 14, a first source 15, a first drain 16 and a barrier layer 17, wherein the first substrate 11, the buffer layer 12, the GaN channel 13 and the barrier layer 17 are stacked in sequence, the first gate 14 is located on a side of the barrier layer 17 away from the GaN channel 13, one end of the first source 15 and the first drain 16 are located on a side of the barrier layer 17 away from the GaN channel 13, and the other end is connected to the GaN channel 13, wherein the other ends of the first source 15 and the first drain 16 of the GaN HEMT device 1 are both located on a side of the buffer layer 12 close to the first substrate 11

[0046] S2. Prepare a SiC JFET device 2, wherein the SiC JFET device 2 comprises a second substrate 21, a SiC channel 22, an n-EPI layer 23, a second source 24 and a second drain 25. The second substrate 21, the SiC channel 22 and the n-EPI layer 23 are stacked in sequence, a p-type doping region 231 and an n-type doping region 232 are provided on a side of the n-EPI layer 23 away from the SiC channel 22, the second drain 25 and the second source 24 are located on a side of the n-EPI layer 23 away from the SiC channel 22, the second drain 25 is connected to the n-type doping region 232, and the second source 24 is connected to the p-type doping region 231;

[0047] S3, removing the first substrate 11, and the first source 15 and the first drain 16 are located at the end of the buffer layer 12 close to the first substrate 11 and are respectively connected to the second source 24 and the second drain 25 of the SiC JFET device 2 by hybrid bonding.

[0048] Example 2

[0049] S1. Prepare a GaN HEMT device 1, wherein the GaN HEMT device 1 comprises a first substrate 11, a buffer layer 12, a GaN channel 13, a first gate 14, a first source 15, a first drain 16 and a barrier layer 17, wherein the first substrate 11, the buffer layer 12, the GaN channel 13 and the barrier layer 17 are stacked in sequence, the first gate 14 is located on a side of the barrier layer 17 away from the GaN channel 13, one end of the first source 15 and the first drain 16 are located on a side of the barrier layer 17 away from the GaN channel 13, and the other end is connected to the GaN channel 13;

[0050] S2. Prepare a SiC JFET device 2, wherein the SiC JFET device 2 comprises a second substrate 21, a SiC channel 22, an n-EPI layer 23, a second source 24 and a second drain 25. The second substrate 21, the SiC channel 22 and the n-EPI layer 23 are stacked in sequence, a p-type doping region 231 and an n-type doping region 232 are provided on a side of the n-EPI layer 23 away from the SiC channel 22, the second drain 25 and the second source 24 are located on a side of the n-EPI layer 23 away from the SiC channel 22, the second drain 25 is connected to the n-type doping region 232, and the second source 24 is connected to the p-type doping region 231;

[0051] S3, rotating the GaN HEMT device 1 until the barrier layer 17 is close to the n-EPI layer 23 of the SiC JFET device 2, and then hybrid bonding the first source 15 and the first drain 16 to the second source 24 and the second drain 25 respectively.

[0052] Example 3

[0053] S1. Prepare a GaN HEMT device 1, wherein the GaN HEMT device 1 comprises a first substrate 11, a buffer layer 12, a GaN channel 13, a first gate 14, a first source 15, a first drain 16 and a barrier layer 17, wherein the first substrate 11, the buffer layer 12, the GaN channel 13 and the barrier layer 17 are stacked in sequence, the first gate 14 is located on a side of the barrier layer 17 away from the GaN channel 13, one end of the first source 15 and the first drain 16 are located on a side of the barrier layer 17 away from the GaN channel 13, and the other end is connected to the GaN channel 13;

[0054] S2. Prepare a SiC JFET device 2, wherein the SiC JFET device 2 comprises a second substrate 21, a SiC channel 22, an n-EPI layer 23, a second source 24 and a second drain 25. The second substrate 21, the SiC channel 22 and the n-EPI layer 23 are stacked in sequence, a p-type doping region 231 and an n-type doping region 232 are provided on a side of the n-EPI layer 23 away from the SiC channel 22, the second drain 25 and the second source 24 are located on a side of the n-EPI layer 23 away from the SiC channel 22, the second drain 25 is connected to the n-type doping region 232, and the second source 24 is connected to the p-type doping region 231;

[0055] S3, rotating the GaN HEMT device 1 until the barrier layer 17 is close to the n-EPI layer 23 of the SiC JFET device 2, and then bonding the first source 15 and the first drain 16 to the corresponding solder bumps of the second source 24 and the second drain 25, respectively.

[0056] The specific raw materials not described in the present invention are all existing materials and can be directly purchased from the market.

[0057] The above are only preferred embodiments of the present invention and are not intended to limit the protection scope of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for preparing an integrated structure of a hybrid heterogeneous integrated circuit, characterized in that: The following steps are involved: S1. Prepare a GaN HEMT device, wherein the GaN HEMT device comprises a first substrate, a buffer layer, a GaN channel, a first gate, a first source, a first drain and a barrier layer, wherein the first substrate, the buffer layer, the GaN channel and the barrier layer are stacked in sequence, the first gate is located on a side of the barrier layer away from the GaN channel, one end of the first source and the first drain is located on a side of the barrier layer away from the GaN channel, and the other end is connected to the GaN channel; S2. Prepare a SiC JFET device, wherein the SiC JFET device comprises a second substrate, a SiC channel, an n-EPI layer, a second source and a second drain, wherein the second substrate, the SiC channel and the n-EPI layer are stacked in sequence, a p-type doping region and an n-type doping region are provided on a side of the n-EPI layer away from the SiC channel, the second drain and the second source are located on a side of the n-EPI layer away from the SiC channel, the second drain is connected to the n-type doping region, and the second source is connected to the p-type doping region; S3. The first drain and the first source of the GaN HEMT device are bonded and connected to the second drain and the second source of the SiC JFET device respectively, to obtain an integrated structure of a hybrid heterogeneous integrated circuit.

2. The method according to claim 1, characterized in that In step S1 , the other ends of the first source and the first drain of the GaN HEMT device are both located on a side of the buffer layer close to the first substrate.

3. The method according to claim 2, characterized in that In step S3, the specific step of bonding connection is to remove the first substrate, and the first source and the first drain are located at the end of the buffer layer close to the first substrate and are bonded to the second source and the second drain of the SiC JFET device respectively.

4. The method according to claim 1, characterized in that In step S3, the specific step of bonding connection is to rotate the GaN HEMT device until the barrier layer is close to the n-EPI layer of the SiC JFET device, and then bond the first source and the first drain to the second source and the second drain respectively.

5. The method according to claim 4, characterized in that The bonding connection is solder bump bonding or hybrid bonding.

6. The method according to claim 1, characterized in that The number of the first source electrodes is two, the number of the second source electrodes is two, and the two first source electrodes and the two second source electrodes are bonded in a one-to-one correspondence.

7. The method according to claim 6, characterized in that The number of the first drain electrode is one, and two first gate electrodes are sandwiched outside the first drain electrode; the number of the second drain electrode is one, and two second gate electrodes are sandwiched outside the second drain electrode.

8. The method according to claim 1, characterized in that The GaN HEMT device further includes a current-carrying layer, which is located on a side of the barrier layer away from the GaN channel.

9. The method according to claim 1, characterized in that: The material of the first substrate includes at least one of Si or SiC.

10. An integrated structure of a hybrid heterogeneous integrated circuit, characterized in that: The integrated structure is prepared by the manufacturing method described in any one of claims 1-9.

Images