Novel GaN power semiconductor device with avalanche overcurrent capability

Abstract

The invention belongs to the technical field of power semiconductors, and particularly relates to a novel GaN power semiconductor device with avalanche overcurrent capability. A transverse GaN device and a vertical GaN device are combined, and a vertical GaN structure is placed below a channel of a transverse GaN structure. When the device works normally, forward bias voltage is applied to the grid, forward bias voltage is applied between the drain and the source, the transverse GaN structure above the device is conducted, current passes through the device, the vertical GaN structure below the device is reversely biased, and almost no current exists. When the device is in a reverse voltage withstanding state, the upper transverse GaN structure has no conduction current, and the lower vertical GaN structure has reverse bias and also has no conduction current. Along with the increase of the voltage between the drain electrode and the source electrode, the lower vertical GaN structure generates avalanche breakdown, and the current flows from the drain electrode to the source electrode mainly through the lower vertical GaN structure under the reverse withstand voltage, so that the novel GaN power semiconductor device has the avalanche breakdown, and the withstand voltage is improved compared with a traditional PGaN gate GaN HEMT (High Electron Mobility Transistor) device.

Description

Technical Field

[0001] The invention belongs to the technical field of power semiconductors, and in particular relates to a novel GaN power semiconductor device with avalanche overcurrent capability. Background Art

[0002] With the continuous progress of modern society and science and technology, the utilization of electric energy is increasingly required, and the utilization rate of electric energy is expected to be as high as possible. In energy conversion, power semiconductors play a very important role. At present, semiconductor power devices have penetrated into our daily lives, greatly improving our quality of life and quality of life. With the continuous development of power electronics technology, the application of GaN devices is becoming more and more abundant. For example, gallium nitride high electron mobility field effect transistor (GaN HEMT) has become a key component in many high-frequency and high-power applications. Its excellent characteristics, such as high frequency response, low conduction loss and high power density, make GaN devices popular in RF power amplifiers, inverters and power supply systems.

[0003] However, although GaN HEMT devices have shown excellent performance in high-frequency, high-power and high-temperature environments, their lack of avalanche capability may reveal disadvantages in certain applications. Compared with silicon-based devices and silicon carbide-based devices, GaN HEMT devices may be more vulnerable to damage when facing sudden high-energy voltage pulses. Whether the power device has avalanche capability directly affects its reliability and performance in practical applications. The most typical example is that even in the process of unclamped inductive load switching (UIS), in the UIS test, silicon-based devices usually have higher avalanche tolerance, which makes silicon-based devices stable under high voltage. The breakdown voltage of silicon-based devices is relatively high. Therefore, under high-energy and high-voltage conditions such as UIS testing, silicon-based devices can better resist the kickback voltage of inductive loads and protect the devices from damage. The almost no avalanche tolerance of GaN HEMT devices may cause the device to fail during the test process or in actual applications, thereby affecting the operation of the system. Secondly, the fact that GaN HEMT devices have almost no avalanche capability may limit their application in some high-power, high-pressure and complex load environments. In particular, in systems that require long-term stable operation, devices with avalanche capability are often more popular. For example, in power electronic systems that need to face sudden voltage shocks, silicon-based devices and silicon carbide-based devices with avalanche capability may be more suitable. They are often better able to cope with various abnormal conditions and improve the reliability and stability of the system. In addition, for silicon-based devices and silicon carbide-based power devices, the inherent avalanche capability of the device can be relied on to dissipate surge energy, but GaN HEMT has no avalanche capability. GaN HEMT devices may have additional overvoltage design to cope with the impact of surge energy to ensure stable operation under abnormal conditions, which may increase the complexity and cost of system design and may affect the performance and efficiency of the device. Vertical GaN devices, namely GaN diodes, have avalanche overcurrent capability and high avalanche tolerance, but their electron mobility is lower than that of GaN HEMT devices, and their frequency range and power density are insufficient. Therefore, there is an urgent need for a new type of GaN device with avalanche capability and high avalanche tolerance so that it can be used in more complex environments. Summary of the invention

[0004] In view of the above problems, the present invention proposes a novel GaN power semiconductor device with avalanche overcurrent capability. The structure of the novel GaN power semiconductor device can be simply described as placing a vertical GaN structure below the channel of the lateral GaN structure. Under normal conduction conditions, its use is no different from that of a GaN HEMT device, both of which conduct electricity through the lateral GaN structure. Under withstand voltage conditions, the novel GaN power semiconductor device can utilize the avalanche effect of the vertical GaN structure below to achieve the avalanche effect of the novel GaN power semiconductor device, so that the current is discharged through the vertical GaN structure below when the device breaks down. The novel GaN power semiconductor device combines the advantages of the lateral GaN structure and the vertical GaN structure in one device.

[0005] The technical solution adopted by the present invention is:

[0006] A novel GaN power semiconductor device with avalanche overcurrent capability, comprising a substrate layer 1, a buffer layer 2, a GaN Buffer layer 3, an N+ type GaN layer 4, an N - The N+ type GaN layer 4, the P+ type GaN layer 6, the unintentionally doped GaN barrier layer 7 and the AlGaN barrier layer 8 form a heterojunction structure. - The P+ type GaN layer 5 and the P+ type GaN layer 6 form a vertical GaN structure; the first metal 10, the P type GaN material layer 9 and the second metal 11 are sequentially provided from one end to the other end of the upper surface of the AlGaN barrier layer 8, and the lateral widths of the GaN barrier layer 7 and the AlGaN barrier layer 8 are equal and smaller than the N - The lateral width of the P+ type GaN layer 5 and the P+ type GaN layer 6, N - The lateral widths of the P+ type GaN layer 5 and the N+ type GaN layer 6 are equal and smaller than the lateral width of the N+ type GaN layer 4. The lateral width of the N+ type GaN layer 4 is smaller than the lateral widths of the substrate layer 1, the buffer layer 2 and the GaN Buffer layer 3. On the side of the second metal 11, the N - The end faces of the P+ type GaN layer 5, the GaN barrier layer 7 and the AlGaN barrier layer 8 are flush in the vertical direction of the device, and the N+ type GaN layer 4 extends beyond the N+ type GaN layer 4 in the lateral direction. -A third metal 12 is provided on the upper surface of a portion of the P+ type GaN layer 5 and away from the second metal 11 on one side; a fourth metal 13 is provided on the side of the first metal 10, which extends beyond the upper surface of a portion of the GaN barrier layer 7 in the lateral direction and away from the first metal 10; a gate metal is provided on the gate GaN material layer 9 to lead out a gate 16, and the gate GaN material layer 9 and the gate metal 16 form a Schottky contact; the first metal 10, the second metal 11, the third metal 12 and the fourth metal 13 form an ohmic contact with the semiconductor material, and the first metal 10 and the fourth metal 13 are connected to form a source 15, and the second metal 11 and the third metal 12 are connected to form a drain 17; the upper surface of the device between the source 15, the gate 16 and the drain 17, and the upper surface of the GaN Buffer layer 3 extending beyond both ends of the N+ type GaN layer 4 in the lateral direction are all covered by a passivation layer 14.

[0007] Furthermore, the doping concentration of the N+ type GaN layer 4 and the P+ type GaN layer 6 is greater than 1e18 cm -3 , so that the N+ type GaN layer 4 and the P+ type GaN layer 6 are in a non-fully depleted state during the withstand voltage.

[0008] Furthermore, GaN Buffer layer 3, N - The thickness of the N+ type GaN layer 5 and the unintentionally doped GaN barrier layer 7 must be such that when the device breaks down, the current flows from the third metal 12 through the N+ type GaN layer 4, N - After the P+ type GaN layer 5 and the P+ type GaN layer 6, the fourth metal 13 is reached. The specific thickness requirement is that the N-type GaN layer 5 has the smallest thickness, followed by the unintentionally doped GaN layer 7, and the GaN Buffer layer 3 is the thickest.

[0009] Furthermore, the material used for the substrate layer 1 is silicon carbide, sapphire or Al2O3; the material used for the passivation layer 14 is silicon nitride or silicon dioxide.

[0010] The beneficial effect of the present invention is that, compared with the conventional GaN HEMT device, when the reverse withstand voltage of the novel GaN power semiconductor device breaks down, the current preferentially flows through the N+ type GaN layer 4, N - The P+ type GaN layer 5 and the P+ type GaN layer 6 form a vertical GaN structure for discharge, and the avalanche breakdown of the novel GaN power semiconductor device is achieved through the avalanche breakdown of the vertical GaN structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a schematic diagram of the structure of an existing PGaN gate enhancement mode GaN HEMT;

[0012] Figure 2It is a schematic structural diagram of a novel GaN power semiconductor device with avalanche overcurrent capability according to the present invention.

[0013] Figure 3 It is a schematic diagram of the structure after epitaxial growth of each layer in the device preparation process of the present invention.

[0014] Figure 4 This is a schematic diagram of the structure after the first etching in the device preparation process of the present invention.

[0015] Figure 5 This is a schematic diagram of the structure after the second etching in the device preparation process of the present invention.

[0016] Figure 6 This is a schematic diagram of the structure after the third etching in the device preparation process of the present invention.

[0017] Figure 7 This is a schematic diagram of the structure after the fourth etching in the device preparation process of the present invention.

[0018] Figure 8 This is a schematic diagram of the structure after the first metal deposition in the device preparation process of the present invention.

[0019] Fig. 9 It is a schematic diagram of the structure after the second metal deposition in the device preparation process of the present invention.

[0020] Fig.10 It is a schematic diagram of the structure after the surface is deposited to form a passivation layer in the device preparation process of the present invention.

[0021] Fig.11 It is a schematic diagram of the structure after the hole is opened in the device preparation process of the present invention.

[0022] Fig.12 It is a schematic diagram of the structure after metal interconnection in the device preparation process of the present invention.

[0023] Fig.13 This is a schematic diagram of the current path when the device of the present invention is working.

[0024] Fig.14 Schematic diagram of the UIS process of the device of the present invention. DETAILED DESCRIPTION

[0025] The technical solution of the present invention is described in detail below in conjunction with the attached drawings.

[0026] like Figure 2 As shown, the structure of the present invention includes, from bottom to top, a substrate layer 1, a buffer layer 2, a GaN Buffer layer 3, an N+ type GaN layer 4, and a N -type GaN layer 5, P+ type GaN layer 6, unintentionally doped GaN barrier layer 7, AlGaN barrier layer 8, wherein the unintentionally doped GaN channel layer 7 and the AlGaN barrier layer 8 form a heterojunction structure, the N+ type GaN layer 4, the N - The AlGaN layer 5 and the P+ GaN layer 6 form a vertical GaN structure; a metal 10 is provided at one end of the AlGaN barrier layer to form an ohmic contact with the semiconductor material, a metal 13 is provided at one end of the P+ GaN layer 6 to form an ohmic contact with the semiconductor material, the metal 10 and the metal 13 are interconnected to form a source metal 15, a gate P-type GaN material layer 9 is provided above the AlGaN barrier layer, the gate GaN material layer 9 is connected to the gate metal 16 to form a Schottky contact, and an enhancement mode device is realized; a metal 11 is provided at the other end of the AlGaN barrier layer to form an ohmic contact with the semiconductor material, a metal 12 is provided at one end of the N+ GaN layer 4 to form an ohmic contact with the semiconductor material, the metal 11 and the metal 12 are interconnected to form a drain metal 17, and the AlGaN barrier layer 8, the GaN Buffer layer 3, the N+ GaN layer 4 and the P+ GaN layer 6 are covered by a passivation layer 14.

[0027] The working principle of the novel GaN power semiconductor device with avalanche overcurrent capability of the present invention is described below.

[0028] like Figure 2 As shown, the novel GaN power semiconductor device with avalanche overcurrent capability of the present invention is shown. Compared with the general PGaN gate enhancement mode GaN HEMT device, its working principle is as follows:

[0029] Normally, in common PGaN gate enhanced GaN HEMT devices, when the forward bias applied to the gate is greater than the threshold voltage, the gate is in the on state. This allows the two-dimensional electron gas under the gate to recover, thereby forming a current between the drain and the source. However, if the applied voltage is less than the threshold voltage, the gate is in the off state, the gate Schottky junction of the device is in a reverse biased state, and there is no two-dimensional electron gas under the gate. In this case, if a forward bias is applied to the drain, most of the drain-source voltage is borne by the depleted channel region due to the discontinuity of carriers in the channel. When the drain-source voltage exceeds the device breakdown voltage, the current increases rapidly and the device breaks down.

[0030] Fig.14 The gate voltage, drain-source voltage and current change curves during the UIS process of a common PGaN gate enhanced GaN HEMT device. The gate is turned on during the t0-t1 period, and the gate is turned off during the t1-t3 period. The drain-source current increases during the t0-t1 period; during the t1-t2 period, the drain-source voltage rises and reaches the maximum voltage V max , V max Usually greater than the device breakdown voltage VB , when V DS Reach V max After that, the voltage drops instantly, and the current rises rapidly and begins to oscillate violently. This process only takes hundreds of nanoseconds. During the time period t2-t3, the drain-source current tends to be stable. During the whole process, the UIS behavior mechanism of the common PGaN gate enhancement GaN HEMT device is similar to the LRC charging and discharging process. There is no voltage clamping phenomenon in the voltage waveform, which makes the device easily damaged.

[0031] The novel GaN power semiconductor device with avalanche overcurrent capability of the present invention has the same working principle as a general PGaN gate enhanced GaN HEMT device in the forward conduction state. A forward bias voltage greater than the threshold voltage is applied to the gate, the gate is in the on state, the two-dimensional electron gas under the gate is restored, a bias voltage is applied between the drain and source, and a current is formed between the drain and source. In the normal conduction state, due to the N+ type GaN layer 4, N - The vertical GaN structure composed of the P+ type GaN layer 5 and the P+ type GaN layer 6 is in a reverse bias state, with only a very small reverse saturation current. Therefore, the drain-source current mainly comes from the upper lateral GaN structure, such as Fig.13 The current path in ②; when the gate is not biased and the device is in a withstand voltage state, the gate is turned off, and the device can be connected by the N+ type GaN layer 4, N - The vertical GaN structure composed of the P+ type GaN layer 5 and the N+ type GaN layer 6 realizes voltage resistance. When the device breaks down, it occurs first in the N+ type GaN layer 4 and the N - The vertical GaN structure composed of the P+ type GaN layer 5 and the P+ type GaN layer 6 is formed, so that the device can be broken down due to the avalanche multiplication effect. When the device breaks down, its current flows to Fig.13 The current path in ⑤.

[0032] Therefore, the most important balance point in this device is how to make the device current mainly flow in the withstand voltage state. Fig.13 The above purpose can be achieved by limiting the thickness of the unintentionally doped GaN layer 7 and the N-type GaN layer 5. The thickness of the N-type GaN layer 5 needs to be lower than the thickness of the unintentionally doped GaN layer to reduce the current in the current path ④. In addition, it is necessary to prevent the current from flowing to the substrate through the current path ③. Therefore, it is also necessary to limit the thickness of the GaNBuffer layer 3. The thickness requirements of the three should be that the GaNBuffer layer 3 is the thickest, followed by the unintentionally doped GaN layer 7, and the N-type GaN layer 5 is the thinnest. In addition, the avalanche breakdown voltage of the new GaN power semiconductor device is determined by the N-type GaN layer 5.

[0033] like Fig.14As shown in the figure, the gate voltage, drain-source voltage and current change curves during the UIS test process. The gate is turned on during the t0-t1 period, and the gate is turned off during the t1-t3 period. The drain-source current increases during the t0-t1 period. During the t1-t3 period, the energy on the inductive load causes the device drain-source voltage to rise and the drain-source current to decrease. Since the new GaN power semiconductor device has a certain avalanche tolerance, the drain-source current is clamped at the avalanche breakdown voltage BV AVA As time goes by, the drain-source current gradually drops to zero. This process takes tens of microseconds, and the energy is successfully discharged through the avalanche effect, which makes the device better able to resist the kickback voltage of the inductive load and protect the device from damage.

[0034] The structure of the present invention can be prepared by the following method, and the process steps are:

[0035] 1. Epitaxially grow a buffer layer 2, a GaN buffer layer 3, an N+ type GaN layer 18, an N- type GaN layer 19, a P+ type GaN layer 20, an unintentionally doped GaN layer 21, an AlGaN layer 22 and a P-type GaN material layer 23 on a substrate 1 in sequence, as follows: Figure 3 shown.

[0036] 2. Etch the P-type GaN material layer outside the gate 9 until it reaches above the AlGaN layer 22. Figure 4 shown.

[0037] 3. Etch the layers 21 and 22 other than the AlGaN layer 8 and the unintentionally doped GaN layer 7 until the P+ type GaN layer 20 is formed. Figure 5 shown.

[0038] 4. Etch the layers 19 and 20 other than the N-type GaN layer 5 and the P+ type GaN layer 6 until the N+ type GaN layer 18 is formed. Figure 6 Shown

[0039] 5. Etch the layer 18 other than the N+ type GaN layer 4 until it reaches above the GaN Buffer layer 3, as shown in FIG. Figure 7 Shown

[0040] 6. Deposit metal in the source region to form an ohmic contact with the semiconductor material to form metal 10; deposit metal in the drain region to form an ohmic contact with the semiconductor material to form metal 11; deposit metal on the N+ type GaN layer 4 to form an ohmic contact with the semiconductor material to form metal 12. Figure 8 shown.

[0041] 7. Deposit metal on the P+ type GaN layer 6 to form an ohmic contact with the semiconductor material to form metal 13. Fig. 9 shown.

[0042] 8. Deposit a passivation layer 14 on the device surface, such as Fig.10 shown.

[0043] 9. Open holes above the P-type GaN layer 9 and the metals 10, 11, 12, and 13, such as Fig.11 shown.

[0044] 10. Deposit metal on the surface of the P-type GaN layer 9 to form a Schottky contact with the semiconductor material; metal 10 and metal 13 form a complete source contact through metal interconnection; metal 11 and metal 12 form a complete drain contact through metal interconnection. Fig.12 shown.

Claims

1. A novel GaN power semiconductor device with avalanche overcurrent capability, characterized in that: The invention comprises a substrate layer (1), a buffer layer (2), a GaN buffer layer (3), an N+ type GaN layer (4), an N - The N+ type GaN layer (4), the N+ type GaN layer (5), the P+ type GaN layer (6), the unintentionally doped GaN barrier layer (7) and the AlGaN barrier layer (8); wherein the unintentionally doped GaN channel layer (7) and the AlGaN barrier layer (8) form a heterojunction structure, and the N+ type GaN layer (4), the N - A P+ type GaN layer (5) and a P+ type GaN layer (6) form a vertical GaN structure; a first metal (10), a P type GaN material layer (9) and a second metal (11) are sequentially provided from one end to the other end of the upper surface of the AlGaN barrier layer (8); the lateral widths of the GaN barrier layer (7) and the AlGaN barrier layer (8) are equal and smaller than the N type GaN layer (5) and the P+ type GaN layer (6); - The lateral width of the P+ type GaN layer (5) and the P+ type GaN layer (6), N - The lateral widths of the N+ type GaN layer (5) and the P+ type GaN layer (6) are equal and smaller than the lateral width of the N+ type GaN layer (4); the lateral width of the N+ type GaN layer (4) is smaller than the lateral widths of the substrate layer (1), the buffer layer (2) and the GaN Buffer layer (3); on the side of the second metal (11), the N - The end faces of the N+ type GaN layer (5), the P+ type GaN layer (6), the GaN barrier layer (7) and the AlGaN barrier layer (8) are flush in the vertical direction of the device, and the N+ type GaN layer (4) extends beyond the N+ type GaN layer (5) in the lateral direction. - A third metal (12) is provided on the upper surface of a portion of the P+ type GaN layer (5) and away from the second metal (11); on the side of the first metal (10), a fourth metal (13) is provided on the side of the P+ type GaN layer (6) that extends beyond the upper surface of a portion of the GaN barrier layer (7) in the lateral direction and away from the first metal (10); a gate metal lead-out gate (16) is provided on the gate GaN material layer (9), and the gate GaN material layer (9) and the gate metal (16) form a Schottky contact; the first metal (10), the second metal (11), the third metal (12) and the fourth metal (13) form an ohmic contact with the semiconductor material, and the first metal (10) and the fourth metal (13) are connected to form a source (15), and the second metal (11) and the third metal (12) are connected to form a drain (17); the upper surface of the device between the source (15), the gate (16) and the drain (17), and the GaN The upper surface of the buffer layer (3) that exceeds both ends of the N+ type GaN layer (4) in the lateral direction is covered by a passivation layer (14).

2. A novel GaN power semiconductor device with avalanche overcurrent capability according to claim 1, characterized in that: The doping concentration of the N+ type GaN layer (4) and the P+ type GaN layer (6) is greater than 1e18 cm -3 , so that it is in a non-fully depleted state during withstand voltage.

3. The novel GaN power semiconductor device with avalanche current capability according to claim 1, characterized in that: GaN Buffer layer (3), N - The thickness of the N+ type GaN layer (5) and the unintentionally doped GaN barrier layer (7) must be such that when the device breaks down, the current flows from the third metal (12) through the N+ type GaN layer (4), the N - type GaN layer (5) and P+ type GaN layer (6) before reaching the fourth metal (13).

4. A novel GaN power semiconductor device with avalanche overcurrent capability according to claim 1, 2 or 3, characterized in that: The material used for the substrate layer (1) is silicon carbide, sapphire or Al2O3; the material used for the passivation layer (14) is silicon nitride or silicon dioxide.

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