Isolation structure for multi-gate device

Abstract

The invention provides an isolation structure for a multi-gate device. The semiconductor structure according to the present disclosure comprises: a substrate; a first base fin and a second base fin generated from the substrate; an isolation structure disposed between the first substrate fin and the second substrate fin; a first plurality of channel members disposed over the first base fin; a second plurality of channel members disposed over the second base fin; a region isolation feature extending into the substrate; a first gate structure surrounding each of the first plurality of channel members; a second gate structure surrounding each of the second plurality of channel members; a first gate cutting feature extending through the first gate structure and into the isolation structure; and a second gate cutting feature extending the second gate structure and into the isolation structure. Each of the first gate cutting feature and the second gate cutting feature is spaced apart from the region isolation feature.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more particularly to an isolation structure for a multi-gate device. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous generation. Over the course of IC evolution, functional density (i.e., the number of interconnected devices per unit chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This shrinking process generally provides benefits by increasing production efficiency and reducing associated costs. This shrinking has also increased the complexity of processing and manufacturing ICs.

[0003] For example, as integrated circuit (IC) technology develops to smaller technology nodes, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current and reducing short channel effect (SCE). Multi-gate devices generally refer to devices having a gate structure or a portion thereof disposed on more than one side of a channel region. Gate all-around (GAA) transistors are examples of multi-gate devices, and they have become popular and promising candidates for high-performance and low-leakage applications. The gate structure of a GAA transistor may extend partially or completely around the channel region to provide access to the channel region on two or more sides. Since its gate structure surrounds the channel region, the GAA transistor may also be referred to as a surround gate transistor (SGT). Since the channel region of a GAA transistor may include a nanowire or a nanosheet and its configuration is similar to a bridge, the GAA transistor may also be referred to as a multi-bridge channel (MBC) transistor, a nanowire transistor or a nanosheet transistor. Nanosheets and nanowires may generally be referred to as nanostructures.

[0004] Dielectric isolation features are used to isolate IC device features that would otherwise be in contact with each other. Dielectric isolation features can have different shapes and properties depending on their application. Summary of the invention

[0005] According to one aspect of the present application, a semiconductor structure is provided, comprising: a substrate; a first base fin and a second base fin generated from the substrate; an isolation structure arranged between the first base fin and the second base fin along a direction; a first plurality of channel members arranged above the first base fin; a second plurality of channel members arranged above the second base fin; a regional isolation feature extending through the isolation structure and into the substrate; a first gate structure surrounding each of the first plurality of channel members; a second gate structure surrounding each of the second plurality of channel members; a first gate cutting feature extending through the first gate structure and into the isolation structure; and a second gate cutting feature extending through the second gate structure and into the isolation structure, wherein, along the direction, each of the first gate cutting feature and the second gate cutting feature is spaced apart from the regional isolation feature.

[0006] According to another aspect of the present application, a method is provided, comprising: receiving a workpiece, the workpiece comprising: a substrate, a first fin-shaped structure, a second fin-shaped structure, and a third fin-shaped structure generated from a top surface of the substrate, an isolation structure located between a lower portion of the first fin-shaped structure and a lower portion of the second fin-shaped structure and between a lower portion of the second fin-shaped structure and a lower portion of the third fin-shaped structure, a dummy gate dielectric layer located above the isolation structure and above a surface of the first fin-shaped structure, the second fin-shaped structure, and the third fin-shaped structure that is higher than the upper portion of the isolation structure, and a dummy gate electrode layer located above the dummy gate dielectric layer; forming a first opening penetrating the dummy gate electrode layer, the first opening being located directly above the second fin-shaped structure; and etching the first opening to expose a dielectric layer in the dummy gate dielectric layer. The invention relates to a method for forming a first fin-shaped structure and a second fin-shaped structure comprising: exposing the dummy gate dielectric layer to expose the second fin-shaped structure, and etching the second fin-shaped structure to form a second opening to extend the first opening; forming a regional isolation feature in the second opening; replacing the dummy gate dielectric layer and the dummy gate electrode layer with a first metal gate structure above the first fin-shaped structure and a second metal gate structure above the third fin-shaped structure after forming the regional isolation feature; forming a first gate cutting opening entering the first metal gate structure between the first fin-shaped structure and the regional isolation feature; forming a second gate cutting opening entering the second metal gate structure between the third fin-shaped structure and the regional isolation feature; and forming a first gate cutting feature and a second gate cutting feature in the first gate cutting opening and the second gate cutting opening, respectively.

[0007] According to another aspect of the present application, a method is provided, comprising: receiving a workpiece, the workpiece comprising: a substrate, an isolation structure located on the substrate; a first active region, a second active region, and a third active region generated from the substrate and extending above the isolation structure, a dummy gate dielectric layer located above the isolation structure and above surfaces of the first active region, the second active region, and the third active region that are higher than the isolation structure, and a dummy gate electrode layer located above the dummy gate dielectric layer; forming a first opening penetrating the dummy gate electrode layer to expose the dummy gate dielectric layer above the second active region; etching the gate dielectric layer exposed in the first opening and etching the second active region to form a second opening; opening to extend the first opening; forming a regional isolation feature in the second opening; after forming the regional isolation feature, replacing the dummy gate dielectric layer and the dummy gate electrode layer with a first metal gate structure above the first active area and a second metal gate structure above the third active area; forming a first gate cutting feature extending through the first metal gate structure, the first gate cutting feature being arranged between the first active area and the regional isolation feature; and forming a second gate cutting feature extending through the second metal gate structure, the second gate cutting feature being arranged between the third active area and the regional isolation feature, wherein the first gate cutting feature and the second gate cutting feature are spaced apart from the regional isolation feature. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] When with Figure 1 When read together, various aspects of the present disclosure can be best understood through the following detailed description. It is emphasized that, according to the standard practice of the industry, various features are not drawn to scale. In fact, for the clarity of discussion, the size of various features may be arbitrarily increased or reduced.

[0009] Figure 1 A flow chart of a method for forming a semiconductor structure according to one or more aspects of the present disclosure is shown.

[0010] Figure 2-19 According to one or more aspects of the present disclosure, Figure 1 Partial cross-sectional views of a workpiece during various manufacturing stages in a method. DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or above a second feature may include an embodiment in which the first feature and the second feature are directly in contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself dictate the relationship between the various embodiments and / or configurations discussed.

[0012] For ease of description, spatially relative terms such as "below," "beneath," "below," "above," "upper," etc. may be used herein to describe the relationship of one element or feature relative to another (one or more) elements or (one or more) features as shown in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0013] In addition, when "about," "approximately," etc. are used to describe a number or a range of numbers, the term is intended to encompass numbers within a reasonable range, taking into account variations inherent in the manufacturing process as understood by those of ordinary skill in the art. For example, based on known manufacturing tolerances associated with manufacturing a feature having the characteristics associated with the described number, a number or range of numbers encompasses a reasonable range that includes the number, such as within + / - 10% of the number. For example, a material layer having a thickness of "about 5 nm" may encompass a size range from 4.25 nm to 5.75 nm, where the manufacturing tolerance associated with depositing the material layer is known to those of ordinary skill in the art to be + / - 15%.

[0014] In order to ensure the functionality of the IC device, different types of dielectric isolation features are formed to separate the originally connected structures. For example, a regional isolation feature can be formed to selectively remove a portion of the active area, thereby dividing the active area into two regions. In some instances, the regional isolation feature can be referred to as a continuous polysilicon on diffusion edge (CPODE) feature. The use of the CPODE feature allows the contact polysilicon pitch (CPP) to be reduced and the size of the standard cell to be reduced. For another example, a gate cutting feature can be formed to divide the gate structure into two gate segments. The gate cutting feature is typically elongated and can cut through more than one gate structure extending parallel to each other. Both the regional isolation feature and the gate cutting feature can be formed before or after forming the high-k metal gate structure.

[0015] The present disclosure provides a process for forming regional isolation features and gate cut features to improve yield and provide balanced performance of the resulting device. In some embodiments, the regional isolation features are formed before replacing the dummy gate stack with a high-k metal gate structure, so that the gate dielectric layer of the high-k metal gate structure eventually extends along the sidewalls of the regional isolation features. The gate cut features are formed after replacing the dummy gate stack with the high-k metal gate structure. As a result, the gate dielectric layer of the high-k metal gate structure does not extend along the sidewalls of the gate cut features. In order to prevent uneven etching due to slow etching of the gate dielectric layer, the widths of the regional isolation features and the gate cut features are selected so that the formation of the gate cut features does not involve etching the gate dielectric layer disposed along the sidewalls of the regional isolation features. The process disclosed in the present disclosure ensures a uniform gate cut feature profile. Uneven gate cut feature profiles may cause changes in the gate structure, resulting in unpredictable threshold voltages and switching characteristics.

[0016] Various aspects of the disclosure will now be described in more detail with reference to the accompanying drawings. Figure 1 A flow chart of a method 100 of forming a semiconductor structure is shown. The method 100 is merely an example and is not intended to limit the present disclosure to what is explicitly shown in the method 100. Additional steps may be provided before, during, and after the method 100, and some of the steps described may be replaced, eliminated, or moved to obtain additional embodiments of the method. For simplicity, not all steps are described in detail herein. Figure 2-19 Method 100 is described, which shows partial cross-sectional views and top views of a workpiece 200 at different stages of manufacture according to an embodiment of method 100. Since a semiconductor structure will be formed from workpiece 200, workpiece 200 may be referred to as semiconductor structure 200 as the context requires. Figure 2-19 In the drawings, the X direction, Y direction, and Z direction are perpendicular to each other and are used consistently. For example, the X direction in one figure is parallel to the X direction in another figure. In addition, throughout this disclosure, the same reference numerals are used to represent similar features.

[0017] refer to Figure 1 and Figure 2 The method 100 includes a block 102 in which a workpiece 200 is received. Figure 2As shown, the workpiece 200 includes a substrate 202 and a stack 204 disposed on the substrate 202. In one embodiment, the substrate 202 may be a silicon (Si) substrate. In some other embodiments, the substrate 202 may include other semiconductor materials, such as germanium (Ge), silicon germanium (SiGe), or III-V semiconductor materials. Exemplary III-V semiconductor materials may include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlInAs), gallium indium phosphide (GaInP), and gallium indium arsenide (InGaAs). The substrate 202 may also include an insulating layer, such as a silicon oxide layer, to have a silicon on insulator (SOI) structure or a germanium on insulator (GeOI) structure. In some embodiments, the substrate 202 may include one or more well regions, such as an n-type well region doped with an n-type dopant (i.e., phosphorus (P) or arsenic (As)) or a p-type well region doped with a p-type dopant (i.e., boron (B)), for forming different types of devices. The doping of the n-type well and the p-type well may be formed using ion implantation or thermal diffusion.

[0018] Still reference Figure 2 , the stack 204 may include a plurality of channel layers 208 interlaced with a plurality of sacrificial layers 206. The channel layers 208 and the sacrificial layers 206 may have different semiconductor compositions. In some embodiments, the channel layers 208 are formed of silicon (Si) and the sacrificial layers 206 are formed of silicon germanium (SiGe). In these embodiments, the additional germanium content in the sacrificial layers 206 allows for selective removal or recessing of the sacrificial layers 206 without significantly damaging the channel layers 208. In some embodiments, the sacrificial layers 206 and the channel layers 208 may be deposited using an epitaxial process. The stack 204 may be epitaxially deposited using CVD deposition techniques (e.g., vapor phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy (MBE), and / or other suitable processes. The sacrificial layers 206 and the channel layers 208 are sequentially deposited alternately to form the stack 204. Figure 2 The stack 204 is shown to include three (3) sacrificial layers 206 and three (3) channel layers 208, which is for illustration purposes only and is not intended to be limiting beyond what is specifically recited in the claims. The number of layers in the stack 204 depends on the desired number of channel components of the semiconductor device 200. In some embodiments, the number of channel layers 208 is between 2 and 10.

[0019] refer to Figure 1 and Figure 3, the method 100 includes block 104, in which a fin structure 210 is formed. In some embodiments, at block 104, a portion of the stack 204 and the substrate 202 are patterned to form the fin structure 210 defined by the trench 211. Figure 3 As shown, each fin-shaped structure 210 includes a base portion 210B formed by a portion of the substrate 202 and a top portion 210T formed by the stack 204. The top portion 210T is disposed above the base portion 210B. The fin-shaped structure 210 extends longitudinally from the substrate 202 along the Y direction and vertically along the Z direction. The fin-shaped structure 210 can be patterned using a suitable process including a double patterning process or a multiple patterning process. In general, a double patterning process or a multiple patterning process combines a photolithography process with a self-alignment process, thereby allowing a pattern to be created with, for example, a pitch smaller than that obtainable using a single direct photolithography process. For example, in one embodiment, a hard mask layer is first deposited on the stack 204, and then a material layer is formed on the hard mask. The material layer is patterned using a photolithography process. Spacers are formed along the patterned material layer using a self-alignment process. The material layer is then removed, and the remaining spacers or mandrels may then be used to pattern a hard mask layer, and the patterned hard mask layer may then be used to pattern the fin structure 210 by etching the stack 204 and the substrate 202. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. Figure 3 As shown, in some embodiments, the fin structures 210 are arranged at a first pitch P1, and the first pitch P1 is the sum of a first spacing S1 between two adjacent fin structures 210 and a first width W1 of the fin structures 210 along the X direction. In some embodiments, the first width W1 may be between about 5 nm and about 100 nm, and the first spacing S1 may be between about 20 nm and about 200 nm. The first pitch P1 may be between about 25 nm and about 300 nm.

[0020] refer to Figure 1 and Figure 4 The method 100 includes a block 106 in which an isolation feature 212 is formed. After forming the fin structure 210, a fin structure 212 is formed between adjacent fin structures 210. Figure 4The isolation feature 212 shown. The isolation feature 212 may also be referred to as a shallow trench isolation (STI) feature 212. In an exemplary process, a dielectric material for the isolation feature 212 is first deposited on the workpiece 200, and the trenches 211 between the fin structures 210 are filled with the dielectric material. In some embodiments, the dielectric material may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics, combinations thereof, and / or other suitable materials. In various examples, the dielectric material may be deposited by a CVD process, a flowable CVD (FCVD) process, spin coating, and / or other suitable processes. The deposited dielectric material is then thinned and planarized, for example, by a chemical mechanical polishing (CMP) process, until at least a portion of the fin structure 210 is exposed. The planarized dielectric material is further recessed by a dry etching process, a wet etching process, and / or a combination thereof to form the isolation feature 212. As Figure 4 As shown, the top portion 210T of the fin structure 210 rises above the isolation feature 212 , while the base portion 210B is surrounded by the isolation feature 212 .

[0021] refer to Figure 1 and Figure 5 , the method 100 includes a block 108 in which a dummy gate stack 220 is formed over the fin structure 210. In some embodiments, a gate replacement process (or a gate-last process) is employed, wherein the dummy gate stack 220 is used as a placeholder for a functional gate structure. Other processes and configurations are also possible. Figure 5 In some embodiments shown, the dummy gate stack 220 includes a dummy dielectric layer 214 and a dummy electrode 216 disposed on the dummy dielectric layer 214. The region of the fin structure 210 located below the dummy gate stack 220 may be referred to as a channel region. Each channel region in the fin structure 210 is sandwiched between two source / drain regions along the Y direction to form a source / drain. In an exemplary process, the dummy dielectric layer 214 is uniformly deposited on the workpiece 200 by CVD. In this exemplary process, the dummy dielectric layer 214 is deposited on the top surface of the isolation feature 212 and the exposed surface of the fin structure 210. Then, a material layer for the dummy electrode 216 is uniformly deposited on the dummy dielectric layer 214. Then, the dummy dielectric layer 214 and the material layer for the dummy electrode 216 are patterned using a photolithography process to form the dummy gate stack 220. In some embodiments, the dummy dielectric layer 214 may include silicon oxide, and the dummy electrode 216 may include polysilicon.

[0022] like Figure 5As shown, each fin structure 210 has a first height H1 as measured from the top surface of the substrate 202. The dummy gate stack 220 may have a second height H2 as measured from the top surface of the fin structure 210. In some embodiments, the first height H1 may be between about 10 nm and about 200 nm, and the second height may be between about 10 nm and about 200 nm.

[0023] Although Figure 2-14 Although not explicitly shown, after forming the dummy gate stack 220, at least one gate spacer 222 ( Fig.15 ). At least one gate spacer 222 may include two or more gate spacer layers. The dielectric material for at least one gate spacer 222 may be selected to allow for selective removal of the dummy gate stack. Suitable dielectric materials for at least one gate spacer 222 may include silicon nitride, silicon oxycarbonitride, silicon carbonitride, silicon oxide, silicon oxycarbon, silicon carbide, silicon oxynitride, and / or combinations thereof. In an exemplary process, at least one gate spacer may be conformally deposited on the workpiece 200 using CVD, sub-atmospheric CVD (SACVD), or ALD. At least one gate spacer 222 will remain in the final structure after the dummy gate stack 220 is removed and replaced with a functional gate structure. Now briefly refer to Fig.15 , Fig.15 2 is a partial top view of the workpiece 200, wherein the dummy gate stack 220 has been replaced by the gate structure 250. Fig.15 As shown, at least one gate spacer 222 remains disposed along the sidewalls of the gate structure 250 .

[0024] refer to Figure 1 and Figure 5 The method 100 includes block 110, in which a source / drain feature 236 is formed. The operations of block 110 include recessing the source / drain region of the fin structure 210 to form a source / drain recess, forming an internal spacer feature, depositing the source / drain feature 236 (e.g., Fig.15 ), and depositing an interlayer dielectric layer 232 over the source / drain features 236 (as shown in Fig.15 ). In the dummy gate stack 220 and at least one gate spacer 222 (as shown Fig.15) is used as an etching mask, the workpiece 200 is anisotropically etched to form source / drain electrode recesses above the source / drain regions of the fin-shaped structure 210. The anisotropic etching of frame 110 may include a dry etching process or a suitable etching process. For example, the dry etching process may be implemented with oxygen-containing gas, hydrogen, fluorine-containing gas (e.g., CF4, SF6, NF3, CH2F2, CHF3 and / or C2F6), chlorine-containing gas (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gas (e.g., HBr and / or CHBr3), iodine-containing gas, other suitable gases and / or plasmas and / or combinations thereof.

[0025] Although not specifically shown in the figure, the operation of box 110 also includes forming an internal spacer feature to stagger the channel layer 208. After forming the source / drain recess, the sacrificial layer 206 exposed in the source / drain electrode recess is first selectively and partially recessed to form the internal spacer recess, while the exposed channel layer 208 is substantially not etched. In an embodiment where the channel layer 208 is mainly composed of silicon (Si) and the sacrificial layer 206 is mainly composed of silicon germanium (SiGe), the selective partial recess of the sacrificial layer 206 may include APM etching (e.g., ammonium hydroxide-hydrogen peroxide-water mixture). After forming the internal spacer recess, the internal spacer material layer is then conformally deposited on the workpiece 200 (including above and inside the internal spacer recess) using CVD or ALD. The internal spacer material may include silicon nitride, silicon oxycarbonitride, silicon carbonitride, silicon oxide, silicon oxycarbon, silicon carbide, or silicon oxynitride. After depositing the internal spacer material layer, the internal spacer material layer is etched back to form the internal spacer feature.

[0026] The operations of block 110 also include depositing source / drain features 236 in the source / drain recesses (at Fig.15202 and channel layer 208). In some embodiments, source / drain features 236 may be selectively and epitaxially deposited on exposed semiconductor surfaces of substrate 202 and channel layer 208. Source / drain features 236 may be deposited using an epitaxial process, such as vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. Source / drain features 236 may be n-type or p-type. When source / drain features 236 are n-type, they may include silicon (Si) and may be doped with n-type dopants, such as phosphorus (P) or arsenic (As). When source / drain features 236 are p-type, they may include silicon germanium (SiGe) or germanium (Ge) and may be doped with p-type dopants, such as boron (B) or boron difluoride (BF2). Doping of the source / drain features 236 may be performed in-situ by their deposition or ex-situ using an implantation process such as a junction implantation process. Although not explicitly shown, the source / drain features 236 may include multiple epitaxial layers having different doping concentrations.

[0027] After depositing source / drain features 236 over the source / drain regions of the fin structure 210 , block 110 includes depositing an ILD layer 232 (eg, Fig.15 The ILD layer 232 may be deposited by spin coating, FCVD process or other suitable deposition techniques. After the ILD layer 232 is deposited, a planarization process (e.g., a chemical mechanical polishing (CMP) process) may be performed on the workpiece 200 to provide a flat top surface exposing the dummy gate stack 220. In some embodiments not explicitly shown in the figure, a contact etch stop layer (CESL) may be conformally deposited on the workpiece 200 and the source / drain features 236 before the ILD layer 232 is deposited. In those embodiments, the CESL may include silicon nitride and may be deposited using ALD or CVD.

[0028] refer to Figure 1 and Figure 6-8 The method 100 includes a block 112 in which a region isolation opening 2260 is formed. The operations of block 112 may include depositing a first hard mask layer 224 (eg, Figure 6 As shown, a first opening 226 is formed to expose the fin structure 210 (as shown Figure 7), and extending the first opening 226 into the exposed fin structure 210 (as shown in Figure 8 First refer to Figure 6 . The first hard mask layer 224 may include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride or silicon oxynitride, and may be deposited using CVD or a suitable method. The first hard mask layer 224 may be patterned using a combination of photolithography and etching processes. After patterning the first hard mask layer 224, the patterned first hard mask layer 224 may be applied as an etching mask to etch the dummy electrode 216 to form a first opening 226. In some embodiments, the etching of the dummy electrode 216 may be a dry etching process including the use of a reactive gas and a polymer gas. The reactive gas may include chlorine (Cl2), hydrogen bromide (HBr), tetrafluoromethane (CF4) or hydrogen (H2) or other gas species that may react with the dummy electrode 216. The polymer gas refers to a gas species that may form byproducts during the etching step of forming the passivation layer. Exemplary polymer gases include nitrogen (N2), oxygen (O2) or carbon dioxide (CO2). The use of polymer gas results in the redeposition of byproducts, thereby slowing down the etching process. In some embodiments, the dry etching process may include a plasma source having a source power between about 50 W and about 800 W. In addition, the dry etching process may include a bias power between 0 W and about 800 W, a pressure between 3 mTorr and about 80 mTorr, and a process temperature between about 20° C. and about 60° C. Figure 7 As shown, the dry etching process for forming the first opening 226 can be selective to the dummy electrode 216 and slow down significantly when it reaches the dummy dielectric layer 214 on the isolation feature 212 and the fin structure 210. In this sense, the dummy dielectric layer 214 acts as an etch stop layer. In some embodiments, in order to provide a straight sidewall profile for the first opening 226, a periodic etching process including alternating etching cycles and oxidation cycles can be used. In some embodiments, despite the cyclic etching process, the sidewalls of the first opening 226 can taper downward.

[0029] Reference now Figure 8. A dry etching process different from the dry etching process for forming the first opening 226 may be performed to extend the first opening 226 downward along the depth of the fin structure 210 to form a second opening 2260. In some embodiments, the dry etching process for extending the first opening 226 includes using a reactive gas and a polymer gas. The reactive gas may include chlorine (Cl2), hydrogen bromide (HBr), tetrafluoromethane (CF4), hexafluorobutadiene (C4H6), hydrogen (H2), or nitrogen trifluoride (NF3). The polymer gas refers to a gas species that may form a byproduct during the etching step of forming the passivation layer. Exemplary polymer gases include nitrogen (N2), methane (CH4), silicon tetrachloride (SiCl4), carbon dioxide (CO2), oxygen (O2), or sulfur dioxide (SO2). In some embodiments, the dry etching process for forming the second opening 2260 may include a plasma source having a source power between about 0 W and about 1500 W. In addition, the dry etching process may include a bias power between about 0 W and about 800 W, a pressure between 3 mTorr and about 100 mTorr, and a process temperature between about 20° C. and about 100° C. In some embodiments, the etching processes for forming the first opening 226 and the second opening 2260 are performed in different etching systems (or etchers). Figure 8 As shown, the dry etching process for forming the second opening 2260 can be selective to the base portion 210B, so that the second opening 2260 experiences a step change in width. In some other embodiments, the dry etching process for forming the second opening 2260 can have a lower selectivity to the base portion 210B, and can etch more isolation features 212 or even the substrate 202. As a result, the sidewalls of the second opening 2260 can be substantially continuous and not characterized by a step change in width along the X direction. The second opening 2260 can also be referred to as a region isolation opening 2260.

[0030] refer to Figure 1 and Fig. 9 , the method 100 includes a block 114, in which a regional isolation feature 230 is formed in the second opening 2260. In block 114, a dielectric material for the regional isolation feature 230 is deposited over the second opening 2260 by plasma enhanced CVD (PECVD), atomic layer deposition (ALD), low pressure CVD (LPCVD), or CVD. In some embodiments, the dielectric material may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbon nitride oxide, or a suitable dielectric material. After the dielectric material for the regional isolation feature 230 is deposited, a planarization process such as a chemical mechanical polishing (CMP) process may be performed to form the regional isolation feature 230 and remove excess material, including the patterned first hard mask layer 224.

[0031] refer to Figure 1 and Fig.10 , the method 100 includes a block 116 in which the dummy gate stack 220 is removed. After forming the regional isolation features 230, the exposed dummy gate stack 220 is removed from the workpiece 200 by a selective etching process. The selective etching process can be a selective wet etching process, a selective dry etching process, or a combination thereof. In the depicted embodiment, the selective etching process selectively removes the dummy dielectric layer 214 and the dummy electrode 216 without substantially damaging the at least one gate spacer 222 ( Fig.15 ), the regional isolation feature 230, and the channel region of the fin structure 210 that is not removed during the formation of the regional isolation feature 230. The removal of the dummy gate stack 220 forms a gate trench 234 above the channel region of the fin structure 210. The gate trench 234 is formed along the Y direction through at least one gate spacer 222 (as shown in FIG. Fig.15 as shown).

[0032] refer to Figure 1 and Fig.11 The method 100 includes block 118, in which the channel member 2080 is released from the sacrificial layer 206. After removing the dummy gate stack 220, the channel layer 208 and the sacrificial layer 206 in the channel region are exposed in the gate trench, such as Fig.10 The exposed sacrificial layer 206 between the channel layers 208 may be selectively removed to release the channel layers 208, thereby forming a channel member 2080, as shown in FIG. Fig.11 As shown. Channel members 2080 are stacked vertically (one stacked on top of another) along the Z direction, and are vertically spaced apart from each other by removing the space left by the sacrificial layer 206. The selective removal of the sacrificial layer 206 can be implemented by selective dry etching, selective wet etching or other selective etching processes. In some embodiments, the selective wet etching includes APM etching (e.g., ammonia hydroxide-hydrogen peroxide-water mixture). In some alternative embodiments, the selective removal includes silicon germanium oxidation, followed by silicon germanium oxide removal. For example, oxidation can be provided by ozone cleaning, and then silicon germanium oxide is removed by an etchant such as NH4OH. With the removal of the sacrificial layer 206 in the channel region, the top surface of the channel member 2080 and the base portion 210B and the isolation feature 212 are exposed in the gate trench 234.

[0033] refer to Figure 1 and Fig.12, the method 100 includes a frame 120, in which a gate structure 250 is formed to surround each channel member 2080. The gate structure 250 may include an interface layer 242 on the top surface of the channel member 2080 and the base portion 210B, a gate dielectric layer 244 on the interface layer 242, and a gate electrode layer 246 on the gate dielectric layer 244. In some embodiments, the interface layer 242 includes silicon oxide and may be formed due to a pre-cleaning process. An exemplary pre-cleaning process may include using RCASC-1 (ammonia, hydrogen peroxide and water) and / or RCASC-2 (hydrochloric acid, hydrogen peroxide and water). The pre-cleaning process oxidizes the exposed surfaces of the channel member 2080 and the base portion 210B to form the interface layer 242. A gate dielectric layer 244 is then deposited on the interface layer 242 using ALD, CVD and / or other suitable methods. The gate dielectric layer 244 may include a high-K dielectric material. As used herein, high-k dielectric material includes dielectric materials having a high dielectric constant, for example, greater than the dielectric constant of thermal silicon oxide (-3.9). In one embodiment, the gate dielectric layer 244 may include hafnium oxide. Alternatively, the gate dielectric layer 244 may include other high-K dielectrics, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium oxide silicon (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba,Sr)TiO3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials.

[0034] After forming or depositing the interface layer 242 and the gate dielectric layer 244, a gate electrode layer 246 is deposited on the gate dielectric layer 244. The gate electrode layer 246 may be a multilayer structure including at least one work function layer and a metal filling layer. For example, at least one work function layer may include titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), or tantalum carbide (TaC). The metal filling layer may include aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals, or other suitable metal materials or combinations thereof. In various embodiments, the gate electrode layer may be formed by ALD, PVD, CVD, electron beam evaporation, or other suitable processes.

[0035] In various embodiments, a planarization process such as a CMP process may be performed to remove excess material to provide a substantially planar top surface of the gate structure 250. Fig.12 , (one or more) gate structures 250 surround each channel member 2080. Fig.12 In FIG. 2 , the regional isolation feature 230 appears to divide the gate structure 250 into different sections. Note that the regional isolation feature 230 is not designed or intended to divide the gate structure 250. Fig.15 As shown, the regional isolation feature 230 is intended to divide the active area, including the channel member 2080 and the base portion 210B, along the Y direction. As a result, the regional isolation feature 230 and the second opening 2260 are not elongated along the Y direction but are more rounded. Although in some cases, the regional isolation feature 230 fully divides the gate structure 250 into insulated gate segments along the X direction, the downward tapering shape of the regional isolation feature 230 often prevents it from completely dividing the dummy gate stack 220 into segments. The remaining dummy gate stack material can then be replaced with gate structure material. To this end, the gate cutting feature 270 (described below) is still needed to divide the gate structure 250 into different segments. As shown in FIG. Fig.15 As shown, each gate cut feature 270 is elongated along the Y direction, and such a shape and associated lithography process are more efficient in partitioning the gate structure 250 in a controlled manner.

[0036] refer to Figure 1 and Figure 13-15 , the method 100 includes block 122, in which a gate cut feature 270 is formed. The operations of block 122 may include forming a gate cut opening 262 (eg, Fig.13 ) and forming a gate cut feature 270 in the gate cut opening 262 (as shown in FIG. Fig.14 and Fig.15 ). Fig.13 In order to form the gate cutting opening 262, a second hard mask layer 260 is deposited on the workpiece 200 (including on the gate structure 250). In terms of composition and formation process, the second hard mask layer 260 can be similar to the first hard mask layer 224. A photolithography process and an etching process are then performed to pattern the second hard mask layer 260. The patterned second hard mask layer 260 is then used as an etching mask to etch a portion of the gate structure 250, the gate dielectric layer 244, and the isolation feature 212. The etching process for forming the gate cutting opening 262 can be a dry etching process including the use of chlorine (Cl2), hydrogen (H2), oxygen (O2), or other chlorine-containing etchants. In some embodiments, the etching process applied to form the gate cutting opening 262 may include multiple etching steps using an etchant that is more selective to the corresponding gate material, and may include wet etching, dry etching, or a combination thereof. As Fig.13 As shown, each gate cut opening 262 extends completely through the gate structure 250 and into the isolation feature 212. Fig.13 As shown, each gate cut opening 262 tapers downward.

[0037] It has been observed that due to the etch-resistant properties of the high-k dielectric material, the etching process used to form the gate cut opening 262 may inevitably etch the gate dielectric layer 244 at a slower rate. When the gate cut opening 262 vertically overlaps the regional isolation feature 230 in any way, the etching may be slowed by the gate dielectric layer 244 disposed along the sidewalls of the regional isolation feature 230. This slowdown coupled with varying degrees of overlap may result in uneven depth and shape of the gate cut opening 262. In turn, the various segments of the gate structure 250 may have a different shape and width (along the X direction) than the channel member 2080. Variations in shape and width in the gate cut opening 262 (and ultimately, the gate cut feature 270) may cause variations in the threshold voltage of the transistor, which is undesirable. For the foregoing reasons, one feature of the present disclosure is to ensure that the gate cut opening 262 does not cut into the regional isolation feature 230. As Fig.13 As shown, although the gate cut openings 262 may be close to the regional isolation features 230, they do not cut into the regional isolation features 230. In other words, the gate cut openings 262 are spaced apart from the regional isolation features 230 by at least a portion of the gate electrode layer 246 and a portion of the gate dielectric layer 244.

[0038] After forming the gate cut opening 262, a dielectric material for the gate cut feature 270 is deposited over the gate cut opening 262 by plasma enhanced CVD (PECVD), atomic layer deposition (ALD), low pressure CVD (LPCVD), or CVD. In some embodiments, the dielectric material for the gate cut feature 270 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, or a suitable dielectric material. After depositing the dielectric material for the gate cut feature 270, a planarization process such as a chemical mechanical polishing (CMP) process may be performed to form a dielectric material. Fig.14 The gate cut feature 270 shown in FIG. 1 and the excess material is removed, including the patterned second hard mask layer 260. Fig.14 As shown, similar to the gate cut opening 262 , each gate cut feature 270 tapers downward.

[0039] Still reference Fig.14 . In embodiments where the regional isolation feature 230 includes a step change in width, the regional isolation feature 230 can be divided into an upper portion 230U above a level at which the step change occurs and a lower portion 230L below the level. In some embodiments, each of the upper portion 230U and the lower portion 230L tapers downward but has discontinuous sidewalls. The upper portion 230U includes a second width W2 at its top surface and a second width W3 at an interface with the lower portion 230L. The lower portion 230L includes a fourth width W4 at an interface with the upper portion 230U and a fifth width W5 at its bottom surface. In some cases, due to the downward taper, the third width W3 is approximately 80% to approximately 95% of the second width W2, and the fifth width W5 is approximately 80% to approximately 95% of the fourth width W4. The third width W3 is greater than the fourth width W4. In some cases, the ratio of the fourth width W4 to the third width W3 can be between approximately 20% and approximately 100% (wherein there is no step change). As Fig.15 As shown, each gate cut feature 270 may have a sixth width W6 at its top surface. In some embodiments, the sixth width W6 may be between about 10 nm and about 100 nm. To ensure that the region isolation feature 230 fits between two adjacent gate cut features 270 without any boundary merging, the second width W2 may be equal to or less than the first width W1 (e.g., Figure 3 ) and the first spacing S1 (also as Figure 3The second width W2 is equal to or less than (W1+S1-W6). In any case, the second width W2 cannot be less than the first width W1. The regional isolation feature 230 extends deeper into the substrate 202 than the gate cut feature 270. In some embodiments, the regional isolation feature 230 extends completely through the base portion 210B and well into the substrate 202, while the gate cut feature 270 terminates in the isolation feature 212. In some embodiments, the regional isolation feature 230 may have a first depth D1 from the top surface of the regional isolation feature 230 to its bottom surface in the substrate 202, and the gate cut feature 270 may have a second depth D2 from the top surface of the gate cut feature 270 to its bottom surface in the isolation feature 212. The first depth D1 is greater than the second depth D2. For active areas not affected by the area isolation features 230 , a lateral gate thickness G along the sidewalls of the channel member 2080 may be defined as half the difference between the first spacing S1 and the sixth width W6 (ie, G=( S1 − W6 ) / 2).

[0040] Fig.15 Shows Fig.14 A partial top view of the workpiece 200 shown in FIG. Fig.15 As shown, each gate structure 250 (whether or not divided by the gate cutting feature 270) extends longitudinally along the X direction. Each active area including the base portion 210B and the channel member 2080 disposed on the base portion 210B extends longitudinally along the Y direction. In general, the fin-shaped structure 210 can be regarded as an approximate representation of the active area. It can be seen that the active area and the gate structure 250 extend in directions perpendicular to each other. Each vertical stack of the channel member 2080 extends between two source / drain features 236 along the Y direction and contacts the two source / drain features 236. The source / drain features 236 are shown in dotted lines because they are at least covered by the ILD layer 232. Along the Y direction, each gate structure 250 is sandwiched between two parts of at least one gate spacer 222. Since the regional isolation feature 230 is formed before the gate structure 250 is formed, the gate dielectric layer 244 is disposed along the sidewalls of the regional isolation feature 230. The gate cutting feature 270 is formed after the gate structure 250 is formed. As a result, the gate cut feature 270 cuts through the gate structure 250, but the gate dielectric layer 244 does not extend along the sidewalls of the gate cut feature 270. Fig.15 In some embodiments shown, the gate cut feature 270 is elongated more along the Y direction than the area isolation feature 230. Fig.15, the region isolation feature 230 includes a first length L1 along the Y direction, and each gate cutting feature 270 includes a second length L2 along the Y direction. The second length L2 is greater than the first length L1. In some embodiments, the ratio of the second length L2 to the first length L1 is between about 1.5 and about 4.0.

[0041] Fig.16 and Fig.17 An alternative embodiment is shown in which the dry etch forming the second opening 2260 at frame 112 is less selective to the base 210B. As a result, a continuous region isolation feature 2300 can be formed. The continuous region isolation feature 2300 is characterized by a continuous sidewall and no step change in width. In some embodiments, the continuous region isolation feature 2300 can taper downward in a continuous manner and terminate in the substrate 202. Despite the continuous sidewall, no gate cut feature 270 overlaps the continuous region isolation feature 2300 vertically.

[0042] Fig.18 and Fig.19 Yet another alternative embodiment is shown in which giant area isolation features 2302 cut into multiple substrate portions to separate multiple active areas. Fig.18 The giant region isolation feature 2302 only spans two fin structures 210 , but it should be understood that the giant region isolation feature 2302 can be used to divide more than two fin structures 210 . In some embodiments, the giant region isolation feature 2302 can span 2 to 10 fin structures 210 .

[0043] In one exemplary aspect, the present disclosure relates to a semiconductor structure. The semiconductor structure includes: a substrate; a first substrate fin and a second substrate fin generated from the substrate; an isolation structure disposed between the first substrate fin and the second substrate fin along a direction; a first plurality of channel members disposed on the first substrate fin; a second plurality of channel members disposed on the second substrate fin; a regional isolation feature extending through the isolation structure and into the substrate; a first gate structure surrounding each of the first plurality of channel members; a second gate structure surrounding each of the second plurality of channel members; a first gate cut feature extending through the first gate structure and into the isolation structure; and a second gate cut feature extending through the second gate structure and into the isolation structure. Along the direction, each of the first gate cut feature and the second gate cut feature is spaced apart from the regional isolation feature.

[0044] In some embodiments, the first gate structure includes a first gate dielectric layer and a first gate electrode layer located above the first gate dielectric layer, and a portion of the first gate dielectric layer is disposed along the sidewall of the regional isolation feature. In some embodiments, the first gate cut feature is in direct contact with the first gate electrode layer. In some embodiments, the bottom surface of the regional isolation feature is lower than the bottom surface of the first gate cut feature. In some embodiments, the second gate cut feature tapers continuously from the top surface of the second gate structure toward the isolation structure. In some embodiments, the regional isolation feature includes a lower portion and an upper portion located above the lower portion, and the width of the regional isolation feature along the direction undergoes a step change between the lower portion and the upper portion. In some embodiments, the lower portion tapers downward. In some embodiments, the upper portion tapers downward.

[0045] In another exemplary aspect, the present disclosure relates to a method. The method includes: receiving a workpiece, the workpiece including: a substrate, a first fin-shaped structure, a second fin-shaped structure, and a third fin-shaped structure generated from a top surface of the substrate, an isolation structure located between a lower portion of the first fin-shaped structure and a lower portion of the second fin-shaped structure and between a lower portion of the second fin-shaped structure and a lower portion of the third fin-shaped structure, a dummy gate dielectric layer located above the isolation structure and above a surface of the first fin-shaped structure, the second fin-shaped structure, and the third fin-shaped structure that is higher than an upper portion of the isolation structure, and a dummy gate electrode layer located above the dummy gate dielectric layer; forming a first opening through the dummy gate electrode layer, the first opening being located directly above the second fin structure; etching the dummy gate electrode layer exposed in the first opening; A dielectric layer is formed to expose the second fin-shaped structure, and the second fin-shaped structure is etched to form a second opening to extend the first opening; a regional isolation feature is formed in the second opening; after forming the regional isolation feature, the dummy gate dielectric layer and the dummy gate electrode layer are replaced with a first metal gate structure above the first fin-shaped structure and a second metal gate structure above the third fin-shaped structure; a first gate cutting opening entering the first metal gate structure is formed between the first fin-shaped structure and the regional isolation feature; a second gate cutting opening entering the second metal gate structure is formed between the third fin-shaped structure and the regional isolation feature; and a first gate cutting feature and a second gate cutting feature are formed in the first gate cutting opening and the second gate cutting opening, respectively.

[0046] In some embodiments, neither the first gate cut opening nor the second gate cut opening cuts into the regional isolation feature. In some embodiments, the first opening exposes the dummy gate dielectric layer disposed on the isolation structure. In some embodiments, the second opening terminates in the substrate below the second fin structure. In some embodiments, each of the upper portions of the first fin structure, the second fin structure, and the third fin structure includes a stack, the stack including a plurality of channel layers interlaced with a plurality of sacrificial layers. In some embodiments, the replacement includes selectively removing the plurality of sacrificial layers to release the plurality of channel layers into a plurality of channel members. In some instances, the first metal gate structure includes a first gate dielectric layer and a first gate electrode layer located above the first gate dielectric layer, the second metal gate structure includes a second gate dielectric layer and a second gate electrode layer located above the second gate dielectric layer, a portion of the first gate dielectric layer extends along a first sidewall of the regional isolation feature, a portion of the second gate dielectric layer extends along a second sidewall of the regional isolation feature, and the second sidewall is opposite to the first sidewall. In some embodiments, the first gate cutting opening is formed without cutting into the portion of the first gate dielectric layer extending along the first sidewall of the regional isolation feature, and the second gate cutting opening is formed without cutting into the portion of the second gate dielectric layer extending along the second sidewall of the regional isolation feature.

[0047] In another exemplary aspect, the present disclosure relates to a method. The method includes: receiving a workpiece, the workpiece including: a substrate, an isolation structure located on the substrate; a first active region, a second active region, and a third active region generated from the substrate and extending above the isolation structure, a dummy gate dielectric layer located above the isolation structure and above surfaces of the first active region, the second active region, and the third active region above the isolation structure, and a dummy gate electrode layer located above the dummy gate dielectric layer; forming a first opening through the dummy gate electrode layer to expose the dummy gate dielectric layer above the second active region; etching the gate dielectric layer exposed in the first opening, and etching the second gate dielectric layer; The invention relates to a method for forming a dummy gate dielectric layer and a dummy gate electrode layer, wherein the dummy gate dielectric layer and the dummy gate electrode layer are replaced by a first metal gate structure on the first active region and a second metal gate structure on the third active region after the regional isolation feature is formed; a first gate cut feature extending through the first metal gate structure is formed, and the first gate cut feature is disposed between the first active region and the regional isolation feature; and a second gate cut feature extending through the second metal gate structure is formed, and the second gate cut feature is disposed between the third active region and the regional isolation feature. The first gate cut feature and the second gate cut feature are spaced apart from the regional isolation feature.

[0048] In some embodiments, the first metal gate structure includes a first gate dielectric layer and a first gate electrode layer located above the first gate dielectric layer, wherein the second metal gate structure includes a second gate dielectric layer and a second gate electrode layer located above the second gate dielectric layer, a portion of the first gate dielectric layer extends along the first sidewall of the regional isolation feature, and a portion of the second gate dielectric layer extends along the second sidewall of the regional isolation feature, and the second sidewall is opposite to the first sidewall. In some embodiments, forming the first opening includes using chlorine, hydrogen bromide, tetrafluoromethane, hydrogen, nitrogen, oxygen, or carbon dioxide. In some instances, extending the first opening includes using chlorine, hydrogen bromide, tetrafluoromethane, hexafluorobutadiene, hydrogen, nitrogen trifluoride, silicon tetrachloride, carbon dioxide, oxygen, or sulfur dioxide.

[0049] The features of several embodiments have been summarized above so that those skilled in the art can better understand the detailed description that follows. Those skilled in the art should understand that they can easily use this disclosure as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also be aware that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that they can make various modifications, substitutions, and changes to this document without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure comprising: substrate; a first base fin and a second base fin generated from the substrate; an isolation structure disposed between the first base fin and the second base fin along a direction; a first plurality of channel members disposed over the first substrate fin; a second plurality of channel members disposed over the second base fin; an area isolation feature extending through the isolation structure and into the substrate; a first gate structure surrounding each of the first plurality of channel members; a second gate structure surrounding each of the second plurality of channel members; a first gate cut feature extending through the first gate structure and into the isolation structure; and a second gate cut feature extending through the second gate structure and into the isolation structure, Wherein, along the direction, each of the first gate cutting feature and the second gate cutting feature is spaced apart from the regional isolation feature.

2. The semiconductor structure according to claim 1, in, The first gate structure includes a first gate dielectric layer and a first gate electrode layer located on the first gate dielectric layer. Wherein, a portion of the first gate dielectric layer is disposed along a sidewall of the regional isolation feature.

3. The semiconductor structure according to claim 2, wherein: The first gate cut feature is in direct contact with the first gate electrode layer.

4. The semiconductor structure according to claim 1, wherein: A bottom surface of the area isolation feature is lower than a bottom surface of the first gate cut feature.

5. The semiconductor structure according to claim 1, wherein: The second gate cut feature tapers continuously from a top surface of the second gate structure toward the isolation structure.

6. The semiconductor structure according to claim 1, in, The region isolation feature includes a lower portion and an upper portion located above the lower portion, Wherein, a width of the region isolation feature along the direction undergoes a step change between the lower portion and the upper portion.

7. The semiconductor structure according to claim 6, wherein: The lower portion tapers downwardly.

8. The semiconductor structure according to claim 6, wherein: The upper portion tapers downwardly.

9. A method comprising: A workpiece is received, the workpiece comprising: Substrate, a first fin-shaped structure, a second fin-shaped structure, and a third fin-shaped structure generated from a top surface of the substrate, an isolation structure located between a lower portion of the first fin-shaped structure and a lower portion of the second fin-shaped structure and between a lower portion of the second fin-shaped structure and a lower portion of the third fin-shaped structure, a dummy gate dielectric layer located above the isolation structure and above surfaces of the first fin-shaped structure, the second fin-shaped structure, and the third fin-shaped structure above an upper portion of the isolation structure, and a dummy gate electrode layer, located on the dummy gate dielectric layer; forming a first opening penetrating the dummy gate electrode layer, wherein the first opening is located directly above the second fin-shaped structure; extending the first opening by etching the dummy gate dielectric layer exposed in the first opening to expose the second fin-shaped structure, and etching the second fin-shaped structure to form a second opening; forming a region isolation feature in the second opening; After forming the area isolation features, replacing the dummy gate dielectric layer and the dummy gate electrode layer with a first metal gate structure over the first fin-shaped structure and a second metal gate structure over the third fin-shaped structure; forming a first gate cut opening into the first metal gate structure between the first fin structure and the area isolation feature; forming a second gate cut opening into the second metal gate structure between the third fin structure and the area isolation feature; and A first gate cut feature and a second gate cut feature are formed in the first gate cut opening and the second gate cut opening, respectively.

10. A method comprising: A workpiece is received, the workpiece comprising: Substrate, an isolation structure, located on the substrate; a first active region, a second active region and a third active region generated from the substrate and extending higher than the isolation structure, a dummy gate dielectric layer located above the isolation structure and above surfaces of the first active region, the second active region, and the third active region that are higher than the isolation structure, and a dummy gate electrode layer, located on the dummy gate dielectric layer; forming a first opening penetrating the dummy gate electrode layer to expose the dummy gate dielectric layer above the second active region; extending the first opening by etching the gate dielectric layer exposed in the first opening and etching the second active area to form a second opening; forming a region isolation feature in the second opening; After forming the area isolation features, replacing the dummy gate dielectric layer and the dummy gate electrode layer with a first metal gate structure over the first active area and a second metal gate structure over the third active area; forming a first gate cut feature extending through the first metal gate structure, the first gate cut feature being disposed between the first active region and the region isolation feature; and forming a second gate cut feature extending through the second metal gate structure, the second gate cut feature being disposed between the third active region and the regional isolation feature, The first gate cutting feature and the second gate cutting feature are spaced apart from the regional isolation feature.

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