Power semiconductor device layout

Abstract

The invention discloses a power semiconductor device which is provided with a substrate layer, an epitaxial layer, a well region, a source region and a well contact region. The epitaxial layer is provided with an epitaxial layer upper surface and an epitaxial layer lower surface, and the epitaxial layer lower surface is connected with the substrate layer. The well regions are distributed in the epitaxial layer and are distributed in a strip shape in the first direction of the upper surface of the epitaxial layer. The source regions are distributed in the well region and are distributed in a strip shape in the first direction of the upper surface of the epitaxial layer. The well contact region is distributed in the source region and overlaps with the source region in the first direction of the upper surface of the epitaxial layer. According to the invention, the well contact region is distributed in the source region, so that the size of the power semiconductor device is reduced, and the on-resistance of the power semiconductor device is reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a layout and structure of a power semiconductor device. Background Art

[0002] Figure 1 FIG. 1 shows a cross-sectional view of a conventional MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device 100. Figure 1 As shown, the MOSFET device 100 includes a semiconductor layer 111, and a gate structure 112 located on the semiconductor layer 111. The gate structure 112 includes a polysilicon gate 112a and an insulating layer 112b that wraps the polysilicon gate 112a. The semiconductor layer 111 includes a substrate layer 101, an epitaxial layer 102 located on the substrate layer 101, a well region 103 located in the epitaxial layer 102, and an adjacent source region 104 and a well contact region 105 located in the well region 103. At the same time, the lower surface of the semiconductor layer 111, that is, the surface of the substrate layer 101 of the device, is covered with a metal layer as a drain electrode 106, and the upper surface of the semiconductor layer 111, that is, the exposed surface of the source region 104, is covered with a metal layer as a source electrode 107. In the MOSFET device 100, as shown in FIG. Figure 1 As shown in FIG. 1 , the size of the cell on the cross section is L=Lohmic+2Lgs+2Loverlap+2Lch+Ljfet. Currently, the length of each part has reached the limit of the current process capability, and it is difficult to further reduce the cell size of the device, resulting in the device's on-resistance cannot be further reduced. Summary of the invention

[0003] The present application provides a power semiconductor device, which places a well contact region in a partial source region of a strip-shaped cell, thereby reducing the cell size of the device, thereby further reducing the on-resistance of the device.

[0004] According to one embodiment of the present application, a power semiconductor device is provided, comprising: a substrate layer; an epitaxial layer, having an epitaxial layer upper surface and an epitaxial layer lower surface, wherein the epitaxial layer lower surface is connected to the substrate layer; a well region, distributed in the epitaxial layer, and distributed in a strip shape in a first direction of the epitaxial layer upper surface; a source region, distributed in the well region, and distributed in a strip shape in a first direction of the epitaxial layer upper surface; and a well contact region, distributed in the source region, and overlapping with the source region in the first direction of the epitaxial layer upper surface.

[0005] According to a power semiconductor device of an embodiment of the present application, a plurality of the well contact regions are distributed in the one strip-shaped source region, and the plurality of well contact regions are distributed at equal distances in the first direction.

[0006] According to a power semiconductor device of an embodiment of the present application, a plurality of the well contact regions are distributed in the one strip-shaped source region, and a distance between adjacent well contact regions is greater than 0.5 μm.

[0007] According to a power semiconductor device of an embodiment of the present application, in a second direction on the upper surface of the epitaxial layer, the width of the well contact region is equal to the width of the source region, and the second direction is perpendicular to the first direction.

[0008] According to a power semiconductor device of an embodiment of the present application, in a second direction on the upper surface of the epitaxial layer, the width of the well contact region is greater than the width of the source region, and the second direction is perpendicular to the first direction.

[0009] According to a power semiconductor device of an embodiment of the present application, in a second direction on the upper surface of the epitaxial layer, the width of the well contact region is smaller than the width of the source region, and the second direction is perpendicular to the first direction.

[0010] According to a power semiconductor device according to an embodiment of the present application, the depth of the well contact region is greater than the depth of the source region.

[0011] According to a power semiconductor device according to an embodiment of the present application, the depth of the well contact region is equal to the depth of the source region.

[0012] According to a power semiconductor device of an embodiment of the present application, the well contact regions in the adjacent source regions are distributed on a straight line in a second direction on the upper surface of the epitaxial layer, and the second direction is perpendicular to the first direction.

[0013] According to a power semiconductor device of an embodiment of the present application, the well contact regions in adjacent source regions are distributed on different straight lines in a second direction on the upper surface of the epitaxial layer, and the second direction is perpendicular to the first direction.

[0014] The power semiconductor device according to the aforementioned embodiment further includes: a gate oxide layer located on the epitaxial layer; and a gate electrode layer located on the gate oxide layer and covering the gate oxide layer; wherein the gate oxide layer and the gate electrode layer cover other areas except the well contact area and the surrounding area of ​​the well contact area. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The above and other objects, features and advantages of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings:

[0016] Figure 1 A cross-sectional view of a conventional MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device 100 is shown;

[0017] Figure 2 is a schematic plan view of a partial region of a power semiconductor device 200 according to an embodiment of the present application;

[0018] Figure 3 According to an embodiment of the present application, Figure 2 A schematic diagram of a first cross section 300 of the power semiconductor device 200 along line AA′ in FIG.

[0019] Figure 4 According to an embodiment of the present application, Figure 2 A schematic diagram of a second cross section 400 of the power semiconductor device 200 along line BB';

[0020] Figure 5 A schematic plan view of a partial region of a power semiconductor device 500 according to an embodiment of the present application is shown;

[0021] Figure 6 According to an embodiment of the present application, Figure 5 A schematic diagram of a second cross section 600 of the power semiconductor device 500 along line BB';

[0022] Figure 7 is a schematic plan view of a partial region of a power semiconductor device 700 according to another embodiment of the present application;

[0023] Figure 8 According to an embodiment of the present application, Figure 7 A schematic diagram of a second cross section 800 of the power semiconductor device 700 along line BB';

[0024] Fig. 9 is a schematic plan view of a partial region of a power semiconductor device 900 according to an embodiment of the present application;

[0025] Fig.10 FIG. 1 is a schematic plan view of a partial region of a power semiconductor device 1000 according to an embodiment of the present application. DETAILED DESCRIPTION

[0026] The specific embodiments of the present application will be described in detail below. It should be noted that the embodiments described herein are only for illustration and are not intended to limit the present application. In the following description, a large number of specific details are set forth in order to provide a thorough understanding of the present application. However, it is obvious to those of ordinary skill in the art that these specific details do not have to be adopted to implement the present application. In other examples, in order to avoid confusing the present application, known circuits, materials or methods are not specifically described.

[0027] Throughout the specification, references to "one embodiment", "an embodiment", "an example" or "an example" mean that a particular feature, structure or characteristic described in conjunction with the embodiment or example is included in at least one embodiment of the present application. Therefore, the phrases "in one embodiment", "in an embodiment", "an example" or "an example" appearing in various places throughout the specification do not necessarily refer to the same embodiment or example. In addition, particular features, structures or characteristics may be combined in one or more embodiments or examples in any appropriate combination and / or sub-combination. In addition, it should be understood by those of ordinary skill in the art that the drawings provided herein are for illustrative purposes and that the drawings are not necessarily drawn to scale. The same reference numerals indicate the same elements. The term "and / or" used herein includes any and all combinations of one or more related listed items. The drawings are not drawn to scale and are for illustrative purposes only. For clarity, unless otherwise specified, the same elements have been designated by corresponding reference numerals in different drawings.

[0028] The terms “having,” “comprising,” “including,” “including,” and the like are open ended, and these terms indicate the presence of stated structures, elements, or features, but do not exclude additional elements or features.

[0029] When describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or region, it may mean that it is directly on the other layer or region, or that other layers or regions are included between it and the other layer or region. Furthermore, if the device is turned over, the layer or region will be "below" or "beneath" another layer or region.

[0030] If it is intended to describe a situation where it is directly on another layer or another area, this article will use the expression “directly on…” or “on… and adjacent to…”.

[0031] In this document, relative doping concentrations are described by indicating "-" or "+" next to the doping type "n" or "p". For example, "n-" means that the doping concentration is lower than the doping concentration of an "n"-doped region, while the "n"-doped region has a higher doping concentration than the "n-"-doped region. Doping regions of the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different "n"-doped regions may have the same or different absolute doping concentrations.

[0032] In an embodiment of the present application, each semiconductor layer or region has a first conductivity type or a second conductivity type. The first conductivity type refers to one of n-type or p-type, and the second conductivity type is the other one. That is to say, the semiconductor layer with the first conductivity type can be an n-type semiconductor layer or a p-type semiconductor layer. When the semiconductor layer with the first conductivity type is an n-type semiconductor layer, the semiconductor layer with the second conductivity type is a p-type semiconductor layer. The n-type semiconductor layer is formed by doping n-type impurities in the semiconductor layer. The n-type impurities can be pentavalent elements such as phosphorus, arsenic, and nitrogen. The p-type semiconductor layer is formed by doping p-type impurities in the semiconductor layer. The p-type impurities can be trivalent elements such as boron, indium, gallium, and aluminum.

[0033] Figure 2 FIG. 2 is a schematic plan view of a partial area of ​​a power semiconductor device 200 according to an embodiment of the present application. It should be understood that Figure 2 Only a partial planar structure of the power semiconductor device 200 on one horizontal plane is shown, which does not represent the overall structure of the power semiconductor device 200. Figure 2 As shown, a single cell 208 of the power semiconductor device 200 includes an epitaxial platform region 202, a well region 203, a source region 204, and a well contact region 205. The epitaxial platform region 202, the well region 203, and the source region 204 are in a strip shape, and their longitudinal direction is parallelly distributed along a first direction (y direction as shown in the figure). Among them, the well region 203 is distributed on both sides of the epitaxial platform region 202, the source region is distributed in the well region 203, and the well contact region 205 is distributed in the source region 204 of the strip cell, and there is a certain interval between adjacent well contact regions 205 distributed along the same straight line in the first direction.

[0034] exist Figure 2 In the embodiment, a single cell 208 of the power semiconductor device 200 includes an epitaxial platform region 202 and well regions 203 distributed on both sides of the epitaxial platform region 202. Adjacent cells share the well region 203. The well region 203 includes an active region 204 and a well contact region 205 distributed in the source region 204. The well contact region 205 is embedded in the source region 204 and is distributed on the same straight line as the source region 204.

[0035] Figure 2 The embodiment shows a partial area of ​​the upper surface 209 of the epitaxial layer of the power semiconductor device 200. The actual power semiconductor device 200 is composed of a plurality of cells. On the layout composed of the plurality of cells, a plurality of well contact regions 205 are distributed in the source region 204. In some embodiments, the well contact regions 205 in the strip source region 204 are distributed at equal distances. In some embodiments, the spacing h1 between adjacent well contact regions 205 in the strip source region 204 is at least 0.5 μm.

[0036] Figure 2Each sub-area shown in FIG. 2 is a structure on one of the horizontal planes 209 of the power semiconductor device 200 , such as the upper surface of the epitaxial layer. Figure 2 The area between the upper and lower dotted lines is the area of ​​the gate oxide layer or the gate electrode layer 212 covering the horizontal plane. In order to show the structure of each area on the horizontal plane, the device structure covering the horizontal plane is not drawn in the figure, but only the dotted lines are used to indicate the position of the gate oxide layer and the gate electrode layer. Therefore, the area between the two dotted lines in the figure represents the position of the gate oxide layer and the gate electrode layer, not the actual gate oxide layer and the gate electrode layer.

[0037] Figure 3 According to an embodiment of the present application, Figure 2 Schematic diagram of a first cross section 300 of a power semiconductor device 200 along line AA' in FIG. The first cross section 300 and the second direction, i.e. Figure 2 The x direction is parallel to the first direction, i.e. Figure 2 The y direction is vertical. Figure 3 As shown, the power semiconductor device 200 includes: a substrate layer 201, an epitaxial layer 219, a well region 203, a source region 204, a gate oxide layer 214, a gate electrode layer 212, a source electrode layer 207 and a drain electrode layer 206. The epitaxial layer 219 is located on the first surface of the substrate layer 201, and the drain electrode layer 206 covers the second surface of the substrate layer 201, and the first surface and the second surface are opposite and parallel. The epitaxial layer 219 has an epitaxial layer upper surface 209 and an epitaxial layer lower surface 210 that are opposite and parallel. Among them, the lower surface 210 of the epitaxial layer 219 covers the first surface of the substrate layer 201, and the upper surface 209 is covered by the gate oxide layer 214 on the first cross section 300. The epitaxial layer includes a plurality of well regions 203, extending from the epitaxial layer upper surface 209 to the inside of the epitaxial layer. The plurality of well regions 203 are isolated by the epitaxial platform region 202 and have approximately the same spacing. It should be understood that the epitaxial platform region 202 is a part of the epitaxial layer 219. The source region 204 is located in each well region 203, extending from the upper surface 209 of the epitaxial layer to the inside of the well region, wherein the bottom of the source region 204 does not reach the bottom of the well region 203, that is, the distance between the bottom of the well region 203 and the upper surface 209 of the epitaxial layer is greater than the distance between the bottom of the source region 204 and the upper surface 209 of the epitaxial layer. Both the well region 203 and the source region 204 are exposed to the upper surface 209 of the epitaxial layer. The gate oxide layer 214 covers the upper surface 209 of the epitaxial layer, isolating the gate electrode layer 212 thereon from the upper surface 209 of the epitaxial layer below. The gate electrode layer 212 is covered with an interlayer dielectric layer 213, and the source electrode layer 207 is located on the interlayer dielectric layer 213, and the gate electrode layer 212 and the source electrode layer 207 are isolated by the interlayer dielectric layer 213.

[0038] In one embodiment, the gate oxide layer 214 is silicon dioxide with a thickness between 5 and 200 nanometers. In other embodiments, the gate oxide layer 214 may also include other insulating materials such as silicon nitride and aluminum nitride. The interlayer dielectric layer 213 may be the same insulating material as the gate oxide layer 214, or may be other different insulating materials. The thickness of the interlayer dielectric layer 213 is much greater than the thickness of the gate oxide layer 214.

[0039] In one embodiment, the epitaxial layer 219 is of a single conductivity type and has a substantially uniform concentration. In some embodiments, the epitaxial layer 219 includes multiple semiconductor layers with different doping concentrations. For example, the epitaxial layer 219 may include a first semiconductor layer with a first doping concentration and a second semiconductor layer with a second doping concentration, wherein the first semiconductor layer is located in a region below the well region at a certain distance from the bottom of the well region, and the second semiconductor layer is located above the first semiconductor layer, and the first doping concentration is less than the second doping concentration. In other embodiments, the epitaxial layer 219 may also be composed of more semiconductor layers with different doping concentrations.

[0040] In one embodiment, the substrate layer 201, the epitaxial layer 219 and the source region 204 have a first doping type, and the well region 203 and the well contact region 205 have a second doping type. In one embodiment, the first doping type is n-type doping, and the second doping type is p-type doping. It should be understood that in other embodiments, the first doping type may be p-type doping, and the second doping type may be n-type doping. In one embodiment, the doping concentration of the well contact region 205 is greater than the doping concentration of the well region 203, and the doping concentration of the substrate layer 201 is greater than the doping concentration of the epitaxial layer 219.

[0041] exist Figure 3 In the embodiment, the epitaxial terrace region 202 located between the well regions 203 and the portion close to the gate oxide layer 214 form a JFET region. Figure 3 As can be seen in the figure, in the first cross section 300, there is no well contact region 205, so the size of a single cell of the power semiconductor device 200 is L= Ls+2Lch+Ljfet. Compared with the prior art, since the well contact region 205 is located in the source region 204, but not in the second direction (such as Figure 2 In the x direction shown in FIG. 1 ), the first cross section 300 overlaps with the source region 204 in size, that is, the well contact region 205 is not included in the first cross section 300, and further, the ohmic contact region (the contact between the source electrode layer and the well contact region and the source region) is not included. Therefore, in the second direction, that is, in the direction perpendicular to the length of the source region, there is no need to have Figure 1The ohmic contact region, the overlap region between the gate oxide layer and the source region, and the thickness of the sidewall of the interlayer dielectric layer are shown, that is, the dimensions Lohmic, Loverlap, and Lgs are omitted. Furthermore, since no ohmic contact is required, the width of the source region can also be greatly reduced, so that the size of the device can be greatly reduced, so that the semiconductor device 200 can have a smaller device area.

[0042] Figure 4 According to an embodiment of the present application, Figure 2 FIG. 4 is a schematic diagram of a second cross section 400 of the power semiconductor device 200 along line BB' in FIG. Figure 4 As shown, the second cross section 400 includes: a substrate layer 201, an epitaxial layer 219, a well region 203, a well contact region 205, an interlayer dielectric layer 213, a source electrode layer 207, and a drain electrode layer 206. In the second cross section 400, the well contact region 205 is located in each well region 203, extending from the upper surface 209 of the epitaxial layer to the inside of the well region. The well region 203 and the well contact region 205 are both exposed on the upper surface of the epitaxial layer. In the second cross section 400, the gate oxide layer 214 and the gate electrode layer 212 are not distributed. The source electrode layer 207 extends downward through the window in the interlayer dielectric layer 213 and contacts the well contact region 205 and the part of the well region 203 exposed on the upper surface 209 of the epitaxial layer, as well as the part not in the second cross section 400. Figure 4 That is, in order to make the well contact region 205 contact with the source electrode layer 207, so as to connect the potential of the well region 203 to the source potential of the device (i.e., the potential connected to the source electrode layer), a plurality of windows are opened in the interlayer dielectric layer 213, and the source electrode layer 207 partially extends downward to fill the windows in the interlayer dielectric layer 213, or in some embodiments, the windows in the interlayer dielectric layer 213 may be filled with a conductive through-hole structure, so as to electrically connect the well contact region 205 and the source region 204 to the source electrode layer 207, and further to the source potential of the power semiconductor device 200.

[0043] Different from the first cross section 300, in the second cross section 400, the well contact region 205 replaces the source region 204 and is located in the well region 203. Also, in the second cross section 400, the gate oxide layer 214 and the gate electrode layer 212 are not distributed. Figure 2 From the perspective of FIG. 2 , in the longitudinal direction of the cell 208, i.e., in a partial area of ​​the strip-shaped source region, a well contact region 205 is distributed, and this area is used to connect the well contact region 205 and a partial area of ​​the source region 204 to the source electrode layer 207. Therefore, the gate oxide layer 214 and the gate electrode layer 212 are not distributed in this end area.

[0044] Figure 5 FIG. 5 is a schematic plan view of a partial area of ​​a power semiconductor device 500 according to an embodiment of the present application. It should be understood that Figure 5Only a partial planar structure of the power semiconductor device 500 on one horizontal plane is shown, which does not represent the overall structure of the power semiconductor device 500. Figure 5 As shown, Figure 5 As shown, a single cell 508 of the power semiconductor device 500 includes an epitaxial platform region 202, a well region 203, a source region 204, and a well contact region 205. The epitaxial platform region 202, the well region 203, and the source region 204 are in the shape of long strips, and their longitudinal direction is parallelly distributed along the first direction (y direction as shown in the figure). Among them, the well region 203 is distributed on both sides of the epitaxial platform region 202, the source region 204 is distributed in the well region 203, and the well contact region 205 is distributed in a part of the source region 204. There is a certain interval h1 between adjacent well contact regions 205 distributed along the same straight line in the first direction. In some embodiments, the interval is at least 0.5μm.

[0045] exist Figure 5 In the embodiment, Figure 2 The difference between the embodiments is that the gate oxide layer and the gate electrode layer extend along the first direction to the area between the two adjacent well regions in the two end regions of the cell 508, covering the epitaxial platform region 202 between the two adjacent well regions, and partial areas of the adjacent well regions on both sides of the epitaxial platform region 202. This increases the current density of the device. In other words, the gate oxide layer and the gate electrode layer cover other areas except the well contact region 205 and its surrounding areas, wherein the well contact region 205 and its surrounding areas are the areas within the dotted box in the figure.

[0046] The first cross section of the power semiconductor device 500 along line AA′ is as follows: Figure 3 As shown, no further description is given here.

[0047] Figure 6 According to an embodiment of the present application, Figure 5 FIG. 6 is a schematic diagram of a second cross section 600 of a power semiconductor device 500 along line BB' in FIG. Figure 6 As shown, the second cross section 600 includes a substrate layer 201, an epitaxial layer 219, a well region 203, a well contact region 205, a gate oxide layer 214, a gate electrode layer 212, an interlayer dielectric layer 213, a source electrode layer 207, and a drain electrode layer 206. Figure 4 Compared with the second cross section 400 shown, in the coverage area of ​​the interlayer dielectric layer 213, on the epitaxial platform region 202, there is also a gate structure, namely, a gate oxide layer 214 and a gate electrode layer 212. The gate structure generates a channel in the sidewall portion of the well region below it close to the epitaxial platform region 202, thereby further improving the current density of the device.

[0048] exist Figure 2-Figure 6In the embodiment, the well contact region 205 is distributed at both ends of the cell 208. In other embodiments, the well contact region can be distributed at any position of the source region 204, overlapping with the source region 204 in the first direction or having the same central axis. In addition, the well contact region 205 does not need to be distributed in each strip of the source region 204. A person of ordinary skill in the art can select the distribution of the well contact region 205 in the source region 204 as needed under the enlightenment of the disclosure of the present invention. When the well contact region 205 is not distributed in each strip of the source region 204, or the well contact region 205 is staggered in the second direction instead of in a straight line, the cell in the second cross section does not have the well contact region 205 distributed in both adjacent well regions. The second cross section referred to in the embodiment of the present invention refers to a cross section including at least one cross section of the well contact region 205.

[0049] Figure 7 FIG. 7 is a schematic plan view of a partial region of a power semiconductor device 700 according to another embodiment of the present application. It should be understood that Figure 7 Only a partial planar structure of the power semiconductor device 700 on one horizontal plane is shown, which does not represent the overall structure of the power semiconductor device 700. Figure 7 As shown, a single cell 708 of the power semiconductor device 700 includes an epitaxial platform region 202, a well region 203 and a source region 204. The epitaxial platform region 202, the well region 203 and the source region 204 are in the shape of long strips, and their longitudinal directions are parallelly distributed along a first direction (y direction as shown in the figure). Among them, the well region 203 is distributed on both sides of the epitaxial platform region 202, and the source region is distributed in the well region 203.

[0050] and Figure 2 and Figure 5 The difference in the embodiment is that in Figure 7 In the embodiment, the well contact regions 205 in different source regions 204 are staggered in the second direction, that is, the well contact regions 205 in adjacent source regions 204 are arranged on different straight lines.

[0051] exist Figure 7 In the embodiment, the first cross section along the AA′ line has the same structure as the first cross section 300 of the power semiconductor device 200 , and therefore, for the sake of simplicity, it will not be described in detail here.

[0052] Figure 8 According to an embodiment of the present application, Figure 7 FIG. 8 is a schematic diagram of a second cross section 800 of a power semiconductor device 700 along line BB'. Figure 8As shown, the second cross section 800 includes: a substrate layer 201, an epitaxial layer 219, a well region 203, a source region 204, a gate oxide layer 214, a gate electrode layer 212, an interlayer dielectric layer 213, a source electrode layer 207, and a drain electrode layer 206. In the second cross section 800, the source electrode layer 207 extends downward through the window in the interlayer dielectric layer 213 and contacts the well contact region 205 and the well region region (a part of the well region connected to the sidewall of the well contact region 205 along the first direction) and the source region region (a part of the source region connected to the sidewall of the well contact region 205 along the second direction) around the well contact region 205, thereby connecting the potentials of the source region 204 and the well region 203 to the potential of the source electrode layer 207.

[0053] Fig. 9 FIG. 9 is a schematic plan view of a partial area of ​​a power semiconductor device 900 according to an embodiment of the present application. It should be understood that Fig. 9 Only a partial planar structure of the power semiconductor device 900 on one horizontal plane is shown, which does not represent the overall structure of the power semiconductor device 900. Figure 2 Compared with the embodiment, Fig. 9 In the embodiment, the width of the well contact region 905 in the second direction is greater than the width of the source region 204 in the second direction, that is, the well contact region 905 is wider than the source region 204, which is beneficial to increase the area of ​​the well contact region and improve the current capability of the power semiconductor device 900. It should be understood that in order to further increase the current channel of the device and reduce the on-resistance, in some embodiments, Fig. 9 On the basis of the first direction, the gate oxide layer 214 and the gate electrode layer 212 are extended to the middle area of ​​the adjacent well contact region, that is, the coverage area of ​​the gate oxide layer 214 and the gate electrode layer 212 on the upper surface 209 of the epitaxial layer can be as follows Figure 5 shown.

[0054] Fig.10 FIG. 1 is a schematic plan view of a partial area of ​​a power semiconductor device 1000 according to an embodiment of the present application. It should be understood that Fig.10 Only a partial planar structure of the power semiconductor device 1000 on one horizontal plane is shown, which does not represent the overall structure of the power semiconductor device 1000. Figure 7 Compared with the embodiment, Fig.10 In the embodiment, the width of the well contact region 1005 in the second direction is greater than the width of the source region 204 in the direction, that is, the well contact region 1005 is wider than the source region 204 , which is beneficial to increase the area of ​​the well contact region and improve the current capacity of the power semiconductor device 1000 .

[0055] The embodiments of the present application illustrate the case where the width of the well contact region is greater than or equal to the width of the source region. It should be understood that in some embodiments, the width of the well contact region may also be smaller than the width of the source region.

[0056] In the above-mentioned embodiment, the well region 203, the well contact region 205 and the source region 204 all extend vertically from the surface of the epitaxial layer to the inside thereof. The distance from the upper surface 209 of the epitaxial layer to the bottom of the well region 203 in the direction perpendicular to the upper surface 209 of the epitaxial layer is the depth of the well region 203, the distance from the upper surface 209 of the epitaxial layer to the bottom of the well contact region 205 in the direction perpendicular to the upper surface 209 of the epitaxial layer is the depth of the well contact region 205, and the distance from the upper surface 209 of the epitaxial layer to the bottom of the source region 204 in the direction perpendicular to the upper surface 209 of the epitaxial layer is the depth of the source region 204. In some embodiments, the depth of the well region 203 is greater than the depths of the source region 204 and the well contact region 205. In some embodiments, the depth of the source region 204 is consistent with the depth of the well contact region 205. In some embodiments, the depth of the well contact region 205 is greater than the depth of the source region 204.

[0057] The embodiment of the present application shows a schematic diagram of the structure of a single epitaxial layer. In some embodiments, the epitaxial layer may include multiple epitaxial layers with different doping concentrations. In these embodiments, the well region 203 may be disposed in the uppermost epitaxial layer, that is, the epitaxial layer closest to the source electrode layer 207.

[0058] This application uses MOSFET devices as an example to illustrate the principles of the invention. It should be understood that the present invention is also applicable to power semiconductor devices of other structures, such as IGBTs, etc. After reading this application, a person of ordinary skill in the art can make improvements based on the device layout of this application as needed and apply it to devices of other structures or types.

[0059] The embodiments of the present application can be used not only for devices using silicon as a semiconductor base layer, but also for devices using wide bandgap materials, such as SiC and GaN, as a semiconductor base layer.

[0060] The embodiments of the present application are described above, and these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and the modifications based on the present application. The present application is only limited by the claims and their full scope and equivalents.

Claims

1. A power semiconductor device, comprising: substrate layer; The epitaxial layer has an epitaxial layer upper surface and an epitaxial layer lower surface, wherein the epitaxial layer lower surface is in contact with the substrate layer; The well region is distributed in the epitaxial layer and is distributed in a strip shape in a first direction on the upper surface of the epitaxial layer; A source region is distributed in the well region and is distributed in a strip shape in a first direction on the upper surface of the epitaxial layer; and The well contact region is distributed in the source region and overlaps with the source region in a first direction on the upper surface of the epitaxial layer. 2 . The power semiconductor device according to claim 1 , wherein a plurality of the well contact regions are distributed in the one strip-shaped source region, and the plurality of well contact regions are distributed at equal distances in the first direction. 3 . The power semiconductor device according to claim 1 , wherein a plurality of the well contact regions are distributed in the one strip-shaped source region, and a distance between adjacent well contact regions is greater than 0.5 μm. 4 . The power semiconductor device according to claim 1 , wherein in a second direction on the upper surface of the epitaxial layer, a width of the well contact region is equal to a width of the source region, and the second direction is perpendicular to the first direction. 5 . The power semiconductor device according to claim 1 , wherein in a second direction on the upper surface of the epitaxial layer, a width of the well contact region is greater than a width of the source region, and the second direction is perpendicular to the first direction. 6 . The power semiconductor device according to claim 1 , wherein in a second direction on the upper surface of the epitaxial layer, a width of the well contact region is smaller than a width of the source region, and the second direction is perpendicular to the first direction. 7 . The power semiconductor device of claim 1 , wherein a depth of the well contact region is greater than a depth of the source region. 8 . The power semiconductor device of claim 1 , wherein a depth of the well contact region is equal to a depth of the source region. 9 . The power semiconductor device according to claim 1 , wherein the well contact regions in the adjacent source regions are distributed in a straight line in a second direction on the upper surface of the epitaxial layer, and the second direction is perpendicular to the first direction. 10 . The power semiconductor device according to claim 1 , wherein the well contact regions in the adjacent source regions are distributed on different straight lines in a second direction on the upper surface of the epitaxial layer, and the second direction is perpendicular to the first direction.

11. The power semiconductor device according to any one of claims 1 to 10, further comprising: a gate oxide layer, located on the epitaxial layer; as well as A gate electrode layer is located on the gate oxide layer and covers the gate oxide layer; The gate oxide layer and the gate electrode layer cover other regions except the well contact region and the region around the well contact region.

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