Oxide semiconductor-based ferroelectric vertical transistor and method for manufacturing the same

Abstract

The application belongs to the technical field of microelectronic devices, and discloses an oxide semiconductor-based ferroelectric vertical transistor and a preparation method thereof.The ferroelectric vertical transistor comprises a substrate, a gate metal electrode, a gate ferroelectric layer, a gate insulating dielectric layer, an island-shaped source electrode, an oxide semiconductor, a source contact electrode and a top drain electrode.The application uses hafnium oxide-based ferroelectric material as the gate ferroelectric material, can realize information writing and reading, amplify the regulation effect of the gate voltage on the channel, reduce the ratio of the gate capacitance to the channel capacitance, reduce the working voltage of the transistor, and reduce the power consumption of the ferroelectric vertical transistor.In addition, a gate insulating dielectric layer is further prepared on the gate ferroelectric film to promote the formation of the ferroelectric phase, and the introduction of the insulating dielectric layer can inhibit the injection of charges, thereby adjusting the polarization state of the hafnium oxide-based ferroelectric material and improving the overall performance of the ferroelectric transistor.

Description

Technical Field

[0001] This invention belongs to the field of microelectronic device technology, and more specifically, relates to a ferroelectric vertical transistor based on oxide semiconductor and its fabrication method. Background Technology

[0002] With the continuous development of the information age and global interconnection, the amount of data generated globally has experienced explosive growth in recent years, characterized by short cycles and exponential increases. The emergence of new scenarios such as robots, smart living, and autonomous driving has led to the development of increasingly large-scale models to support massive data processing demands. However, transistor technology is nearing the limits of Moore's Law, and further miniaturization of transistors faces challenges such as short-channel effects, tunneling effects, and excessive power consumption. Simultaneously, due to the inherent properties of the electron Boltzmann distribution, the subthreshold swing limit of transistors is approximately 60mV / decade, making it difficult for traditional planar MOSFETs to achieve low power consumption in large-scale integrated circuits. Therefore, to meet the massive data storage demands and overcome the power consumption problems of large-scale integrated circuits, it is necessary to develop ultra-low-power, fast-read / write, and stable-performance memory devices.

[0003] Inorganic ferroelectric transistors have unique advantages in low-power devices. Their main principle is to utilize the polarization reversal property of ferroelectric materials for writing and reading information, thereby achieving information storage. Currently, mainstream ferroelectric memories are mainly divided into two types: 1T1C and 1T. 1T1C type data reading is destructive, requiring rewriting after reading, with a limited maximum number of reads. Furthermore, the circuit contains a capacitor in addition to the transistor, which is not conducive to high-density integration. In contrast, the 1T type structure with a single transistor is non-destructive, has a relatively simple structure, and is easier to integrate on a large scale. While two-dimensional materials are advantageous channel materials for extending the Mohr's limit, their high contact resistance at the metal electrode interface increases device power consumption and is incompatible with CMOS processes. Therefore, developing transistors that can overcome the short-channel effect, have low power consumption, high storage characteristics, and are compatible with CMOS processes is an important direction for the future of memory transistors. Summary of the Invention

[0004] In view of the above-mentioned defects or improvement needs of the prior art, the present invention provides a ferroelectric vertical transistor based on oxide semiconductor and its fabrication method. The purpose is to construct a ferroelectric vertical transistor with ultra-short channel, low power consumption and high storage characteristics, thereby solving the technical problems of short channel effect and tunneling effect that occur in traditional planar transistors as the channel size is miniaturized.

[0005] To achieve the above objectives, according to one aspect of the present invention, a ferroelectric vertical transistor based on an oxide semiconductor is provided. The ferroelectric vertical transistor includes a substrate 100, a gate metal electrode 200, a gate ferroelectric layer 300, a gate insulating dielectric layer 400, an island source 500, an oxide semiconductor 600, a source contact electrode 700, and a top drain 800. The substrate 100, gate metal electrode 200, gate ferroelectric layer 300, gate insulating dielectric layer 400, and island source 500 are stacked layer by layer from bottom to top. The oxide semiconductor 600 and source contact electrode 700 are disposed on the island source, and the top drain 800 is disposed on the oxide semiconductor 600. The channel length of the ferroelectric vertical transistor is equal to the actual thickness of the oxide semiconductor 600. The ferroelectric vertical transistor achieves data erasure and writing by controlling the polarization direction of the gate ferroelectric layer 300 through positive and negative gate voltages.

[0006] Preferably, the substrate 100 is a rigid substrate or a flexible substrate with an insulating layer.

[0007] Preferably, the gate metal electrode 200 is a tungsten electrode prepared by magnetron sputtering or electron beam evaporation, with a thickness of 30 nm to 80 nm.

[0008] Preferably, the gate ferroelectric layer 300 is one of HZO, HfO2, and ZrO2 thin films prepared by atomic layer deposition, and its thickness is 5nm to 20nm.

[0009] Preferably, the gate insulating dielectric layer 400 is an Al2O3 thin film prepared by atomic layer deposition, with a thickness of 3nm to 5nm.

[0010] Preferably, the island-shaped source electrode 500 is configured as one of ultrathin island-shaped aluminum prepared by magnetron sputtering and ultrathin island-shaped silver prepared by thermal evaporation.

[0011] Preferably, the oxide semiconductor 600 is a semiconductor layer prepared by magnetron sputtering, and its thickness is 10nm to 25nm.

[0012] Preferably, the source contact electrode 700 is one of aluminum, silver, gold and indium tin oxide, and its thickness is 40nm to 80nm; the top drain electrode 800 is one of aluminum, silver, gold and indium tin oxide, and its thickness is 40nm to 80nm.

[0013] According to another aspect of the present invention, a method for fabricating a ferroelectric vertical transistor based on oxide semiconductor is provided, comprising the following steps:

[0014] (1) A tungsten electrode is prepared on a substrate 100 with an insulating layer by magnetron sputtering or electron beam evaporation to serve as a gate metal electrode 200.

[0015] (2) On the gate metal electrode 200, the gate ferroelectric layer 300 and the gate insulating dielectric layer 400 are prepared sequentially from bottom to top by atomic layer deposition. Then, the gate ferroelectric layer 300 and the gate insulating dielectric layer 400 are rapidly annealed in a rapid annealing furnace at a temperature of 350℃~450℃ and an annealing time of 40s~60s.

[0016] (3) On the gate insulating dielectric layer 400, an ultra-thin island aluminum prepared by magnetron sputtering or an ultra-thin island silver prepared by thermal evaporation is annealed to form an island source electrode 500.

[0017] (4) A window is opened on the island source electrode 500 by photolithography or masking, and an oxide semiconductor 600 is prepared by magnetron sputtering.

[0018] (5) Windows are opened on the island source 500 and oxide semiconductor 600 by photolithography or masking, and then the top drain 800 is prepared on the oxide semiconductor 600 and the source contact electrode 700 is prepared on the island source 500 by thermal evaporation, magnetron sputtering or printing to obtain a ferroelectric vertical transistor.

[0019] (6) The ferroelectric vertical transistor is annealed as a whole to complete the fabrication of the ferroelectric vertical transistor.

[0020] Preferably, in step (3), the magnetron sputtering process parameters are set as follows: power 60W-80W, pressure 1.3×10-4Torr; the metal thickness of the island source electrode 500 is in the range of 5nm-15nm, and the annealing temperature is between 150℃ and 250℃.

[0021] In summary, compared with the prior art, the ferroelectric vertical transistor based on oxide semiconductor and its fabrication method provided by the present invention have the following advantages:

[0022] 1. This invention mainly proposes a novel inorganic ferroelectric vertical transistor structure. It adopts a vertical structure design, and the channel length of the vertical transistor is determined by the thickness of the oxide semiconductor. The short channel of the transistor is achieved by preparing an ultra-thin, high-quality semiconductor thin film. The ultra-short semiconductor channel brings high current density and high-speed response speed to the transistor. At the same time, the use of magnetron sputtering or thermal evaporation to deposit an ultra-thin island metal as the source increases the controllability of the transistor source preparation.

[0023] 2. This invention utilizes hafnium oxide-based ferroelectric materials as gate ferroelectric materials. On the one hand, it utilizes the polarization of ferroelectric materials in different directions under positive and negative gate voltages to realize the writing and reading of information. On the other hand, the application of hafnium oxide-based ferroelectric materials can amplify the control effect of gate voltage on the channel, reduce the ratio of gate capacitance to channel capacitance, reduce the operating voltage of the transistor, and thus reduce the power consumption of the device.

[0024] 3. This invention promotes the formation of the ferroelectric phase by preparing a gate insulating dielectric layer on the gate ferroelectric layer film. At the same time, the introduction of the insulating dielectric layer can suppress charge injection, thereby adjusting the polarization state of the hafnium oxide-based ferroelectric material, so that the ferroelectric vertical transistor has high hysteresis and a large storage window, thus improving the overall performance of the ferroelectric vertical transistor. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the structure obtained in step 1 of the preparation method in this embodiment of the invention;

[0026] Figure 2 This is a schematic diagram of the structure obtained in step 2 of the preparation method in this embodiment of the invention;

[0027] Figure 3 This is a schematic diagram of the structure obtained in step 3 of the preparation method in this embodiment of the invention;

[0028] Figure 4 This is a schematic diagram of the structure obtained in step 4 of the preparation method in this embodiment of the invention;

[0029] Figure 5 This is a schematic diagram of the structure obtained in step 5 of the preparation method in this embodiment of the invention;

[0030] Figure 6 This is a schematic diagram of the structure obtained in step 6 of the preparation method in this embodiment of the invention;

[0031] Figure 7 This is a schematic diagram of the structure obtained in step 7 of the preparation method in this embodiment of the invention;

[0032] Figure 8 This is a schematic diagram of the expected transfer characteristic curve of the ferroelectric vertical transistor prepared in the embodiment of the present invention;

[0033] In all the accompanying drawings, the same reference numerals are used to denote the same elements or structures, wherein:

[0034] 100—Substrate, 200—Gate metal electrode, 300—Gate ferroelectric layer, 400—Gate insulating dielectric layer, 500—Island source, 600—Oxide semiconductor, 700—Source contact electrode, 800—Top drain. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0036] This embodiment introduces an In₂O₃ ferroelectric vertical transistor based on HZO and its fabrication method. This ferroelectric vertical transistor, as shown in the example... Figure 7 As shown, the structure includes a substrate (100), a gate metal electrode (200), a gate ferroelectric layer (300), a gate insulating dielectric layer (400), an island source (500), an oxide semiconductor (600), a source contact electrode (700), and a top drain (800). The substrate (100), gate metal electrode (200), gate ferroelectric layer (300), gate insulating dielectric layer (400), and island source (500) are stacked layer by layer from bottom to top. The oxide semiconductor (600) and the source contact electrode (700) are disposed on the island source, and the top drain (800) is disposed on the oxide semiconductor (600). The channel length of the ferroelectric vertical transistor is the actual thickness of the oxide semiconductor (600). The ferroelectric vertical transistor controls the polarization direction of the gate ferroelectric layer (300) through positive and negative gate voltages, thereby realizing the erasure and writing of data by the ferroelectric vertical transistor.

[0037] The specific steps of a method for fabricating an In2O3 ferroelectric vertical transistor based on HZO are as follows:

[0038] Step 1: Prepare substrate 100.

[0039] Select a silicon wafer with 300nm SiO2, cut it into 2cm×2cm pieces using a dicing machine, then ultrasonically clean it in acetone and isopropanol for 15 minutes each, rinse it thoroughly with deionized water, and dry it with nitrogen gas before using it as a substrate. Figure 1 .

[0040] Step 2: Fabrication of the gate metal electrode 200.

[0041] Tungsten electrodes were fabricated using a DC target via magnetron sputtering. A substrate with a 250 μm × 350 μm window pre-written using laser direct writing was placed in a cavity. After evacuation, the experiment began. The process parameters were 120 W DC and 50 sccm Ar. A 50 nm tungsten electrode was fabricated as the gate metal electrode. Figure 2 .

[0042] Step 3: Fabrication of the gate ferroelectric layer 300.

[0043] Using atomic layer deposition (ALD), the oxygen, zirconium, and hafnium sources are preheated. The sample is placed in the reaction chamber, which is then evacuated. A 15 nm HZO thin film is grown on the gate metal electrode at a reaction temperature of 300 °C. Figure 3 .

[0044] Step 4: Preparation of gate insulating dielectric layer 400.

[0045] Using atomic layer deposition (ALD), the oxygen and aluminum sources are preheated, the sample is placed in the reaction chamber, and then the chamber is evacuated. A 5nm Al₂O₃ film is grown on the HZO film as the gate insulating dielectric layer at a reaction temperature of 280℃. Figure 4 The prepared film was then subjected to rapid annealing at 450°C for 45 seconds in a rapid annealing furnace to promote the formation of the HZO ferroelectric phase.

[0046] Step 5: Preparation of island-shaped source electrode 500.

[0047] Using a magnetron sputtering system, the chamber is evacuated to a high vacuum, and DC sputtering is performed on the gate insulating dielectric layer at a power of 80W for a pre-sputtering time of 5 minutes. Then, the substrate baffle is opened, and sputtering continues for another 5 minutes. Finally, annealing at 150°C is performed to form an island-shaped source electrode. Figure 5 .

[0048] Step 6: Fabrication of oxide semiconductor 600.

[0049] A 150μm × 250μm window was opened on the island-shaped source electrode obtained in step 5 using laser direct writing. Then, In₂O₃ was prepared by DC sputtering using magnetron sputtering with process parameters of 60W, 35sccm Ar, and 5sccm O₂, resulting in a 20nm In₂O₃ oxide semiconductor. Figure 6 .

[0050] Step 7: Fabrication of source contact electrode 700 and top drain electrode 800.

[0051] Using laser direct writing, 100μm × 100μm windows were created on the island-shaped source electrode 500 obtained in step 5 and the semiconductor channel 600 obtained in step 6, respectively. Then, Al was fabricated using magnetron sputtering with DC sputtering at 80W and 20sccm Ar to prepare 50nm Al as the source contact electrode 700 and the top drain electrode 800. Figure 7 .

[0052] Step 8: Annealing of ferroelectric vertical transistors.

[0053] In a tube furnace, the ferroelectric vertical transistors are annealed as a whole. The process involves annealing at 250°C for 1 hour under a nitrogen atmosphere to complete the fabrication of the ferroelectric vertical transistors.

[0054] The transfer characteristic curve of the ferroelectric vertical transistor in this embodiment is expected to yield the experimental results as follows: Figure 8 This embodiment employs a hafnium oxide-based ferroelectric dielectric layer, which amplifies the gate voltage's control over the channel, reduces the gate capacitance to channel capacitance ratio, and enables low-power transistor operation. The fabricated ferroelectric vertical transistor is expected to exhibit low subthreshold swing. Furthermore, the addition of an extra gate insulating dielectric layer above the ferroelectric gate layer further promotes the formation of the ferroelectric phase in the ferroelectric material, resulting in a ferroelectric vertical transistor with high hysteresis and a large memory window.

[0055] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An oxide semiconductor-based ferroelectric vertical transistor, characterized by: The ferroelectric vertical transistor includes a substrate (100), a gate metal electrode (200), a gate ferroelectric layer (300), a gate insulating dielectric layer (400), an island source (500), an oxide semiconductor (600), a source contact electrode (700), and a top drain (800). The substrate (100), gate metal electrode (200), gate ferroelectric layer (300), gate insulating dielectric layer (400), and island source (500) are stacked layer by layer from bottom to top. The oxide semiconductor (600) and the source contact electrode (700) are disposed on the island source, and the top drain (800) is disposed on the oxide semiconductor (600). The channel length of the ferroelectric vertical transistor is the actual thickness of the oxide semiconductor (600). The ferroelectric vertical transistor can control the polarization direction of the gate ferroelectric layer (300) by positive and negative gate voltage, thereby realizing the erasure and writing of data by the ferroelectric vertical transistor.

2. The oxide semiconductor-based ferroelectric vertical transistor according to claim 1, wherein: The substrate (100) is a rigid substrate or a flexible substrate with an insulating layer.

3. The oxide semiconductor-based ferroelectric vertical transistor according to claim 1, wherein: The gate metal electrode (200) is a tungsten electrode prepared by magnetron sputtering or electron beam evaporation, with a thickness of 30 nm to 80 nm.

4. The oxide semiconductor-based ferroelectric vertical transistor according to claim 1, wherein The gate ferroelectric layer (300) is one of HZO, HfO2, and ZrO2 thin films prepared by atomic layer deposition, with a thickness of 5 nm to 20 nm.

5. The oxide semiconductor-based ferroelectric vertical transistor according to claim 1, wherein The gate insulating dielectric layer (400) is an Al2O3 thin film prepared by atomic layer deposition, with a thickness of 3nm to 5nm.

6. The ferroelectric vertical transistor based on oxide semiconductor according to claim 1, characterized in that, The island-shaped source electrode (500) is configured as either an ultrathin island-shaped aluminum prepared by magnetron sputtering or an ultrathin island-shaped silver prepared by thermal evaporation.

7. The ferroelectric vertical transistor based on oxide semiconductor according to claim 1, characterized in that, The oxide semiconductor (600) is a semiconductor layer prepared by magnetron sputtering, with a thickness of 10 nm to 25 nm.

8. The ferroelectric vertical transistor based on oxide semiconductor according to claim 1, characterized in that, The source contact electrode (700) is one of aluminum, silver, gold and indium tin oxide, and its thickness is 40nm to 80nm; the top drain electrode (800) is one of aluminum, silver, gold and indium tin oxide, and its thickness is 40nm to 80nm.

9. A method for fabricating a ferroelectric vertical transistor based on oxide semiconductor as described in any one of claims 1-8, characterized in that, Includes the following steps: (1) A tungsten electrode is prepared on a substrate (100) with an insulating layer by magnetron sputtering or electron beam evaporation as a gate metal electrode (200); (2) On the gate metal electrode (200), the gate ferroelectric layer (300) and the gate insulating dielectric layer (400) are prepared sequentially from bottom to top by atomic layer deposition. Then, the gate ferroelectric layer (300) and the gate insulating dielectric layer (400) are rapidly annealed in a rapid annealing furnace at a temperature of 350℃~450℃ and an annealing time of 40s~60s. (3) On the gate insulating dielectric layer (400), an ultra-thin island aluminum prepared by magnetron sputtering or an ultra-thin island silver prepared by thermal evaporation is annealed to form an island source electrode (500). (4) A window is opened on the island source electrode (500) by photolithography or masking, and an oxide semiconductor (600) is prepared by magnetron sputtering; (5) Windows are opened on the island source (500) and oxide semiconductor (600) respectively by photolithography or masking. Then, the top drain (800) is prepared on the oxide semiconductor (600) and the source contact electrode (700) is prepared on the island source (500) by thermal evaporation, magnetron sputtering or printing to obtain a ferroelectric vertical transistor. (6) The ferroelectric vertical transistor is annealed as a whole to complete the fabrication of the ferroelectric vertical transistor.

10. The method for fabricating a ferroelectric vertical transistor based on oxide semiconductor according to claim 1, characterized in that: In step (3), the magnetron sputtering process parameters are set as follows: power 60W-80W, pressure 1.3×10-4Torr; the metal thickness of the island source electrode (500) is 5nm-15nm, and the annealing temperature is between 150℃ and 250℃.

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