Variable doping high-reliability planar gate silicon carbide VDMOS and preparation method thereof

Abstract

The invention provides a varied doping high-reliability planar gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the upper side surface of the silicon carbide substrate to form a drift layer; a barrier layer is formed, etching and ion implantation are carried out, and a first N-type region, a second N-type region and a P-type well region are formed; a barrier layer is formed again, etching and ion implantation are carried out, and an N-type source region is formed; a barrier layer is formed again, etching and ion implantation are carried out, and a third N-type region is formed; a barrier layer is formed again, and a gate dielectric layer is formed through etching and deposition; and re-forming a barrier layer, etching, depositing metal, forming a gate metal layer and a source metal layer, and removing the barrier layer to complete preparation. The transverse layout of the on-resistance of the device is accurately controlled, so that the current is uniformly distributed in the device, heat concentration is avoided, and the reliability of the device is improved.

Description

Technical Field

[0001] The invention relates to a variable doping high-reliability planar gate silicon carbide VDMOS and a preparation method thereof. Background Art

[0002] Silicon carbide VDMOS is a typical representative of silicon carbide power devices and is widely used in electric vehicles, aerospace, power conversion and other fields.

[0003] In applications such as motor control systems or load switches, when the motor or load is short-circuited, the VDMOS will be directly connected to the bus voltage. Since the VDMOS is in the on state at this time, it will generate an instantaneous short-circuit current of hundreds of amperes, resulting in a very large internal transient temperature rise. Therefore, it is urgent to provide a silicon carbide power VDMOS to ensure that its on-resistance is low enough and the heat is not concentrated. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a variable doping high-reliability planar gate silicon carbide VDMOS and a preparation method thereof, accurately controlling the lateral layout of the on-resistance of the device so that the current is evenly distributed inside the device, avoiding heat concentration and improving device reliability.

[0005] In a first aspect, the present invention provides a method for preparing a variable doping high-reliability planar gate silicon carbide VDMOS, comprising the following steps:

[0006] Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially growing on the side of the silicon carbide substrate to form a drift layer;

[0007] Step 2: forming a barrier layer above the drift layer, etching the barrier layer to form a through hole, and performing ion implantation on the drift layer to form a first N-type region;

[0008] Step 3, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation on the drift layer to form a second N-type region;

[0009] Step 4: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation on the drift layer to form a P-type well region;

[0010] Step 5, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation on the P-type well region to form an N-type source region;

[0011] Step 6: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation on the drift layer to form a third N-type region;

[0012] Step 7, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing to form a gate dielectric layer;

[0013] Step 8, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing metal, and forming a gate metal layer;

[0014] Step 9: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, deposit metal to form a source metal layer, remove the barrier layer, and complete the preparation.

[0015] In a second aspect, the present invention provides a variable doping high-reliability planar gate silicon carbide VDMOS, wherein the silicon carbide VDMOS is prepared by the method for preparing a variable doping high-reliability planar gate silicon carbide VDMOS according to the first aspect.

[0016] The advantages of the present invention are:

[0017] 1. The present invention constructs a Schottky diode inside the device, which can effectively reduce the forward conduction voltage drop of the device, increase the reverse recovery speed of the device, and reduce the conduction loss and switching loss of the device;

[0018] Second, the present invention constructs a first N-type region, a second N-type region and a third N-type region with variable doping on the left and right sides and below the P-type well region of the device, and the doping concentration relationship of the three regions is the first N-type region> the second N-type region> the third N-type region, so as to achieve a relatively uniform lateral distribution of the body resistance from the bottom of the device gate to the drain, thereby achieving uniform current distribution inside the device, avoiding current concentration and the resulting concentrated heat distribution inside the device, and improving the reliability of the device;

[0019] 3. The present invention can effectively shield the parasitic capacitance from the gate to the drain by providing the third N-type region and the second N-type region, that is, it can reduce the Maitreya capacitance of the device and improve the switching speed of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The present invention will be further described below in conjunction with embodiments with reference to the accompanying drawings.

[0021] Figure 1 The schematic diagram of the variable doping high-reliability planar gate silicon carbide VDMOS of the present invention is shown.

[0022] Figure 2 This is a cross-sectional view of the process of a variable doping high reliability planar gate silicon carbide VDMOS of the present invention Figure 1 .

[0023] Figure 3 This is a cross-sectional view of the process of a variable doping high reliability planar gate silicon carbide VDMOS of the present invention Figure 2 .

[0024] Figure 4 This is a cross-sectional view of the process of a variable doping high reliability planar gate silicon carbide VDMOS of the present invention Figure 3 .

[0025] Figure 5 This is a cross-sectional view of the process of a variable doping high reliability planar gate silicon carbide VDMOS of the present invention Figure 4 .

[0026] Figure 6 This is a cross-sectional view of the process of a variable doping high reliability planar gate silicon carbide VDMOS of the present invention Figure 5 .

[0027] Figure 7 This is a cross-sectional view of the process of a variable doping high reliability planar gate silicon carbide VDMOS of the present invention Figure 6 .

[0028] Figure 8 This is a cross-sectional view of the process of a variable doping high reliability planar gate silicon carbide VDMOS of the present invention Figure 7 .

[0029] Fig. 9 This is a cross-sectional view of the process of a variable doping high reliability planar gate silicon carbide VDMOS of the present invention Figure 8 .

[0030] Fig.10 This is a cross-sectional view of the process of a variable doping high reliability planar gate silicon carbide VDMOS of the present invention Figure 9 . DETAILED DESCRIPTION

[0031] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0033] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "in contact with ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0034] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientations described in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0035] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0036] like Figures 1 to 10 As shown, the embodiment of the present application provides a method for preparing a variable doping high-reliability planar gate silicon carbide VDMOS, comprising the following steps:

[0037] Step 1: depositing metal on the lower side of the silicon carbide substrate 101 to form a drain metal layer 110; epitaxially growing on the side of the silicon carbide substrate 101 to form a drift layer 102;

[0038] Step 2: forming a barrier layer 111 on the drift layer 102, etching the barrier layer to form a through hole, and performing ion implantation on the drift layer 102 to form a first N-type region 103, wherein the ion implantation energy is 10-270kev;

[0039] Step 3, removing the original barrier layer 111, re-forming the barrier layer 111, etching the barrier layer 111 to form a through hole, and performing ion implantation on the drift layer 102 to form a second N-type region 104, the ion implantation energy is 170-270kev;

[0040] Step 4: remove the original barrier layer 111, re-form the barrier layer 111, etch the barrier layer 111 to form a through hole, perform ion implantation on the drift layer 102 to form a P-type well region 106, and the ion implantation energy is 10-170kev;

[0041] Step 5, remove the original barrier layer 111, re-form the barrier layer 111, etch the barrier layer 111 to form a through hole, perform ion implantation on the P-type well region 106 to form an N-type source region 1061, and the ion implantation energy is 10-70kev;

[0042] Step 6: remove the original barrier layer 111, re-form the barrier layer 111, etch the barrier layer 111 to form a through hole, perform ion implantation on the drift layer 102 to form a third N-type region 105, and the ion implantation energy is 10-270kev;

[0043] Step 7, removing the original barrier layer 111, re-forming the barrier layer 111, etching the barrier layer 111 to form a through hole, and depositing to form a gate dielectric layer 107;

[0044] Step 8, removing the original barrier layer 111, re-forming the barrier layer 111, etching the barrier layer 111 to form a through hole, depositing metal, and forming a gate metal layer 109;

[0045] Step 9, remove the original barrier layer 111, re-form the barrier layer 111, etch the barrier layer 111 to form a through hole, deposit metal to form a source metal layer 108, remove the barrier layer 111, and complete the preparation.

[0046] like Figure 1 As shown, the above manufacturing method obtains gate silicon carbide VDMOS, including:

[0047] Silicon carbide substrate 101,

[0048] A drift layer 102, wherein the lower side of the drift layer 102 is connected to the upper side of the silicon carbide substrate 101;

[0049] A first N-type region 103 , wherein a lower side of the first N-type region 103 is connected to an upper side of the drift layer 102 ;

[0050] A second N-type region 104 , wherein a lower side of the second N-type region 104 is connected to an upper side of the drift layer 102 ;

[0051] A third N-type region 105, wherein the lower side of the third N-type region 105 is connected to the upper side of the drift layer 102; the outer side of the second N-type region 104 is connected to the inner side of the first N-type region 103, and the inner side of the second N-type region 104 is connected to the outer side of the third N-type region 105;

[0052] A P-type well region 106, wherein the lower side of the P-type well region 106 is connected to the second N-type region 104, the outer side of the P-type well region 106 is connected to the inner side of the first N-type region 103, and the inner side of the P-type well region 106 is connected to the outer side of the third N-type region 105; an N-type source region 1061 is provided on the P-type well region 106;

[0053] A gate dielectric layer 107, wherein the lower side of the gate dielectric layer 107 is respectively connected to the upper side of the P-type well region 106, the upper side of the N-type source region 1061 and the upper side of the third N-type region 105;

[0054] A source metal layer 108 , wherein the source metal layer 108 is respectively connected to the first N-type region 103 , the P-type well region 106 , and the N-type source region 1061 ;

[0055] A gate metal layer 109 , wherein the gate metal layer 109 is connected to the gate dielectric layer 107 ;

[0056] and a drain metal layer 110 , wherein the drain metal layer 110 is connected to the lower side of the silicon carbide substrate 101 .

[0057] Preferably, in this embodiment, the doping concentration of the first N-type region 103 is greater than the doping concentration of the second N-type region 104, and the doping concentration of the second N-type region 104 is greater than the doping concentration of the third N-type region 105; the doping concentration of the drift layer 102 is less than the doping concentration of the third N-type region 105; the thickness of the first N-type region 103 is equal to the thickness of the third N-type region 105; and the thickness of the first N-type region 103 is greater than the thickness of the second N-type region 104.

[0058] The silicon carbide substrate 101 is of N-type with a doping concentration of 2-8e18cm -3 ; The drift layer 102 is N-type, and its doping concentration is 2-8e15cm -3 ; The doping concentration of the first N-type region 103 is 5-8e17cm -3, the doping concentration of the second N-type region 104 is 1-5e17cm -3 , the doping concentration of the third N-type region 105 is 5-8e16cm -3 , the doping concentration of the P-type well region 106 is 5e17 cm -3 The gate dielectric layer 107 is silicon dioxide, and the doping concentration of the N-type source region 1061 is 2e18cm -3 ;

[0059] The doping concentration of the N-type silicon carbide substrate 101 is to ensure that a low-resistance ohmic contact is formed with the drain metal layer 110, thereby reducing the overall on-resistance of the device. The doping concentration of the N-type drift layer 102 is a compromise between the reverse withstand voltage and the on-resistance of the device. The doping concentrations of the first N-type region 103, the second N-type region 104, and the third N-type region 105 and their relationship are to achieve a relatively uniform distribution of the body resistance of the device from the drain to the region directly below the device gate in the lateral direction inside the device, thereby redistributing the electrons from the N-type source region 1061 through the second N-type region 104 below the P-type well region 106, so that the current is more uniformly distributed in the lateral direction inside the device, thereby reducing the overall on-resistance of the device, avoiding current concentration, and improving the thermal reliability of the device. The doping concentration of the first N-type region 103 is also to form a Schottky contact with the source metal layer 108 instead of an ohmic contact, so as to construct a parasitic Schottky diode of the device. The doping concentration of the N-type source region 1061 is to form an ohmic contact with the source metal layer 108 and reduce the contact resistance.

[0060] The thickness of the N-type silicon carbide substrate 101 of the device of the present invention is 1 μm, the thickness of the N-type drift layer 102 is 20-40 μm, which can be adjusted within the above range according to different requirements for the withstand voltage characteristics of the device, the thickness of the second N-type region 104 is 300 nm, the thickness of the first N-type region 103 is 800 nm, the thickness of the third N-type region 105 is 800 nm, the thickness of the N-type source region 1061 is 200 nm, the thickness of the P-type well region 106 below the N-type source region 1061 is 300 nm, and the thickness of the P-type well region 106 in the contact area with the source metal layer 108 is 500 nm; the width of the contact area between the first N-type region 103 and the source metal layer 108 is 300-600 nm, which can be individually designed according to the freewheeling capability of the body diode, and the thickness of the insulating medium is 50 nm;

[0061] The source metal layer 108 and the first N-type region 103 form a Schottky diode, which can effectively reduce the forward conduction voltage drop of the device, increase the reverse recovery speed of the device, and reduce the conduction loss and switching loss of the device;

[0062] The first N-type region 103, the second N-type region 104 and the third N-type region 105 with variable doping are constructed on the left and right sides and below the P-type well region 106 of the device, so as to achieve a relatively uniform lateral distribution of the body resistance from the bottom of the device gate to the drain, thereby achieving uniform current distribution inside the device, avoiding current concentration and the resulting concentrated heat distribution inside the device, and improving the reliability of the device;

[0063] The N-type doping of the second N-type region 104 and the third N-type region 105 can effectively shield the parasitic capacitance from the gate to the drain, that is, can reduce the Maitreya capacitance of the device and improve the switching speed of the device.

[0064] Although the specific implementation modes of the present invention are described above, those skilled in the art should understand that the specific implementation modes described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A method for preparing a variable doping high-reliability planar gate silicon carbide VDMOS, characterized in that: The steps include: Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially growing on the side of the silicon carbide substrate to form a drift layer; Step 2: forming a barrier layer above the drift layer, etching the barrier layer to form a through hole, and performing ion implantation on the drift layer to form a first N-type region; Step 3, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation on the drift layer to form a second N-type region; Step 4: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation on the drift layer to form a P-type well region; Step 5, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation on the P-type well region to form an N-type source region; Step 6: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation on the drift layer to form a third N-type region; Step 7, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing to form a gate dielectric layer; Step 8, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing metal, and forming a gate metal layer; Step 9: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, deposit metal to form a source metal layer, remove the barrier layer, and complete the preparation.

2. The method for preparing a variable doping high-reliability planar gate silicon carbide VDMOS according to claim 1, characterized in that: The doping concentration of the first N-type region is greater than the doping concentration of the second N-type region, and the doping concentration of the second N-type region is greater than the doping concentration of the third N-type region.

3. The method for preparing a variable doping high reliability planar gate silicon carbide VDMOS according to claim 1, characterized in that: The doping concentration of the drift layer is lower than the doping concentration of the third N-type region.

4. The method for preparing a variable doping high reliability planar gate silicon carbide VDMOS according to claim 1, characterized in that: The thickness of the first N-type region is equal to the thickness of the third N-type region; the thickness of the first N-type region is greater than the thickness of the second N-type region.

5. A variable doping high reliability planar gate silicon carbide VDMOS, characterized in that: The silicon carbide VDMOS is prepared by any one of the preparation methods of claim 1 to claim 4.

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