Semiconductor device and method for manufacturing semiconductor device

Abstract

The application discloses a semiconductor device and a manufacturing method thereof. The semiconductor device comprises: a substrate semiconductor substrate having a first main surface and a second main surface opposite to the first main surface; an insulated gate bipolar transistor region; a fast recovery diode region; an insulating layer provided with a first contact hole and a second contact hole respectively located in the fast recovery diode region and the insulated gate bipolar transistor region; a first semiconductor region located in the fast recovery diode region; a first titanium film provided in the first contact hole; a second semiconductor region located in the insulated gate bipolar transistor region; a second titanium film provided in the second contact hole; the depth of the first semiconductor region from the first main surface to the semiconductor substrate in a first direction is A, the depth of the second semiconductor region from the first main surface to the semiconductor substrate in the first direction is B, and A and B satisfy the relationship: A <= 0.45B. The technical scheme can improve the reverse recovery performance of the semiconductor device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically to a semiconductor device and a method for manufacturing the semiconductor device. Background Technology

[0002] For trench gate reverse-conducting insulated gate bipolar transistors (RC-IGBTs), in order to avoid poor electrical contact in the contact hole area, a titanium metal layer is usually formed between the tungsten layer and the semiconductor part in the contact hole area. However, when the contact with the semiconductor part (P-type base region) is formed through the titanium layer, there is a problem that the contact with the P-type base region deteriorates, which leads to the deterioration of the forward conduction characteristics of the device. To solve this problem, a P+ layer is usually formed in the contact area.

[0003] In related technologies, for the Insulated Gate Bipolar Transistor (IGBT) region of a trench gate reverse-conductive IGBT, the P+ layer can effectively extract holes and prevent latch-up. However, for the Fast Recovery Diode (FRD) region, the formation of the P+ layer leads to enhanced hole injection efficiency, resulting in increased peak current during reverse recovery and deteriorating reverse recovery performance.

[0004] Therefore, improvements are needed to at least partially address the aforementioned problems. Summary of the Invention

[0005] The present invention aims to at least partially solve the above-mentioned problems. Therefore, one object of the present invention is to provide a semiconductor device that can improve reverse recovery performance without affecting forward conduction. Another object of the present invention is to provide a method for manufacturing said semiconductor device.

[0006] The semiconductor device has a semiconductor substrate, the semiconductor substrate having a drift layer of a first conductivity type between a first main surface and a second main surface, wherein the first main surface and the second main surface are disposed opposite to each other in a first direction, and the semiconductor device includes:

[0007] An insulated gate bipolar transistor region has a trench gate extending from the first main surface of the semiconductor substrate through an emitter layer of a first conductivity type and a base layer of a second conductivity type to the drift layer, and a collector layer of the second conductivity type disposed on the second main surface side compared to the drift layer, wherein there are multiple trench gates, the multiple trench gates are spaced apart in a second direction, the length of the trench gates extends in a third direction, and the first direction, the second direction and the third direction are perpendicular to each other;

[0008] The fast recovery diode region has an anode layer of a second conductivity type disposed on the first main surface side compared to the drift layer, and a cathode layer of the first conductivity type disposed on the second main surface side compared to the drift layer;

[0009] An insulating layer is disposed on the first main surface. The insulating layer is provided with a first contact hole and a second contact hole. The second contact hole is located in the region of the insulated gate bipolar transistor, and the first contact hole is located in the region of the fast recovery diode.

[0010] The fast recovery diode region further includes a first semiconductor region of a second conductivity type and a first titanium film;

[0011] A first semiconductor region of a second conductivity type is selectively disposed on the first main surface side of the anode layer. Compared with the anode layer, the impurity concentration of the second conductivity type is higher. The side of the first semiconductor region facing the first main surface constitutes at least a portion of the first main surface. The first contact hole penetrates the insulating layer and exposes the first semiconductor region.

[0012] A first titanium film is disposed in the first contact hole and in contact with the first semiconductor region. The first semiconductor region is electrically connected to the emitter metal through the first contact hole.

[0013] The insulated gate bipolar transistor region further includes a second semiconductor region of a second conductivity type and a second titanium film;

[0014] The second semiconductor region is selectively disposed on the first main surface side of the base layer, and has a higher impurity concentration of the second conductivity type compared to the base layer. The emitter layer is selectively disposed on the first main surface side of the base layer. The side of the second semiconductor region and the emitter layer facing the first main surface both constitute at least a portion of the first main surface. The second contact hole penetrates the insulating layer and exposes the second semiconductor region and the emitter layer.

[0015] The second titanium film is disposed in the second contact hole and contacts the second semiconductor region. The second semiconductor region and the emitter layer are both electrically connected to the emitter metal through the second contact hole.

[0016] Wherein, the depth of the first semiconductor region from the first main surface to the semiconductor substrate in the first direction is set as A, and the depth of the second semiconductor region from the first main surface to the semiconductor substrate in the first direction is set as B, and A and B satisfy the relationship: A≤0.45B.

[0017] The above technical solution has the following advantages and beneficial effects: For the region of the insulated gate bipolar transistor, the relatively deep second semiconductor region can effectively reduce contact resistance and effectively extract holes, preventing latch-up effects in the semiconductor device; For the region of the fast recovery diode, the relatively shallow first semiconductor region can reduce contact resistance on the one hand, and effectively reduce the hole injection efficiency in the region of the fast recovery diode on the other hand, thereby reducing the peak current of reverse recovery and improving the reverse recovery performance of the semiconductor device. By setting the depth of the first semiconductor region and the second semiconductor region in the first direction within the above-mentioned range, a good balance can be achieved in terms of reducing contact resistance and reducing hole injection efficiency.

[0018] In some embodiments, the first titanium film on the side adjacent to the first semiconductor region in the first contact hole in the first direction is in contact with the first semiconductor region to form a first titanium silicide layer. The first titanium silicide layer extends from the first main surface into the semiconductor substrate in the first direction. The depth of the first titanium silicide layer from the first main surface into the semiconductor substrate in the first direction is set to C. C, A, and B satisfy the relationship: A≤C≤0.5B.

[0019] The second titanium film on the side adjacent to the second semiconductor region in the first direction within the second contact hole contacts the second semiconductor region to form a second titanium silicide layer. The second titanium silicide layer extends from the first main surface into the semiconductor substrate in the first direction. The depth of the second titanium silicide layer from the first main surface into the semiconductor substrate in the first direction is set to D, and D and B satisfy the relationship: D≤B.

[0020] The above technical solution has the following advantages and beneficial effects: When C≥A, since the first semiconductor region is consumed by the generated first titanium silicide layer, on the one hand, the contact resistance can be reduced, and on the other hand, the hole injection in the fast recovery diode region can be reduced, thereby reducing the reverse recovery peak current and improving the reverse recovery performance; when C≤0.5B, the difference between the first titanium silicide layer and the first semiconductor region is not too large, avoiding the increase in the contact resistance of the first titanium silicide layer caused by the first semiconductor region being far insufficient to consume it, thus reducing the contact resistance of the first titanium film, suppressing the increase in voltage drop during forward conduction of the diode, and improving the deterioration of the forward conduction characteristics of the fast recovery diode. By setting the depth of the first titanium silicide layer in the first direction within the above range, a good balance can be achieved in terms of reducing contact resistance and reducing hole injection efficiency.

[0021] In some embodiments, the region where the first semiconductor region (7) is located is entirely located in the region where the first titanium silicide layer (8012) is located.

[0022] In some embodiments, the first titanium film on the side adjacent to the first semiconductor region in the first contact hole in the first direction is in contact with the first semiconductor region to form a first titanium silicide layer. The first titanium silicide layer extends from the first main surface into the semiconductor substrate in the first direction. The depth of the first titanium silicide layer from the first main surface into the semiconductor substrate in the first direction is set to C, and C and A satisfy the relationship: C < A.

[0023] The second titanium film on the side adjacent to the second semiconductor region in the first direction within the second contact hole contacts the second semiconductor region to form a second titanium silicide layer. The second titanium silicide layer extends from the first main surface into the semiconductor substrate in the first direction. The depth of the second titanium silicide layer from the first main surface into the semiconductor substrate in the first direction is set to D, and D and B satisfy the relationship: D≤B.

[0024] The above technical solution has the following advantages and beneficial effects: When C < A, the first semiconductor region still has some remaining after being consumed by the first titanium silicide layer, thereby reducing the contact resistance of the first titanium film, reducing the forward voltage drop, and reducing conduction losses. Simultaneously, the first titanium silicide layer consumes part of the first semiconductor region, reducing hole injection in the fast recovery diode region, reducing the reverse recovery peak current, and improving reverse recovery performance. By setting the depth of the first titanium silicide layer in the first direction within the above-mentioned range, a good balance can be achieved in terms of reducing contact resistance and reducing hole injection efficiency.

[0025] In some embodiments, the region where the first titanium silicide layer (8012) is located is entirely located within the region where the first semiconductor region (7) is located.

[0026] In some embodiments, C and D satisfy the relationship: C = D.

[0027] The above technical solution has the following advantages and beneficial effects: by setting the depth C of the first titanium silicide layer in the first direction and the depth D of the second titanium silicide layer in the first direction to be equal, they can be formed in the same process, thereby effectively simplifying the manufacturing process, reducing production costs, and shortening the production cycle.

[0028] In some embodiments, the doping impurity implantation energy of the first semiconductor region is less than that of the second semiconductor region, and the doping impurity implantation energy of the first semiconductor region is Q, where Q satisfies the relationship: 10 keV ≤ Q ≤ 40 keV; and / or

[0029] The impurity doping concentration of the first semiconductor region is less than or equal to the impurity doping concentration of the second semiconductor region; and / or,

[0030] The doping impurity implantation dose of the first semiconductor region is D, and D satisfies the relationship: 2E14≤D≤8E14.

[0031] In some embodiments, the insulated gate bipolar transistor region includes a first region and a second region, and there are multiple first regions and multiple second regions. There are multiple emitter layers and multiple second semiconductor regions. The multiple emitter layers are disposed one-to-one in the base layers of the multiple first regions, and the multiple second semiconductor regions are disposed one-to-one in the base layers of the multiple second regions. The multiple first regions and multiple second regions are arranged alternately in a third direction.

[0032] In some embodiments, the insulated gate bipolar transistor region includes a first region and a second region, and there are multiple first regions and multiple second regions. There are multiple emitter layers and multiple second semiconductor regions. The multiple emitter layers are disposed one-to-one in the base layers of the multiple first regions, and the multiple second semiconductor regions are disposed one-to-one in the base layers of the multiple second regions. The multiple first regions and the multiple second regions are arranged alternately in a second direction.

[0033] The manufacturing method is applicable to the semiconductor device described above, and the manufacturing method includes the following steps:

[0034] A semiconductor substrate is provided, wherein the semiconductor substrate has a first main surface and a second main surface opposite to the first main surface, and the first main surface and the second main surface are spaced apart in a first direction;

[0035] A plurality of trench gates are formed from the first main surface of the semiconductor substrate and extend toward the second main surface, wherein the plurality of trench gates are spaced apart in a second direction, wherein the first direction and the second direction are perpendicular to each other;

[0036] A base layer, an anode layer, and an emitter layer are formed on the side of the semiconductor substrate facing the first main surface, wherein the base layer is located in the region of the insulated gate bipolar transistor, and the anode layer is located in the region of the fast recovery diode;

[0037] An insulating layer is deposited on the first main surface, and a first contact hole and a second contact hole are etched on the insulating layer, wherein the first contact hole and the second contact hole both penetrate the insulating layer, the first contact hole is located in the region of the fast recovery diode, and the second contact hole is located in the region of the insulated gate bipolar transistor.

[0038] First, dopant of a second conductivity type is implanted into the anode layer exposed by the first contact hole to form a first semiconductor region of the second conductivity type. Then, dopant of the second conductivity type is implanted into the base layer exposed by the second contact hole to form a second semiconductor region of the second conductivity type. The depth of the second semiconductor region in the first direction is greater than the depth of the first semiconductor region in the first direction.

[0039] Simultaneously, dopant of a second conductivity type is implanted into the anode layer exposed by the first contact hole and the base layer exposed by the second contact hole to form a first semiconductor region of the second conductivity type in the anode layer and a sub-semiconductor region of the second conductivity type with the same depth as the first semiconductor region in the base layer. Then, dopant of the second conductivity type is implanted into the portion of the base layer corresponding to the sub-semiconductor region to form a second semiconductor region, wherein the depth of the second semiconductor region is greater than the depth of the first semiconductor region.

[0040] A first titanium film and a second titanium film are formed, respectively located in the first contact hole and the second contact hole, wherein the first titanium film is in contact with the first semiconductor region and the second titanium film is in contact with the second semiconductor region.

[0041] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0042] The following drawings, which are incorporated herein by reference and are used to understand this application, illustrate embodiments of the invention and their descriptions, thereby explaining the apparatus and principles of the invention. In the drawings,

[0043] Figure 1This is a schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0044] Figure 2 for Figure 1 A schematic diagram of region A in the middle;

[0045] Figure 3 for Figure 2 Schematic diagram of the cross section in the middle BB direction;

[0046] Figure 4 for Figure 2 A schematic diagram of the cross-section in the CC direction;

[0047] Figure 5 for Figure 4 A schematic diagram of region D in the middle;

[0048] Figure 6 This is a cross-sectional schematic diagram in the CC direction according to other embodiments of the present invention;

[0049] Figure 7 This is a schematic flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0050] Figures 8-17 This is a cross-sectional schematic diagram of each stage of a semiconductor device manufacturing method according to an embodiment of the present invention.

[0051] Explanation of reference numerals in the attached figures:

[0052] 100. Semiconductor device; 1001. Insulated-gate bipolar transistor region; 10011. First region; 10012. Second region; 1002. Transition region; 1003. Fast recovery diode region;

[0053] 1. Semiconductor substrate; 101. First main surface; 102. Second main surface;

[0054] 2. Drift layer; 3. Carrier storage layer; 4. Base layer; 5. Gate trench; 6. Trench gate; 7. First semiconductor region;

[0055] 8. Insulating layer; 801. First contact hole; 8011. First titanium film; 8012. First titanium silicide layer; 802. Second contact hole; 8021. Second titanium film; 8022. Second titanium silicide layer;

[0056] 9. Second semiconductor region; 10. Emitter layer; 11. Field cutoff layer; 12. Collector layer; 13. Collector metal layer; 14. Cathode layer; 15. Anode layer; 16. Tungsten layer; 17. Emitter metal layer; 18. Virtual gate trench; 19. Virtual gate. Detailed Implementation

[0057] The following description provides numerous specific details to offer a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described to avoid confusion with this application.

[0058] It should be understood that this application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of this application to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0059] It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or part discussed below may be referred to as the second element, component, area, layer, or part.

[0060] Spatial relation terms such as "below," "under," "below," "under," "above," and "above" are used here for convenience to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of devices in use and operation.

[0061] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0062] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures) of this application. Thus, variations in the shown shape are contemplated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this application should not be limited to the specific shapes shown herein, but include shape deviations due to, for example, manufacturing processes. Consequently, the figures are substantially schematic, and their shapes are not intended to show the actual shape of the device and are not intended to limit the scope of this application.

[0063] The following is for reference. Figures 1-5 A semiconductor device 100 according to an embodiment of the present invention will be described by way of example. This semiconductor device 100 is, for example, a reverse-conducting insulated-gate bipolar transistor. In the following description, N and P represent the conductivity type of the semiconductor. In this invention, the first conductivity type is described as N-type and the second conductivity type as P-type. Similarly, the first conductivity type can also be P-type and the second conductivity type as N-type.

[0064] Semiconductor device 100 includes a semiconductor substrate 1. The semiconductor substrate 1 has a first main surface 101 and a second main surface 102, which are disposed opposite to each other in a first direction. The semiconductor substrate 1 has a drift layer 2 of a first conductivity type between the first main surface 101 and the second main surface 102. The drift layer 2 typically has a low doping concentration, therefore it has a high resistance and can withstand high voltages.

[0065] Furthermore, the semiconductor device 100 includes an insulated gate bipolar transistor region 1001, a fast recovery diode region 1003, and an insulating layer 8.

[0066] The insulated gate bipolar transistor (IGBT) region 1001 has a trench gate 6 extending from the first main surface 101 of the semiconductor substrate 1 through a first conductivity type emitter layer 10 and a second conductivity type base layer 4 to a drift layer 2, and a second conductivity type collector layer 12 disposed on the second main surface 102 side compared to the drift layer 2. The second conductivity type base layer 4 is located on the side of the drift layer 2 away from the second main surface 102, and this side of the base layer 4 away from the second main surface 102 can constitute a portion of the first main surface 101. The first conductivity type emitter layer 10 is located on the side of the base layer 4 away from the second main surface 102, and this side of the emitter layer 10 can constitute a portion of the first main surface 101. The doping concentration of the first conductivity type emitter layer 10 can be higher than the doping concentration of the drift layer 2. For example, a semiconductor device 100 has a gate trench 5 extending from a first main surface 101 to a second main surface 102, penetrating the emitter layer 10 and the base layer 4 to reach the drift layer 2. A trench gate 6 is formed by providing a gate trench electrode within the gate trench 5, separated by a gate trench insulating film. The gate trench electrode faces the drift layer 2 separated by the gate trench insulating film. The gate trench insulating film of the trench gate 6 is in contact with the base layer 4 and the emitter layer 10. If a gate driving voltage is applied to the gate trench electrode, a channel is formed in the base layer 4 in contact with the gate trench insulating film of the trench gate 6. There are multiple trench gates 6, which are spaced apart in a second direction, and the length of the trench gate 6 extends in a third direction. For example, the gate trench insulating film and the gate trench electrode can be made of silicon dioxide and polysilicon, respectively. The first direction, the second direction, and the third direction are perpendicular to each other.

[0067] The fast recovery diode region 1003 has an anode layer 15 of a second conductivity type disposed on the side of the first main surface 101 compared to the drift layer 2, and a cathode layer 14 of a first conductivity type disposed on the side of the second main surface 102 compared to the drift layer 2. The anode layer 15, on the side away from the second main surface 102, constitutes a portion of the first main surface 101, and the doping concentration of the anode layer 15 can be the same as or approximately the same as that of the base layer 4. The cathode layer 14, on the side away from the first main surface 101, constitutes a portion of the second main surface 102, and the doping concentration of the cathode layer 14 is greater than that of the drift region.

[0068] For example, the fast recovery diode region 1003 also has a dummy gate 19 extending from the first main surface 101 of the semiconductor substrate 1 through an anode layer 15 of a second conductivity type to the drift layer 2. For example, the semiconductor device 100 forms a dummy gate trench 18 extending from the first main surface 101 to the second main surface 102, extending through the anode layer 15 to the drift layer 2, and a dummy gate 19 is formed by providing a dummy gate trench electrode within the dummy gate trench 18 through a dummy gate trench insulating film. The dummy gate trench electrode faces the drift layer 2 through the dummy gate trench insulating film. The dummy gate trench insulating film of the dummy trench gate 6 is in contact with the anode layer 15. There are multiple dummy gates 19, and the multiple dummy gates 19 are spaced apart in the second direction. For example, the materials of the dummy gate trench insulating film and the dummy gate trench electrode can be silicon dioxide and polysilicon, respectively.

[0069] An insulating layer 8 is disposed on the first main surface 101. The insulating layer 8 has a first contact hole 801 and a second contact hole 802. The second contact hole 802 is located in the region 1001 of the insulated gate bipolar transistor, and the first contact hole 801 is located in the region 1003 of the fast recovery diode. Both the first contact hole 801 and the second contact hole 802 penetrate the insulating layer.

[0070] For further details, please see the appendix. Figure 4 , 5 The fast recovery diode region 1003 also includes a first semiconductor region 7 of a second conductivity type and a first titanium film 8011, and the insulated gate bipolar transistor region 1001 also includes a second semiconductor region 9 of a second conductivity type and a second titanium film 8021.

[0071] A first semiconductor region 7 of the second conductivity type is selectively disposed on the first main surface 101 side of the anode layer 15, and has a higher impurity concentration of the second conductivity type compared to the anode layer 15. That is, the doping concentration of the first semiconductor region 7 is higher than that of the anode layer 15. The side of the first semiconductor region 7 facing the first main surface 101 constitutes at least a portion of the first main surface 101. A first contact hole 801 penetrates the insulating layer 8 and exposes the side of the first semiconductor region 7 away from the second main surface 102.

[0072] A first titanium film 8011 is disposed within the first contact hole 801, contacting the first semiconductor region 7. The first semiconductor region 7 is electrically connected to the emitter metal 17 through the first contact hole 801. Correspondingly, the anode layer 15 is electrically connected to the emitter metal 17 through the first semiconductor region 7. Exemplarily, the first titanium film 8011 may be disposed on the inner wall of the first contact hole 801, contacting the inner wall of the first contact hole 801 and located between the emitter metal 17 and the inner wall of the first contact hole 801. Exemplarily, the material of the first titanium film 8011 may include titanium and / or titanium nitride.

[0073] A second semiconductor region 9 of the second conductivity type is selectively disposed on the first main surface 101 side of the base layer 4, and has a higher impurity concentration of the second conductivity type compared to the base layer 4. That is, the doping concentration of the second semiconductor region 9 is higher than that of the base layer 4. An emitter layer 10 is selectively disposed on the first main surface 101 side of the base layer 4, and the sides of the second semiconductor region 9 and the emitter layer 10 facing the first main surface 101 each constitute at least a portion of the first main surface 101. A second contact hole 802 penetrates the insulating layer 8 and exposes the second semiconductor region 9 and the emitter layer 10. It should be noted that the exposure of the second semiconductor region 9 and the emitter layer 10 can be at the same second contact hole 802 (which exposes both the second semiconductor region 9 and the emitter layer 10 adjacent to the second semiconductor region 9), or at different second contact holes 802 (that is, some second contact holes 802 expose only the second semiconductor region 9, and some second contact holes 802 expose only the emitter layer 10).

[0074] The second titanium film 8021 is disposed within the second contact hole 802, contacting the second semiconductor region 9. Both the second semiconductor region 9 and the emitter layer 10 are electrically connected to the emitter metal 17 through the second contact hole 802. Correspondingly, the base layer 4 is electrically connected to the emitter metal 17 through the second semiconductor region 9. Exemplarily, the second titanium film 8021 may be disposed on the inner wall and bottom of the second contact hole 802, with the second contact hole 802 in contact with its inner wall and located between the emitter metal 17 and the inner wall of the second contact hole 802. Exemplarily, the material of the second titanium film 8021 may include titanium and / or titanium nitride.

[0075] The semiconductor device 100 may further include a tungsten layer 16 and an emitter metal 17. The tungsten layer 16 is located in the first contact hole 801 and the second contact hole 802 and is in contact with the first titanium film 8011 or the second titanium film. The emitter metal 17 is located on the side of the insulating layer 8 away from the first main surface 101 and is in contact with the tungsten layer 16. For example, the emitter metal 17 may be made of aluminum, copper, or the like.

[0076] See appendix Figure 5 The first semiconductor region 7 is defined to extend from the first main surface 101 to the semiconductor substrate 1 in the first direction (i.e., Figure 5The depth of the second semiconductor region 9 in the first direction (vertical direction) is A, and the depth of the second semiconductor region 9 from the first main surface 101 into the semiconductor substrate 1 in the first direction is B. A and B satisfy the relationship: A ≤ 0.45B. For example, A can be 0.1B, 0.15B, 0.2B, 0.25B, 0.3B, 0.35B, 0.4B, 0.45B, or any two of the above values. It should be noted that the "depth in the first direction" mentioned in this application refers to the maximum depth of the corresponding region or layer in the first direction, that is, its deepest depth in the first direction.

[0077] For the insulated gate bipolar transistor region 1001, the relatively deep second semiconductor region 9 can effectively reduce contact resistance and effectively extract holes, preventing latch-up in the semiconductor device 100. For the fast recovery diode region 1003, the relatively shallow first semiconductor region 7 can reduce contact resistance and effectively reduce hole injection efficiency in the fast recovery diode region 1003, thereby reducing the peak reverse recovery current and improving the reverse recovery performance of the semiconductor device 100. By setting the depth of the first semiconductor region 7 and the second semiconductor region 9 in the first direction within the above range (A≤0.45B), a good balance can be achieved in terms of reducing contact resistance and reducing hole injection efficiency.

[0078] See appendix Figure 4 , 5 In this embodiment, both the first semiconductor region 7 and the anode region 15 are made of silicon. A first titanium film 8011, located in the first contact hole 801 on the side adjacent to the first semiconductor region 7 in a first direction, contacts the first semiconductor region 7 to form a first titanium silicide layer 8012. The first titanium silicide layer 8012 extends from the first main surface 101 into the semiconductor substrate 1 along a first direction (in...). Figure 5 Extending from the top to the bottom, the first titanium silicide layer 8012 is defined as having a depth C from the first main surface 101 to the semiconductor substrate 1 in the first direction. C, A, and B satisfy the relationship: A≤C≤0.5B. In this embodiment, A=C≤0.5B.

[0079] When C≥A, since the first semiconductor region 7 is consumed by the generated first titanium silicide layer 8012, it can reduce the contact resistance on the one hand, and reduce the hole injection efficiency of the fast recovery diode region 1003 on the other hand, thereby reducing the reverse recovery peak current and improving the reverse recovery performance. When C≤0.5B, the depth of the first titanium silicide layer 8012 is not too different from the depth of the first semiconductor region 7, avoiding the first semiconductor region 7 being far insufficient to consume the first titanium silicide layer 8012, which would lead to an increase in the contact resistance of the first titanium silicide layer 8012. This reduces the contact resistance of the first titanium film 8011, suppresses the increase in voltage drop during forward conduction of the fast recovery diode, and improves the deterioration of the forward conduction characteristics of the fast recovery diode. By setting the depth of the first titanium silicide layer 8012 in the first direction within the above range (A≤C≤0.5B), a good balance can be achieved in terms of reducing contact resistance and reducing hole injection efficiency.

[0080] Furthermore, when C≥A, there are two cases. One case is that the region where the first semiconductor region 7 is located is completely located in the region where the first titanium silicide layer 8012 is located, that is, the region where the first titanium silicide layer 8012 is formed completely overlaps with the region where the first semiconductor region 7 is located (e.g., Figure 5 (As shown), or, the region where the first semiconductor region 7 is located is completely within the region where the first titanium silicide layer 8012 is formed. In this case, the first semiconductor region 7 is completely confined within the first titanium silicide layer 8012, which can effectively reduce the hole injection efficiency of the fast recovery diode region 1003, reduce the reverse recovery peak current, and improve the reverse recovery performance. Another case is that the region where the first semiconductor region 7 is located and the region where the first titanium silicide layer 8012 is located partially overlap, and the region where the first semiconductor region 7 is located is not completely within the region where the first titanium silicide layer 8012 is located. In this case, the hole injection efficiency of the fast recovery diode region 1003 can also be reduced to a certain extent, the reverse recovery peak current can be reduced, and the reverse recovery performance can be improved. It should be noted that the regions where the first semiconductor region 7 is located and the regions where the first titanium silicide layer 8012 is located refer to the space occupied by the first semiconductor region 7 in the substrate 1 and the space occupied by the first titanium silicide layer 8012 in the substrate 1, respectively.

[0081] In this embodiment, the material of the second semiconductor region 9 is silicon. A second titanium film 8021, located in the second contact hole 802 on the side adjacent to the second semiconductor region 9 in the first direction, contacts the second semiconductor region 9 to form a second titanium silicide layer 8022. The second titanium silicide layer 8022 extends from the first main surface 101 into the semiconductor substrate 1 along the first direction. The depth of the second titanium silicide layer 8022 from the first main surface 101 into the semiconductor substrate 1 in the first direction is set to D, where D and B satisfy the relationship: D ≤ B. Preferably, D < B. By setting the relationship between D and B within the above range, holes can be effectively extracted from the second semiconductor region 9, preventing latch-up effects in the device.

[0082] In some embodiments, both the first semiconductor region 7 and the anode region 15 are made of silicon. A first titanium film 8011, located in the first contact hole 801 on the side adjacent to the first semiconductor region 7 in a first direction, contacts the first semiconductor region 7 to form a first titanium silicide layer 8012. The first titanium silicide layer 8012 extends from the first main surface 101 into the semiconductor substrate 1 along a first direction (in...). Figure 5 (Extending from top to bottom), the depth of the first titanium silicide layer 8012 from the first main surface 101 to the semiconductor substrate 1 in the first direction is set to C, and C and A satisfy the relationship: C < A.

[0083] When C < A, the first semiconductor region 7 still has some remaining after being consumed by the first titanium silicide layer 8012. This reduces the contact resistance of the first titanium film 8011, lowers the forward voltage drop, and reduces conduction losses. Simultaneously, the consumption of a portion of the first semiconductor region 7 by the first titanium silicide layer 8012 reduces hole injection in the fast recovery diode region 1003, lowers the reverse recovery peak current, and improves reverse recovery performance. By setting the depth of the first titanium silicide layer 8012 in the first direction within the aforementioned range (C < A), a good balance can be achieved between reducing contact resistance and reducing hole injection efficiency.

[0084] Furthermore, when C < A, there are two scenarios. One is that the region containing the first titanium silicide layer 8012 is completely located within the region containing the first semiconductor region 7; that is, the region containing the first titanium silicide layer 8012 is entirely within the region containing the first semiconductor region 7. The other scenario is that the region containing the first titanium silicide layer 8012 and the region containing the first semiconductor region 7 partially overlap, meaning the region containing the first titanium silicide layer 8012 is not completely located within the region containing the first semiconductor region 7. In both cases, the forward voltage drop can be reduced, conduction losses can be decreased, and hole injection in the fast recovery diode region 1003 can be reduced, thus lowering the reverse recovery peak current and improving reverse recovery performance. It should be noted that the regions containing the first titanium silicide layer 8012 and the first semiconductor region 7 refer to the spaces occupied by the first titanium silicide layer 8012 and the first semiconductor region 7 in the substrate 1, respectively.

[0085] In some embodiments, C (the depth of the first titanium silicide layer 8012 from the first main surface 101 to the semiconductor substrate 1 in the first direction) and D (the depth of the second titanium silicide layer 8022 from the first main surface 101 to the semiconductor substrate 1 in the first direction) satisfy the relationship: C = D. Specifically, during the fabrication of the semiconductor device 100, a first titanium film 8011 and a second titanium film 8021 of the same thickness are formed on the sidewalls and bottom of the first contact hole 801 (the side of the first contact hole 801 facing the second main surface 102) and the sidewalls and bottom of the second contact hole 802 (the side of the first contact hole 801 facing the second main surface 102), respectively, by means of CVD (Chemical Vapor Deposition) and other suitable deposition processes. The first titanium film 8011 and the second titanium film 8021 of the same thickness are in contact with the first semiconductor region 7 and the second semiconductor region 9, respectively, forming a first titanium silicide layer 8012 and a second titanium silicide layer 8022 of the same depth. That is, the first titanium silicide layer 8012 and the second titanium silicide layer 8022 can be formed in the same process, thereby effectively simplifying the manufacturing process, reducing production costs, and shortening the production cycle. In some embodiments, the depths of C and D can be different; for example, C can be greater than D.

[0086] In this embodiment, the doping impurity implantation energy of the first semiconductor region 7 is less than that of the second semiconductor region 9. The doping impurity implantation energy of the first semiconductor region 7 is set as Q, and Q satisfies the relationship: 10keV≤Q≤40keV.

[0087] By setting the doping impurity implantation energy Q of the first semiconductor region 7 within the aforementioned range and configuring it to be less than the doping impurity implantation energy of the second semiconductor region 9, A (the depth of the first semiconductor region 7 from the first main surface 101 to the semiconductor substrate 1 in the first direction) can be ≤0.45B (the depth of the second semiconductor region 9 from the first main surface 101 to the semiconductor substrate 1 in the first direction is B). This achieves the effect of reducing contact resistance on the one hand, and effectively reduces the hole injection efficiency of the fast recovery diode region 1003 on the other hand, reduces the peak current of reverse recovery, and improves the reverse recovery performance of the semiconductor device 100, thereby achieving a good balance between reducing contact resistance and reducing hole injection efficiency.

[0088] In this embodiment, the impurity doping concentration of the first semiconductor region 7 is less than or equal to the impurity doping concentration of the second semiconductor region 9. Since A (the depth of the first semiconductor region 7 from the first main surface 101 to the semiconductor substrate 1 in the first direction) ≤ 0.45B (the depth of the second semiconductor region 9 from the first main surface 101 to the semiconductor substrate 1 in the first direction is B), even if the impurity doping concentration of the first semiconductor region 7 is equal to the impurity doping concentration of the second semiconductor region 9, the hole injection efficiency of the fast recovery diode region 1003 can be effectively reduced. When the impurity doping concentration of the first semiconductor region 7 is less than the impurity doping concentration of the second semiconductor region 9, on the one hand, the contact resistance can be reduced, and on the other hand, the hole injection efficiency of the fast recovery diode region 1003 can be reduced more effectively, thereby reducing the peak current of reverse recovery and improving the reverse recovery performance of the semiconductor device 100, thus achieving a good balance between reducing contact resistance and reducing hole injection efficiency.

[0089] For example, the doping impurity implantation dose of the first semiconductor region 7 is D, and D satisfies the relationship: 2E14≤D≤8E14.

[0090] By setting the doping impurity implantation dose D of the first semiconductor region 7 within the above range, the contact degradation problem between the first titanium film 8011 and the semiconductor substrate 1 can be improved on the one hand, and the hole injection efficiency of the fast recovery diode region 1003 can be reduced on the other hand, thereby reducing the peak current of reverse recovery and improving the reverse recovery performance of the semiconductor device.

[0091] See appendix Figure 2-4In this embodiment, the insulated gate bipolar transistor (IGBT) region 1001 includes a first region 10011 and a second region 10012. There are multiple first regions 10011 and multiple second regions 10012. There are also multiple emitter layers 10 and multiple second semiconductor regions 9. Multiple emitter layers 10 are correspondingly disposed in the base layers 4 of the multiple first regions 10011, and multiple second semiconductor regions 9 are correspondingly disposed in the base layers 4 of the multiple second regions 10012. That is, only the emitter layer 10 is disposed on the side of the base layer 4 of the first region 10011 away from the second main surface 102, without the second semiconductor region 9 (e.g., ...). Figure 3 (As shown); the base layer 4 in the second region 10012, located away from the second main surface 102, is provided with only the second semiconductor region 9, and without the emitter layer 10 (as shown). Figure 4 (As shown). Accordingly, the second contact hole 802 located in the first region 10011 penetrates the insulating layer 8 and exposes the emitter layer 10, and the second contact hole 802 located in the second region 10012 penetrates the insulating layer 8 and exposes the second semiconductor region 9. The plurality of first regions 10011 and the plurality of second regions 10012 are arranged alternately in the third direction.

[0092] See appendix Figure 6 In another embodiment, the insulated gate bipolar transistor region 1001 includes a first region 10011 and a second region 10012, each with multiple first regions 10011 and multiple second regions 10012. There are also multiple emitter layers 10 and multiple second semiconductor regions 9. The multiple emitter layers 10 are correspondingly disposed in the base layers 4 of the multiple first regions 10011, and the multiple second semiconductor regions 9 are correspondingly disposed in the base layers 4 of the multiple second regions 10012. The multiple first regions 10011 and the multiple second regions 10012 are sequentially staggered in a second direction. That is, in the second direction (i.e.... Figure 6 In the left-right direction, emitter layers 10 are provided on both sides of the second semiconductor region 9, and the second semiconductor region 9 is in contact with the emitter layers 10 on both sides. The second contact hole 802 penetrates the insulating layer 8. The second contact hole 802 can expose only the second semiconductor region 9, or it can expose both the second semiconductor region 9 and a portion of the emitter layer 10 adjacent to the second semiconductor region 9.

[0093] In this embodiment, the semiconductor device 100 further includes a carrier storage layer 3 of a first conductivity type, the doping concentration of which is greater than that of the drift layer 2. In a first direction, the carrier storage layer 3 is located between the drift layer 2 and the base layer 4, and between the drift layer 2 and the anode layer 15. Both the gate trench 6 and the dummy gate trench 18 extend through the carrier storage layer 3 into the drift layer 2. The arrangement of the carrier storage layer 3 can effectively improve the switching speed of the semiconductor device, stabilize the operating state of the semiconductor device, prevent excessively high voltage spikes or current surges due to rapid changes in carriers, reduce switching losses, and allow the semiconductor device to switch between the on and off states more quickly and stably. The carrier storage layer 3 can also increase the withstand voltage of the semiconductor device. It can help the drift layer 2 withstand higher reverse voltages, preventing the semiconductor device from being damaged. In some embodiments, the carrier storage layer 3 may not be provided in the semiconductor device 100. In the first direction, the drift layer 2 and the base layer 4 are in direct contact, and the drift layer 2 and the anode layer 15 are in direct contact.

[0094] In this embodiment, the semiconductor device 100 further includes a field-stop layer 11 of a first conductivity type, the doping concentration of which is greater than that of the drift layer 2. In a first direction, the field-stop layer 11 is located between the drift layer 2 and the collector layer 12, and between the drift layer 2 and the cathode layer 14. The main function of the field-stop layer 11 is to terminate the electric field in the off-state of the semiconductor device, preventing the electric field from penetrating to the collector layer 12, thereby improving the withstand voltage capability. When a high voltage is applied, the field-stop layer 11 can withstand a portion of the electric field, causing the electric field to gradually weaken before reaching the collector layer 12, thus preventing breakdown of the collector layer 12. The field-stop layer 11 can also reduce the duration and amplitude of the tail current by adjusting the carrier distribution and extraction speed. Reducing the tail current helps to lower turn-off losses. In some embodiments, the conductor device 100 may not have a field-stop layer 11 of the first conductivity type; in the first direction, the drift layer 2 and the collector layer 12 are in direct contact, and the drift layer 2 and the cathode layer 14 are in direct contact.

[0095] See attached document Figure 7-17 An exemplary method for manufacturing a semiconductor device according to an embodiment of this application will be described. This manufacturing method is applicable to the semiconductor device 100 described above, and includes the following steps:

[0096] S10: Provide semiconductor substrate 1.

[0097] The semiconductor substrate 1 has a first main surface 101 and a second main surface 102 opposite to the first main surface 101, and the first main surface 101 and the second main surface 102 are spaced apart in a first direction. The substrate is a substrate of a first conductivity type, and the material of the substrate can be silicon.

[0098] S20: A plurality of trench gates 6 are formed extending from the first main surface 101 of the semiconductor substrate 1 toward the second main surface 102.

[0099] In this configuration, multiple trench gates 6 are spaced apart in the second direction, wherein the first direction and the second direction are perpendicular to each other.

[0100] For example, in step S20, a plurality of virtual gates 19 extending from the first main surface 101 of the semiconductor substrate 1 toward the second main surface 102 can be formed simultaneously.

[0101] For example, in step S20, see Appendix Figure 8 First, a patterned mask layer can be formed on the first main surface 101 of the semiconductor substrate 1. Then, the semiconductor substrate 1 is etched using the mask layer as a mask to form a plurality of gate trenches 5 and a plurality of dummy gate trenches 18. The gate trenches 5 are located in the insulated gate bipolar transistor region 1001 and the fast recovery diode region 1003. The plurality of trench gates 5 and dummy gate trenches 18 extend from the first main surface 101 of the semiconductor substrate 1 toward the second main surface 102 and are spaced apart in the second direction. Then, the mask layer is removed, and a gate trench insulating film is formed on the inner surface of the trench gates 5 and a dummy gate trench insulating film is formed on the inner surface of the dummy gate trenches 18 by thermal oxidation or CVD process. Then, gate electrode material (e.g., polysilicon doped with n-type or p-type impurities) is deposited in the gate trenches 5 and dummy gate trenches 18 and planarized to form gate trench electrodes and dummy gate trench electrodes. A trench gate 6 is formed by setting a gate trench electrode in the gate trench 5 with a gate trench insulating film in between. A virtual gate 19 is formed by setting a virtual gate trench electrode in the virtual gate trench 18 with a virtual gate trench insulating film in between.

[0102] S30: A base layer 4, an anode layer 15, and an emitter layer 10 are formed on the side of the semiconductor substrate 1 facing the first main surface 101.

[0103] The base layer 4 is located in the insulated gate bipolar transistor region 1001, and the anode layer 15 is located in the fast recovery diode region 1003.

[0104] For example, in step S30, firstly, see Appendix Figure 9Through ion implantation, doped impurities of a first conductivity type and a second conductivity type are implanted and pushed into the semiconductor substrate 1 on the side facing the first main surface 101 to form a carrier storage layer 3, a base layer 4, and an anode layer 15. For example, before doping impurity implantation, a patterned mask layer needs to be formed on the first main surface 101. This mask layer covers the side of the gate trench 5 and the dummy gate 19 away from the first main surface. After the storage layer 3, base layer 4, and anode layer 15 are formed, the mask layer is removed.

[0105] Then, see appendix. Figure 10 An emitter layer 10 is formed by implanting dopant of a first conductivity type onto the side of the base layer 4 away from the second main surface 102 using an ion implantation process. For example, before implanting the dopant, a patterned mask layer is formed on the first main surface 101. This mask layer covers the side of the gate trench 5 and the dummy gate 19 away from the first main surface, and also covers the anode layer 15 and part of the base layer 4. After the emitter layer 10 is formed, the mask layer is removed.

[0106] S40: An insulating layer 8 is deposited on the first main surface 101, and a first contact hole 801 and a second contact hole 802 are etched on the insulating layer 8.

[0107] The first contact hole 801 and the second contact hole 802 both penetrate the insulating layer 8. The first contact hole 801 is located in the fast recovery diode region 1003, and the second contact hole 802 is located in the insulated gate bipolar transistor region 1001. The first contact hole 801 and the second contact hole 802 expose the anode layer 15 and the base layer 4, respectively.

[0108] For example, see Appendix Figure 11 , 12 (Appendix) Figure 12 For the appendix Figure 11 (Partial enlarged schematic diagram at point E) In step S40, an insulating layer 8 can be deposited on the first main surface 101 by a deposition process such as CVD. The insulating layer can be, for example, a silicon dioxide layer. Then, a patterned mask layer is formed on the insulating layer 8, and the insulating layer 8 is etched using the mask layer as a mask to form a first contact hole 801 and a second contact hole 802 penetrating the insulating layer 8. Then, the mask layer is removed.

[0109] S50: First, dopant of the second conductivity type is injected into the anode layer 15 exposed by the first contact hole 801 to form a first semiconductor region 7 of the second conductivity type. Then, dopant of the second conductivity type is injected into the base layer 4 exposed by the second contact hole 802 to form a second semiconductor region 9 of the second conductivity type.

[0110] Wherein, the depth of the second semiconductor region 9 in the first direction is greater than the depth of the first semiconductor region 7 in the first direction. For example, the first semiconductor region 7 is defined as extending from the first main surface 101 to within the semiconductor substrate 1 in the first direction (i.e.,... Figure 5 Let A be the depth of the first semiconductor region 7 (in the vertical direction), and let B be the depth of the second semiconductor region 9 from the first main surface 101 into the semiconductor substrate 1 in the first direction. A and B satisfy the relationship: A ≤ 0.45B. For example, the doping impurity implantation energy of the first semiconductor region 7 is less than that of the second semiconductor region 9. Let Q be the doping impurity implantation energy of the first semiconductor region 7, where Q satisfies the relationship: 10 keV ≤ Q ≤ 40 keV. For example, let D be the doping impurity implantation dose of the first semiconductor region 7, where D satisfies the relationship: 2E14 ≤ D ≤ 8E14.

[0111] For example, see Appendix Figure 11 , 12 (Appendix) Figure 12 For the appendix Figure 11 (Partial enlarged schematic diagram at point E) In step S50, a first mask layer can be formed in the second contact hole 802 to protect the base layer 4; then, through an ion implantation process, dopants of a second conductivity type are implanted into the anode layer 15 exposed in the first contact hole 801 to form a first semiconductor region 7 of the second conductivity type; then, the first mask layer is removed, and a second mask layer is formed in the first contact hole 801 to protect the first semiconductor region 7; then, through an ion implantation process, dopants of a second conductivity type are implanted into the base layer 4 exposed in the second contact hole 802 to form a second semiconductor region 9 of the second conductivity type.

[0112] In some other embodiments, step S50 may be as follows: simultaneously implanting dopant of a second conductivity type into the anode layer 15 exposed by the first contact hole 801 and the base layer 4 exposed by the second contact hole 802, to form a first semiconductor region 7 of the second conductivity type in the anode layer 15 and a sub-semiconductor region of the second conductivity type with the same depth as the first semiconductor region 7 in the base layer 4, and then implanting dopant of the second conductivity type into the portion of the base layer 4 corresponding to the sub-semiconductor region to form a second semiconductor region 9. The depth of the second semiconductor region 9 is greater than the depth of the first semiconductor region 7. For example, the first semiconductor region 7 is defined as extending from the first main surface 101 to within the semiconductor substrate 1 in a first direction (i.e.,...). Figure 5Let A be the depth of the first semiconductor region 7 (in the vertical direction), and let B be the depth of the second semiconductor region 9 from the first main surface 101 into the semiconductor substrate 1 in the first direction. A and B satisfy the relationship: A ≤ 0.45B. For example, the doping impurity implantation energy of the first semiconductor region 7 is less than that of the second semiconductor region 9. Let Q be the doping impurity implantation energy of the first semiconductor region 7, where Q satisfies the relationship: 10 keV ≤ Q ≤ 40 keV. For example, let D be the doping impurity implantation dose of the first semiconductor region 7, where D satisfies the relationship: 2E14 ≤ D ≤ 8E14.

[0113] S60: Form a first titanium film 8011 and a second titanium film 8021 located in the first contact hole 801 and the second contact hole 802, respectively.

[0114] The first titanium film 8011 is in contact with the first semiconductor region 7, and the second titanium film 8021 is in contact with the second semiconductor region 9.

[0115] For example, see Appendix Figure 13 , 14 (Appendix) Figure 14 For the appendix Figure 13 (A partially enlarged schematic diagram at point F) shows that a titanium-containing material can be deposited integrally in the first contact hole 801, the second contact hole 802, and the side of the insulating layer 8 away from the first main surface 101 using a CVD process or other suitable deposition process, to form a first titanium film 8011 and a second titanium film 8021 in the first contact hole 801 and the second contact hole 802, respectively. For example, the titanium-containing material may include titanium and / or titanium nitride.

[0116] A first titanium film 8011, adjacent to the first main surface 101, contacts the first semiconductor region 7 to form a first titanium silicide layer 8012. A second titanium film 8021, adjacent to the first main surface 101, contacts the second semiconductor region 9 to form a second titanium silicide layer 8022. The depth of the first semiconductor region 7 from the first main surface 101 into the semiconductor substrate 1 in a first direction is set to A; the depth of the second semiconductor region 9 from the first main surface 101 into the semiconductor substrate 1 in a first direction is set to B; and the depth of the first titanium silicide layer 8012 from the first main surface 101 into the semiconductor substrate 1 in a first direction is set to C. C, A, and B satisfy the relationship: A ≤ C ≤ 0.5B; or C and A satisfy the relationship: C < A. For example, the region containing the first semiconductor region 7 is completely located within the region containing the first titanium silicide layer 8012, or the region containing the first titanium silicide layer 8012 is completely located within the region containing the first semiconductor region 7.

[0117] Within the second contact hole 802, the second titanium film 8021 on the side adjacent to the second semiconductor region 9 in the first direction is in contact with the second semiconductor region 9 to form a second titanium silicide layer 8022. The second titanium silicide layer 8022 extends from the first main surface 101 into the semiconductor substrate 1 along the first direction. The depth of the second titanium silicide layer 8022 from the first main surface 101 into the semiconductor substrate 1 in the first direction is set to D. D and B satisfy the relationship: D≤B.

[0118] For example, after step S60, the method for manufacturing a semiconductor device may further include the following steps:

[0119] See appendix Figure 15 Tungsten metal is deposited in the first contact hole 801 and the second contact hole 802 by CVD process or other suitable deposition process and then etched back to form a tungsten layer 16 in the first contact hole 801 and the second contact hole 802. The tungsten layer 16 located in the fast recovery diode region 1003 is in contact with the first titanium film 8011 and the first titanium silicide layer 8012, and the tungsten layer 16 located in the insulated gate bipolar transistor region 1001 is in contact with the second titanium film 8021 and the second titanium silicide layer 8022.

[0120] See appendix for details. Figure 15 A metal layer 17 is formed by depositing a layer of metal on the side of the titanium-containing material and tungsten layer 16 away from the first main surface 101 using a CVD process or other suitable deposition process. For example, the metal can be aluminum, copper, etc.

[0121] See appendix for details. Figure 16 The semiconductor substrate 1 is thinned on the side away from the first main surface 101 by a thinning process such as CMP, and a field stop layer 11 is formed by implanting doped impurities of the first conductivity type by an ion implantation process.

[0122] See appendix for details. Figure 17 By means of ion implantation, dopants of a first conductivity type and dopants of a second conductivity type are implanted on the side of the field stop layer 11 away from the first main surface to form a cathode layer 14 and a collector layer 12. Specifically, dopants of the first conductivity type are implanted in the field stop layer 11 located in the fast recovery diode region 1003 region, and dopants of the second conductivity type are implanted in the field stop layer 11 located in the insulated gate bipolar transistor region 1001.

[0123] See appendix for details. Figure 17 A metal layer is deposited on the side of the cathode layer 14 away from the first main surface 101 and the side of the collector layer 12 away from the first main surface 101 by means of CVD process or other suitable deposition process to form collector metal layer 13.

[0124] Thus, the process steps of the semiconductor device manufacturing method according to the embodiments of this application are completed. It is understood that the semiconductor device manufacturing method of this embodiment includes not only the above steps, but may also include other necessary steps before, during or after the above steps, all of which are included within the scope of the manufacturing method of this embodiment.

[0125] Although exemplary embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above exemplary embodiments are merely illustrative and are not intended to limit the scope of this application. Various changes and modifications can be made therein by those skilled in the art without departing from the scope and spirit of this application. All such changes and modifications are intended to be included within the scope of this application as claimed in the appended claims.

[0126] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed.

[0127] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of this application may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0128] Similarly, it should be understood that, in order to streamline this application and aid in understanding one or more of the various inventive aspects, features of this application may sometimes be grouped together in a single embodiment, figure, or description thereof in the description of exemplary embodiments of this application. However, this approach should not be construed as reflecting an intention that the claimed application requires more features than are expressly recited in each claim. Rather, as reflected in the corresponding claims, its inventive point lies in solving the corresponding technical problem with features fewer than all features of a single disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into that detailed description, wherein each claim itself is a separate embodiment of this application.

[0129] Those skilled in the art will understand that, apart from the mutual exclusion of features, all features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all processes or elements of any method or apparatus so disclosed can be combined in any combination. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) may be replaced by an alternative feature serving the same, equivalent, or similar purpose.

[0130] Furthermore, those skilled in the art will understand that although some embodiments described herein include certain features but not others included in other embodiments, combinations of features from different embodiments are intended to be within the scope of this application and form different embodiments. For example, in the claims, any one of the claimed embodiments can be used in any combination.

[0131] It should be noted that the above embodiments are illustrative of this application and not restrictive of this application, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims.

Claims

1. A semiconductor device (100) having a semiconductor substrate (1) having a drift layer (2) of a first conductivity type between a first main surface (101) and a second main surface (102), wherein, The first main surface (101) and the second main surface (102) are disposed opposite to each other in a first direction. The semiconductor device (100) is characterized in that it includes: An insulated gate bipolar transistor region (1001) has a trench gate (6) extending from the first main surface (101) of the semiconductor substrate (1) through an emitter layer (10) of a first conductivity type and a base layer (4) of a second conductivity type to the drift layer (2), and a collector layer (12) of the second conductivity type disposed on the side of the second main surface (102) compared to the drift layer (2), wherein there are multiple trench gates (6), the multiple trench gates (6) are spaced apart in a second direction, the length of the trench gates (6) extends in a third direction, and the first direction, the second direction and the third direction are perpendicular to each other; The fast recovery diode region (1003) has an anode layer (15) of a second conductivity type disposed on the side of the first main surface (101) compared to the drift layer (2), and a cathode layer (14) of the first conductivity type disposed on the side of the second main surface (102) compared to the drift layer (2). An insulating layer (8) is disposed on the first main surface (101). The insulating layer (8) is provided with a first contact hole (801) and a second contact hole (802). The second contact hole (802) is located in the region of the insulated gate bipolar transistor (1001), and the first contact hole (801) is located in the region of the fast recovery diode (1003). The fast recovery diode region (1003) also includes a first semiconductor region (7) of a second conductivity type and a first titanium film (8011). The first semiconductor region (7) is selectively disposed on the first main surface (101) side of the anode layer (15), and has a higher impurity concentration of the second conductivity type compared to the anode layer (15). The side of the first semiconductor region (7) facing the first main surface (101) constitutes at least a portion of the first main surface (101). The first contact hole (801) penetrates the insulating layer (8) and exposes the first semiconductor region (7). The first titanium film (8011) is disposed in the first contact hole (801) and contacts the first semiconductor region (7). The first semiconductor region (7) is electrically connected to the emitter metal (17) through the first contact hole (801). The insulated gate bipolar transistor region (1001) also includes a second semiconductor region (9) of a second conductivity type and a second titanium film (8021). The second semiconductor region (9) is selectively disposed on the first main surface (101) side of the base layer (4), and has a higher impurity concentration of the second conductivity type compared to the base layer (4). The emitter layer (10) is selectively disposed on the first main surface (101) side of the base layer (4). The side of the second semiconductor region (9) and the emitter layer (10) facing the first main surface (101) constitutes at least a portion of the first main surface (101). The second contact hole (802) penetrates the insulating layer (8) and exposes the second semiconductor region (9) and the emitter layer (10). The second titanium film (8021) is disposed in the second contact hole (802) and contacts the second semiconductor region (9). The second semiconductor region (9) and the emitter layer (10) are both electrically connected to the emitter metal (17) through the second contact hole (802). Wherein, the depth of the first semiconductor region (7) from the first main surface (101) to the semiconductor substrate (1) in the first direction is set to A, and the depth of the second semiconductor region (9) from the first main surface (101) to the semiconductor substrate (1) in the first direction is set to B. A and B satisfy the relationship: A≤0.45B; The first titanium film (8011) on the side of the first semiconductor region (7) adjacent to the first contact hole (801) in the first direction is in contact with the first semiconductor region (7) to form a first titanium silicide layer (8012). The first titanium silicide layer (8012) extends from the first main surface (101) into the semiconductor substrate (1) in the first direction. The depth of the first titanium silicide layer (8012) from the first main surface (101) into the semiconductor substrate (1) in the first direction is set to C. C, A and B satisfy the relationship: A≤C≤0.5B.

2. The semiconductor device (100) according to claim 1, characterized in that, The second titanium film (8021) on the side of the second semiconductor region (9) adjacent to the second contact hole (802) in the first direction is in contact with the second semiconductor region (9) to form a second titanium silicide layer (8022). The second titanium silicide layer (8022) extends from the first main surface (101) into the semiconductor substrate (1) in the first direction. The depth of the second titanium silicide layer (8022) from the first main surface (101) into the semiconductor substrate (1) in the first direction is set to D. D and B satisfy the relationship: D≤B.

3. The semiconductor device (100) according to claim 1, characterized in that, The region where the first semiconductor region (7) is located is entirely located in the region where the first titanium silicide layer (8012) is located.

4. The semiconductor device (100) according to any one of claims 1-3, characterized in that, C and D satisfy the relationship: C=D.

5. The semiconductor device (100) according to claim 1, characterized in that, The doping impurity implantation energy of the first semiconductor region (7) is less than that of the second semiconductor region (9). The doping impurity implantation energy of the first semiconductor region (7) is Q, which satisfies the relationship: 10 keV ≤ Q ≤ 40 keV; and / or, The impurity doping concentration of the first semiconductor region (7) is less than or equal to the impurity doping concentration of the second semiconductor region (9); and / or, The doping impurity implantation dose of the first semiconductor region (7) is D, and D satisfies the relationship: 2E14≤D≤8E14.

6. The semiconductor device (100) according to claim 1, characterized in that, The insulated gate bipolar transistor region (1001) includes a first region (10011) and a second region (10012), and there are multiple first regions (10011) and multiple second regions (10012). There are multiple emitter layers (10) and multiple second semiconductor regions (9). Multiple emitter layers (10) are disposed one-to-one in the base layers (4) of multiple first regions (10011), and multiple second semiconductor regions (9) are disposed one-to-one in the base layers (4) of multiple second regions (10012). Multiple first regions (10011) and multiple second regions (10012) are arranged alternately in a third direction.

7. The semiconductor device (100) according to claim 1, characterized in that, The insulated gate bipolar transistor region (1001) includes a first region (10011) and a second region (10012), and there are multiple first regions (10011) and multiple second regions (10012). There are multiple emitter layers (10) and multiple second semiconductor regions (9). Multiple emitter layers (10) are disposed one-to-one in the base layers (4) of multiple first regions (10011), and multiple second semiconductor regions (9) are disposed one-to-one in the base layers (4) of multiple second regions (10012). Multiple first regions (10011) and multiple second regions (10012) are arranged alternately in a second direction.

8. A method for manufacturing a semiconductor device, applicable to the semiconductor device (100) of any one of claims 1-6, characterized in that, Includes the following steps: A semiconductor substrate (1) is provided, wherein the semiconductor substrate (1) has a first main surface (101) and a second main surface (102) opposite to the first main surface (101), the first main surface (101) and the second main surface (102) being spaced apart in a first direction; A plurality of trench gates (6) are formed extending from the first main surface (101) of the semiconductor substrate (1) toward the second main surface (102), wherein the plurality of trench gates (6) are spaced apart in a second direction, wherein the first direction and the second direction are perpendicular to each other; A base layer (4), an anode layer (15), and an emitter layer (10) are formed on the side of the semiconductor substrate (1) facing the first main surface (101), wherein the base layer (4) is located in the region of the insulated gate bipolar transistor (1001), and the anode layer (15) is located in the region of the fast recovery diode (1003). An insulating layer (8) is deposited on the first main surface (101), and a first contact hole (801) and a second contact hole (802) are etched on the insulating layer (8), wherein the first contact hole (801) and the second contact hole (802) both penetrate the insulating layer (8), the first contact hole (801) is located in the fast recovery diode region (1003), and the second contact hole (802) is located in the insulated gate bipolar transistor region (1001); First, dopant of a second conductivity type is implanted into the anode layer (15) exposed by the first contact hole (801) to form a first semiconductor region (7) of the second conductivity type. Then, dopant of a second conductivity type is implanted into the base layer (4) exposed by the second contact hole (802) to form a second semiconductor region (9) of the second conductivity type. The depth of the second semiconductor region (9) in the first direction is greater than the depth of the first semiconductor region (7) in the first direction. Simultaneously, dopant of a second conductivity type is implanted into the anode layer (15) exposed by the first contact hole (801) and the base layer (4) exposed by the second contact hole (802) to form a first semiconductor region (7) of the second conductivity type in the anode layer (15), and a sub-semiconductor region of the second conductivity type with the same depth as the first semiconductor region (7) is formed in the base layer (4). Then, dopant of a second conductivity type is implanted into the portion of the base layer (4) corresponding to the sub-semiconductor region to form a second semiconductor region (9), wherein the depth of the second semiconductor region (9) is greater than the depth of the first semiconductor region (7). A first titanium film (8011) and a second titanium film (8021) are formed in the first contact hole (801) and the second contact hole (802), respectively, wherein the first titanium film (8011) is in contact with the first semiconductor region (7) and the second titanium film (8021) is in contact with the second semiconductor region (9).

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