MPS diode and manufacturing method thereof

Abstract

The present application provides an MPS diode and a method for manufacturing the same, and relates to the field of semiconductor technology. The MPS diode includes: an N-type epitaxial wafer; a terminal region and an active region located on the surface of the N-type epitaxial wafer; wherein the active region includes at least one first P column, the first P column includes a P-type sidewall, a first dielectric layer, an ohmic contact layer, and a second dielectric layer; a passivation protection layer located on the surface of the terminal region; a third dielectric layer and a first metal layer located on the surface of the active region, and a second metal layer located on the back of the epitaxial wafer; wherein the third dielectric layer contacts the second dielectric layer, and the first metal layer is arranged around the third dielectric layer. The MPS diode and the method for manufacturing the same provided by the present application have the advantages of reducing the device area and improving the reliability and robustness of the device.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to an MPS diode and a method for manufacturing the same. Background Art

[0002] The main advantage of the Schottky diode is that its forward conduction voltage is reduced, which helps to reduce conduction losses. At the same time, as a unipolar device, it has no minority carrier storage and reverse recovery phenomena, and can achieve a higher switching frequency, making the Schottky diode widely used in medium and low voltage, small and medium current and medium and high frequency fields.

[0003] However, the main problems of Schottky structure are:

[0004] (1) Due to its low barrier height and the existence of the image force barrier lowering effect, its reverse leakage current is large and increases with the increase of reverse voltage, and the breakdown characteristics are soft.

[0005] (2) Under extreme conditions such as surges in high-power applications, the forward surge current IFSM has poor tolerance, which may cause local overheating of the device or even thermal breakdown to damage the device, resulting in poor surge resistance reliability of the device.

[0006] In order to overcome the above two technical problems at the same time, a common solution is to use MPS (Merged PiNSchottky, mixed PiN / Schottky diode) diodes. On the one hand, by adjusting the cell structure size of the MPS diode, the doping of the P-type region and other conditions, the charge coupling is realized by using the two-dimensional depletion of carriers, so that the strongest electric field on the metal semiconductor contact surface is pushed into the device, the surface electric field of the device is reduced, and the Schottky barrier lowering effect is greatly weakened, the device leakage current is reduced, and a higher breakdown voltage is achieved; on the other hand, a large-size p+ region is introduced into the MPS diode, which is opened at a large current (surge current), and the resulting conductivity modulation effect will greatly reduce the on-resistance of the device, which enhances the forward surge current IFSM tolerance and improves the surge resistance of the device.

[0007] However, the MPS diode in the prior art still has problems such as poor device reliability and robustness. Summary of the invention

[0008] The purpose of the present application is to provide an MPS diode and a method for manufacturing the same, so as to solve the problems of poor device reliability and robustness of the MPS diode in the prior art.

[0009] In order to achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:

[0010] In one aspect, an embodiment of the present application provides an MPS diode, wherein the MPS diode comprises:

[0011] N-type epitaxial wafer;

[0012] The terminal area and the active area are located on the surface of the N-type epitaxial wafer; wherein the active area includes at least one first P column, the first P column includes a P-type sidewall, a first dielectric layer, an ohmic contact layer and a second dielectric layer; a first trench is provided in the middle area of ​​the P-type sidewall, the first dielectric layer and the ohmic contact layer are filled in the first trench, and the first dielectric layer is located at the bottom of the ohmic contact layer; a second trench is provided in the middle area of ​​the top of the ohmic contact layer, and the second dielectric layer is filled in the second trench;

[0013] A passivation protection layer located on the surface of the terminal region;

[0014] A third dielectric layer and a first metal layer are located on the surface of the active area, and a second metal layer is located on the back of the epitaxial wafer; wherein the third dielectric layer is in contact with the second dielectric layer, and the first metal layer is arranged around the third dielectric layer.

[0015] Optionally, the width of the third dielectric layer is greater than or equal to the width of the second dielectric layer; and the depth of the second dielectric layer is greater than the depth of the third dielectric layer.

[0016] Optionally, the surface of the ohmic contact layer is flush with the surface of the P-type side wall, or the surface of the ohmic contact layer is lower than the surface of the P-type side wall.

[0017] Optionally, when the surface of the ohmic contact layer is flush with the surface of the P-type side wall, the parameters of the MPS diode satisfy the formula:

[0018] A=C>B;

[0019] (H2+H3) / B>2:1;

[0020] (H1+H2+H3) / Lp>2 / 3;

[0021] H1 <H2+H3;

[0022] H41=H3≤1 / 2(H2+H3);

[0023] H42<thickness of the first metal layer;

[0024] Among them, A represents the thickness of the left side of the P-type side wall, B represents the width of the first trench, C represents the thickness of the right side of the P-type side wall, H1 represents the thickness of the first dielectric layer, H2 represents the thickness from the bottom of the ohmic contact layer to the bottom of the second dielectric layer, H3 and H41 both represent the thickness of the second dielectric layer, Lp represents the depth of the P-type side wall, and H42 represents the thickness of the third dielectric layer.

[0025] Optionally, when the surface of the ohmic contact layer is lower than the surface of the P-type side wall, the parameters of the MPS diode satisfy the formula:

[0026] A=C>B;

[0027] (H5+H6) / B>2:1;

[0028] (H1+H5+H6) / Lp>2 / 3;

[0029] H1 <H5+H6;

[0030] H41≤1 / 2H5;

[0031] H42<thickness of the first metal layer; wherein A represents the thickness of the left side of the P-type sidewall, B represents the width of the first trench, C represents the thickness of the right side of the P-type sidewall, H1 represents the thickness of the first dielectric layer, H41 represents the thickness of the second dielectric layer, H42 represents the thickness of the third dielectric layer, H5 represents the thickness of the ohmic contact layer, H6 represents the height difference between the surface of the ohmic contact layer and the surface of the P-type sidewall, and Lp represents the depth of the P-type sidewall. Optionally, the MPS diode further includes an N-type polysilicon layer, and when the surface of the ohmic contact layer is level with the surface of the P-type sidewall, the N-type polysilicon layer is located between the ohmic contact layer and the P-type sidewall, and the thickness of the N-type polysilicon layer is equal to that of the second dielectric layer;

[0032] When the surface of the ohmic contact layer is lower than the surface of the P-type side wall, the N-type polysilicon layer is located between the P-type side wall and the first metal layer, and the thickness of the N-type polysilicon layer is equal to the height difference between the surface of the ohmic contact layer and the surface of the P-type side wall.

[0033] Optionally, the number of the second dielectric layer is equal to that of the third dielectric layer, and when the number of the second dielectric layer and the third dielectric layer is 1, the second dielectric layer is located at the center of the ohmic contact layer;

[0034] When there are multiple second dielectric layers and multiple third dielectric layers, the multiple second dielectric layers and multiple third dielectric layers are arranged at equal intervals.

[0035] Optionally, the active area further includes a second P column, the depth of the second P column is the same as the depth of the first P column, and the second P column is a P-type doped region;

[0036] When the difference in number between the first P pillars and the second P pillars is less than or equal to 1, the first P pillars and the second P pillars are arranged alternately;

[0037] When the difference between the number of the first P column and the second P column is greater than 1, at least one second P column is disposed between two adjacent first P columns. On the other hand, an embodiment of the present application further provides a method for manufacturing an MPS diode, for manufacturing the MPS diode as described above, the method comprising:

[0038] Provide N-type epitaxial wafers;

[0039] A terminal area and an active area are fabricated on the surface of the N-type epitaxial wafer; wherein the active area includes at least one first P column, and the first P column includes a P-type sidewall, a first dielectric layer, an ohmic contact layer, and a second dielectric layer; a first trench is disposed in the middle area of ​​the P-type sidewall, the first dielectric layer and the ohmic contact layer are filled in the first trench, and the first dielectric layer is located at the bottom of the ohmic contact layer, a second trench is disposed in the middle area of ​​the top of the ohmic contact layer, and the second dielectric layer is filled in the second trench;

[0040] Making a passivation protection layer based on the surface of the terminal area;

[0041] A third dielectric layer and a first metal layer are fabricated on the surface of the active region, and a second metal layer is fabricated on the back of the epitaxial wafer; wherein the third dielectric layer contacts the second dielectric layer, and the first metal layer surrounds the third dielectric layer.

[0042] Optionally, the step of defining a terminal region and an active region based on the N-type epitaxial wafer includes:

[0043] Performing P+ ion implantation based on the active area position of the epitaxial wafer;

[0044] Fabricating a terminal structure in a terminal region of the epitaxial wafer;

[0045] The epitaxial wafer is subjected to a high temperature furnace tube annealing process;

[0046] Performing a first etching on the region after the P+ ion implantation to form a first trench, wherein the region after the etching forms a P-type sidewall;

[0047] Based on the first trench, a first dielectric layer and an ohmic contact layer are sequentially filled;

[0048] A second trench is formed based on the middle area of ​​the ohmic contact layer, and a second dielectric layer is filled based on the second trench.

[0049] Compared with the prior art, the embodiments of the present application have the following beneficial effects:

[0050] The embodiment of the present application provides an MPS diode and a manufacturing method thereof, wherein the MPS diode comprises: an N-type epitaxial wafer; a terminal region and an active region located on the surface of the N-type epitaxial wafer; wherein the active region comprises at least one first P column, and the first P column comprises a P-type sidewall, a first dielectric layer, an ohmic contact layer and a second dielectric layer; a first trench is arranged in the middle region of the P-type sidewall, and the first dielectric layer and the ohmic contact layer are filled in the first trench, and the first dielectric layer is arranged at the bottom of the ohmic contact layer; a second trench is arranged in the middle region of the top of the ohmic contact layer, and the second dielectric layer is filled in the second trench; a passivation protection layer is arranged on the surface of the terminal region; a third dielectric layer and a first metal layer are arranged on the surface of the active region, and a second metal layer is arranged on the back of the epitaxial wafer; wherein the third dielectric layer is in contact with the second dielectric layer, and the first metal layer is arranged around the third dielectric layer. On the one hand, by setting the first groove to form a large-area P+ ohmic contact area, the chip area can be greatly reduced, and the chip cost can be greatly reduced, or the saved area can be used to make a larger Schottky area, thereby enhancing the unipolar conduction performance of the device, that is, obtaining a lower forward conduction resistance and forward conduction voltage drop. On the other hand, by setting the second dielectric layer in the MPS diode, the current can be dispersed, especially in the high-current bipolar conduction state, which can greatly improve the bipolar conduction performance of the device and the forward surge current IFSM, reduce the large amount of heat generated by high current density, reduce the heat generation power, reduce the probability of thermal failure, and greatly improve the reliability of the device. On the third aspect, on the basis of setting the second dielectric layer, setting the third dielectric layer in the middle area of ​​the front metal can further play the role of thermal stress and internal stress buffering. By flexibly adjusting the size and number of the second dielectric layer and the third dielectric layer, the thermal field distribution and internal stress in this area can be flexibly adjusted, thereby improving the stability, reliability and robustness of the electrical performance of the device; at the same time, it can also further disperse the current in the high current bipolar conduction state, thereby further reducing the large amount of heat generated by the high current density, greatly reducing the device's heating power and the probability of thermal failure, and ultimately greatly improving the device's reliability and robustness.

[0051] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0053] Figure 1A schematic diagram of a first cross-sectional structure of an MPS diode provided in an embodiment of the present application.

[0054] Figure 2 A schematic diagram of a second cross-sectional structure of an MPS diode provided in an embodiment of the present application.

[0055] Figure 3 Schematic diagram of the thermal resistance model of the MPS diode provided in an embodiment of the present application.

[0056] Figure 4 This is a schematic diagram of a first cross-sectional structure of a first P column provided in an embodiment of the present application.

[0057] Figure 5 This is a schematic diagram of the second cross-sectional structure of the first P column provided in an embodiment of the present application.

[0058] Figure 6 This is a schematic diagram of the third cross-sectional structure of the first P column provided in an embodiment of the present application.

[0059] Figure 7 This is a schematic diagram of the fourth cross-sectional structure of the first P column provided in an embodiment of the present application.

[0060] Figure 8 This is a schematic diagram of a third cross-sectional structure of the MPS diode provided in an embodiment of the present application.

[0061] Fig. 9 This is a schematic diagram of a fourth cross-sectional structure of the MPS diode provided in an embodiment of the present application.

[0062] Fig.10 An exemplary flow chart of the MPS diode manufacturing method provided in an embodiment of the present application.

[0063] Fig.11 This is a schematic diagram of the cross-sectional structure corresponding to S1041 provided in an embodiment of the present application.

[0064] Fig.12 This is a schematic diagram of the cross-sectional structure corresponding to S1042 provided in an embodiment of the present application.

[0065] Fig.13 This is a schematic diagram of the cross-sectional structure corresponding to S1043 provided in an embodiment of the present application.

[0066] Fig.14 This is a schematic diagram of the corresponding cross-sectional structure after etching the ohmic contact layer provided in an embodiment of the present application.

[0067] In the figure:

[0068] 101-substrate; 102-epitaxial layer; 103-first P column; 104-second P column; 105-P-type side wall; 106-first dielectric layer; 107-ohmic contact layer; 108-second dielectric layer; 109-third dielectric layer; 110-first metal layer; 111-terminal region; 112-passivation protection layer; 113-second metal layer; 114-N-type polysilicon layer. DETAILED DESCRIPTION

[0069] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0070] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0071] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0072] It should be noted that, in this document, relational terms such as first and second, etc. are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0073] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0074] As described in the background art, the MPS diode in the prior art still has problems such as poor device reliability and robustness.

[0075] In view of this, the present application provides an MPS diode, which achieves the effect of increasing the device breakdown voltage, reducing the chip area, and improving the device reliability and robustness by filling an ohmic contact layer in the groove and setting a first dielectric layer, a second dielectric layer, and a third dielectric layer.

[0076] The MPS diode provided in this application is exemplarily described below:

[0077] As an implementation, see Figure 1 , the MPS diode includes:

[0078] N-type epitaxial wafer;

[0079] A terminal region 111 and an active region are located on the surface of an N-type epitaxial wafer; wherein the active region includes at least one first P column 103, and the first P column 103 includes a P-type sidewall 105, a first dielectric layer 106, an ohmic contact layer 107, and a second dielectric layer 108; a first trench is provided in the middle region of the P-type sidewall 105, and the first dielectric layer 106 and the ohmic contact layer 107 are filled in the first trench, and the first dielectric layer 106 is located at the bottom of the ohmic contact layer 107; a second trench is provided in the middle region of the top of the ohmic contact layer 107, and the second dielectric layer 108 is filled in the second trench; a passivation protection layer 112 is located on the surface of the terminal region 111; a third dielectric layer 109 and a first metal layer 110 are located on the surface of the active region, and a second metal layer 113 is located on the back of the epitaxial wafer; wherein the third dielectric layer 109 is in contact with the second dielectric layer 108, and the first metal layer 110 is arranged around the third dielectric layer 109.

[0080] The N-type epitaxial wafer provided in the present application includes a substrate 101 and an epitaxial layer 102. The substrate 101 may be a SiC substrate, and the epitaxial layer 102 may be an N - Of course, the substrate 101 and the epitaxial layer 102 can also be made of other materials, for example, they can be made of Si material.

[0081] The present application does not limit the number of first P columns 103 in the active area, and the number can be one or more. In addition, the active area also includes a second P column 104, the depth of the second P column 104 is the same as the depth of the first P column 103, and the second P column 104 is a P-type doped region, that is, the second P column 104 is a pure P+ region, and does not include structures such as the first dielectric layer 106, the ohmic contact layer 107, and the second dielectric layer 108. In addition, when the difference in the number of the first P column 103 and the second P column 104 is less than or equal to 1, the first P column 103 and the second P column 104 are arranged alternately; when the difference in the number of the first P column 103 and the second P column 104 is greater than 1, at least one second P column 104 is arranged between two adjacent first P columns 103. Through this arrangement, it can be ensured that there is at least one second P column 104 between two first P columns 103.

[0082] Furthermore, when the first P-pillars 103 and the second P-pillars 104 are arranged alternately, it is more conducive to achieving the best bipolar conduction performance, and more conducive to heat dissipation under large current, thereby improving the thermal performance and thermal reliability of the device. Figure 1 As shown in , the total number of P pillars is 3, on this basis, two second P pillars 104 and one first P pillar 103 may be included, each P pillar is arranged at an interval, and the first P pillar 103 is located between the two second P pillars 104 .

[0083] Similarly, when the total number of P pillars is 5, the number of first P pillars 103 may be 2, and the number of second P pillars 104 may be 3, and they are distributed in an alternating arrangement.

[0084] For the first P column 103 provided in the present application, in one implementation, the first dielectric layer 106 can use a low dielectric constant medium or a high dielectric strength material. For example, when using materials such as PI polyimide, according to Gauss's theorem, the first groove area can withstand the largest possible peak electric field, thereby greatly improving the breakdown voltage of the device.

[0085] Moreover, for MPS diodes, the proportion of the area of ​​the Schottky region and the large-size P+ region in the active area of ​​the device will directly affect the conduction capability of the device under rated current conditions (unipolar conduction performance) and the conduction capability under surge large current impact conditions (bipolar conduction performance). Conventional MPS diodes have a large-size P+ ohmic contact area, which results in a large size of the entire MPS diode. In the present application, a first groove is made and an ohmic contact layer 107 is filled in the first groove, so that a large-area P+ ohmic contact area is formed on the sidewall of the first groove, which can greatly reduce the chip area and greatly reduce the chip cost, or the saved area can be used to make a larger Schottky area, thereby enhancing the unipolar conduction performance of the device, that is, obtaining a lower forward on-resistance and forward on-voltage drop.

[0086] Among them, setting the second dielectric layer 108 in the middle area of ​​the ohmic metal can play the role of dispersing current, especially in the large current bipolar conduction state, it can greatly improve the bipolar conduction performance of the device and the forward surge current IFSM, reduce the large amount of heat generated by high current density, reduce the heat generation power, reduce the probability of thermal failure, and greatly improve the reliability of the device.

[0087] At the same time, in one implementation, the second dielectric layer 108 can be made of a material having both a low dielectric constant and a high thermal conductivity. On the one hand, the low dielectric constant can reduce the impact of the introduction of complex parasitic effects on device performance, thereby enhancing the dynamic characteristics of the device and its control capabilities. On the other hand, the high thermal conductivity can quickly transfer heat energy, which is beneficial to enhancing the heat dissipation performance and heat dissipation efficiency of the device, and greatly improving the reliability and durability of the device.

[0088] In addition, on the basis of the second dielectric layer 108, a third dielectric layer 109 is arranged in the middle area of ​​the front metal, which can further play the role of thermal stress and internal stress buffering. Moreover, the second dielectric layer 108 and the third dielectric layer 109 are generally arranged in pairs. By flexibly adjusting the size and number of the second dielectric layer 108 and the third dielectric layer 109, the thermal field distribution and internal stress in this area can be flexibly adjusted, thereby improving the stability, reliability and robustness of the device's electrical performance. At the same time, the third dielectric layer 109 can further disperse the current in the high current bipolar conduction state, thereby further reducing the large amount of heat generated by the high current density, greatly reducing the device's heating power and the probability of thermal failure, and ultimately greatly improving the device's reliability and robustness.

[0089] It should be noted that the structure of the first P column 103 provided in the present application includes two types, one of which is as follows: Figure 1 As shown, the surface of the ohmic contact layer 107 is flush with the surface of the P-type side wall 105. Figure 2 As shown, the surface of the ohmic contact layer 107 is lower than the surface of the P-type side wall 105. When the surface of the ohmic contact layer 107 is lower than the surface of the P-type side wall 105, the cross-sectional area of ​​the ohmic metal region and the first metal layer 110 filled into the first trench are considered to be the same. In terms of process, the first metal layer 110 is filled into the first trench after etching the ohmic metal. Figure 3 From the perspective of the thermal resistance model, it is equivalent to shortening the original ohmic metal length and increasing the metal length of the first metal layer 110. At the same time, the thermal conductivity of the first metal layer 110 (the material for making the ohmic contact layer 107 is generally metal Ni, and the material for making the first metal layer 110 is generally metal Al) is introduced into the entire first groove area on the basis of the original single ohmic metal thermal conductivity. Therefore, by flexibly adjusting the ratio of the Al metal and ohmic metal areas, the thermal resistance and heat dissipation performance of the device can be flexibly adjusted, as well as the bipolar conduction performance of the device can be flexibly adjusted.

[0090] It can be understood that no matter the surface of the ohmic contact layer 107 is flush with the surface of the P-type side wall 105, or the surface of the ohmic contact layer 107 is lower than the surface of the P-type side wall 105, in the first P column 103, the number of the second dielectric layer 108 and the third dielectric layer 109 may not be limited. For example, the number of the second dielectric layer 108 and the third dielectric layer 109 may be 1, or 2, or may be set to a greater number.

[0091] Furthermore, the depth of the second dielectric layer 108 is greater than the depth of the third dielectric layer 109, so that the device can disperse the current more effectively. At the same time, the width of the third dielectric layer 109 is greater than or equal to the width of the second dielectric layer 108. The overall structure of the second dielectric layer 108 and the third dielectric layer 109 needs to be symmetrical, so the overall structure of the second dielectric layer 108 and the third dielectric layer 109 can be set to "I type" or "T type". Figure 1 and Figure 2 In the embodiment, the overall structure of the second dielectric layer 108 and the third dielectric layer 109 is set to "I type"; Figure 4 In the embodiment, the overall structure of the second dielectric layer 108 and the third dielectric layer 109 is set to be a "T-type".

[0092] In addition, on the basis that the number of the second dielectric layer 108 and the third dielectric layer 109 is equal, when the number of the second dielectric layer 108 and the third dielectric layer 109 is one, the second dielectric layer 108 is located at the center of the ohmic contact layer 107. When the number of the second dielectric layer 108 and the third dielectric layer 109 is multiple, it is required that the structures of the multiple second dielectric layers 108 and the multiple third dielectric layers 109 are the same, that is, the overall structure of the combination of the second dielectric layer 108 and the third dielectric layer 109 is set to "I type" or "T type". In addition, the multiple second dielectric layers 108 and the third dielectric layers 109 are arranged at equal intervals. At the same time, the spacing between the two outermost second dielectric layers 108 and the P-type side wall 105 is equal to the spacing between two adjacent second dielectric layers 108. For example, refer to Figure 5 , the number of the second dielectric layer 108 and the third dielectric layer 109 is 2, and the overall structure of the second dielectric layer 108 and the third dielectric layer 109 is set to "T-type". The parameters in the figure meet the following requirements:

[0093] 3W+2M=L, W is greater than or equal to X (W and X are not equal to 0). Wherein, L represents the width of the ohmic contact layer 107, W represents the spacing between two adjacent second dielectric layers 108, M represents the width of the second dielectric layer 108, and X represents the spacing between two adjacent third dielectric layers 109. Similarly, when the number of the second dielectric layer 108 and the third dielectric layer 109 is 3, the parameters satisfy: 4W+3M=L, W is greater than or equal to X (W and X are not equal to 0); at the same time, W>M is set to make the device performance more stable, and the reliability and robustness performance higher.

[0094] In order to improve the overall performance of the device, it is necessary to define the relevant parameters in the first P column 103:

[0095] See also Figure 6 , when the surface of the ohmic contact layer 107 is flush with the surface of the P-type sidewall 105, the parameters of the MPS diode satisfy the formula:

[0096] A=C>B;

[0097] (H2+H3) / B>2:1;

[0098] (H1+H2+H3) / Lp>2 / 3;

[0099] H1 <H2+H3;

[0100] H41=H3≤1 / 2(H2+H3);

[0101] H42<thickness of the first metal layer;

[0102] Among them, A represents the thickness of the left side of the P-type side wall 105, B represents the width of the first trench, C represents the thickness of the right side of the P-type side wall 105, H1 represents the thickness of the first dielectric layer 106, H2 represents the thickness from the bottom of the ohmic contact layer 107 to the bottom of the second dielectric layer 108, H3 and H41 both represent the thickness of the second dielectric layer 108, Lp represents the depth of the P-type side wall 105, and H42 represents the thickness of the third dielectric layer 109.

[0103] By setting this parameter, the ohmic contact of the large-size P+ region of the device can be made more sufficient, and the bipolar conduction performance of the device (i.e., the bipolar on-resistance under large injection current and the corresponding forward conduction voltage drop VF) and the forward surge current IFSM can be adjusted more flexibly. At the same time, when the parameters of the MPS diode provided in this application meet the condition A=C>B, it is conducive to stabilizing the control of device performance and obtaining more stable bipolar conduction performance under surge and large current impact conditions. In addition, by adjusting the sizes of H1, H2+H3 and H41, H42, the thermal field distribution and internal stress of the device can be flexibly adjusted, thereby improving the stability, reliability and robustness of the device's electrical performance.

[0104] When the surface of the ohmic contact layer 107 is lower than the surface of the P-type side wall 105, see Figure 7 , the parameters of the MPS diode satisfy the formula:

[0105] A=C>B;

[0106] (H5+H6) / B>2:1;

[0107] (H1+H5+H6) / Lp>2 / 3;

[0108] H1 <H5+H6;

[0109] H41≤1 / 2H5;

[0110] H42<thickness of the first metal layer;

[0111] Among them, A represents the thickness of the left side of the P-type side wall 105, B represents the width of the first groove, C represents the thickness of the right side of the P-type side wall 105, H1 represents the thickness of the first dielectric layer 106, H41 represents the thickness of the second dielectric layer 108, H42 represents the thickness of the third dielectric layer 109, H5 represents the thickness of the ohmic contact layer 107, H6 represents the height difference between the surface of the ohmic contact layer and the surface of the P-type side wall 105, and Lp represents the depth of the P-type side wall 105.

[0112] Through this setting, the ohmic contact of the large-size P+ region of the device can be made more sufficient, thereby more flexibly adjusting the bipolar conduction performance of the device (i.e., the bipolar conduction resistance under large injection current and the corresponding forward conduction voltage drop VF) and forward surge current IFSM, etc. At the same time, when the parameters of the MPS diode provided in this application meet the condition A=C>B, it is conducive to stabilizing the control of device performance and obtaining more stable bipolar conduction performance under surge large current impact conditions.

[0113] In addition, the ratio of the first metal layer 110 and the ohmic metal region (i.e., the ratio of H5 to H6) can be flexibly adjusted, thereby flexibly adjusting the thermal resistance and heat dissipation performance of the device, as well as the bipolar conduction performance of the device. At the same time, the present application sets H41 to be less than or equal to 1 / 2H5, and by adjusting the sizes of H1, H5+H6, H41, and H42, the thermal field distribution and internal stress of the device can be flexibly adjusted, thereby improving the stability, reliability, and robustness of the electrical performance of the device.

[0114] In addition, in one implementation, the MPS diode further includes an N-type polysilicon layer 114, see Figure 8 When the surface of the ohmic contact layer 107 is flush with the surface of the P-type sidewall 105 , the N-type polysilicon layer 114 is located between the ohmic contact layer 107 and the P-type sidewall 105 , and the thickness of the N-type polysilicon layer 114 is equal to that of the second dielectric layer 108 .

[0115] See also Fig. 9 When the surface of the ohmic contact layer 107 is lower than the surface of the P-type side wall 105 , the N-type polysilicon layer 114 is located between the P-type side wall 105 and the first metal layer 110 , and the thickness of the N-type polysilicon layer 114 is equal to the height difference between the surface of the ohmic contact layer and the surface of the P-type side wall 105 .

[0116] By introducing N-type ions at the interface, the interface charge sensitivity can be reduced, the surface electric field can be improved, the interface can be electrically neutral, and the surface leakage can be reduced, the device breakdown voltage and dynamic characteristics can be improved, and the device reliability and robustness can be greatly improved. It can also comprehensively and efficiently adjust and improve the device's withstand voltage, dynamic characteristics, bipolar conduction performance, forward surge current IFSM, thermal resistance and heat dissipation performance, etc., so that the device performance is more stable, and the reliability and robustness are higher.

[0117] Based on the above implementation, the present application also provides a method for manufacturing an MPS diode. Fig.10 , the method comprising:

[0118] S102, providing an N-type epitaxial wafer.

[0119] S104, defining a terminal region 111 and an active region based on the surface of an N-type epitaxial wafer; wherein the active region includes at least one first P column 103, and the first P column 103 includes a P-type side wall 105, a first dielectric layer 106, an ohmic contact layer 107, and a second dielectric layer 108; a first trench is disposed in the middle region of the P-type side wall 105, and the first dielectric layer 106 and the ohmic contact layer 107 are filled in the first trench, and the first dielectric layer 106 is located at the bottom of the ohmic contact layer 107, and a second trench is disposed in the middle region of the top of the ohmic contact layer 107, and the second dielectric layer 108 is filled in the second trench.

[0120] S106 , manufacturing a passivation protection layer 112 based on the surface of the terminal region 111 .

[0121] S108, fabricating a third dielectric layer 109 and a first metal layer 110 based on the surface of the active area, and fabricating a second metal layer 113 located on the back side of the epitaxial wafer; wherein the third dielectric layer 109 contacts the second dielectric layer 108, and the first metal layer 110 is disposed around the third dielectric layer 109.

[0122] Among them, S104 includes:

[0123] S1041, performing P+ ion implantation based on the active area position of the epitaxial wafer.

[0124] S1042, manufacturing a terminal structure in the terminal region 111 of the epitaxial wafer.

[0125] S1043, subjecting the epitaxial wafer to a high-temperature furnace tube annealing process.

[0126] S1044 , performing a first etching on the region after the P+ ion implantation to form a first trench, wherein the region after the etching forms a P-type sidewall 105 .

[0127] S1045 , filling the first dielectric layer 106 and the ohmic contact layer 107 in sequence based on the first trench.

[0128] S1046 , manufacturing a second trench based on the middle area of ​​the ohmic contact layer 107 , and filling the second trench with a second dielectric layer 108 .

[0129] Below Figure 1 Taking the structure shown in the figure as an example, the manufacturing method thereof is described as follows:

[0130] See also Fig.11 First, an N-type epitaxial wafer is provided, and P+ ion implantation is performed on the surface of the N-type epitaxial wafer to form a plurality of second P columns 104. Then, the terminal region 111 can be fabricated and subjected to high temperature furnace annealing.

[0131] Next, see Fig.12 , the first P column 103 is manufactured based on the middle second P column 104. Specifically, a first trench is formed in the middle second P column 104 by etching.

[0132] Afterwards, see Fig.13 , based on the first trench, the first dielectric layer 106 is filled, and then the first dielectric layer 106 is etched to retain only the first dielectric layer 106 at the bottom, and an ohmic metal is deposited on the first dielectric layer 106 and annealed to form an ohmic contact layer 107.

[0133] Then, the ohmic contact layer 107 is etched to form a second trench, the width of which is smaller than that of the first trench, and a second dielectric layer 108 is filled in the second trench.

[0134] Then, the third dielectric layer 109 is manufactured. For example, a third dielectric layer 109 can be manufactured by deposition first, and then the third dielectric layer 109 is etched to retain only the third dielectric layer 109 located on the top of the second dielectric layer 108. It can be understood that the width of the etched third dielectric layer 109 can be selected according to actual needs. Then, the first metal layer 110, the passivation protection layer 112 and the second metal layer 113 located on the back side of the epitaxial layer are manufactured. The thickness of the first metal layer 110 is greater than the thickness of the third dielectric layer 109.

[0135] Of course, when it is necessary to manufacture MPS diodes of other structures, it is possible to add processes to the above-mentioned manufacturing method. Figure 2 The MPS diode shown in the above Fig.13 On the basis of, firstly, a wide groove etching is performed on the ohmic contact layer 107 so that the surface of the ohmic contact layer 107 is lower than the surface of the P-type side wall 105, such as Fig.14 Then, the ohmic contact layer 107 is subjected to a second narrow groove etching to form two second trenches, which are then filled with the second dielectric layer 108 .

[0136] When you need to make Figure 8 When the MPS diode shown in FIG. 1 is formed, the ohmic contact layer 107 ( Fig.13 As shown in FIG. 1 , the interface between the ohmic contact layer 107 and the P-type sidewall 105 is etched, and then N-type polysilicon is deposited to form an N-type polysilicon layer 114.

[0137] When you need to make Fig. 9 In the MPS diode shown in FIG. 1 , an ohmic contact layer 107 may be formed, and the surface of the ohmic contact layer 107 may be etched so that the surface is lower than the surface of the P-type side wall 105 ( Fig.14 As shown in FIG. 1 , N-type polysilicon is first deposited on the surface of the ohmic contact layer 107, and then the N-type polysilicon in the middle region is etched to expose the ohmic contact layer 107, thereby retaining the N-type polysilicon layer 114 in contact with the P-type sidewall 105. The second dielectric layer 108 is then manufactured.

[0138] In summary, an embodiment of the present application provides an MPS diode and a manufacturing method thereof, wherein the MPS diode comprises: an N-type epitaxial wafer; a terminal region and an active region located on the surface of the N-type epitaxial wafer; wherein the active region comprises at least one first P column, the first P column comprises a P-type sidewall, a first dielectric layer, an ohmic contact layer and a second dielectric layer; a first trench is provided in the middle region of the P-type sidewall, the first dielectric layer and the ohmic contact layer are filled in the first trench, and the first dielectric layer is located at the bottom of the ohmic contact layer; a second trench is provided in the middle region of the top of the ohmic contact layer, and the second dielectric layer is filled in the second trench; a passivation protection layer is located on the surface of the terminal region; a third dielectric layer and a first metal layer are located on the surface of the active region, and a second metal layer is located on the back of the epitaxial wafer; wherein the third dielectric layer is in contact with the second dielectric layer, and the first metal layer is arranged around the third dielectric layer. On the one hand, by setting the first groove to form a large-area P+ ohmic contact area, the chip area can be greatly reduced, and the chip cost can be greatly reduced, or the saved area can be used to make a larger Schottky area, thereby enhancing the unipolar conduction performance of the device, that is, obtaining a lower forward conduction resistance and forward conduction voltage drop. On the other hand, by setting the second dielectric layer in the MPS diode, the current can be dispersed, especially in the high-current bipolar conduction state, which can greatly improve the bipolar conduction performance of the device and the forward surge current IFSM, reduce the large amount of heat generated by high current density, reduce the heat generation power, reduce the probability of thermal failure, and greatly improve the reliability of the device. On the third aspect, on the basis of setting the second dielectric layer, setting the third dielectric layer in the middle area of ​​the front metal can further play the role of thermal stress and internal stress buffering. By flexibly adjusting the size and number of the second dielectric layer and the third dielectric layer, the thermal field distribution and internal stress in this area can be flexibly adjusted, thereby improving the stability, reliability and robustness of the electrical performance of the device; at the same time, it can also further disperse the current in the high current bipolar conduction state, thereby further reducing the large amount of heat generated by the high current density, greatly reducing the device's heating power and the probability of thermal failure, and ultimately greatly improving the device's reliability and robustness.

[0139] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0140] It will be apparent to those skilled in the art that the present application is not limited to the details of the exemplary embodiments described above, and that the present application can be implemented in other specific forms without departing from the spirit or essential features of the present application. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the present application is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims be included in the present application. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims

1. An MPS diode, characterized in that: The MPS diode comprises: N-type epitaxial wafer; The terminal area and the active area are located on the surface of the N-type epitaxial wafer; wherein the active area includes at least one first P column, the first P column includes a P-type sidewall, a first dielectric layer, an ohmic contact layer and a second dielectric layer; a first trench is provided in the middle area of ​​the P-type sidewall, the first dielectric layer and the ohmic contact layer are filled in the first trench, and the first dielectric layer is located at the bottom of the ohmic contact layer; a second trench is provided in the middle area of ​​the top of the ohmic contact layer, and the second dielectric layer is filled in the second trench; A passivation protection layer located on the surface of the terminal region; A third dielectric layer and a first metal layer are located on the surface of the active area, and a second metal layer is located on the back of the epitaxial wafer; wherein the third dielectric layer is in contact with the second dielectric layer, and the first metal layer is arranged around the third dielectric layer.

2. The MPS diode according to claim 1, characterized in that The width of the third dielectric layer is greater than or equal to the width of the second dielectric layer; and the depth of the second dielectric layer is greater than the depth of the third dielectric layer.

3. The MPS diode according to claim 1, characterized in that The surface of the ohmic contact layer is flush with the surface of the P-type side wall, or the surface of the ohmic contact layer is lower than the surface of the P-type side wall.

4. The MPS diode according to claim 3, characterized in that When the surface of the ohmic contact layer is flush with the surface of the P-type side wall, the parameters of the MPS diode satisfy the formula: A=C>B; (H2+H3) / B>2:1; (H1+H2+H3) / Lp>2 / 3; H1 <H2+H3; H41=H3≤1 / 2(H2+H3); H42<thickness of the first metal layer; Among them, A represents the thickness of the left side of the P-type side wall, B represents the width of the first trench, C represents the thickness of the right side of the P-type side wall, H1 represents the thickness of the first dielectric layer, H2 represents the thickness from the bottom of the ohmic contact layer to the bottom of the second dielectric layer, H3 and H41 both represent the thickness of the second dielectric layer, Lp represents the depth of the P-type side wall, and H42 represents the thickness of the third dielectric layer.

5. The MPS diode according to claim 3, characterized in that When the surface of the ohmic contact layer is lower than the surface of the P-type side wall, the parameters of the MPS diode satisfy the formula: A=C>B; (H5+H6) / B>2:1; (H1+H5+H6) / Lp>2 / 3; H1 <H5+H6; H41≤1 / 2H5; H42<thickness of the first metal layer; wherein A represents the thickness of the left side of the P-type side wall, B represents the width of the first groove, C represents the thickness of the right side of the P-type side wall, H1 represents the thickness of the first dielectric layer, H41 represents the thickness of the second dielectric layer, H42 represents the thickness of the third dielectric layer, H5 represents the thickness of the ohmic contact layer, H6 represents the height difference between the surface of the ohmic contact layer and the surface of the P-type side wall, and Lp represents the depth of the P-type side wall.

6. The MPS diode according to claim 3, characterized in that The MPS diode further includes an N-type polysilicon layer, and when the surface of the ohmic contact layer is flush with the surface of the P-type side wall, the N-type polysilicon layer is located between the ohmic contact layer and the P-type side wall, and the thickness of the N-type polysilicon layer is equal to that of the second dielectric layer; When the surface of the ohmic contact layer is lower than the surface of the P-type side wall, the N-type polysilicon layer is located between the P-type side wall and the first metal layer, and the thickness of the N-type polysilicon layer is equal to the height difference between the surface of the ohmic contact layer and the surface of the P-type side wall.

7. The MPS diode according to claim 1, characterized in that The number of the second dielectric layer is equal to that of the third dielectric layer, and when the number of the second dielectric layer and the third dielectric layer is 1, the second dielectric layer is located at the center of the ohmic contact layer; When there are multiple second dielectric layers and multiple third dielectric layers, the multiple second dielectric layers and multiple third dielectric layers are arranged at equal intervals.

8. The MPS diode according to claim 1, characterized in that The active area further includes a second P column, the depth of the second P column is the same as the depth of the first P column, and the second P column is a P-type doping region; When the difference in number between the first P pillars and the second P pillars is less than or equal to 1, the first P pillars and the second P pillars are arranged alternately; When the difference in number between the first P pillars and the second P pillars is greater than 1, at least one second P pillar is disposed between two adjacent first P pillars.

9. A method for manufacturing a MPS diode, characterized in that: For manufacturing the MPS diode according to any one of claims 1 to 8, the method comprises: Provide N-type epitaxial wafers; A terminal region and an active region are defined based on the surface of the N-type epitaxial wafer; wherein the active region includes at least one first P column, the first P column includes a P-type sidewall, a first dielectric layer, an ohmic contact layer and a second dielectric layer; a first trench is provided in the middle region of the P-type sidewall, the first dielectric layer and the ohmic contact layer are filled in the first trench, and the first dielectric layer is located at the bottom of the ohmic contact layer, a second trench is provided in the middle region of the top of the ohmic contact layer, and the second dielectric layer is filled in the second trench; Making a passivation protection layer based on the surface of the terminal area; A third dielectric layer and a first metal layer are fabricated on the surface of the active region, and a second metal layer is fabricated on the back of the epitaxial wafer; wherein the third dielectric layer contacts the second dielectric layer, and the first metal layer surrounds the third dielectric layer.

10. The method for manufacturing an MPS diode according to claim 9, wherein: The step of defining the terminal region and the active region based on the surface of the N-type epitaxial wafer comprises: Performing P+ ion implantation based on the active area position of the epitaxial wafer; Fabricating a terminal structure in a terminal region of the epitaxial wafer; The epitaxial wafer is subjected to a high temperature furnace tube annealing process; Performing a first etching on the region after the P+ ion implantation to form a first trench, wherein the region after the etching forms a P-type sidewall; Based on the first trench, a first dielectric layer and an ohmic contact layer are sequentially filled; A second trench is formed based on the middle area of ​​the ohmic contact layer, and a second dielectric layer is filled based on the second trench.

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